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@@ -49,3 +49,7 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 .local/share/jupyter/nbextensions/nbTranslate/demo2.gif filter=lfs diff=lfs merge=lfs -text
 .local/share/jupyter/nbextensions/scratchpad/demo.gif filter=lfs diff=lfs merge=lfs -text
 .local/share/jupyter/nbextensions/toc2/demo.gif filter=lfs diff=lfs merge=lfs -text
+wandb/run-20240926_055222-14kj2390/run-14kj2390.wandb filter=lfs diff=lfs merge=lfs -text
+wandb/run-20240926_124123-zc6s8e8w/run-zc6s8e8w.wandb filter=lfs diff=lfs merge=lfs -text
+wandb/run-20240926_192831-378lr5yg/run-378lr5yg.wandb filter=lfs diff=lfs merge=lfs -text
+wandb/run-20240927_021423-clesd0p8/run-clesd0p8.wandb filter=lfs diff=lfs merge=lfs -text

.triton/dump/0db70b0f0846c3c6c38c4ccb3ef979e3/triton_.llir

@@ -0,0 +1,1121 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@assertFunc_1 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_1 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_1 = internal constant [39 x i8] c"index out of bounds: 0 <= tmp16 < 50257"
+@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp3 < 50257"
+@global_smem = external local_unnamed_addr addrspace(3) global [0 x i8]
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr
+
+define void @triton__0d1d2d3d4d5d6de7de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, i32 %6, i32 %7) local_unnamed_addr !dbg !7 {
+  %9 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %10 = lshr i32 %9, 5, !dbg !10
+  %11 = and i32 %10, 7, !dbg !10
+  %12 = and i32 %9, 15, !dbg !10
+  %13 = shl i32 %9, 3, !dbg !11
+  %14 = and i32 %13, 248, !dbg !11
+  %15 = or i32 %14, 4, !dbg !11
+  %urem = and i32 %9, 255, !dbg !11
+  %16 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #6, !dbg !12
+  %17 = shl i32 %16, 4, !dbg !13
+  %18 = or i32 %17, %11, !dbg !14
+  %19 = or i32 %18, 8, !dbg !14
+  %20 = or i32 %17, %12, !dbg !14
+  %21 = sext i32 %18 to i64, !dbg !15
+  %22 = getelementptr i64, ptr addrspace(1) %0, i64 %21, !dbg !15
+  %23 = sext i32 %19 to i64, !dbg !15
+  %24 = getelementptr i64, ptr addrspace(1) %0, i64 %23, !dbg !15
+  %25 = sext i32 %20 to i64, !dbg !15
+  %26 = getelementptr i64, ptr addrspace(1) %0, i64 %25, !dbg !15
+  %27 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %28 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %29 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %30 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %31 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %32 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %33 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %34 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %22, i1 true) #6, !dbg !16
+  %35 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %36 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %37 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %38 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %39 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %40 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %41 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %42 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %24, i1 true) #6, !dbg !16
+  %43 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %26, i1 true) #6, !dbg !16
+  %44 = srem i32 %18, 512, !dbg !17
+  %45 = srem i32 %19, 512, !dbg !17
+  %46 = shl nsw i32 %44, 8, !dbg !18
+  %47 = shl nsw i32 %45, 8, !dbg !18
+  %48 = or i32 %46, %14, !dbg !19
+  %49 = or i32 %46, %15, !dbg !19
+  %50 = or i32 %47, %14, !dbg !19
+  %51 = or i32 %47, %15, !dbg !19
+  %52 = sext i32 %48 to i64, !dbg !20
+  %53 = getelementptr float, ptr addrspace(1) %2, i64 %52, !dbg !20
+  %54 = sext i32 %49 to i64, !dbg !20
+  %55 = getelementptr float, ptr addrspace(1) %2, i64 %54, !dbg !20
+  %56 = sext i32 %50 to i64, !dbg !20
+  %57 = getelementptr float, ptr addrspace(1) %2, i64 %56, !dbg !20
+  %58 = sext i32 %51 to i64, !dbg !20
+  %59 = getelementptr float, ptr addrspace(1) %2, i64 %58, !dbg !20
+  %60 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %53, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %61 = extractvalue { i32, i32, i32, i32 } %60, 0, !dbg !21
+  %62 = extractvalue { i32, i32, i32, i32 } %60, 1, !dbg !21
+  %63 = extractvalue { i32, i32, i32, i32 } %60, 2, !dbg !21
+  %64 = extractvalue { i32, i32, i32, i32 } %60, 3, !dbg !21
+  %65 = bitcast i32 %61 to float, !dbg !21
+  %66 = bitcast i32 %62 to float, !dbg !21
+  %67 = bitcast i32 %63 to float, !dbg !21
+  %68 = bitcast i32 %64 to float, !dbg !21
+  %69 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %55, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %70 = extractvalue { i32, i32, i32, i32 } %69, 0, !dbg !21
+  %71 = extractvalue { i32, i32, i32, i32 } %69, 1, !dbg !21
+  %72 = extractvalue { i32, i32, i32, i32 } %69, 2, !dbg !21
+  %73 = extractvalue { i32, i32, i32, i32 } %69, 3, !dbg !21
+  %74 = bitcast i32 %70 to float, !dbg !21
+  %75 = bitcast i32 %71 to float, !dbg !21
+  %76 = bitcast i32 %72 to float, !dbg !21
+  %77 = bitcast i32 %73 to float, !dbg !21
+  %78 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %57, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %79 = extractvalue { i32, i32, i32, i32 } %78, 0, !dbg !21
+  %80 = extractvalue { i32, i32, i32, i32 } %78, 1, !dbg !21
+  %81 = extractvalue { i32, i32, i32, i32 } %78, 2, !dbg !21
+  %82 = extractvalue { i32, i32, i32, i32 } %78, 3, !dbg !21
+  %83 = bitcast i32 %79 to float, !dbg !21
+  %84 = bitcast i32 %80 to float, !dbg !21
+  %85 = bitcast i32 %81 to float, !dbg !21
+  %86 = bitcast i32 %82 to float, !dbg !21
+  %87 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %59, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %88 = extractvalue { i32, i32, i32, i32 } %87, 0, !dbg !21
+  %89 = extractvalue { i32, i32, i32, i32 } %87, 1, !dbg !21
+  %90 = extractvalue { i32, i32, i32, i32 } %87, 2, !dbg !21
+  %91 = extractvalue { i32, i32, i32, i32 } %87, 3, !dbg !21
+  %92 = bitcast i32 %88 to float, !dbg !21
+  %93 = bitcast i32 %89 to float, !dbg !21
+  %94 = bitcast i32 %90 to float, !dbg !21
+  %95 = bitcast i32 %91 to float, !dbg !21
+  %96 = shl i32 %18, 8, !dbg !22
+  %97 = shl i32 %19, 8, !dbg !22
+  %98 = or i32 %96, %14, !dbg !23
+  %99 = or i32 %97, %14, !dbg !23
+  %100 = sext i32 %98 to i64, !dbg !24
+  %101 = getelementptr i16, ptr addrspace(1) %3, i64 %100, !dbg !24
+  %102 = sext i32 %99 to i64, !dbg !24
+  %103 = getelementptr i16, ptr addrspace(1) %3, i64 %102, !dbg !24
+  %104 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %101, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !25
+  %105 = extractvalue { i32, i32, i32, i32 } %104, 0, !dbg !25
+  %106 = extractvalue { i32, i32, i32, i32 } %104, 1, !dbg !25
+  %107 = extractvalue { i32, i32, i32, i32 } %104, 2, !dbg !25
+  %108 = extractvalue { i32, i32, i32, i32 } %104, 3, !dbg !25
+  %109 = trunc i32 %105 to i16, !dbg !25
+  %extelt.offset = lshr i32 %105, 16, !dbg !25
+  %110 = trunc i32 %extelt.offset to i16, !dbg !25
+  %111 = trunc i32 %106 to i16, !dbg !25
+  %extelt.offset1 = lshr i32 %106, 16, !dbg !25
+  %112 = trunc i32 %extelt.offset1 to i16, !dbg !25
+  %113 = trunc i32 %107 to i16, !dbg !25
+  %extelt.offset2 = lshr i32 %107, 16, !dbg !25
+  %114 = trunc i32 %extelt.offset2 to i16, !dbg !25
+  %115 = trunc i32 %108 to i16, !dbg !25
+  %extelt.offset3 = lshr i32 %108, 16, !dbg !25
+  %116 = trunc i32 %extelt.offset3 to i16, !dbg !25
+  %117 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %103, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !25
+  %118 = extractvalue { i32, i32, i32, i32 } %117, 0, !dbg !25
+  %119 = extractvalue { i32, i32, i32, i32 } %117, 1, !dbg !25
+  %120 = extractvalue { i32, i32, i32, i32 } %117, 2, !dbg !25
+  %121 = extractvalue { i32, i32, i32, i32 } %117, 3, !dbg !25
+  %122 = trunc i32 %118 to i16, !dbg !25
+  %extelt.offset4 = lshr i32 %118, 16, !dbg !25
+  %123 = trunc i32 %extelt.offset4 to i16, !dbg !25
+  %124 = trunc i32 %119 to i16, !dbg !25
+  %extelt.offset5 = lshr i32 %119, 16, !dbg !25
+  %125 = trunc i32 %extelt.offset5 to i16, !dbg !25
+  %126 = trunc i32 %120 to i16, !dbg !25
+  %extelt.offset6 = lshr i32 %120, 16, !dbg !25
+  %127 = trunc i32 %extelt.offset6 to i16, !dbg !25
+  %128 = trunc i32 %121 to i16, !dbg !25
+  %extelt.offset7 = lshr i32 %121, 16, !dbg !25
+  %129 = trunc i32 %extelt.offset7 to i16, !dbg !25
+  %130 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %109) #6, !dbg !26
+  %131 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %110) #6, !dbg !26
+  %132 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %111) #6, !dbg !26
+  %133 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %112) #6, !dbg !26
+  %134 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %113) #6, !dbg !26
+  %135 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %114) #6, !dbg !26
+  %136 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %115) #6, !dbg !26
+  %137 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %116) #6, !dbg !26
+  %138 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %122) #6, !dbg !26
+  %139 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %123) #6, !dbg !26
+  %140 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %124) #6, !dbg !26
+  %141 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %125) #6, !dbg !26
+  %142 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %126) #6, !dbg !26
+  %143 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %127) #6, !dbg !26
+  %144 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %128) #6, !dbg !26
+  %145 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %129) #6, !dbg !26
+  %146 = add i64 %43, 50257, !dbg !27
+  %147 = icmp slt i64 %27, 0, !dbg !28
+  %148 = icmp slt i64 %35, 0, !dbg !28
+  %149 = icmp slt i64 %43, 0, !dbg !28
+  %150 = select i1 %149, i64 %146, i64 %43, !dbg !29
+  %151 = icmp ugt i64 %150, 50256, !dbg !30
+  br i1 %151, label %152, label %153, !dbg !31
+
+152:                                              ; preds = %8
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !31
+  br label %153, !dbg !31
+
+153:                                              ; preds = %152, %8
+  %154 = shl i64 %27, 8, !dbg !32
+  %155 = add i64 %154, 12865792, !dbg !32
+  %156 = select i1 %147, i64 %155, i64 %154, !dbg !32
+  %157 = shl i64 %35, 8, !dbg !32
+  %158 = add i64 %157, 12865792, !dbg !32
+  %159 = select i1 %148, i64 %158, i64 %157, !dbg !32
+  %160 = zext nneg i32 %14 to i64
+  %161 = zext nneg i32 %15 to i64
+  %162 = or i64 %156, %160, !dbg !33
+  %163 = or i64 %156, %161, !dbg !33
+  %164 = or i64 %159, %160, !dbg !33
+  %165 = or i64 %159, %161, !dbg !33
+  %166 = getelementptr float, ptr addrspace(1) %1, i64 %162, !dbg !34
+  %167 = getelementptr float, ptr addrspace(1) %1, i64 %163, !dbg !34
+  %168 = getelementptr float, ptr addrspace(1) %1, i64 %164, !dbg !34
+  %169 = getelementptr float, ptr addrspace(1) %1, i64 %165, !dbg !34
+  %170 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %166, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !35
+  %171 = extractvalue { i32, i32, i32, i32 } %170, 0, !dbg !35
+  %172 = extractvalue { i32, i32, i32, i32 } %170, 1, !dbg !35
+  %173 = extractvalue { i32, i32, i32, i32 } %170, 2, !dbg !35
+  %174 = extractvalue { i32, i32, i32, i32 } %170, 3, !dbg !35
+  %175 = bitcast i32 %171 to float, !dbg !35
+  %176 = bitcast i32 %172 to float, !dbg !35
+  %177 = bitcast i32 %173 to float, !dbg !35
+  %178 = bitcast i32 %174 to float, !dbg !35
+  %179 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %167, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !35
+  %180 = extractvalue { i32, i32, i32, i32 } %179, 0, !dbg !35
+  %181 = extractvalue { i32, i32, i32, i32 } %179, 1, !dbg !35
+  %182 = extractvalue { i32, i32, i32, i32 } %179, 2, !dbg !35
+  %183 = extractvalue { i32, i32, i32, i32 } %179, 3, !dbg !35
+  %184 = bitcast i32 %180 to float, !dbg !35
+  %185 = bitcast i32 %181 to float, !dbg !35
+  %186 = bitcast i32 %182 to float, !dbg !35
+  %187 = bitcast i32 %183 to float, !dbg !35
+  %188 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %168, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !35
+  %189 = extractvalue { i32, i32, i32, i32 } %188, 0, !dbg !35
+  %190 = extractvalue { i32, i32, i32, i32 } %188, 1, !dbg !35
+  %191 = extractvalue { i32, i32, i32, i32 } %188, 2, !dbg !35
+  %192 = extractvalue { i32, i32, i32, i32 } %188, 3, !dbg !35
+  %193 = bitcast i32 %189 to float, !dbg !35
+  %194 = bitcast i32 %190 to float, !dbg !35
+  %195 = bitcast i32 %191 to float, !dbg !35
+  %196 = bitcast i32 %192 to float, !dbg !35
+  %197 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %169, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !35
+  %198 = extractvalue { i32, i32, i32, i32 } %197, 0, !dbg !35
+  %199 = extractvalue { i32, i32, i32, i32 } %197, 1, !dbg !35
+  %200 = extractvalue { i32, i32, i32, i32 } %197, 2, !dbg !35
+  %201 = extractvalue { i32, i32, i32, i32 } %197, 3, !dbg !35
+  %202 = bitcast i32 %198 to float, !dbg !35
+  %203 = bitcast i32 %199 to float, !dbg !35
+  %204 = bitcast i32 %200 to float, !dbg !35
+  %205 = bitcast i32 %201 to float, !dbg !35
+  %206 = fadd float %65, %175, !dbg !36
+  %207 = fadd float %66, %176, !dbg !36
+  %208 = fadd float %67, %177, !dbg !36
+  %209 = fadd float %68, %178, !dbg !36
+  %210 = fadd float %74, %184, !dbg !36
+  %211 = fadd float %75, %185, !dbg !36
+  %212 = fadd float %76, %186, !dbg !36
+  %213 = fadd float %77, %187, !dbg !36
+  %214 = fadd float %83, %193, !dbg !36
+  %215 = fadd float %84, %194, !dbg !36
+  %216 = fadd float %85, %195, !dbg !36
+  %217 = fadd float %86, %196, !dbg !36
+  %218 = fadd float %92, %202, !dbg !36
+  %219 = fadd float %93, %203, !dbg !36
+  %220 = fadd float %94, %204, !dbg !36
+  %221 = fadd float %95, %205, !dbg !36
+  %222 = fadd float %130, %206, !dbg !37
+  %223 = fadd float %131, %207, !dbg !37
+  %224 = fadd float %132, %208, !dbg !37
+  %225 = fadd float %133, %209, !dbg !37
+  %226 = fadd float %134, %210, !dbg !37
+  %227 = fadd float %135, %211, !dbg !37
+  %228 = fadd float %136, %212, !dbg !37
+  %229 = fadd float %137, %213, !dbg !37
+  %230 = fadd float %138, %214, !dbg !37
+  %231 = fadd float %139, %215, !dbg !37
+  %232 = fadd float %140, %216, !dbg !37
+  %233 = fadd float %141, %217, !dbg !37
+  %234 = fadd float %142, %218, !dbg !37
+  %235 = fadd float %143, %219, !dbg !37
+  %236 = fadd float %144, %220, !dbg !37
+  %237 = fadd float %145, %221, !dbg !37
+  %238 = fadd float %222, 0.000000e+00, !dbg !38
+  %239 = fadd float %223, 0.000000e+00, !dbg !38
+  %240 = fadd float %224, 0.000000e+00, !dbg !38
+  %241 = fadd float %225, 0.000000e+00, !dbg !38
+  %242 = fadd float %226, 0.000000e+00, !dbg !38
+  %243 = fadd float %227, 0.000000e+00, !dbg !38
+  %244 = fadd float %228, 0.000000e+00, !dbg !38
+  %245 = fadd float %229, 0.000000e+00, !dbg !38
+  %246 = fadd float %230, 0.000000e+00, !dbg !38
+  %247 = fadd float %231, 0.000000e+00, !dbg !38
+  %248 = fadd float %232, 0.000000e+00, !dbg !38
+  %249 = fadd float %233, 0.000000e+00, !dbg !38
+  %250 = fadd float %234, 0.000000e+00, !dbg !38
+  %251 = fadd float %235, 0.000000e+00, !dbg !38
+  %252 = fadd float %236, 0.000000e+00, !dbg !38
+  %253 = fadd float %237, 0.000000e+00, !dbg !38
+  %254 = fsub float %222, %238, !dbg !42
+  %255 = fsub float %223, %239, !dbg !42
+  %256 = fsub float %224, %240, !dbg !42
+  %257 = fsub float %225, %241, !dbg !42
+  %258 = fsub float %226, %242, !dbg !42
+  %259 = fsub float %227, %243, !dbg !42
+  %260 = fsub float %228, %244, !dbg !42
+  %261 = fsub float %229, %245, !dbg !42
+  %262 = fsub float %230, %246, !dbg !42
+  %263 = fsub float %231, %247, !dbg !42
+  %264 = fsub float %232, %248, !dbg !42
+  %265 = fsub float %233, %249, !dbg !42
+  %266 = fsub float %234, %250, !dbg !42
+  %267 = fsub float %235, %251, !dbg !42
+  %268 = fsub float %236, %252, !dbg !42
+  %269 = fsub float %237, %253, !dbg !42
+  %270 = fmul float %222, %254, !dbg !43
+  %271 = fmul float %223, %255, !dbg !43
+  %272 = fmul float %224, %256, !dbg !43
+  %273 = fmul float %225, %257, !dbg !43
+  %274 = fmul float %226, %258, !dbg !43
+  %275 = fmul float %227, %259, !dbg !43
+  %276 = fmul float %228, %260, !dbg !43
+  %277 = fmul float %229, %261, !dbg !43
+  %278 = fmul float %230, %262, !dbg !43
+  %279 = fmul float %231, %263, !dbg !43
+  %280 = fmul float %232, %264, !dbg !43
+  %281 = fmul float %233, %265, !dbg !43
+  %282 = fmul float %234, %266, !dbg !43
+  %283 = fmul float %235, %267, !dbg !43
+  %284 = fmul float %236, %268, !dbg !43
+  %285 = fmul float %237, %269, !dbg !43
+  %286 = fadd float %270, 0.000000e+00, !dbg !44
+  %287 = fadd float %271, 0.000000e+00, !dbg !44
+  %288 = fadd float %272, 0.000000e+00, !dbg !44
+  %289 = fadd float %273, 0.000000e+00, !dbg !44
+  %290 = fadd float %274, 0.000000e+00, !dbg !44
+  %291 = fadd float %275, 0.000000e+00, !dbg !44
+  %292 = fadd float %276, 0.000000e+00, !dbg !44
+  %293 = fadd float %277, 0.000000e+00, !dbg !44
+  %294 = fadd float %278, 0.000000e+00, !dbg !44
+  %295 = fadd float %279, 0.000000e+00, !dbg !44
+  %296 = fadd float %280, 0.000000e+00, !dbg !44
+  %297 = fadd float %281, 0.000000e+00, !dbg !44
+  %298 = fadd float %282, 0.000000e+00, !dbg !44
+  %299 = fadd float %283, 0.000000e+00, !dbg !44
+  %300 = fadd float %284, 0.000000e+00, !dbg !44
+  %301 = fadd float %285, 0.000000e+00, !dbg !44
+  %302 = fsub float %239, %238, !dbg !45
+  %303 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 2.000000e+00) #6, !dbg !49
+  %304 = fmul float %303, %302, !dbg !50
+  %305 = fadd float %238, %304, !dbg !51
+  %306 = fadd float %286, %287, !dbg !52
+  %307 = fmul float %302, %302, !dbg !53
+  %308 = fmul float %303, %307, !dbg !54
+  %309 = fadd float %308, %306, !dbg !55
+  %310 = fsub float %240, %305, !dbg !45
+  %311 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 3.000000e+00) #6, !dbg !49
+  %312 = fmul float %311, %310, !dbg !50
+  %313 = fadd float %305, %312, !dbg !51
+  %314 = fadd float %288, %309, !dbg !52
+  %315 = fmul float %310, %310, !dbg !53
+  %316 = fmul float %315, 2.000000e+00, !dbg !56
+  %317 = fmul float %311, %316, !dbg !54
+  %318 = fadd float %314, %317, !dbg !55
+  %319 = fsub float %241, %313, !dbg !45
+  %320 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 4.000000e+00) #6, !dbg !49
+  %321 = fmul float %320, %319, !dbg !50
+  %322 = fadd float %313, %321, !dbg !51
+  %323 = fadd float %289, %318, !dbg !52
+  %324 = fmul float %319, %319, !dbg !53
+  %325 = fmul float %324, 3.000000e+00, !dbg !56
+  %326 = fmul float %320, %325, !dbg !54
+  %327 = fadd float %323, %326, !dbg !55
+  %328 = fsub float %242, %322, !dbg !45
+  %329 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 5.000000e+00) #6, !dbg !49
+  %330 = fmul float %329, %328, !dbg !50
+  %331 = fadd float %322, %330, !dbg !51
+  %332 = fadd float %290, %327, !dbg !52
+  %333 = fmul float %328, %328, !dbg !53
+  %334 = fmul float %333, 4.000000e+00, !dbg !56
+  %335 = fmul float %329, %334, !dbg !54
+  %336 = fadd float %332, %335, !dbg !55
+  %337 = fsub float %243, %331, !dbg !45
+  %338 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 6.000000e+00) #6, !dbg !49
+  %339 = fmul float %338, %337, !dbg !50
+  %340 = fadd float %331, %339, !dbg !51
+  %341 = fadd float %291, %336, !dbg !52
+  %342 = fmul float %337, %337, !dbg !53
+  %343 = fmul float %342, 5.000000e+00, !dbg !56
+  %344 = fmul float %338, %343, !dbg !54
+  %345 = fadd float %341, %344, !dbg !55
+  %346 = fsub float %244, %340, !dbg !45
+  %347 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 7.000000e+00) #6, !dbg !49
+  %348 = fmul float %347, %346, !dbg !50
+  %349 = fadd float %340, %348, !dbg !51
+  %350 = fadd float %292, %345, !dbg !52
+  %351 = fmul float %346, %346, !dbg !53
+  %352 = fmul float %351, 6.000000e+00, !dbg !56
+  %353 = fmul float %347, %352, !dbg !54
+  %354 = fadd float %350, %353, !dbg !55
+  %355 = fsub float %245, %349, !dbg !45
+  %356 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 8.000000e+00) #6, !dbg !49
+  %357 = fmul float %356, %355, !dbg !50
+  %358 = fadd float %349, %357, !dbg !51
+  %359 = fadd float %293, %354, !dbg !52
+  %360 = fmul float %355, %355, !dbg !53
+  %361 = fmul float %360, 7.000000e+00, !dbg !56
+  %362 = fmul float %356, %361, !dbg !54
+  %363 = fadd float %359, %362, !dbg !55
+  %364 = fsub float %247, %246, !dbg !45
+  %365 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 2.000000e+00) #6, !dbg !49
+  %366 = fmul float %364, %365, !dbg !50
+  %367 = fadd float %246, %366, !dbg !51
+  %368 = fadd float %294, %295, !dbg !52
+  %369 = fmul float %364, %364, !dbg !53
+  %370 = fmul float %369, %365, !dbg !54
+  %371 = fadd float %368, %370, !dbg !55
+  %372 = fsub float %248, %367, !dbg !45
+  %373 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 3.000000e+00) #6, !dbg !49
+  %374 = fmul float %373, %372, !dbg !50
+  %375 = fadd float %367, %374, !dbg !51
+  %376 = fadd float %296, %371, !dbg !52
+  %377 = fmul float %372, %372, !dbg !53
+  %378 = fmul float %377, 2.000000e+00, !dbg !56
+  %379 = fmul float %373, %378, !dbg !54
+  %380 = fadd float %376, %379, !dbg !55
+  %381 = fsub float %249, %375, !dbg !45
+  %382 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 4.000000e+00) #6, !dbg !49
+  %383 = fmul float %382, %381, !dbg !50
+  %384 = fadd float %375, %383, !dbg !51
+  %385 = fadd float %297, %380, !dbg !52
+  %386 = fmul float %381, %381, !dbg !53
+  %387 = fmul float %386, 3.000000e+00, !dbg !56
+  %388 = fmul float %382, %387, !dbg !54
+  %389 = fadd float %385, %388, !dbg !55
+  %390 = fsub float %250, %384, !dbg !45
+  %391 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 5.000000e+00) #6, !dbg !49
+  %392 = fmul float %391, %390, !dbg !50
+  %393 = fadd float %384, %392, !dbg !51
+  %394 = fadd float %298, %389, !dbg !52
+  %395 = fmul float %390, %390, !dbg !53
+  %396 = fmul float %395, 4.000000e+00, !dbg !56
+  %397 = fmul float %391, %396, !dbg !54
+  %398 = fadd float %394, %397, !dbg !55
+  %399 = fsub float %251, %393, !dbg !45
+  %400 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 6.000000e+00) #6, !dbg !49
+  %401 = fmul float %400, %399, !dbg !50
+  %402 = fadd float %393, %401, !dbg !51
+  %403 = fadd float %299, %398, !dbg !52
+  %404 = fmul float %399, %399, !dbg !53
+  %405 = fmul float %404, 5.000000e+00, !dbg !56
+  %406 = fmul float %400, %405, !dbg !54
+  %407 = fadd float %403, %406, !dbg !55
+  %408 = fsub float %252, %402, !dbg !45
+  %409 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 7.000000e+00) #6, !dbg !49
+  %410 = fmul float %409, %408, !dbg !50
+  %411 = fadd float %402, %410, !dbg !51
+  %412 = fadd float %300, %407, !dbg !52
+  %413 = fmul float %408, %408, !dbg !53
+  %414 = fmul float %413, 6.000000e+00, !dbg !56
+  %415 = fmul float %409, %414, !dbg !54
+  %416 = fadd float %412, %415, !dbg !55
+  %417 = fsub float %253, %411, !dbg !45
+  %418 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 8.000000e+00) #6, !dbg !49
+  %419 = fmul float %418, %417, !dbg !50
+  %420 = fadd float %411, %419, !dbg !51
+  %421 = fadd float %301, %416, !dbg !52
+  %422 = fmul float %417, %417, !dbg !53
+  %423 = fmul float %422, 7.000000e+00, !dbg !56
+  %424 = fmul float %418, %423, !dbg !54
+  %425 = fadd float %421, %424, !dbg !55
+  %426 = bitcast float %358 to i32, !dbg !57
+  %427 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %426, i32 16, i32 31), !dbg !57
+  %428 = bitcast i32 %427 to float, !dbg !57
+  %429 = bitcast float %363 to i32, !dbg !57
+  %430 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %429, i32 16, i32 31), !dbg !57
+  %431 = bitcast i32 %430 to float, !dbg !57
+  %432 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 1090519040, i32 16, i32 31), !dbg !57
+  %433 = bitcast i32 %432 to float, !dbg !57
+  %434 = fsub float %428, %358, !dbg !45
+  %435 = fadd float %433, 8.000000e+00, !dbg !59
+  %436 = fcmp oeq float %435, 0.000000e+00, !dbg !60
+  %437 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %433, float %435) #6, !dbg !49
+  %438 = select i1 %436, float 0.000000e+00, float %437, !dbg !61
+  %439 = fmul float %438, %434, !dbg !50
+  %440 = fadd float %358, %439, !dbg !51
+  %441 = fadd float %363, %431, !dbg !52
+  %442 = fmul float %434, %434, !dbg !53
+  %443 = fmul float %442, 8.000000e+00, !dbg !56
+  %444 = fmul float %438, %443, !dbg !54
+  %445 = fadd float %441, %444, !dbg !55
+  %446 = bitcast float %440 to i32, !dbg !57
+  %447 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %446, i32 8, i32 31), !dbg !57
+  %448 = bitcast i32 %447 to float, !dbg !57
+  %449 = bitcast float %445 to i32, !dbg !57
+  %450 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %449, i32 8, i32 31), !dbg !57
+  %451 = bitcast i32 %450 to float, !dbg !57
+  %452 = bitcast float %435 to i32, !dbg !57
+  %453 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %452, i32 8, i32 31), !dbg !57
+  %454 = bitcast i32 %453 to float, !dbg !57
+  %455 = fsub float %448, %440, !dbg !45
+  %456 = fadd float %435, %454, !dbg !59
+  %457 = fcmp oeq float %456, 0.000000e+00, !dbg !60
+  %458 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %454, float %456) #6, !dbg !49
+  %459 = select i1 %457, float 0.000000e+00, float %458, !dbg !61
+  %460 = fmul float %459, %455, !dbg !50
+  %461 = fadd float %440, %460, !dbg !51
+  %462 = fadd float %445, %451, !dbg !52
+  %463 = fmul float %455, %455, !dbg !53
+  %464 = fmul float %435, %463, !dbg !56
+  %465 = fmul float %459, %464, !dbg !54
+  %466 = fadd float %462, %465, !dbg !55
+  %467 = bitcast float %461 to i32, !dbg !57
+  %468 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %467, i32 4, i32 31), !dbg !57
+  %469 = bitcast i32 %468 to float, !dbg !57
+  %470 = bitcast float %466 to i32, !dbg !57
+  %471 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %470, i32 4, i32 31), !dbg !57
+  %472 = bitcast i32 %471 to float, !dbg !57
+  %473 = bitcast float %456 to i32, !dbg !57
+  %474 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %473, i32 4, i32 31), !dbg !57
+  %475 = bitcast i32 %474 to float, !dbg !57
+  %476 = fsub float %469, %461, !dbg !45
+  %477 = fadd float %456, %475, !dbg !59
+  %478 = fcmp oeq float %477, 0.000000e+00, !dbg !60
+  %479 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %475, float %477) #6, !dbg !49
+  %480 = select i1 %478, float 0.000000e+00, float %479, !dbg !61
+  %481 = fmul float %480, %476, !dbg !50
+  %482 = fadd float %461, %481, !dbg !51
+  %483 = fadd float %466, %472, !dbg !52
+  %484 = fmul float %476, %476, !dbg !53
+  %485 = fmul float %456, %484, !dbg !56
+  %486 = fmul float %480, %485, !dbg !54
+  %487 = fadd float %483, %486, !dbg !55
+  %488 = bitcast float %482 to i32, !dbg !57
+  %489 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %488, i32 2, i32 31), !dbg !57
+  %490 = bitcast i32 %489 to float, !dbg !57
+  %491 = bitcast float %487 to i32, !dbg !57
+  %492 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %491, i32 2, i32 31), !dbg !57
+  %493 = bitcast i32 %492 to float, !dbg !57
+  %494 = bitcast float %477 to i32, !dbg !57
+  %495 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %494, i32 2, i32 31), !dbg !57
+  %496 = bitcast i32 %495 to float, !dbg !57
+  %497 = fsub float %490, %482, !dbg !45
+  %498 = fadd float %477, %496, !dbg !59
+  %499 = fcmp oeq float %498, 0.000000e+00, !dbg !60
+  %500 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %496, float %498) #6, !dbg !49
+  %501 = select i1 %499, float 0.000000e+00, float %500, !dbg !61
+  %502 = fmul float %497, %501, !dbg !50
+  %503 = fadd float %482, %502, !dbg !51
+  %504 = fadd float %487, %493, !dbg !52
+  %505 = fmul float %497, %497, !dbg !53
+  %506 = fmul float %477, %505, !dbg !56
+  %507 = fmul float %501, %506, !dbg !54
+  %508 = fadd float %504, %507, !dbg !55
+  %509 = bitcast float %503 to i32, !dbg !57
+  %510 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %509, i32 1, i32 31), !dbg !57
+  %511 = bitcast float %508 to i32, !dbg !57
+  %512 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %511, i32 1, i32 31), !dbg !57
+  %513 = bitcast float %498 to i32, !dbg !57
+  %514 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %513, i32 1, i32 31), !dbg !57
+  %515 = bitcast i32 %514 to float, !dbg !57
+  %516 = fadd float %498, %515, !dbg !59
+  %517 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %515, float %516) #6, !dbg !49
+  %518 = bitcast float %420 to i32, !dbg !57
+  %519 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %518, i32 16, i32 31), !dbg !57
+  %520 = bitcast i32 %519 to float, !dbg !57
+  %521 = bitcast float %425 to i32, !dbg !57
+  %522 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %521, i32 16, i32 31), !dbg !57
+  %523 = bitcast i32 %522 to float, !dbg !57
+  %524 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 1090519040, i32 16, i32 31), !dbg !57
+  %525 = bitcast i32 %524 to float, !dbg !57
+  %526 = fsub float %520, %420, !dbg !45
+  %527 = fadd float %525, 8.000000e+00, !dbg !59
+  %528 = fcmp oeq float %527, 0.000000e+00, !dbg !60
+  %529 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %525, float %527) #6, !dbg !49
+  %530 = select i1 %528, float 0.000000e+00, float %529, !dbg !61
+  %531 = fmul float %526, %530, !dbg !50
+  %532 = fadd float %420, %531, !dbg !51
+  %533 = fadd float %425, %523, !dbg !52
+  %534 = fmul float %526, %526, !dbg !53
+  %535 = fmul float %534, 8.000000e+00, !dbg !56
+  %536 = fmul float %535, %530, !dbg !54
+  %537 = fadd float %533, %536, !dbg !55
+  %538 = bitcast float %532 to i32, !dbg !57
+  %539 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %538, i32 8, i32 31), !dbg !57
+  %540 = bitcast i32 %539 to float, !dbg !57
+  %541 = bitcast float %537 to i32, !dbg !57
+  %542 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %541, i32 8, i32 31), !dbg !57
+  %543 = bitcast i32 %542 to float, !dbg !57
+  %544 = bitcast float %527 to i32, !dbg !57
+  %545 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %544, i32 8, i32 31), !dbg !57
+  %546 = bitcast i32 %545 to float, !dbg !57
+  %547 = fsub float %540, %532, !dbg !45
+  %548 = fadd float %527, %546, !dbg !59
+  %549 = fcmp oeq float %548, 0.000000e+00, !dbg !60
+  %550 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %546, float %548) #6, !dbg !49
+  %551 = select i1 %549, float 0.000000e+00, float %550, !dbg !61
+  %552 = fmul float %547, %551, !dbg !50
+  %553 = fadd float %532, %552, !dbg !51
+  %554 = fadd float %537, %543, !dbg !52
+  %555 = fmul float %547, %547, !dbg !53
+  %556 = fmul float %527, %555, !dbg !56
+  %557 = fmul float %551, %556, !dbg !54
+  %558 = fadd float %554, %557, !dbg !55
+  %559 = bitcast float %553 to i32, !dbg !57
+  %560 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %559, i32 4, i32 31), !dbg !57
+  %561 = bitcast i32 %560 to float, !dbg !57
+  %562 = bitcast float %558 to i32, !dbg !57
+  %563 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %562, i32 4, i32 31), !dbg !57
+  %564 = bitcast i32 %563 to float, !dbg !57
+  %565 = bitcast float %548 to i32, !dbg !57
+  %566 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %565, i32 4, i32 31), !dbg !57
+  %567 = bitcast i32 %566 to float, !dbg !57
+  %568 = fsub float %561, %553, !dbg !45
+  %569 = fadd float %548, %567, !dbg !59
+  %570 = fcmp oeq float %569, 0.000000e+00, !dbg !60
+  %571 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %567, float %569) #6, !dbg !49
+  %572 = select i1 %570, float 0.000000e+00, float %571, !dbg !61
+  %573 = fmul float %568, %572, !dbg !50
+  %574 = fadd float %553, %573, !dbg !51
+  %575 = fadd float %558, %564, !dbg !52
+  %576 = fmul float %568, %568, !dbg !53
+  %577 = fmul float %548, %576, !dbg !56
+  %578 = fmul float %572, %577, !dbg !54
+  %579 = fadd float %575, %578, !dbg !55
+  %580 = bitcast float %574 to i32, !dbg !57
+  %581 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %580, i32 2, i32 31), !dbg !57
+  %582 = bitcast i32 %581 to float, !dbg !57
+  %583 = bitcast float %579 to i32, !dbg !57
+  %584 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %583, i32 2, i32 31), !dbg !57
+  %585 = bitcast i32 %584 to float, !dbg !57
+  %586 = bitcast float %569 to i32, !dbg !57
+  %587 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %586, i32 2, i32 31), !dbg !57
+  %588 = bitcast i32 %587 to float, !dbg !57
+  %589 = fsub float %582, %574, !dbg !45
+  %590 = fadd float %569, %588, !dbg !59
+  %591 = fcmp oeq float %590, 0.000000e+00, !dbg !60
+  %592 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %588, float %590) #6, !dbg !49
+  %593 = select i1 %591, float 0.000000e+00, float %592, !dbg !61
+  %594 = fmul float %589, %593, !dbg !50
+  %595 = fadd float %574, %594, !dbg !51
+  %596 = fadd float %579, %585, !dbg !52
+  %597 = fmul float %589, %589, !dbg !53
+  %598 = fmul float %569, %597, !dbg !56
+  %599 = fmul float %593, %598, !dbg !54
+  %600 = fadd float %596, %599, !dbg !55
+  %601 = bitcast float %595 to i32, !dbg !57
+  %602 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %601, i32 1, i32 31), !dbg !57
+  %603 = bitcast float %600 to i32, !dbg !57
+  %604 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %603, i32 1, i32 31), !dbg !57
+  %605 = bitcast float %590 to i32, !dbg !57
+  %606 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %605, i32 1, i32 31), !dbg !57
+  %607 = bitcast i32 %606 to float, !dbg !57
+  %608 = fadd float %590, %607, !dbg !59
+  %609 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %607, float %608) #6, !dbg !49
+  %610 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %53, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !62
+  %611 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %55, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !62
+  %612 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %57, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !62
+  %613 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %59, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !62
+  %614 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %101, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !63
+  %615 = extractvalue { i32, i32, i32, i32 } %614, 0, !dbg !63
+  %616 = extractvalue { i32, i32, i32, i32 } %614, 1, !dbg !63
+  %617 = extractvalue { i32, i32, i32, i32 } %614, 2, !dbg !63
+  %618 = extractvalue { i32, i32, i32, i32 } %614, 3, !dbg !63
+  %619 = trunc i32 %615 to i16, !dbg !63
+  %extelt.offset8 = lshr i32 %615, 16, !dbg !63
+  %620 = trunc i32 %extelt.offset8 to i16, !dbg !63
+  %621 = trunc i32 %616 to i16, !dbg !63
+  %extelt.offset9 = lshr i32 %616, 16, !dbg !63
+  %622 = trunc i32 %extelt.offset9 to i16, !dbg !63
+  %623 = trunc i32 %617 to i16, !dbg !63
+  %extelt.offset10 = lshr i32 %617, 16, !dbg !63
+  %624 = trunc i32 %extelt.offset10 to i16, !dbg !63
+  %625 = trunc i32 %618 to i16, !dbg !63
+  %extelt.offset11 = lshr i32 %618, 16, !dbg !63
+  %626 = trunc i32 %extelt.offset11 to i16, !dbg !63
+  %627 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %103, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !63
+  %628 = extractvalue { i32, i32, i32, i32 } %627, 0, !dbg !63
+  %629 = extractvalue { i32, i32, i32, i32 } %627, 1, !dbg !63
+  %630 = extractvalue { i32, i32, i32, i32 } %627, 2, !dbg !63
+  %631 = extractvalue { i32, i32, i32, i32 } %627, 3, !dbg !63
+  %632 = trunc i32 %628 to i16, !dbg !63
+  %extelt.offset12 = lshr i32 %628, 16, !dbg !63
+  %633 = trunc i32 %extelt.offset12 to i16, !dbg !63
+  %634 = trunc i32 %629 to i16, !dbg !63
+  %extelt.offset13 = lshr i32 %629, 16, !dbg !63
+  %635 = trunc i32 %extelt.offset13 to i16, !dbg !63
+  %636 = trunc i32 %630 to i16, !dbg !63
+  %extelt.offset14 = lshr i32 %630, 16, !dbg !63
+  %637 = trunc i32 %extelt.offset14 to i16, !dbg !63
+  %638 = trunc i32 %631 to i16, !dbg !63
+  %extelt.offset15 = lshr i32 %631, 16, !dbg !63
+  %639 = trunc i32 %extelt.offset15 to i16, !dbg !63
+  %640 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %619) #6, !dbg !64
+  %641 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %620) #6, !dbg !64
+  %642 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %621) #6, !dbg !64
+  %643 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %622) #6, !dbg !64
+  %644 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %623) #6, !dbg !64
+  %645 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %624) #6, !dbg !64
+  %646 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %625) #6, !dbg !64
+  %647 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %626) #6, !dbg !64
+  %648 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %632) #6, !dbg !64
+  %649 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %633) #6, !dbg !64
+  %650 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %634) #6, !dbg !64
+  %651 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %635) #6, !dbg !64
+  %652 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %636) #6, !dbg !64
+  %653 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %637) #6, !dbg !64
+  %654 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %638) #6, !dbg !64
+  %655 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %639) #6, !dbg !64
+  %656 = zext nneg i32 %urem to i64, !dbg !65
+  %657 = getelementptr float, ptr addrspace(1) %4, i64 %656, !dbg !65
+  %658 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %657, i1 true, i32 0, i1 true) #6, !dbg !66
+  br i1 %151, label %659, label %660, !dbg !67
+
+659:                                              ; preds = %153
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 883, ptr nonnull @assertFunc_1, i64 1), !dbg !67
+  br label %660, !dbg !67
+
+660:                                              ; preds = %659, %153
+  %661 = bitcast i32 %604 to float, !dbg !57
+  %662 = fadd float %600, %661, !dbg !52
+  %663 = bitcast i32 %602 to float, !dbg !57
+  %664 = fsub float %663, %595, !dbg !45
+  %665 = fmul float %664, %664, !dbg !53
+  %666 = fmul float %590, %665, !dbg !56
+  %667 = fcmp oeq float %608, 0.000000e+00, !dbg !60
+  %668 = select i1 %667, float 0.000000e+00, float %609, !dbg !61
+  %669 = fmul float %668, %666, !dbg !54
+  %670 = fadd float %662, %669, !dbg !55
+  %671 = bitcast i32 %512 to float, !dbg !57
+  %672 = fadd float %508, %671, !dbg !52
+  %673 = bitcast i32 %510 to float, !dbg !57
+  %674 = fsub float %673, %503, !dbg !45
+  %675 = fmul float %674, %674, !dbg !53
+  %676 = fmul float %498, %675, !dbg !56
+  %677 = fcmp oeq float %516, 0.000000e+00, !dbg !60
+  %678 = select i1 %677, float 0.000000e+00, float %517, !dbg !61
+  %679 = fmul float %678, %676, !dbg !54
+  %680 = fadd float %672, %679, !dbg !55
+  %681 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %166, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !68
+  %682 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %167, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !68
+  %683 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %168, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !68
+  %684 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %169, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !68
+  %685 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %686 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %687 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %688 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %689 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %690 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %691 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %692 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %680, float 2.560000e+02) #6, !dbg !69
+  %693 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %694 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %695 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %696 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %697 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %698 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %699 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %700 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %670, float 2.560000e+02) #6, !dbg !69
+  %701 = fadd float %685, 0x3EE4F8B580000000, !dbg !70
+  %702 = fadd float %693, 0x3EE4F8B580000000, !dbg !70
+  %703 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %.not.i = icmp eq i32 %703, 0, !dbg !71
+  br i1 %.not.i, label %706, label %704, !dbg !71
+
+704:                                              ; preds = %660
+  %705 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %701), !dbg !71
+  br label %__nv_rsqrtf.exit, !dbg !71
+
+706:                                              ; preds = %660
+  %707 = tail call float @llvm.nvvm.rsqrt.approx.f(float %701), !dbg !71
+  br label %__nv_rsqrtf.exit, !dbg !71
+
+__nv_rsqrtf.exit:                                 ; preds = %704, %706
+  %.0.i = phi float [ %705, %704 ], [ %707, %706 ], !dbg !71
+  %708 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %709 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %710 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %711 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %712 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %713 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %714 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %715 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %.not.i37 = icmp eq i32 %715, 0, !dbg !71
+  br i1 %.not.i37, label %718, label %716, !dbg !71
+
+716:                                              ; preds = %__nv_rsqrtf.exit
+  %717 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %702), !dbg !71
+  br label %__nv_rsqrtf.exit39, !dbg !71
+
+718:                                              ; preds = %__nv_rsqrtf.exit
+  %719 = tail call float @llvm.nvvm.rsqrt.approx.f(float %702), !dbg !71
+  br label %__nv_rsqrtf.exit39, !dbg !71
+
+__nv_rsqrtf.exit39:                               ; preds = %716, %718
+  %.0.i38 = phi float [ %717, %716 ], [ %719, %718 ], !dbg !71
+  %720 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %721 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %722 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %723 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %724 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %725 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %726 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !71
+  %727 = extractvalue { i32, i32, i32, i32 } %684, 3, !dbg !68
+  %728 = bitcast i32 %727 to float, !dbg !68
+  %729 = extractvalue { i32, i32, i32, i32 } %613, 3, !dbg !62
+  %730 = bitcast i32 %729 to float, !dbg !62
+  %731 = fadd float %730, %728, !dbg !72
+  %732 = fadd float %655, %731, !dbg !73
+  %733 = fmul float %664, %668, !dbg !50
+  %734 = fadd float %595, %733, !dbg !51
+  %735 = fsub float %732, %734, !dbg !74
+  %736 = extractvalue { i32, i32, i32, i32 } %684, 2, !dbg !68
+  %737 = bitcast i32 %736 to float, !dbg !68
+  %738 = extractvalue { i32, i32, i32, i32 } %613, 2, !dbg !62
+  %739 = bitcast i32 %738 to float, !dbg !62
+  %740 = fadd float %739, %737, !dbg !72
+  %741 = fadd float %654, %740, !dbg !73
+  %742 = fsub float %741, %734, !dbg !74
+  %743 = extractvalue { i32, i32, i32, i32 } %684, 1, !dbg !68
+  %744 = bitcast i32 %743 to float, !dbg !68
+  %745 = extractvalue { i32, i32, i32, i32 } %613, 1, !dbg !62
+  %746 = bitcast i32 %745 to float, !dbg !62
+  %747 = fadd float %746, %744, !dbg !72
+  %748 = fadd float %653, %747, !dbg !73
+  %749 = fsub float %748, %734, !dbg !74
+  %750 = extractvalue { i32, i32, i32, i32 } %684, 0, !dbg !68
+  %751 = bitcast i32 %750 to float, !dbg !68
+  %752 = extractvalue { i32, i32, i32, i32 } %613, 0, !dbg !62
+  %753 = bitcast i32 %752 to float, !dbg !62
+  %754 = fadd float %753, %751, !dbg !72
+  %755 = fadd float %652, %754, !dbg !73
+  %756 = fsub float %755, %734, !dbg !74
+  %757 = extractvalue { i32, i32, i32, i32 } %683, 3, !dbg !68
+  %758 = bitcast i32 %757 to float, !dbg !68
+  %759 = extractvalue { i32, i32, i32, i32 } %612, 3, !dbg !62
+  %760 = bitcast i32 %759 to float, !dbg !62
+  %761 = fadd float %760, %758, !dbg !72
+  %762 = fadd float %651, %761, !dbg !73
+  %763 = fsub float %762, %734, !dbg !74
+  %764 = extractvalue { i32, i32, i32, i32 } %683, 2, !dbg !68
+  %765 = bitcast i32 %764 to float, !dbg !68
+  %766 = extractvalue { i32, i32, i32, i32 } %612, 2, !dbg !62
+  %767 = bitcast i32 %766 to float, !dbg !62
+  %768 = fadd float %767, %765, !dbg !72
+  %769 = fadd float %650, %768, !dbg !73
+  %770 = fsub float %769, %734, !dbg !74
+  %771 = extractvalue { i32, i32, i32, i32 } %683, 1, !dbg !68
+  %772 = bitcast i32 %771 to float, !dbg !68
+  %773 = extractvalue { i32, i32, i32, i32 } %612, 1, !dbg !62
+  %774 = bitcast i32 %773 to float, !dbg !62
+  %775 = fadd float %774, %772, !dbg !72
+  %776 = fadd float %649, %775, !dbg !73
+  %777 = fsub float %776, %734, !dbg !74
+  %778 = extractvalue { i32, i32, i32, i32 } %683, 0, !dbg !68
+  %779 = bitcast i32 %778 to float, !dbg !68
+  %780 = extractvalue { i32, i32, i32, i32 } %612, 0, !dbg !62
+  %781 = bitcast i32 %780 to float, !dbg !62
+  %782 = fadd float %781, %779, !dbg !72
+  %783 = fadd float %648, %782, !dbg !73
+  %784 = fsub float %783, %734, !dbg !74
+  %785 = extractvalue { i32, i32, i32, i32 } %682, 3, !dbg !68
+  %786 = bitcast i32 %785 to float, !dbg !68
+  %787 = extractvalue { i32, i32, i32, i32 } %611, 3, !dbg !62
+  %788 = bitcast i32 %787 to float, !dbg !62
+  %789 = fadd float %788, %786, !dbg !72
+  %790 = fadd float %647, %789, !dbg !73
+  %791 = fmul float %674, %678, !dbg !50
+  %792 = fadd float %503, %791, !dbg !51
+  %793 = fsub float %790, %792, !dbg !74
+  %794 = extractvalue { i32, i32, i32, i32 } %682, 2, !dbg !68
+  %795 = bitcast i32 %794 to float, !dbg !68
+  %796 = extractvalue { i32, i32, i32, i32 } %611, 2, !dbg !62
+  %797 = bitcast i32 %796 to float, !dbg !62
+  %798 = fadd float %797, %795, !dbg !72
+  %799 = fadd float %646, %798, !dbg !73
+  %800 = fsub float %799, %792, !dbg !74
+  %801 = extractvalue { i32, i32, i32, i32 } %682, 1, !dbg !68
+  %802 = bitcast i32 %801 to float, !dbg !68
+  %803 = extractvalue { i32, i32, i32, i32 } %611, 1, !dbg !62
+  %804 = bitcast i32 %803 to float, !dbg !62
+  %805 = fadd float %804, %802, !dbg !72
+  %806 = fadd float %645, %805, !dbg !73
+  %807 = fsub float %806, %792, !dbg !74
+  %808 = extractvalue { i32, i32, i32, i32 } %682, 0, !dbg !68
+  %809 = bitcast i32 %808 to float, !dbg !68
+  %810 = extractvalue { i32, i32, i32, i32 } %611, 0, !dbg !62
+  %811 = bitcast i32 %810 to float, !dbg !62
+  %812 = fadd float %811, %809, !dbg !72
+  %813 = fadd float %644, %812, !dbg !73
+  %814 = fsub float %813, %792, !dbg !74
+  %815 = extractvalue { i32, i32, i32, i32 } %681, 3, !dbg !68
+  %816 = bitcast i32 %815 to float, !dbg !68
+  %817 = extractvalue { i32, i32, i32, i32 } %610, 3, !dbg !62
+  %818 = bitcast i32 %817 to float, !dbg !62
+  %819 = fadd float %818, %816, !dbg !72
+  %820 = fadd float %643, %819, !dbg !73
+  %821 = fsub float %820, %792, !dbg !74
+  %822 = extractvalue { i32, i32, i32, i32 } %681, 2, !dbg !68
+  %823 = bitcast i32 %822 to float, !dbg !68
+  %824 = extractvalue { i32, i32, i32, i32 } %610, 2, !dbg !62
+  %825 = bitcast i32 %824 to float, !dbg !62
+  %826 = fadd float %825, %823, !dbg !72
+  %827 = fadd float %642, %826, !dbg !73
+  %828 = fsub float %827, %792, !dbg !74
+  %829 = extractvalue { i32, i32, i32, i32 } %681, 1, !dbg !68
+  %830 = bitcast i32 %829 to float, !dbg !68
+  %831 = extractvalue { i32, i32, i32, i32 } %610, 1, !dbg !62
+  %832 = bitcast i32 %831 to float, !dbg !62
+  %833 = fadd float %832, %830, !dbg !72
+  %834 = fadd float %641, %833, !dbg !73
+  %835 = fsub float %834, %792, !dbg !74
+  %836 = extractvalue { i32, i32, i32, i32 } %681, 0, !dbg !68
+  %837 = bitcast i32 %836 to float, !dbg !68
+  %838 = extractvalue { i32, i32, i32, i32 } %610, 0, !dbg !62
+  %839 = bitcast i32 %838 to float, !dbg !62
+  %840 = fadd float %839, %837, !dbg !72
+  %841 = fadd float %640, %840, !dbg !73
+  %842 = fsub float %841, %792, !dbg !74
+  %843 = fmul float %842, %.0.i, !dbg !75
+  %844 = fmul float %835, %.0.i, !dbg !75
+  %845 = fmul float %828, %.0.i, !dbg !75
+  %846 = fmul float %821, %.0.i, !dbg !75
+  %847 = fmul float %814, %.0.i, !dbg !75
+  %848 = fmul float %807, %.0.i, !dbg !75
+  %849 = fmul float %800, %.0.i, !dbg !75
+  %850 = fmul float %793, %.0.i, !dbg !75
+  %851 = fmul float %784, %.0.i38, !dbg !75
+  %852 = fmul float %777, %.0.i38, !dbg !75
+  %853 = fmul float %770, %.0.i38, !dbg !75
+  %854 = fmul float %763, %.0.i38, !dbg !75
+  %855 = fmul float %756, %.0.i38, !dbg !75
+  %856 = fmul float %749, %.0.i38, !dbg !75
+  %857 = fmul float %742, %.0.i38, !dbg !75
+  %858 = fmul float %735, %.0.i38, !dbg !75
+  %859 = getelementptr float, ptr addrspace(3) @global_smem, i64 %656, !dbg !76
+  store i32 %658, ptr addrspace(3) %859, align 4, !dbg !76
+  tail call void @llvm.nvvm.barrier0(), !dbg !76
+  %860 = getelementptr float, ptr addrspace(3) @global_smem, i64 %160, !dbg !76
+  %861 = load float, ptr addrspace(3) %860, align 32, !dbg !76
+  %862 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 1, !dbg !76
+  %863 = load float, ptr addrspace(3) %862, align 4, !dbg !76
+  %864 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 2, !dbg !76
+  %865 = load float, ptr addrspace(3) %864, align 8, !dbg !76
+  %866 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 3, !dbg !76
+  %867 = load float, ptr addrspace(3) %866, align 4, !dbg !76
+  %868 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 4, !dbg !76
+  %869 = load float, ptr addrspace(3) %868, align 16, !dbg !76
+  %870 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 5, !dbg !76
+  %871 = load float, ptr addrspace(3) %870, align 4, !dbg !76
+  %872 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 6, !dbg !76
+  %873 = load float, ptr addrspace(3) %872, align 8, !dbg !76
+  %874 = getelementptr inbounds <8 x float>, ptr addrspace(3) %860, i64 0, i64 7, !dbg !76
+  %875 = load float, ptr addrspace(3) %874, align 4, !dbg !76
+  %876 = fmul float %843, %861, !dbg !76
+  %877 = fmul float %844, %863, !dbg !76
+  %878 = fmul float %845, %865, !dbg !76
+  %879 = fmul float %846, %867, !dbg !76
+  %880 = fmul float %847, %869, !dbg !76
+  %881 = fmul float %848, %871, !dbg !76
+  %882 = fmul float %849, %873, !dbg !76
+  %883 = fmul float %850, %875, !dbg !76
+  %884 = fmul float %851, %861, !dbg !76
+  %885 = fmul float %852, %863, !dbg !76
+  %886 = fmul float %853, %865, !dbg !76
+  %887 = fmul float %854, %867, !dbg !76
+  %888 = fmul float %855, %869, !dbg !76
+  %889 = fmul float %856, %871, !dbg !76
+  %890 = fmul float %857, %873, !dbg !76
+  %891 = fmul float %858, %875, !dbg !76
+  %892 = getelementptr i16, ptr addrspace(1) %5, i64 %100, !dbg !77
+  %893 = getelementptr i16, ptr addrspace(1) %5, i64 %102, !dbg !77
+  %894 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %876) #6, !dbg !78
+  %895 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %877) #6, !dbg !78
+  %896 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %878) #6, !dbg !78
+  %897 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %879) #6, !dbg !78
+  %898 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %880) #6, !dbg !78
+  %899 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %881) #6, !dbg !78
+  %900 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %882) #6, !dbg !78
+  %901 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %883) #6, !dbg !78
+  %902 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %884) #6, !dbg !78
+  %903 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %885) #6, !dbg !78
+  %904 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %886) #6, !dbg !78
+  %905 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %887) #6, !dbg !78
+  %906 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %888) #6, !dbg !78
+  %907 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %889) #6, !dbg !78
+  %908 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %890) #6, !dbg !78
+  %909 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %891) #6, !dbg !78
+  %910 = insertelement <2 x i16> undef, i16 %894, i64 0, !dbg !78
+  %911 = insertelement <2 x i16> %910, i16 %895, i64 1, !dbg !78
+  %912 = bitcast <2 x i16> %911 to i32, !dbg !78
+  %913 = insertelement <2 x i16> undef, i16 %896, i64 0, !dbg !78
+  %914 = insertelement <2 x i16> %913, i16 %897, i64 1, !dbg !78
+  %915 = bitcast <2 x i16> %914 to i32, !dbg !78
+  %916 = insertelement <2 x i16> undef, i16 %898, i64 0, !dbg !78
+  %917 = insertelement <2 x i16> %916, i16 %899, i64 1, !dbg !78
+  %918 = bitcast <2 x i16> %917 to i32, !dbg !78
+  %919 = insertelement <2 x i16> undef, i16 %900, i64 0, !dbg !78
+  %920 = insertelement <2 x i16> %919, i16 %901, i64 1, !dbg !78
+  %921 = bitcast <2 x i16> %920 to i32, !dbg !78
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %912, i32 %915, i32 %918, i32 %921, ptr addrspace(1) %892, i1 true) #6, !dbg !78
+  %922 = insertelement <2 x i16> undef, i16 %902, i64 0, !dbg !78
+  %923 = insertelement <2 x i16> %922, i16 %903, i64 1, !dbg !78
+  %924 = bitcast <2 x i16> %923 to i32, !dbg !78
+  %925 = insertelement <2 x i16> undef, i16 %904, i64 0, !dbg !78
+  %926 = insertelement <2 x i16> %925, i16 %905, i64 1, !dbg !78
+  %927 = bitcast <2 x i16> %926 to i32, !dbg !78
+  %928 = insertelement <2 x i16> undef, i16 %906, i64 0, !dbg !78
+  %929 = insertelement <2 x i16> %928, i16 %907, i64 1, !dbg !78
+  %930 = bitcast <2 x i16> %929 to i32, !dbg !78
+  %931 = insertelement <2 x i16> undef, i16 %908, i64 0, !dbg !78
+  %932 = insertelement <2 x i16> %931, i16 %909, i64 1, !dbg !78
+  %933 = bitcast <2 x i16> %932 to i32, !dbg !78
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %924, i32 %927, i32 %930, i32 %933, ptr addrspace(1) %893, i1 true) #6, !dbg !78
+  ret void, !dbg !79
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #3 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #5
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cpn3lawg65lpi63gv6c6pn4oikhg6qva2h2qjdpxe6qj4lvttwez.py", directory: "/tmp/torchinductor_root/pn")
+!4 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"maxntidx", i32 256}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6de7de", linkageName: "triton__0d1d2d3d4d5d6de7de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 22, column: 44, scope: !7)
+!11 = !DILocation(line: 24, column: 33, scope: !7)
+!12 = !DILocation(line: 21, column: 28, scope: !7)
+!13 = !DILocation(line: 21, column: 33, scope: !7)
+!14 = !DILocation(line: 22, column: 23, scope: !7)
+!15 = !DILocation(line: 26, column: 30, scope: !7)
+!16 = !DILocation(line: 26, column: 35, scope: !7)
+!17 = !DILocation(line: 27, column: 18, scope: !7)
+!18 = !DILocation(line: 35, column: 44, scope: !7)
+!19 = !DILocation(line: 35, column: 40, scope: !7)
+!20 = !DILocation(line: 35, column: 34, scope: !7)
+!21 = !DILocation(line: 35, column: 50, scope: !7)
+!22 = !DILocation(line: 36, column: 44, scope: !7)
+!23 = !DILocation(line: 36, column: 40, scope: !7)
+!24 = !DILocation(line: 36, column: 34, scope: !7)
+!25 = !DILocation(line: 36, column: 50, scope: !7)
+!26 = !DILocation(line: 36, column: 101, scope: !7)
+!27 = !DILocation(line: 37, column: 22, scope: !7)
+!28 = !DILocation(line: 38, column: 22, scope: !7)
+!29 = !DILocation(line: 39, column: 36, scope: !7)
+!30 = !DILocation(line: 40, column: 40, scope: !7)
+!31 = !DILocation(line: 40, column: 55, scope: !7)
+!32 = !DILocation(line: 41, column: 44, scope: !7)
+!33 = !DILocation(line: 41, column: 40, scope: !7)
+!34 = !DILocation(line: 41, column: 34, scope: !7)
+!35 = !DILocation(line: 41, column: 52, scope: !7)
+!36 = !DILocation(line: 42, column: 22, scope: !7)
+!37 = !DILocation(line: 44, column: 22, scope: !7)
+!38 = !DILocation(line: 98, column: 22, scope: !39, inlinedAt: !41)
+!39 = distinct !DILexicalBlockFile(scope: !7, file: !40, discriminator: 0)
+!40 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!41 = !DILocation(line: 47, column: 41, scope: !39)
+!42 = !DILocation(line: 101, column: 30, scope: !39, inlinedAt: !41)
+!43 = !DILocation(line: 101, column: 22, scope: !39, inlinedAt: !41)
+!44 = !DILocation(line: 101, column: 13, scope: !39, inlinedAt: !41)
+!45 = !DILocation(line: 108, column: 21, scope: !46, inlinedAt: !47)
+!46 = distinct !DILexicalBlockFile(scope: !39, file: !40, discriminator: 0)
+!47 = !DILocation(line: 120, column: 46, scope: !46, inlinedAt: !48)
+!48 = !DILocation(line: 53, column: 44, scope: !46)
+!49 = !DILocation(line: 110, column: 60, scope: !46, inlinedAt: !47)
+!50 = !DILocation(line: 112, column: 25, scope: !46, inlinedAt: !47)
+!51 = !DILocation(line: 112, column: 17, scope: !46, inlinedAt: !47)
+!52 = !DILocation(line: 113, column: 15, scope: !46, inlinedAt: !47)
+!53 = !DILocation(line: 113, column: 30, scope: !46, inlinedAt: !47)
+!54 = !DILocation(line: 113, column: 49, scope: !46, inlinedAt: !47)
+!55 = !DILocation(line: 113, column: 22, scope: !46, inlinedAt: !47)
+!56 = !DILocation(line: 113, column: 38, scope: !46, inlinedAt: !47)
+!57 = !DILocation(line: 120, column: 46, scope: !39, inlinedAt: !58)
+!58 = !DILocation(line: 53, column: 44, scope: !39)
+!59 = !DILocation(line: 109, column: 28, scope: !46, inlinedAt: !47)
+!60 = !DILocation(line: 110, column: 39, scope: !46, inlinedAt: !47)
+!61 = !DILocation(line: 110, column: 49, scope: !46, inlinedAt: !47)
+!62 = !DILocation(line: 62, column: 51, scope: !7)
+!63 = !DILocation(line: 63, column: 51, scope: !7)
+!64 = !DILocation(line: 63, column: 103, scope: !7)
+!65 = !DILocation(line: 64, column: 35, scope: !7)
+!66 = !DILocation(line: 64, column: 40, scope: !7)
+!67 = !DILocation(line: 68, column: 57, scope: !7)
+!68 = !DILocation(line: 69, column: 54, scope: !7)
+!69 = !DILocation(line: 75, column: 24, scope: !7)
+!70 = !DILocation(line: 77, column: 24, scope: !7)
+!71 = !DILocation(line: 78, column: 30, scope: !7)
+!72 = !DILocation(line: 70, column: 24, scope: !7)
+!73 = !DILocation(line: 72, column: 24, scope: !7)
+!74 = !DILocation(line: 73, column: 24, scope: !7)
+!75 = !DILocation(line: 79, column: 24, scope: !7)
+!76 = !DILocation(line: 80, column: 24, scope: !7)
+!77 = !DILocation(line: 82, column: 29, scope: !7)
+!78 = !DILocation(line: 82, column: 52, scope: !7)
+!79 = !DILocation(line: 58, column: 4, scope: !7)

.triton/dump/174400122b6dbc99e086544aa1856b9f/triton_.llir

@@ -0,0 +1,330 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@assertFunc_1 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_1 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_1 = internal constant [39 x i8] c"index out of bounds: 0 <= tmp13 < 50257"
+@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp3 < 50257"
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr
+
+define void @triton__0d1d2d3d4d5de6de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i32 %5, i32 %6) local_unnamed_addr !dbg !7 {
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %9 = lshr i32 %8, 2, !dbg !10
+  %10 = and i32 %9, 63, !dbg !10
+  %11 = and i32 %8, 63, !dbg !10
+  %12 = and i32 %8, 3, !dbg !11
+  %13 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #5, !dbg !12
+  %14 = shl i32 %13, 6, !dbg !13
+  %15 = or i32 %14, %10, !dbg !14
+  %16 = or i32 %14, %11, !dbg !14
+  %17 = sext i32 %15 to i64, !dbg !15
+  %18 = getelementptr i64, ptr addrspace(1) %0, i64 %17, !dbg !15
+  %19 = sext i32 %16 to i64, !dbg !15
+  %20 = getelementptr i64, ptr addrspace(1) %0, i64 %19, !dbg !15
+  %21 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %18, i1 true) #5, !dbg !16
+  %22 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %20, i1 true) #5, !dbg !16
+  %23 = srem i32 %15, 512, !dbg !17
+  %24 = shl nsw i32 %23, 8, !dbg !18
+  %25 = add i64 %22, 50257, !dbg !19
+  %26 = icmp slt i64 %21, 0, !dbg !20
+  %27 = icmp slt i64 %22, 0, !dbg !20
+  %28 = select i1 %27, i64 %25, i64 %22, !dbg !21
+  %.fr8 = freeze i64 %28, !dbg !22
+  %29 = icmp ugt i64 %.fr8, 50256, !dbg !22
+  %30 = shl i64 %21, 8, !dbg !23
+  %31 = add i64 %30, 12865792, !dbg !23
+  %32 = select i1 %26, i64 %31, i64 %30, !dbg !23
+  %33 = getelementptr float, ptr addrspace(1) %1, i64 %32
+  br i1 %29, label %.split.us, label %.split, !dbg !24
+
+.split.us:                                        ; preds = %7, %.split.us
+  %34 = phi float [ %50, %.split.us ], [ 0.000000e+00, %7 ]
+  %35 = phi float [ %55, %.split.us ], [ 0.000000e+00, %7 ]
+  %36 = phi float [ %52, %.split.us ], [ 0.000000e+00, %7 ]
+  %37 = phi i32 [ %56, %.split.us ], [ 0, %7 ]
+  %38 = or i32 %37, %12, !dbg !25
+  %39 = add i32 %38, %24, !dbg !26
+  %40 = sext i32 %39 to i64, !dbg !27
+  %41 = getelementptr float, ptr addrspace(1) %2, i64 %40, !dbg !27
+  %42 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %41, i1 true, i32 0, i1 true) #5, !dbg !28
+  %43 = bitcast i32 %42 to float, !dbg !28
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !24
+  %44 = zext nneg i32 %38 to i64, !dbg !29
+  %45 = getelementptr float, ptr addrspace(1) %33, i64 %44, !dbg !30
+  %46 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %45, i1 true, i32 0, i1 true) #5, !dbg !31
+  %47 = bitcast i32 %46 to float, !dbg !31
+  %48 = fadd float %43, %47, !dbg !32
+  %49 = fsub float %48, %36, !dbg !33
+  %50 = fadd float %34, 1.000000e+00, !dbg !37
+  %51 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %49, float %50) #5, !dbg !38
+  %52 = fadd float %36, %51, !dbg !39
+  %53 = fsub float %48, %52, !dbg !40
+  %54 = fmul float %49, %53, !dbg !41
+  %55 = fadd float %35, %54, !dbg !42
+  %56 = add nuw nsw i32 %37, 4, !dbg !43
+  %57 = icmp ult i32 %37, 252, !dbg !43
+  br i1 %57, label %.split.us, label %.split5.us, !dbg !43
+
+.split:                                           ; preds = %7, %.split
+  %58 = phi float [ %74, %.split ], [ 0.000000e+00, %7 ]
+  %59 = phi float [ %79, %.split ], [ 0.000000e+00, %7 ]
+  %60 = phi float [ %76, %.split ], [ 0.000000e+00, %7 ]
+  %61 = phi i32 [ %80, %.split ], [ 0, %7 ]
+  %62 = or i32 %61, %12, !dbg !25
+  %63 = add i32 %62, %24, !dbg !26
+  %64 = sext i32 %63 to i64, !dbg !27
+  %65 = getelementptr float, ptr addrspace(1) %2, i64 %64, !dbg !27
+  %66 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %65, i1 true, i32 0, i1 true) #5, !dbg !28
+  %67 = bitcast i32 %66 to float, !dbg !28
+  %68 = zext nneg i32 %62 to i64, !dbg !29
+  %69 = getelementptr float, ptr addrspace(1) %33, i64 %68, !dbg !30
+  %70 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %69, i1 true, i32 0, i1 true) #5, !dbg !31
+  %71 = bitcast i32 %70 to float, !dbg !31
+  %72 = fadd float %67, %71, !dbg !32
+  %73 = fsub float %72, %60, !dbg !33
+  %74 = fadd float %58, 1.000000e+00, !dbg !37
+  %75 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %73, float %74) #5, !dbg !38
+  %76 = fadd float %60, %75, !dbg !39
+  %77 = fsub float %72, %76, !dbg !40
+  %78 = fmul float %73, %77, !dbg !41
+  %79 = fadd float %59, %78, !dbg !42
+  %80 = add nuw nsw i32 %61, 4, !dbg !43
+  %81 = icmp ult i32 %61, 252, !dbg !43
+  br i1 %81, label %.split, label %.split5.us, !dbg !43
+
+.split5.us:                                       ; preds = %.split, %.split.us
+  %.us-phi = phi float [ %52, %.split.us ], [ %76, %.split ]
+  %.us-phi6 = phi float [ %55, %.split.us ], [ %79, %.split ]
+  %.us-phi7 = phi float [ %50, %.split.us ], [ %74, %.split ]
+  %82 = bitcast float %.us-phi to i32, !dbg !44
+  %83 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %82, i32 2, i32 31), !dbg !44
+  %84 = bitcast i32 %83 to float, !dbg !44
+  %85 = bitcast float %.us-phi6 to i32, !dbg !44
+  %86 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %85, i32 2, i32 31), !dbg !44
+  %87 = bitcast i32 %86 to float, !dbg !44
+  %88 = bitcast float %.us-phi7 to i32, !dbg !44
+  %89 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %88, i32 2, i32 31), !dbg !44
+  %90 = bitcast i32 %89 to float, !dbg !44
+  %91 = fsub float %84, %.us-phi, !dbg !46
+  %92 = fadd float %.us-phi7, %90, !dbg !50
+  %93 = fcmp oeq float %92, 0.000000e+00, !dbg !51
+  %94 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %90, float %92) #5, !dbg !52
+  %95 = select i1 %93, float 0.000000e+00, float %94, !dbg !53
+  %96 = fmul float %91, %95, !dbg !54
+  %97 = fadd float %.us-phi, %96, !dbg !55
+  %98 = fadd float %.us-phi6, %87, !dbg !56
+  %99 = fmul float %91, %91, !dbg !57
+  %100 = fmul float %.us-phi7, %99, !dbg !58
+  %101 = fmul float %100, %95, !dbg !59
+  %102 = fadd float %98, %101, !dbg !60
+  %103 = bitcast float %97 to i32, !dbg !44
+  %104 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %103, i32 1, i32 31), !dbg !44
+  %105 = bitcast i32 %104 to float, !dbg !44
+  %106 = bitcast float %102 to i32, !dbg !44
+  %107 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %106, i32 1, i32 31), !dbg !44
+  %108 = bitcast i32 %107 to float, !dbg !44
+  %109 = bitcast float %92 to i32, !dbg !44
+  %110 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %109, i32 1, i32 31), !dbg !44
+  %111 = bitcast i32 %110 to float, !dbg !44
+  %112 = fsub float %105, %97, !dbg !46
+  %113 = fadd float %92, %111, !dbg !50
+  %114 = fcmp oeq float %113, 0.000000e+00, !dbg !51
+  %115 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %111, float %113) #5, !dbg !52
+  %116 = select i1 %114, float 0.000000e+00, float %115, !dbg !53
+  %117 = fmul float %112, %116, !dbg !54
+  %118 = fadd float %97, %117, !dbg !55
+  %119 = fadd float %102, %108, !dbg !56
+  %120 = fmul float %112, %112, !dbg !57
+  %121 = fmul float %92, %120, !dbg !58
+  %122 = fmul float %116, %121, !dbg !59
+  %123 = fadd float %119, %122, !dbg !60
+  %124 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %123, float 2.560000e+02) #5, !dbg !61
+  %125 = fadd float %124, 0x3EE4F8B580000000, !dbg !62
+  %126 = shl i32 %15, 8, !dbg !63
+  br label %127, !dbg !64
+
+127:                                              ; preds = %.split5.us, %__nv_rsqrtf.exit
+  %128 = phi i32 [ 0, %.split5.us ], [ %157, %__nv_rsqrtf.exit ]
+  %129 = or i32 %128, %12, !dbg !65
+  %130 = add i32 %129, %24, !dbg !66
+  %131 = sext i32 %130 to i64, !dbg !67
+  %132 = getelementptr float, ptr addrspace(1) %2, i64 %131, !dbg !67
+  %133 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %132, i1 true, i32 0, i1 true) #5, !dbg !68
+  %134 = bitcast i32 %133 to float, !dbg !68
+  %135 = zext nneg i32 %129 to i64, !dbg !69
+  %136 = getelementptr float, ptr addrspace(1) %3, i64 %135, !dbg !69
+  %137 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %136, i1 true, i32 0, i1 true) #5, !dbg !70
+  %138 = bitcast i32 %137 to float, !dbg !70
+  br i1 %29, label %139, label %140, !dbg !71
+
+139:                                              ; preds = %127
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 883, ptr nonnull @assertFunc_1, i64 1), !dbg !71
+  br label %140, !dbg !71
+
+140:                                              ; preds = %139, %127
+  %141 = getelementptr float, ptr addrspace(1) %33, i64 %135, !dbg !72
+  %142 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %141, i1 true, i32 0, i1 true) #5, !dbg !73
+  %143 = bitcast i32 %142 to float, !dbg !73
+  %144 = fadd float %134, %143, !dbg !74
+  %145 = fsub float %144, %118, !dbg !75
+  %146 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !76
+  %.not.i = icmp eq i32 %146, 0, !dbg !76
+  br i1 %.not.i, label %149, label %147, !dbg !76
+
+147:                                              ; preds = %140
+  %148 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %125), !dbg !76
+  br label %__nv_rsqrtf.exit, !dbg !76
+
+149:                                              ; preds = %140
+  %150 = tail call float @llvm.nvvm.rsqrt.approx.f(float %125), !dbg !76
+  br label %__nv_rsqrtf.exit, !dbg !76
+
+__nv_rsqrtf.exit:                                 ; preds = %147, %149
+  %.0.i = phi float [ %148, %147 ], [ %150, %149 ], !dbg !76
+  %151 = fmul float %145, %.0.i, !dbg !77
+  %152 = fmul float %151, %138, !dbg !78
+  %153 = add i32 %129, %126, !dbg !79
+  %154 = sext i32 %153 to i64, !dbg !80
+  %155 = getelementptr i16, ptr addrspace(1) %4, i64 %154, !dbg !80
+  %156 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %152) #5, !dbg !81
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %156, ptr addrspace(1) %155, i1 true) #5, !dbg !81
+  %157 = add nuw nsw i32 %128, 4, !dbg !64
+  %158 = icmp ult i32 %128, 252, !dbg !64
+  br i1 %158, label %127, label %159, !dbg !64
+
+159:                                              ; preds = %__nv_rsqrtf.exit
+  ret void, !dbg !82
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #2 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #3
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #4
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cgx5lxpuexpindj4dsmjz5x42uhyy7iskevq7ovzpwagb3t5powj.py", directory: "/tmp/torchinductor_root/gx")
+!4 = !{ptr @triton__0d1d2d3d4d5de6de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5de6de, !"maxntidx", i32 256}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5de6de", linkageName: "triton__0d1d2d3d4d5de6de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 22, column: 44, scope: !7)
+!11 = !DILocation(line: 24, column: 33, scope: !7)
+!12 = !DILocation(line: 21, column: 28, scope: !7)
+!13 = !DILocation(line: 21, column: 33, scope: !7)
+!14 = !DILocation(line: 22, column: 23, scope: !7)
+!15 = !DILocation(line: 26, column: 30, scope: !7)
+!16 = !DILocation(line: 26, column: 35, scope: !7)
+!17 = !DILocation(line: 27, column: 18, scope: !7)
+!18 = !DILocation(line: 35, column: 44, scope: !7)
+!19 = !DILocation(line: 36, column: 22, scope: !7)
+!20 = !DILocation(line: 37, column: 22, scope: !7)
+!21 = !DILocation(line: 38, column: 36, scope: !7)
+!22 = !DILocation(line: 39, column: 40, scope: !7)
+!23 = !DILocation(line: 40, column: 44, scope: !7)
+!24 = !DILocation(line: 39, column: 55, scope: !7)
+!25 = !DILocation(line: 32, column: 27, scope: !7)
+!26 = !DILocation(line: 35, column: 40, scope: !7)
+!27 = !DILocation(line: 35, column: 34, scope: !7)
+!28 = !DILocation(line: 35, column: 50, scope: !7)
+!29 = !DILocation(line: 40, column: 40, scope: !7)
+!30 = !DILocation(line: 40, column: 34, scope: !7)
+!31 = !DILocation(line: 40, column: 52, scope: !7)
+!32 = !DILocation(line: 41, column: 22, scope: !7)
+!33 = !DILocation(line: 96, column: 20, scope: !34, inlinedAt: !36)
+!34 = distinct !DILexicalBlockFile(scope: !7, file: !35, discriminator: 0)
+!35 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!36 = !DILocation(line: 44, column: 38, scope: !34)
+!37 = !DILocation(line: 97, column: 26, scope: !34, inlinedAt: !36)
+!38 = !DILocation(line: 98, column: 30, scope: !34, inlinedAt: !36)
+!39 = !DILocation(line: 98, column: 22, scope: !34, inlinedAt: !36)
+!40 = !DILocation(line: 101, column: 30, scope: !34, inlinedAt: !36)
+!41 = !DILocation(line: 101, column: 22, scope: !34, inlinedAt: !36)
+!42 = !DILocation(line: 47, column: 48, scope: !7)
+!43 = !DILocation(line: 31, column: 36, scope: !7)
+!44 = !DILocation(line: 120, column: 46, scope: !34, inlinedAt: !45)
+!45 = !DILocation(line: 50, column: 41, scope: !34)
+!46 = !DILocation(line: 108, column: 21, scope: !47, inlinedAt: !48)
+!47 = distinct !DILexicalBlockFile(scope: !34, file: !35, discriminator: 0)
+!48 = !DILocation(line: 120, column: 46, scope: !47, inlinedAt: !49)
+!49 = !DILocation(line: 50, column: 41, scope: !47)
+!50 = !DILocation(line: 109, column: 28, scope: !47, inlinedAt: !48)
+!51 = !DILocation(line: 110, column: 39, scope: !47, inlinedAt: !48)
+!52 = !DILocation(line: 110, column: 60, scope: !47, inlinedAt: !48)
+!53 = !DILocation(line: 110, column: 49, scope: !47, inlinedAt: !48)
+!54 = !DILocation(line: 112, column: 25, scope: !47, inlinedAt: !48)
+!55 = !DILocation(line: 112, column: 17, scope: !47, inlinedAt: !48)
+!56 = !DILocation(line: 113, column: 15, scope: !47, inlinedAt: !48)
+!57 = !DILocation(line: 113, column: 30, scope: !47, inlinedAt: !48)
+!58 = !DILocation(line: 113, column: 38, scope: !47, inlinedAt: !48)
+!59 = !DILocation(line: 113, column: 49, scope: !47, inlinedAt: !48)
+!60 = !DILocation(line: 113, column: 22, scope: !47, inlinedAt: !48)
+!61 = !DILocation(line: 69, column: 23, scope: !7)
+!62 = !DILocation(line: 71, column: 24, scope: !7)
+!63 = !DILocation(line: 76, column: 39, scope: !7)
+!64 = !DILocation(line: 55, column: 36, scope: !7)
+!65 = !DILocation(line: 56, column: 27, scope: !7)
+!66 = !DILocation(line: 59, column: 41, scope: !7)
+!67 = !DILocation(line: 59, column: 35, scope: !7)
+!68 = !DILocation(line: 59, column: 51, scope: !7)
+!69 = !DILocation(line: 60, column: 35, scope: !7)
+!70 = !DILocation(line: 60, column: 40, scope: !7)
+!71 = !DILocation(line: 64, column: 57, scope: !7)
+!72 = !DILocation(line: 65, column: 35, scope: !7)
+!73 = !DILocation(line: 65, column: 54, scope: !7)
+!74 = !DILocation(line: 66, column: 24, scope: !7)
+!75 = !DILocation(line: 67, column: 24, scope: !7)
+!76 = !DILocation(line: 72, column: 30, scope: !7)
+!77 = !DILocation(line: 73, column: 24, scope: !7)
+!78 = !DILocation(line: 74, column: 24, scope: !7)
+!79 = !DILocation(line: 76, column: 35, scope: !7)
+!80 = !DILocation(line: 76, column: 29, scope: !7)
+!81 = !DILocation(line: 76, column: 52, scope: !7)
+!82 = !DILocation(line: 55, column: 4, scope: !7)

.triton/dump/21d0195c63fb062bfc567b79c9bb2771/triton_.llir

@@ -0,0 +1,321 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3d4d5d6d7d8de9de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, ptr addrspace(1) %7, i32 %8, i32 %9) local_unnamed_addr !dbg !5 {
+  %11 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %12 = and i32 %11, 31, !dbg !8
+  %13 = lshr i32 %11, 5, !dbg !8
+  %14 = and i32 %13, 1, !dbg !8
+  %urem = shl i32 %11, 2, !dbg !8
+  %15 = and i32 %urem, 252, !dbg !8
+  %16 = or i32 %15, 1, !dbg !8
+  %17 = or i32 %15, 2, !dbg !8
+  %18 = or i32 %15, 3, !dbg !8
+  %19 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !9
+  %20 = shl i32 %19, 8, !dbg !10
+  %21 = or i32 %20, %15, !dbg !11
+  %22 = sext i32 %21 to i64, !dbg !12
+  %23 = getelementptr i16, ptr addrspace(1) %1, i64 %22, !dbg !12
+  %24 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %23, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !13
+  %25 = extractvalue { i32, i32 } %24, 0, !dbg !13
+  %26 = extractvalue { i32, i32 } %24, 1, !dbg !13
+  %27 = trunc i32 %25 to i16, !dbg !13
+  %extelt.offset = lshr i32 %25, 16, !dbg !13
+  %28 = trunc i32 %extelt.offset to i16, !dbg !13
+  %29 = trunc i32 %26 to i16, !dbg !13
+  %extelt.offset1 = lshr i32 %26, 16, !dbg !13
+  %30 = trunc i32 %extelt.offset1 to i16, !dbg !13
+  %31 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %27) #3, !dbg !14
+  %32 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %28) #3, !dbg !14
+  %33 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %29) #3, !dbg !14
+  %34 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %30) #3, !dbg !14
+  %35 = zext nneg i32 %15 to i64, !dbg !15
+  %36 = getelementptr float, ptr addrspace(1) %2, i64 %35, !dbg !15
+  %37 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %36, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !16
+  %38 = extractvalue { i32, i32, i32, i32 } %37, 0, !dbg !16
+  %39 = extractvalue { i32, i32, i32, i32 } %37, 1, !dbg !16
+  %40 = extractvalue { i32, i32, i32, i32 } %37, 2, !dbg !16
+  %41 = extractvalue { i32, i32, i32, i32 } %37, 3, !dbg !16
+  %42 = bitcast i32 %38 to float, !dbg !16
+  %43 = bitcast i32 %39 to float, !dbg !16
+  %44 = bitcast i32 %40 to float, !dbg !16
+  %45 = bitcast i32 %41 to float, !dbg !16
+  %46 = getelementptr float, ptr addrspace(1) %3, i64 %22, !dbg !17
+  %47 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %46, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !18
+  %48 = extractvalue { i32, i32, i32, i32 } %47, 0, !dbg !18
+  %49 = extractvalue { i32, i32, i32, i32 } %47, 1, !dbg !18
+  %50 = extractvalue { i32, i32, i32, i32 } %47, 2, !dbg !18
+  %51 = extractvalue { i32, i32, i32, i32 } %47, 3, !dbg !18
+  %52 = bitcast i32 %48 to float, !dbg !18
+  %53 = bitcast i32 %49 to float, !dbg !18
+  %54 = bitcast i32 %50 to float, !dbg !18
+  %55 = bitcast i32 %51 to float, !dbg !18
+  %56 = sext i32 %19 to i64, !dbg !19
+  %57 = getelementptr float, ptr addrspace(1) %4, i64 %56, !dbg !19
+  %58 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %57, i1 true) #3, !dbg !20
+  %59 = bitcast i32 %58 to float, !dbg !20
+  %60 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %57, i1 true) #3, !dbg !20
+  %61 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %57, i1 true) #3, !dbg !20
+  %62 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %57, i1 true) #3, !dbg !20
+  %63 = getelementptr float, ptr addrspace(1) %5, i64 %56, !dbg !21
+  %64 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %63, i1 true) #3, !dbg !22
+  %65 = bitcast i32 %64 to float, !dbg !22
+  %66 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %63, i1 true) #3, !dbg !22
+  %67 = bitcast i32 %66 to float, !dbg !22
+  %68 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %63, i1 true) #3, !dbg !22
+  %69 = bitcast i32 %68 to float, !dbg !22
+  %70 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %63, i1 true) #3, !dbg !22
+  %71 = bitcast i32 %70 to float, !dbg !22
+  %72 = getelementptr i64, ptr addrspace(1) %6, i64 %56, !dbg !23
+  %73 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %72, i1 true) #3, !dbg !24
+  %74 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %72, i1 true) #3, !dbg !24
+  %75 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %72, i1 true) #3, !dbg !24
+  %76 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %72, i1 true) #3, !dbg !24
+  %77 = getelementptr float, ptr addrspace(1) %0, i64 %22, !dbg !25
+  %78 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %77, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !26
+  %79 = extractvalue { i32, i32, i32, i32 } %78, 0, !dbg !26
+  %80 = extractvalue { i32, i32, i32, i32 } %78, 1, !dbg !26
+  %81 = extractvalue { i32, i32, i32, i32 } %78, 2, !dbg !26
+  %82 = extractvalue { i32, i32, i32, i32 } %78, 3, !dbg !26
+  %83 = bitcast i32 %79 to float, !dbg !26
+  %84 = bitcast i32 %80 to float, !dbg !26
+  %85 = bitcast i32 %81 to float, !dbg !26
+  %86 = bitcast i32 %82 to float, !dbg !26
+  %87 = fmul float %31, %42, !dbg !27
+  %88 = fmul float %32, %43, !dbg !27
+  %89 = fmul float %33, %44, !dbg !27
+  %90 = fmul float %34, %45, !dbg !27
+  %91 = fadd float %87, %88, !dbg !28
+  %92 = fadd float %89, %91, !dbg !28
+  %93 = fadd float %90, %92, !dbg !28
+  %94 = bitcast float %93 to i32, !dbg !34
+  %95 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %94, i32 16, i32 31), !dbg !34
+  %96 = bitcast i32 %95 to float, !dbg !34
+  %97 = fadd float %93, %96, !dbg !28
+  %98 = bitcast float %97 to i32, !dbg !34
+  %99 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %98, i32 8, i32 31), !dbg !34
+  %100 = bitcast i32 %99 to float, !dbg !34
+  %101 = fadd float %97, %100, !dbg !28
+  %102 = bitcast float %101 to i32, !dbg !34
+  %103 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %102, i32 4, i32 31), !dbg !34
+  %104 = bitcast i32 %103 to float, !dbg !34
+  %105 = fadd float %101, %104, !dbg !28
+  %106 = bitcast float %105 to i32, !dbg !34
+  %107 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %106, i32 2, i32 31), !dbg !34
+  %108 = bitcast i32 %107 to float, !dbg !34
+  %109 = fadd float %105, %108, !dbg !28
+  %110 = bitcast float %109 to i32, !dbg !34
+  %111 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %110, i32 1, i32 31), !dbg !34
+  %112 = bitcast i32 %111 to float, !dbg !34
+  %113 = fadd float %109, %112, !dbg !28
+  %114 = icmp eq i32 %12, 0, !dbg !34
+  %115 = zext nneg i32 %14 to i64, !dbg !34
+  %116 = getelementptr float, ptr addrspace(3) @global_smem, i64 %115, !dbg !34
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %116, float %113, i1 %114) #3, !dbg !34
+  tail call void @llvm.nvvm.barrier0(), !dbg !34
+  %117 = icmp slt i32 %11, 2, !dbg !34
+  %118 = sext i32 %11 to i64, !dbg !34
+  %119 = getelementptr float, ptr addrspace(3) @global_smem, i64 %118, !dbg !34
+  %120 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %119, i1 %117) #3, !dbg !34
+  %121 = bitcast float %120 to i32, !dbg !34
+  %122 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %121, i32 1, i32 31), !dbg !34
+  %123 = bitcast i32 %122 to float, !dbg !34
+  %124 = fadd float %120, %123, !dbg !28
+  %125 = and i32 %11, 1, !dbg !34
+  %126 = icmp eq i32 %125, 0, !dbg !34
+  %127 = and i1 %117, %126, !dbg !34
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %119, float %124, i1 %127) #3, !dbg !34
+  tail call void @llvm.nvvm.barrier0(), !dbg !34
+  %128 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !34
+  %129 = fadd float %128, 0.000000e+00, !dbg !36
+  %130 = fsub float %52, %59, !dbg !40
+  %131 = fsub float %53, %59, !dbg !40
+  %132 = fsub float %54, %59, !dbg !40
+  %133 = fsub float %55, %59, !dbg !40
+  %134 = fmul float %130, %65, !dbg !41
+  %135 = fmul float %131, %65, !dbg !41
+  %136 = fmul float %132, %65, !dbg !41
+  %137 = fmul float %133, %65, !dbg !41
+  %138 = fmul float %87, %134, !dbg !42
+  %139 = fmul float %88, %135, !dbg !42
+  %140 = fmul float %89, %136, !dbg !42
+  %141 = fmul float %90, %137, !dbg !42
+  tail call void @llvm.nvvm.barrier0(), !dbg !43
+  %142 = fadd float %138, %139, !dbg !45
+  %143 = fadd float %140, %142, !dbg !45
+  %144 = fadd float %141, %143, !dbg !45
+  %145 = bitcast float %144 to i32, !dbg !43
+  %146 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %145, i32 16, i32 31), !dbg !43
+  %147 = bitcast i32 %146 to float, !dbg !43
+  %148 = fadd float %144, %147, !dbg !45
+  %149 = bitcast float %148 to i32, !dbg !43
+  %150 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %149, i32 8, i32 31), !dbg !43
+  %151 = bitcast i32 %150 to float, !dbg !43
+  %152 = fadd float %148, %151, !dbg !45
+  %153 = bitcast float %152 to i32, !dbg !43
+  %154 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %153, i32 4, i32 31), !dbg !43
+  %155 = bitcast i32 %154 to float, !dbg !43
+  %156 = fadd float %152, %155, !dbg !45
+  %157 = bitcast float %156 to i32, !dbg !43
+  %158 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %157, i32 2, i32 31), !dbg !43
+  %159 = bitcast i32 %158 to float, !dbg !43
+  %160 = fadd float %156, %159, !dbg !45
+  %161 = bitcast float %160 to i32, !dbg !43
+  %162 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %161, i32 1, i32 31), !dbg !43
+  %163 = bitcast i32 %162 to float, !dbg !43
+  %164 = fadd float %160, %163, !dbg !45
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %116, float %164, i1 %114) #3, !dbg !43
+  tail call void @llvm.nvvm.barrier0(), !dbg !43
+  %165 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %119, i1 %117) #3, !dbg !43
+  %166 = bitcast float %165 to i32, !dbg !43
+  %167 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %166, i32 1, i32 31), !dbg !43
+  %168 = bitcast i32 %167 to float, !dbg !43
+  %169 = fadd float %165, %168, !dbg !45
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %119, float %169, i1 %127) #3, !dbg !43
+  tail call void @llvm.nvvm.barrier0(), !dbg !43
+  %170 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !43
+  %171 = fadd float %170, 0.000000e+00, !dbg !48
+  %172 = icmp eq i64 %73, -1, !dbg !50
+  %173 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %65, float 2.560000e+02) #3, !dbg !51
+  %174 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %67, float 2.560000e+02) #3, !dbg !51
+  %175 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %69, float 2.560000e+02) #3, !dbg !51
+  %176 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %71, float 2.560000e+02) #3, !dbg !51
+  %177 = fmul float %87, 2.560000e+02, !dbg !52
+  %178 = fmul float %88, 2.560000e+02, !dbg !52
+  %179 = fmul float %89, 2.560000e+02, !dbg !52
+  %180 = fmul float %90, 2.560000e+02, !dbg !52
+  %181 = fsub float %177, %129, !dbg !53
+  %182 = fsub float %178, %129, !dbg !53
+  %183 = fsub float %179, %129, !dbg !53
+  %184 = fsub float %180, %129, !dbg !53
+  %185 = fmul float %134, %171, !dbg !54
+  %186 = fmul float %135, %171, !dbg !54
+  %187 = fmul float %136, %171, !dbg !54
+  %188 = fmul float %137, %171, !dbg !54
+  %189 = fsub float %181, %185, !dbg !55
+  %190 = fsub float %182, %186, !dbg !55
+  %191 = fsub float %183, %187, !dbg !55
+  %192 = fsub float %184, %188, !dbg !55
+  %193 = fmul float %173, %189, !dbg !56
+  %194 = fmul float %173, %190, !dbg !56
+  %195 = fmul float %173, %191, !dbg !56
+  %196 = fmul float %173, %192, !dbg !56
+  %197 = fadd float %193, %83, !dbg !57
+  %198 = fadd float %194, %84, !dbg !57
+  %199 = fadd float %195, %85, !dbg !57
+  %200 = fadd float %196, %86, !dbg !57
+  %201 = select i1 %172, float 0.000000e+00, float %197, !dbg !58
+  %202 = select i1 %172, float 0.000000e+00, float %198, !dbg !58
+  %203 = select i1 %172, float 0.000000e+00, float %199, !dbg !58
+  %204 = select i1 %172, float 0.000000e+00, float %200, !dbg !58
+  %205 = icmp slt i64 %73, 0, !dbg !59
+  %206 = shl i64 %73, 8, !dbg !60
+  %207 = add i64 %206, 12865792, !dbg !60
+  %208 = select i1 %205, i64 %207, i64 %206, !dbg !60
+  %209 = zext nneg i32 %16 to i64
+  %210 = zext nneg i32 %17 to i64
+  %211 = zext nneg i32 %18 to i64
+  %212 = or i64 %208, %35, !dbg !61
+  %213 = or i64 %208, %209, !dbg !61
+  %214 = or i64 %208, %210, !dbg !61
+  %215 = or i64 %208, %211, !dbg !61
+  %216 = getelementptr float, ptr addrspace(1) %7, i64 %212, !dbg !62
+  %217 = getelementptr float, ptr addrspace(1) %7, i64 %213, !dbg !62
+  %218 = getelementptr float, ptr addrspace(1) %7, i64 %214, !dbg !62
+  %219 = getelementptr float, ptr addrspace(1) %7, i64 %215, !dbg !62
+  %220 = insertelement <1 x float> undef, float %201, i64 0, !dbg !63
+  %221 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %216, <1 x float> %220, i1 true) #3, !dbg !63
+  %222 = insertelement <1 x float> undef, float %202, i64 0, !dbg !63
+  %223 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %217, <1 x float> %222, i1 true) #3, !dbg !63
+  %224 = insertelement <1 x float> undef, float %203, i64 0, !dbg !63
+  %225 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %218, <1 x float> %224, i1 true) #3, !dbg !63
+  %226 = insertelement <1 x float> undef, float %204, i64 0, !dbg !63
+  %227 = tail call float asm sideeffect "mov.u32 $0, 0x0;\0A\09@$3 atom.global.gpu.acq_rel.add.f32 $0, [ $1 + 0 ], $2;", "=r,l,r,b"(ptr addrspace(1) %219, <1 x float> %226, i1 true) #3, !dbg !63
+  ret void, !dbg !64
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "cqryxm46jcxyr3qdktqirn53eap7h3pjjqiqavyqqyvflabjpvmd.py", directory: "/tmp/torchinductor_root/qr")
+!3 = !{ptr @triton__0d1d2d3d4d5d6d7d8de9de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3d4d5d6d7d8de9de, !"maxntidx", i32 64}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6d7d8de9de", linkageName: "triton__0d1d2d3d4d5d6d7d8de9de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 26, column: 26, scope: !5)
+!9 = !DILocation(line: 23, column: 28, scope: !5)
+!10 = !DILocation(line: 30, column: 40, scope: !5)
+!11 = !DILocation(line: 30, column: 36, scope: !5)
+!12 = !DILocation(line: 30, column: 30, scope: !5)
+!13 = !DILocation(line: 30, column: 46, scope: !5)
+!14 = !DILocation(line: 30, column: 67, scope: !5)
+!15 = !DILocation(line: 31, column: 30, scope: !5)
+!16 = !DILocation(line: 31, column: 35, scope: !5)
+!17 = !DILocation(line: 32, column: 30, scope: !5)
+!18 = !DILocation(line: 32, column: 46, scope: !5)
+!19 = !DILocation(line: 33, column: 30, scope: !5)
+!20 = !DILocation(line: 33, column: 35, scope: !5)
+!21 = !DILocation(line: 34, column: 31, scope: !5)
+!22 = !DILocation(line: 34, column: 36, scope: !5)
+!23 = !DILocation(line: 35, column: 31, scope: !5)
+!24 = !DILocation(line: 35, column: 36, scope: !5)
+!25 = !DILocation(line: 36, column: 35, scope: !5)
+!26 = !DILocation(line: 36, column: 51, scope: !5)
+!27 = !DILocation(line: 38, column: 18, scope: !5)
+!28 = !DILocation(line: 233, column: 15, scope: !29, inlinedAt: !32)
+!29 = distinct !DILexicalBlockFile(scope: !31, file: !30, discriminator: 0)
+!30 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!31 = distinct !DILexicalBlockFile(scope: !5, file: !30, discriminator: 0)
+!32 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !33)
+!33 = !DILocation(line: 41, column: 57, scope: !29)
+!34 = !DILocation(line: 243, column: 36, scope: !31, inlinedAt: !35)
+!35 = !DILocation(line: 41, column: 57, scope: !31)
+!36 = !DILocation(line: 8, column: 15, scope: !37, inlinedAt: !39)
+!37 = distinct !DILexicalBlockFile(scope: !5, file: !38, discriminator: 0)
+!38 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!39 = !DILocation(line: 41, column: 44, scope: !37)
+!40 = !DILocation(line: 42, column: 19, scope: !5)
+!41 = !DILocation(line: 43, column: 20, scope: !5)
+!42 = !DILocation(line: 44, column: 19, scope: !5)
+!43 = !DILocation(line: 243, column: 36, scope: !31, inlinedAt: !44)
+!44 = !DILocation(line: 47, column: 59, scope: !31)
+!45 = !DILocation(line: 233, column: 15, scope: !29, inlinedAt: !46)
+!46 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !47)
+!47 = !DILocation(line: 47, column: 59, scope: !29)
+!48 = !DILocation(line: 8, column: 15, scope: !37, inlinedAt: !49)
+!49 = !DILocation(line: 47, column: 45, scope: !37)
+!50 = !DILocation(line: 49, column: 21, scope: !5)
+!51 = !DILocation(line: 51, column: 20, scope: !5)
+!52 = !DILocation(line: 52, column: 19, scope: !5)
+!53 = !DILocation(line: 53, column: 20, scope: !5)
+!54 = !DILocation(line: 54, column: 20, scope: !5)
+!55 = !DILocation(line: 55, column: 20, scope: !5)
+!56 = !DILocation(line: 56, column: 20, scope: !5)
+!57 = !DILocation(line: 57, column: 20, scope: !5)
+!58 = !DILocation(line: 59, column: 35, scope: !5)
+!59 = !DILocation(line: 61, column: 20, scope: !5)
+!60 = !DILocation(line: 63, column: 56, scope: !5)
+!61 = !DILocation(line: 63, column: 52, scope: !5)
+!62 = !DILocation(line: 63, column: 30, scope: !5)
+!63 = !DILocation(line: 63, column: 83, scope: !5)
+!64 = !DILocation(line: 63, column: 4, scope: !5)

.triton/dump/21d0195c63fb062bfc567b79c9bb2771/triton_.ttir

@@ -0,0 +1,87 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8de9de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg9: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant dense<0.000000e+00> : tensor<256xbf16>
+    %cst_0 = arith.constant 0.000000e+00 : f32
+    %cst_1 = arith.constant dense<256> : tensor<1xi64>
+    %cst_2 = arith.constant dense<0> : tensor<1xi64>
+    %cst_3 = arith.constant dense<50257> : tensor<1xi64>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_5 = arith.constant dense<2.560000e+02> : tensor<256xf32>
+    %cst_6 = arith.constant dense<2.560000e+02> : tensor<1xf32>
+    %cst_7 = arith.constant dense<-1> : tensor<1xi64>
+    %cst_8 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_8 : tensor<256xi32>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32>
+    %5 = arith.addi %1, %4 : tensor<256xi32>
+    %6 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %8 = tt.load %7, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %9 = arith.extf %8 : tensor<256xbf16> to tensor<256xf32>
+    %10 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %11 = tt.addptr %10, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %12 = tt.load %11, %2, %cst_4 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %13 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %16 = tt.addptr %arg4, %0 : !tt.ptr<f32, 1>, i32
+    %17 = tt.splat %16 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    %18 = tt.load %17 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32>
+    %19 = tt.addptr %arg5, %0 : !tt.ptr<f32, 1>, i32
+    %20 = tt.splat %19 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    %21 = tt.load %20 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32>
+    %22 = tt.addptr %arg6, %0 : !tt.ptr<i64, 1>, i32
+    %23 = tt.splat %22 : (!tt.ptr<i64, 1>) -> tensor<1x!tt.ptr<i64, 1>>
+    %24 = tt.load %23 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xi64>
+    %25 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %26 = tt.addptr %25, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %27 = tt.load %26, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %28 = arith.mulf %9, %12 : tensor<256xf32>
+    %29 = arith.select %2, %28, %cst_4 : tensor<256xi1>, tensor<256xf32>
+    %30 = "tt.reduce"(%29) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %63 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %63 : f32
+    }) : (tensor<256xf32>) -> f32
+    %31 = arith.addf %30, %cst_0 : f32
+    %32 = tt.broadcast %18 : (tensor<1xf32>) -> tensor<256xf32>
+    %33 = arith.subf %15, %32 : tensor<256xf32>
+    %34 = tt.broadcast %21 : (tensor<1xf32>) -> tensor<256xf32>
+    %35 = arith.mulf %33, %34 : tensor<256xf32>
+    %36 = arith.mulf %28, %35 : tensor<256xf32>
+    %37 = arith.select %2, %36, %cst_4 : tensor<256xi1>, tensor<256xf32>
+    %38 = "tt.reduce"(%37) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %63 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %63 : f32
+    }) : (tensor<256xf32>) -> f32
+    %39 = arith.addf %38, %cst_0 : f32
+    %40 = arith.cmpi eq, %24, %cst_7 : tensor<1xi64>
+    %41 = arith.divf %21, %cst_6 : tensor<1xf32>
+    %42 = arith.mulf %28, %cst_5 : tensor<256xf32>
+    %43 = tt.splat %31 : (f32) -> tensor<256xf32>
+    %44 = arith.subf %42, %43 : tensor<256xf32>
+    %45 = tt.splat %39 : (f32) -> tensor<256xf32>
+    %46 = arith.mulf %35, %45 : tensor<256xf32>
+    %47 = arith.subf %44, %46 : tensor<256xf32>
+    %48 = tt.broadcast %41 : (tensor<1xf32>) -> tensor<256xf32>
+    %49 = arith.mulf %48, %47 : tensor<256xf32>
+    %50 = arith.addf %27, %49 : tensor<256xf32>
+    %51 = tt.broadcast %40 : (tensor<1xi1>) -> tensor<256xi1>
+    %52 = arith.select %51, %cst_4, %50 : tensor<256xi1>, tensor<256xf32>
+    %53 = arith.addi %24, %cst_3 : tensor<1xi64>
+    %54 = arith.cmpi slt, %24, %cst_2 : tensor<1xi64>
+    %55 = arith.select %54, %53, %24 : tensor<1xi1>, tensor<1xi64>
+    %56 = arith.muli %55, %cst_1 : tensor<1xi64>
+    %57 = tt.broadcast %56 : (tensor<1xi64>) -> tensor<256xi64>
+    %58 = arith.extsi %1 : tensor<256xi32> to tensor<256xi64>
+    %59 = arith.addi %58, %57 : tensor<256xi64>
+    %60 = tt.splat %arg7 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %61 = tt.addptr %60, %59 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi64>
+    %62 = "tt.atomic_rmw"(%61, %52, %2) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<256x!tt.ptr<f32, 1>>, tensor<256xf32>, tensor<256xi1>) -> tensor<256xf32>
+    tt.return
+  }
+}

.triton/dump/345a87a492fd703c73ab83265a21fcb6/triton_.llir

@@ -0,0 +1,980 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@assertFunc_1 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_1 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_1 = internal constant [39 x i8] c"index out of bounds: 0 <= tmp13 < 50257"
+@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp3 < 50257"
+@global_smem = external local_unnamed_addr addrspace(3) global [0 x i8]
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr
+
+define void @triton__0d1d2d3d4d5de6de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i32 %5, i32 %6) local_unnamed_addr !dbg !7 {
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %9 = lshr i32 %8, 5, !dbg !10
+  %10 = and i32 %9, 7, !dbg !10
+  %11 = and i32 %8, 15, !dbg !10
+  %12 = shl i32 %8, 3, !dbg !11
+  %13 = and i32 %12, 248, !dbg !11
+  %14 = or i32 %13, 4, !dbg !11
+  %urem = and i32 %8, 255, !dbg !11
+  %15 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #6, !dbg !12
+  %16 = shl i32 %15, 4, !dbg !13
+  %17 = or i32 %16, %10, !dbg !14
+  %18 = or i32 %17, 8, !dbg !14
+  %19 = or i32 %16, %11, !dbg !14
+  %20 = sext i32 %17 to i64, !dbg !15
+  %21 = getelementptr i64, ptr addrspace(1) %0, i64 %20, !dbg !15
+  %22 = sext i32 %18 to i64, !dbg !15
+  %23 = getelementptr i64, ptr addrspace(1) %0, i64 %22, !dbg !15
+  %24 = sext i32 %19 to i64, !dbg !15
+  %25 = getelementptr i64, ptr addrspace(1) %0, i64 %24, !dbg !15
+  %26 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %27 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %28 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %29 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %30 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %31 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %32 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %33 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #6, !dbg !16
+  %34 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %35 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %36 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %37 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %38 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %39 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %40 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %41 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %23, i1 true) #6, !dbg !16
+  %42 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %25, i1 true) #6, !dbg !16
+  %43 = srem i32 %17, 512, !dbg !17
+  %44 = srem i32 %18, 512, !dbg !17
+  %45 = shl nsw i32 %43, 8, !dbg !18
+  %46 = shl nsw i32 %44, 8, !dbg !18
+  %47 = or i32 %45, %13, !dbg !19
+  %48 = or i32 %45, %14, !dbg !19
+  %49 = or i32 %46, %13, !dbg !19
+  %50 = or i32 %46, %14, !dbg !19
+  %51 = sext i32 %47 to i64, !dbg !20
+  %52 = getelementptr float, ptr addrspace(1) %2, i64 %51, !dbg !20
+  %53 = sext i32 %48 to i64, !dbg !20
+  %54 = getelementptr float, ptr addrspace(1) %2, i64 %53, !dbg !20
+  %55 = sext i32 %49 to i64, !dbg !20
+  %56 = getelementptr float, ptr addrspace(1) %2, i64 %55, !dbg !20
+  %57 = sext i32 %50 to i64, !dbg !20
+  %58 = getelementptr float, ptr addrspace(1) %2, i64 %57, !dbg !20
+  %59 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %52, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %60 = extractvalue { i32, i32, i32, i32 } %59, 0, !dbg !21
+  %61 = extractvalue { i32, i32, i32, i32 } %59, 1, !dbg !21
+  %62 = extractvalue { i32, i32, i32, i32 } %59, 2, !dbg !21
+  %63 = extractvalue { i32, i32, i32, i32 } %59, 3, !dbg !21
+  %64 = bitcast i32 %60 to float, !dbg !21
+  %65 = bitcast i32 %61 to float, !dbg !21
+  %66 = bitcast i32 %62 to float, !dbg !21
+  %67 = bitcast i32 %63 to float, !dbg !21
+  %68 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %54, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %69 = extractvalue { i32, i32, i32, i32 } %68, 0, !dbg !21
+  %70 = extractvalue { i32, i32, i32, i32 } %68, 1, !dbg !21
+  %71 = extractvalue { i32, i32, i32, i32 } %68, 2, !dbg !21
+  %72 = extractvalue { i32, i32, i32, i32 } %68, 3, !dbg !21
+  %73 = bitcast i32 %69 to float, !dbg !21
+  %74 = bitcast i32 %70 to float, !dbg !21
+  %75 = bitcast i32 %71 to float, !dbg !21
+  %76 = bitcast i32 %72 to float, !dbg !21
+  %77 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %56, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %78 = extractvalue { i32, i32, i32, i32 } %77, 0, !dbg !21
+  %79 = extractvalue { i32, i32, i32, i32 } %77, 1, !dbg !21
+  %80 = extractvalue { i32, i32, i32, i32 } %77, 2, !dbg !21
+  %81 = extractvalue { i32, i32, i32, i32 } %77, 3, !dbg !21
+  %82 = bitcast i32 %78 to float, !dbg !21
+  %83 = bitcast i32 %79 to float, !dbg !21
+  %84 = bitcast i32 %80 to float, !dbg !21
+  %85 = bitcast i32 %81 to float, !dbg !21
+  %86 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %58, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !21
+  %87 = extractvalue { i32, i32, i32, i32 } %86, 0, !dbg !21
+  %88 = extractvalue { i32, i32, i32, i32 } %86, 1, !dbg !21
+  %89 = extractvalue { i32, i32, i32, i32 } %86, 2, !dbg !21
+  %90 = extractvalue { i32, i32, i32, i32 } %86, 3, !dbg !21
+  %91 = bitcast i32 %87 to float, !dbg !21
+  %92 = bitcast i32 %88 to float, !dbg !21
+  %93 = bitcast i32 %89 to float, !dbg !21
+  %94 = bitcast i32 %90 to float, !dbg !21
+  %95 = add i64 %42, 50257, !dbg !22
+  %96 = icmp slt i64 %26, 0, !dbg !23
+  %97 = icmp slt i64 %34, 0, !dbg !23
+  %98 = icmp slt i64 %42, 0, !dbg !23
+  %99 = select i1 %98, i64 %95, i64 %42, !dbg !24
+  %100 = icmp ugt i64 %99, 50256, !dbg !25
+  br i1 %100, label %101, label %102, !dbg !26
+
+101:                                              ; preds = %7
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !26
+  br label %102, !dbg !26
+
+102:                                              ; preds = %101, %7
+  %103 = shl i64 %26, 8, !dbg !27
+  %104 = add i64 %103, 12865792, !dbg !27
+  %105 = select i1 %96, i64 %104, i64 %103, !dbg !27
+  %106 = shl i64 %34, 8, !dbg !27
+  %107 = add i64 %106, 12865792, !dbg !27
+  %108 = select i1 %97, i64 %107, i64 %106, !dbg !27
+  %109 = zext nneg i32 %13 to i64
+  %110 = zext nneg i32 %14 to i64
+  %111 = or i64 %105, %109, !dbg !28
+  %112 = or i64 %105, %110, !dbg !28
+  %113 = or i64 %108, %109, !dbg !28
+  %114 = or i64 %108, %110, !dbg !28
+  %115 = getelementptr float, ptr addrspace(1) %1, i64 %111, !dbg !29
+  %116 = getelementptr float, ptr addrspace(1) %1, i64 %112, !dbg !29
+  %117 = getelementptr float, ptr addrspace(1) %1, i64 %113, !dbg !29
+  %118 = getelementptr float, ptr addrspace(1) %1, i64 %114, !dbg !29
+  %119 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %115, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !30
+  %120 = extractvalue { i32, i32, i32, i32 } %119, 0, !dbg !30
+  %121 = extractvalue { i32, i32, i32, i32 } %119, 1, !dbg !30
+  %122 = extractvalue { i32, i32, i32, i32 } %119, 2, !dbg !30
+  %123 = extractvalue { i32, i32, i32, i32 } %119, 3, !dbg !30
+  %124 = bitcast i32 %120 to float, !dbg !30
+  %125 = bitcast i32 %121 to float, !dbg !30
+  %126 = bitcast i32 %122 to float, !dbg !30
+  %127 = bitcast i32 %123 to float, !dbg !30
+  %128 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %116, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !30
+  %129 = extractvalue { i32, i32, i32, i32 } %128, 0, !dbg !30
+  %130 = extractvalue { i32, i32, i32, i32 } %128, 1, !dbg !30
+  %131 = extractvalue { i32, i32, i32, i32 } %128, 2, !dbg !30
+  %132 = extractvalue { i32, i32, i32, i32 } %128, 3, !dbg !30
+  %133 = bitcast i32 %129 to float, !dbg !30
+  %134 = bitcast i32 %130 to float, !dbg !30
+  %135 = bitcast i32 %131 to float, !dbg !30
+  %136 = bitcast i32 %132 to float, !dbg !30
+  %137 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %117, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !30
+  %138 = extractvalue { i32, i32, i32, i32 } %137, 0, !dbg !30
+  %139 = extractvalue { i32, i32, i32, i32 } %137, 1, !dbg !30
+  %140 = extractvalue { i32, i32, i32, i32 } %137, 2, !dbg !30
+  %141 = extractvalue { i32, i32, i32, i32 } %137, 3, !dbg !30
+  %142 = bitcast i32 %138 to float, !dbg !30
+  %143 = bitcast i32 %139 to float, !dbg !30
+  %144 = bitcast i32 %140 to float, !dbg !30
+  %145 = bitcast i32 %141 to float, !dbg !30
+  %146 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %118, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !30
+  %147 = extractvalue { i32, i32, i32, i32 } %146, 0, !dbg !30
+  %148 = extractvalue { i32, i32, i32, i32 } %146, 1, !dbg !30
+  %149 = extractvalue { i32, i32, i32, i32 } %146, 2, !dbg !30
+  %150 = extractvalue { i32, i32, i32, i32 } %146, 3, !dbg !30
+  %151 = bitcast i32 %147 to float, !dbg !30
+  %152 = bitcast i32 %148 to float, !dbg !30
+  %153 = bitcast i32 %149 to float, !dbg !30
+  %154 = bitcast i32 %150 to float, !dbg !30
+  %155 = fadd float %64, %124, !dbg !31
+  %156 = fadd float %65, %125, !dbg !31
+  %157 = fadd float %66, %126, !dbg !31
+  %158 = fadd float %67, %127, !dbg !31
+  %159 = fadd float %73, %133, !dbg !31
+  %160 = fadd float %74, %134, !dbg !31
+  %161 = fadd float %75, %135, !dbg !31
+  %162 = fadd float %76, %136, !dbg !31
+  %163 = fadd float %82, %142, !dbg !31
+  %164 = fadd float %83, %143, !dbg !31
+  %165 = fadd float %84, %144, !dbg !31
+  %166 = fadd float %85, %145, !dbg !31
+  %167 = fadd float %91, %151, !dbg !31
+  %168 = fadd float %92, %152, !dbg !31
+  %169 = fadd float %93, %153, !dbg !31
+  %170 = fadd float %94, %154, !dbg !31
+  %171 = fadd float %155, 0.000000e+00, !dbg !32
+  %172 = fadd float %156, 0.000000e+00, !dbg !32
+  %173 = fadd float %157, 0.000000e+00, !dbg !32
+  %174 = fadd float %158, 0.000000e+00, !dbg !32
+  %175 = fadd float %159, 0.000000e+00, !dbg !32
+  %176 = fadd float %160, 0.000000e+00, !dbg !32
+  %177 = fadd float %161, 0.000000e+00, !dbg !32
+  %178 = fadd float %162, 0.000000e+00, !dbg !32
+  %179 = fadd float %163, 0.000000e+00, !dbg !32
+  %180 = fadd float %164, 0.000000e+00, !dbg !32
+  %181 = fadd float %165, 0.000000e+00, !dbg !32
+  %182 = fadd float %166, 0.000000e+00, !dbg !32
+  %183 = fadd float %167, 0.000000e+00, !dbg !32
+  %184 = fadd float %168, 0.000000e+00, !dbg !32
+  %185 = fadd float %169, 0.000000e+00, !dbg !32
+  %186 = fadd float %170, 0.000000e+00, !dbg !32
+  %187 = fsub float %155, %171, !dbg !36
+  %188 = fsub float %156, %172, !dbg !36
+  %189 = fsub float %157, %173, !dbg !36
+  %190 = fsub float %158, %174, !dbg !36
+  %191 = fsub float %159, %175, !dbg !36
+  %192 = fsub float %160, %176, !dbg !36
+  %193 = fsub float %161, %177, !dbg !36
+  %194 = fsub float %162, %178, !dbg !36
+  %195 = fsub float %163, %179, !dbg !36
+  %196 = fsub float %164, %180, !dbg !36
+  %197 = fsub float %165, %181, !dbg !36
+  %198 = fsub float %166, %182, !dbg !36
+  %199 = fsub float %167, %183, !dbg !36
+  %200 = fsub float %168, %184, !dbg !36
+  %201 = fsub float %169, %185, !dbg !36
+  %202 = fsub float %170, %186, !dbg !36
+  %203 = fmul float %155, %187, !dbg !37
+  %204 = fmul float %156, %188, !dbg !37
+  %205 = fmul float %157, %189, !dbg !37
+  %206 = fmul float %158, %190, !dbg !37
+  %207 = fmul float %159, %191, !dbg !37
+  %208 = fmul float %160, %192, !dbg !37
+  %209 = fmul float %161, %193, !dbg !37
+  %210 = fmul float %162, %194, !dbg !37
+  %211 = fmul float %163, %195, !dbg !37
+  %212 = fmul float %164, %196, !dbg !37
+  %213 = fmul float %165, %197, !dbg !37
+  %214 = fmul float %166, %198, !dbg !37
+  %215 = fmul float %167, %199, !dbg !37
+  %216 = fmul float %168, %200, !dbg !37
+  %217 = fmul float %169, %201, !dbg !37
+  %218 = fmul float %170, %202, !dbg !37
+  %219 = fadd float %203, 0.000000e+00, !dbg !38
+  %220 = fadd float %204, 0.000000e+00, !dbg !38
+  %221 = fadd float %205, 0.000000e+00, !dbg !38
+  %222 = fadd float %206, 0.000000e+00, !dbg !38
+  %223 = fadd float %207, 0.000000e+00, !dbg !38
+  %224 = fadd float %208, 0.000000e+00, !dbg !38
+  %225 = fadd float %209, 0.000000e+00, !dbg !38
+  %226 = fadd float %210, 0.000000e+00, !dbg !38
+  %227 = fadd float %211, 0.000000e+00, !dbg !38
+  %228 = fadd float %212, 0.000000e+00, !dbg !38
+  %229 = fadd float %213, 0.000000e+00, !dbg !38
+  %230 = fadd float %214, 0.000000e+00, !dbg !38
+  %231 = fadd float %215, 0.000000e+00, !dbg !38
+  %232 = fadd float %216, 0.000000e+00, !dbg !38
+  %233 = fadd float %217, 0.000000e+00, !dbg !38
+  %234 = fadd float %218, 0.000000e+00, !dbg !38
+  %235 = fsub float %172, %171, !dbg !39
+  %236 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 2.000000e+00) #6, !dbg !43
+  %237 = fmul float %236, %235, !dbg !44
+  %238 = fadd float %171, %237, !dbg !45
+  %239 = fadd float %219, %220, !dbg !46
+  %240 = fmul float %235, %235, !dbg !47
+  %241 = fmul float %236, %240, !dbg !48
+  %242 = fadd float %241, %239, !dbg !49
+  %243 = fsub float %173, %238, !dbg !39
+  %244 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 3.000000e+00) #6, !dbg !43
+  %245 = fmul float %244, %243, !dbg !44
+  %246 = fadd float %238, %245, !dbg !45
+  %247 = fadd float %221, %242, !dbg !46
+  %248 = fmul float %243, %243, !dbg !47
+  %249 = fmul float %248, 2.000000e+00, !dbg !50
+  %250 = fmul float %244, %249, !dbg !48
+  %251 = fadd float %247, %250, !dbg !49
+  %252 = fsub float %174, %246, !dbg !39
+  %253 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 4.000000e+00) #6, !dbg !43
+  %254 = fmul float %253, %252, !dbg !44
+  %255 = fadd float %246, %254, !dbg !45
+  %256 = fadd float %222, %251, !dbg !46
+  %257 = fmul float %252, %252, !dbg !47
+  %258 = fmul float %257, 3.000000e+00, !dbg !50
+  %259 = fmul float %253, %258, !dbg !48
+  %260 = fadd float %256, %259, !dbg !49
+  %261 = fsub float %175, %255, !dbg !39
+  %262 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 5.000000e+00) #6, !dbg !43
+  %263 = fmul float %262, %261, !dbg !44
+  %264 = fadd float %255, %263, !dbg !45
+  %265 = fadd float %223, %260, !dbg !46
+  %266 = fmul float %261, %261, !dbg !47
+  %267 = fmul float %266, 4.000000e+00, !dbg !50
+  %268 = fmul float %262, %267, !dbg !48
+  %269 = fadd float %265, %268, !dbg !49
+  %270 = fsub float %176, %264, !dbg !39
+  %271 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 6.000000e+00) #6, !dbg !43
+  %272 = fmul float %271, %270, !dbg !44
+  %273 = fadd float %264, %272, !dbg !45
+  %274 = fadd float %224, %269, !dbg !46
+  %275 = fmul float %270, %270, !dbg !47
+  %276 = fmul float %275, 5.000000e+00, !dbg !50
+  %277 = fmul float %271, %276, !dbg !48
+  %278 = fadd float %274, %277, !dbg !49
+  %279 = fsub float %177, %273, !dbg !39
+  %280 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 7.000000e+00) #6, !dbg !43
+  %281 = fmul float %280, %279, !dbg !44
+  %282 = fadd float %273, %281, !dbg !45
+  %283 = fadd float %225, %278, !dbg !46
+  %284 = fmul float %279, %279, !dbg !47
+  %285 = fmul float %284, 6.000000e+00, !dbg !50
+  %286 = fmul float %280, %285, !dbg !48
+  %287 = fadd float %283, %286, !dbg !49
+  %288 = fsub float %178, %282, !dbg !39
+  %289 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 8.000000e+00) #6, !dbg !43
+  %290 = fmul float %289, %288, !dbg !44
+  %291 = fadd float %282, %290, !dbg !45
+  %292 = fadd float %226, %287, !dbg !46
+  %293 = fmul float %288, %288, !dbg !47
+  %294 = fmul float %293, 7.000000e+00, !dbg !50
+  %295 = fmul float %289, %294, !dbg !48
+  %296 = fadd float %292, %295, !dbg !49
+  %297 = fsub float %180, %179, !dbg !39
+  %298 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 2.000000e+00) #6, !dbg !43
+  %299 = fmul float %297, %298, !dbg !44
+  %300 = fadd float %179, %299, !dbg !45
+  %301 = fadd float %227, %228, !dbg !46
+  %302 = fmul float %297, %297, !dbg !47
+  %303 = fmul float %302, %298, !dbg !48
+  %304 = fadd float %301, %303, !dbg !49
+  %305 = fsub float %181, %300, !dbg !39
+  %306 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 3.000000e+00) #6, !dbg !43
+  %307 = fmul float %306, %305, !dbg !44
+  %308 = fadd float %300, %307, !dbg !45
+  %309 = fadd float %229, %304, !dbg !46
+  %310 = fmul float %305, %305, !dbg !47
+  %311 = fmul float %310, 2.000000e+00, !dbg !50
+  %312 = fmul float %306, %311, !dbg !48
+  %313 = fadd float %309, %312, !dbg !49
+  %314 = fsub float %182, %308, !dbg !39
+  %315 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 4.000000e+00) #6, !dbg !43
+  %316 = fmul float %315, %314, !dbg !44
+  %317 = fadd float %308, %316, !dbg !45
+  %318 = fadd float %230, %313, !dbg !46
+  %319 = fmul float %314, %314, !dbg !47
+  %320 = fmul float %319, 3.000000e+00, !dbg !50
+  %321 = fmul float %315, %320, !dbg !48
+  %322 = fadd float %318, %321, !dbg !49
+  %323 = fsub float %183, %317, !dbg !39
+  %324 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 5.000000e+00) #6, !dbg !43
+  %325 = fmul float %324, %323, !dbg !44
+  %326 = fadd float %317, %325, !dbg !45
+  %327 = fadd float %231, %322, !dbg !46
+  %328 = fmul float %323, %323, !dbg !47
+  %329 = fmul float %328, 4.000000e+00, !dbg !50
+  %330 = fmul float %324, %329, !dbg !48
+  %331 = fadd float %327, %330, !dbg !49
+  %332 = fsub float %184, %326, !dbg !39
+  %333 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 6.000000e+00) #6, !dbg !43
+  %334 = fmul float %333, %332, !dbg !44
+  %335 = fadd float %326, %334, !dbg !45
+  %336 = fadd float %232, %331, !dbg !46
+  %337 = fmul float %332, %332, !dbg !47
+  %338 = fmul float %337, 5.000000e+00, !dbg !50
+  %339 = fmul float %333, %338, !dbg !48
+  %340 = fadd float %336, %339, !dbg !49
+  %341 = fsub float %185, %335, !dbg !39
+  %342 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 7.000000e+00) #6, !dbg !43
+  %343 = fmul float %342, %341, !dbg !44
+  %344 = fadd float %335, %343, !dbg !45
+  %345 = fadd float %233, %340, !dbg !46
+  %346 = fmul float %341, %341, !dbg !47
+  %347 = fmul float %346, 6.000000e+00, !dbg !50
+  %348 = fmul float %342, %347, !dbg !48
+  %349 = fadd float %345, %348, !dbg !49
+  %350 = fsub float %186, %344, !dbg !39
+  %351 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float 1.000000e+00, float 8.000000e+00) #6, !dbg !43
+  %352 = fmul float %351, %350, !dbg !44
+  %353 = fadd float %344, %352, !dbg !45
+  %354 = fadd float %234, %349, !dbg !46
+  %355 = fmul float %350, %350, !dbg !47
+  %356 = fmul float %355, 7.000000e+00, !dbg !50
+  %357 = fmul float %351, %356, !dbg !48
+  %358 = fadd float %354, %357, !dbg !49
+  %359 = bitcast float %291 to i32, !dbg !51
+  %360 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %359, i32 16, i32 31), !dbg !51
+  %361 = bitcast i32 %360 to float, !dbg !51
+  %362 = bitcast float %296 to i32, !dbg !51
+  %363 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %362, i32 16, i32 31), !dbg !51
+  %364 = bitcast i32 %363 to float, !dbg !51
+  %365 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 1090519040, i32 16, i32 31), !dbg !51
+  %366 = bitcast i32 %365 to float, !dbg !51
+  %367 = fsub float %361, %291, !dbg !39
+  %368 = fadd float %366, 8.000000e+00, !dbg !53
+  %369 = fcmp oeq float %368, 0.000000e+00, !dbg !54
+  %370 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %366, float %368) #6, !dbg !43
+  %371 = select i1 %369, float 0.000000e+00, float %370, !dbg !55
+  %372 = fmul float %371, %367, !dbg !44
+  %373 = fadd float %291, %372, !dbg !45
+  %374 = fadd float %296, %364, !dbg !46
+  %375 = fmul float %367, %367, !dbg !47
+  %376 = fmul float %375, 8.000000e+00, !dbg !50
+  %377 = fmul float %371, %376, !dbg !48
+  %378 = fadd float %374, %377, !dbg !49
+  %379 = bitcast float %373 to i32, !dbg !51
+  %380 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %379, i32 8, i32 31), !dbg !51
+  %381 = bitcast i32 %380 to float, !dbg !51
+  %382 = bitcast float %378 to i32, !dbg !51
+  %383 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %382, i32 8, i32 31), !dbg !51
+  %384 = bitcast i32 %383 to float, !dbg !51
+  %385 = bitcast float %368 to i32, !dbg !51
+  %386 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %385, i32 8, i32 31), !dbg !51
+  %387 = bitcast i32 %386 to float, !dbg !51
+  %388 = fsub float %381, %373, !dbg !39
+  %389 = fadd float %368, %387, !dbg !53
+  %390 = fcmp oeq float %389, 0.000000e+00, !dbg !54
+  %391 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %387, float %389) #6, !dbg !43
+  %392 = select i1 %390, float 0.000000e+00, float %391, !dbg !55
+  %393 = fmul float %392, %388, !dbg !44
+  %394 = fadd float %373, %393, !dbg !45
+  %395 = fadd float %378, %384, !dbg !46
+  %396 = fmul float %388, %388, !dbg !47
+  %397 = fmul float %368, %396, !dbg !50
+  %398 = fmul float %392, %397, !dbg !48
+  %399 = fadd float %395, %398, !dbg !49
+  %400 = bitcast float %394 to i32, !dbg !51
+  %401 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %400, i32 4, i32 31), !dbg !51
+  %402 = bitcast i32 %401 to float, !dbg !51
+  %403 = bitcast float %399 to i32, !dbg !51
+  %404 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %403, i32 4, i32 31), !dbg !51
+  %405 = bitcast i32 %404 to float, !dbg !51
+  %406 = bitcast float %389 to i32, !dbg !51
+  %407 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %406, i32 4, i32 31), !dbg !51
+  %408 = bitcast i32 %407 to float, !dbg !51
+  %409 = fsub float %402, %394, !dbg !39
+  %410 = fadd float %389, %408, !dbg !53
+  %411 = fcmp oeq float %410, 0.000000e+00, !dbg !54
+  %412 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %408, float %410) #6, !dbg !43
+  %413 = select i1 %411, float 0.000000e+00, float %412, !dbg !55
+  %414 = fmul float %409, %413, !dbg !44
+  %415 = fadd float %394, %414, !dbg !45
+  %416 = fadd float %399, %405, !dbg !46
+  %417 = fmul float %409, %409, !dbg !47
+  %418 = fmul float %389, %417, !dbg !50
+  %419 = fmul float %413, %418, !dbg !48
+  %420 = fadd float %416, %419, !dbg !49
+  %421 = bitcast float %415 to i32, !dbg !51
+  %422 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %421, i32 2, i32 31), !dbg !51
+  %423 = bitcast i32 %422 to float, !dbg !51
+  %424 = bitcast float %420 to i32, !dbg !51
+  %425 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %424, i32 2, i32 31), !dbg !51
+  %426 = bitcast i32 %425 to float, !dbg !51
+  %427 = bitcast float %410 to i32, !dbg !51
+  %428 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %427, i32 2, i32 31), !dbg !51
+  %429 = bitcast i32 %428 to float, !dbg !51
+  %430 = fsub float %423, %415, !dbg !39
+  %431 = fadd float %410, %429, !dbg !53
+  %432 = fcmp oeq float %431, 0.000000e+00, !dbg !54
+  %433 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %429, float %431) #6, !dbg !43
+  %434 = select i1 %432, float 0.000000e+00, float %433, !dbg !55
+  %435 = fmul float %430, %434, !dbg !44
+  %436 = fadd float %415, %435, !dbg !45
+  %437 = fadd float %420, %426, !dbg !46
+  %438 = fmul float %430, %430, !dbg !47
+  %439 = fmul float %410, %438, !dbg !50
+  %440 = fmul float %434, %439, !dbg !48
+  %441 = fadd float %437, %440, !dbg !49
+  %442 = bitcast float %436 to i32, !dbg !51
+  %443 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %442, i32 1, i32 31), !dbg !51
+  %444 = bitcast float %441 to i32, !dbg !51
+  %445 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %444, i32 1, i32 31), !dbg !51
+  %446 = bitcast float %431 to i32, !dbg !51
+  %447 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %446, i32 1, i32 31), !dbg !51
+  %448 = bitcast i32 %447 to float, !dbg !51
+  %449 = fadd float %431, %448, !dbg !53
+  %450 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %448, float %449) #6, !dbg !43
+  %451 = bitcast float %353 to i32, !dbg !51
+  %452 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %451, i32 16, i32 31), !dbg !51
+  %453 = bitcast i32 %452 to float, !dbg !51
+  %454 = bitcast float %358 to i32, !dbg !51
+  %455 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %454, i32 16, i32 31), !dbg !51
+  %456 = bitcast i32 %455 to float, !dbg !51
+  %457 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 1090519040, i32 16, i32 31), !dbg !51
+  %458 = bitcast i32 %457 to float, !dbg !51
+  %459 = fsub float %453, %353, !dbg !39
+  %460 = fadd float %458, 8.000000e+00, !dbg !53
+  %461 = fcmp oeq float %460, 0.000000e+00, !dbg !54
+  %462 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %458, float %460) #6, !dbg !43
+  %463 = select i1 %461, float 0.000000e+00, float %462, !dbg !55
+  %464 = fmul float %459, %463, !dbg !44
+  %465 = fadd float %353, %464, !dbg !45
+  %466 = fadd float %358, %456, !dbg !46
+  %467 = fmul float %459, %459, !dbg !47
+  %468 = fmul float %467, 8.000000e+00, !dbg !50
+  %469 = fmul float %468, %463, !dbg !48
+  %470 = fadd float %466, %469, !dbg !49
+  %471 = bitcast float %465 to i32, !dbg !51
+  %472 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %471, i32 8, i32 31), !dbg !51
+  %473 = bitcast i32 %472 to float, !dbg !51
+  %474 = bitcast float %470 to i32, !dbg !51
+  %475 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %474, i32 8, i32 31), !dbg !51
+  %476 = bitcast i32 %475 to float, !dbg !51
+  %477 = bitcast float %460 to i32, !dbg !51
+  %478 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %477, i32 8, i32 31), !dbg !51
+  %479 = bitcast i32 %478 to float, !dbg !51
+  %480 = fsub float %473, %465, !dbg !39
+  %481 = fadd float %460, %479, !dbg !53
+  %482 = fcmp oeq float %481, 0.000000e+00, !dbg !54
+  %483 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %479, float %481) #6, !dbg !43
+  %484 = select i1 %482, float 0.000000e+00, float %483, !dbg !55
+  %485 = fmul float %480, %484, !dbg !44
+  %486 = fadd float %465, %485, !dbg !45
+  %487 = fadd float %470, %476, !dbg !46
+  %488 = fmul float %480, %480, !dbg !47
+  %489 = fmul float %460, %488, !dbg !50
+  %490 = fmul float %484, %489, !dbg !48
+  %491 = fadd float %487, %490, !dbg !49
+  %492 = bitcast float %486 to i32, !dbg !51
+  %493 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %492, i32 4, i32 31), !dbg !51
+  %494 = bitcast i32 %493 to float, !dbg !51
+  %495 = bitcast float %491 to i32, !dbg !51
+  %496 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %495, i32 4, i32 31), !dbg !51
+  %497 = bitcast i32 %496 to float, !dbg !51
+  %498 = bitcast float %481 to i32, !dbg !51
+  %499 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %498, i32 4, i32 31), !dbg !51
+  %500 = bitcast i32 %499 to float, !dbg !51
+  %501 = fsub float %494, %486, !dbg !39
+  %502 = fadd float %481, %500, !dbg !53
+  %503 = fcmp oeq float %502, 0.000000e+00, !dbg !54
+  %504 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %500, float %502) #6, !dbg !43
+  %505 = select i1 %503, float 0.000000e+00, float %504, !dbg !55
+  %506 = fmul float %501, %505, !dbg !44
+  %507 = fadd float %486, %506, !dbg !45
+  %508 = fadd float %491, %497, !dbg !46
+  %509 = fmul float %501, %501, !dbg !47
+  %510 = fmul float %481, %509, !dbg !50
+  %511 = fmul float %505, %510, !dbg !48
+  %512 = fadd float %508, %511, !dbg !49
+  %513 = bitcast float %507 to i32, !dbg !51
+  %514 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %513, i32 2, i32 31), !dbg !51
+  %515 = bitcast i32 %514 to float, !dbg !51
+  %516 = bitcast float %512 to i32, !dbg !51
+  %517 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %516, i32 2, i32 31), !dbg !51
+  %518 = bitcast i32 %517 to float, !dbg !51
+  %519 = bitcast float %502 to i32, !dbg !51
+  %520 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %519, i32 2, i32 31), !dbg !51
+  %521 = bitcast i32 %520 to float, !dbg !51
+  %522 = fsub float %515, %507, !dbg !39
+  %523 = fadd float %502, %521, !dbg !53
+  %524 = fcmp oeq float %523, 0.000000e+00, !dbg !54
+  %525 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %521, float %523) #6, !dbg !43
+  %526 = select i1 %524, float 0.000000e+00, float %525, !dbg !55
+  %527 = fmul float %522, %526, !dbg !44
+  %528 = fadd float %507, %527, !dbg !45
+  %529 = fadd float %512, %518, !dbg !46
+  %530 = fmul float %522, %522, !dbg !47
+  %531 = fmul float %502, %530, !dbg !50
+  %532 = fmul float %526, %531, !dbg !48
+  %533 = fadd float %529, %532, !dbg !49
+  %534 = bitcast float %528 to i32, !dbg !51
+  %535 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %534, i32 1, i32 31), !dbg !51
+  %536 = bitcast float %533 to i32, !dbg !51
+  %537 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %536, i32 1, i32 31), !dbg !51
+  %538 = bitcast float %523 to i32, !dbg !51
+  %539 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %538, i32 1, i32 31), !dbg !51
+  %540 = bitcast i32 %539 to float, !dbg !51
+  %541 = fadd float %523, %540, !dbg !53
+  %542 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %540, float %541) #6, !dbg !43
+  %543 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %52, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !56
+  %544 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %54, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !56
+  %545 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %56, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !56
+  %546 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %58, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !56
+  %547 = zext nneg i32 %urem to i64, !dbg !57
+  %548 = getelementptr float, ptr addrspace(1) %3, i64 %547, !dbg !57
+  %549 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %548, i1 true, i32 0, i1 true) #6, !dbg !58
+  br i1 %100, label %550, label %551, !dbg !59
+
+550:                                              ; preds = %102
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 883, ptr nonnull @assertFunc_1, i64 1), !dbg !59
+  br label %551, !dbg !59
+
+551:                                              ; preds = %550, %102
+  %552 = bitcast i32 %537 to float, !dbg !51
+  %553 = fadd float %533, %552, !dbg !46
+  %554 = bitcast i32 %535 to float, !dbg !51
+  %555 = fsub float %554, %528, !dbg !39
+  %556 = fmul float %555, %555, !dbg !47
+  %557 = fmul float %523, %556, !dbg !50
+  %558 = fcmp oeq float %541, 0.000000e+00, !dbg !54
+  %559 = select i1 %558, float 0.000000e+00, float %542, !dbg !55
+  %560 = fmul float %559, %557, !dbg !48
+  %561 = fadd float %553, %560, !dbg !49
+  %562 = bitcast i32 %445 to float, !dbg !51
+  %563 = fadd float %441, %562, !dbg !46
+  %564 = bitcast i32 %443 to float, !dbg !51
+  %565 = fsub float %564, %436, !dbg !39
+  %566 = fmul float %565, %565, !dbg !47
+  %567 = fmul float %431, %566, !dbg !50
+  %568 = fcmp oeq float %449, 0.000000e+00, !dbg !54
+  %569 = select i1 %568, float 0.000000e+00, float %450, !dbg !55
+  %570 = fmul float %569, %567, !dbg !48
+  %571 = fadd float %563, %570, !dbg !49
+  %572 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %115, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !60
+  %573 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %116, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !60
+  %574 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %117, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !60
+  %575 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %118, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #6, !dbg !60
+  %576 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %577 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %578 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %579 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %580 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %581 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %582 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %583 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %571, float 2.560000e+02) #6, !dbg !61
+  %584 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %585 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %586 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %587 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %588 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %589 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %590 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %591 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %561, float 2.560000e+02) #6, !dbg !61
+  %592 = fadd float %576, 0x3EE4F8B580000000, !dbg !62
+  %593 = fadd float %584, 0x3EE4F8B580000000, !dbg !62
+  %594 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %.not.i = icmp eq i32 %594, 0, !dbg !63
+  br i1 %.not.i, label %597, label %595, !dbg !63
+
+595:                                              ; preds = %551
+  %596 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %592), !dbg !63
+  br label %__nv_rsqrtf.exit, !dbg !63
+
+597:                                              ; preds = %551
+  %598 = tail call float @llvm.nvvm.rsqrt.approx.f(float %592), !dbg !63
+  br label %__nv_rsqrtf.exit, !dbg !63
+
+__nv_rsqrtf.exit:                                 ; preds = %595, %597
+  %.0.i = phi float [ %596, %595 ], [ %598, %597 ], !dbg !63
+  %599 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %600 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %601 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %602 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %603 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %604 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %605 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %606 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %.not.i22 = icmp eq i32 %606, 0, !dbg !63
+  br i1 %.not.i22, label %609, label %607, !dbg !63
+
+607:                                              ; preds = %__nv_rsqrtf.exit
+  %608 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %593), !dbg !63
+  br label %__nv_rsqrtf.exit24, !dbg !63
+
+609:                                              ; preds = %__nv_rsqrtf.exit
+  %610 = tail call float @llvm.nvvm.rsqrt.approx.f(float %593), !dbg !63
+  br label %__nv_rsqrtf.exit24, !dbg !63
+
+__nv_rsqrtf.exit24:                               ; preds = %607, %609
+  %.0.i23 = phi float [ %608, %607 ], [ %610, %609 ], !dbg !63
+  %611 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %612 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %613 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %614 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %615 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %616 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %617 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !63
+  %618 = extractvalue { i32, i32, i32, i32 } %575, 3, !dbg !60
+  %619 = bitcast i32 %618 to float, !dbg !60
+  %620 = extractvalue { i32, i32, i32, i32 } %546, 3, !dbg !56
+  %621 = bitcast i32 %620 to float, !dbg !56
+  %622 = fadd float %621, %619, !dbg !64
+  %623 = fmul float %555, %559, !dbg !44
+  %624 = fadd float %528, %623, !dbg !45
+  %625 = fsub float %622, %624, !dbg !65
+  %626 = extractvalue { i32, i32, i32, i32 } %575, 2, !dbg !60
+  %627 = bitcast i32 %626 to float, !dbg !60
+  %628 = extractvalue { i32, i32, i32, i32 } %546, 2, !dbg !56
+  %629 = bitcast i32 %628 to float, !dbg !56
+  %630 = fadd float %629, %627, !dbg !64
+  %631 = fsub float %630, %624, !dbg !65
+  %632 = extractvalue { i32, i32, i32, i32 } %575, 1, !dbg !60
+  %633 = bitcast i32 %632 to float, !dbg !60
+  %634 = extractvalue { i32, i32, i32, i32 } %546, 1, !dbg !56
+  %635 = bitcast i32 %634 to float, !dbg !56
+  %636 = fadd float %635, %633, !dbg !64
+  %637 = fsub float %636, %624, !dbg !65
+  %638 = extractvalue { i32, i32, i32, i32 } %575, 0, !dbg !60
+  %639 = bitcast i32 %638 to float, !dbg !60
+  %640 = extractvalue { i32, i32, i32, i32 } %546, 0, !dbg !56
+  %641 = bitcast i32 %640 to float, !dbg !56
+  %642 = fadd float %641, %639, !dbg !64
+  %643 = fsub float %642, %624, !dbg !65
+  %644 = extractvalue { i32, i32, i32, i32 } %574, 3, !dbg !60
+  %645 = bitcast i32 %644 to float, !dbg !60
+  %646 = extractvalue { i32, i32, i32, i32 } %545, 3, !dbg !56
+  %647 = bitcast i32 %646 to float, !dbg !56
+  %648 = fadd float %647, %645, !dbg !64
+  %649 = fsub float %648, %624, !dbg !65
+  %650 = extractvalue { i32, i32, i32, i32 } %574, 2, !dbg !60
+  %651 = bitcast i32 %650 to float, !dbg !60
+  %652 = extractvalue { i32, i32, i32, i32 } %545, 2, !dbg !56
+  %653 = bitcast i32 %652 to float, !dbg !56
+  %654 = fadd float %653, %651, !dbg !64
+  %655 = fsub float %654, %624, !dbg !65
+  %656 = extractvalue { i32, i32, i32, i32 } %574, 1, !dbg !60
+  %657 = bitcast i32 %656 to float, !dbg !60
+  %658 = extractvalue { i32, i32, i32, i32 } %545, 1, !dbg !56
+  %659 = bitcast i32 %658 to float, !dbg !56
+  %660 = fadd float %659, %657, !dbg !64
+  %661 = fsub float %660, %624, !dbg !65
+  %662 = extractvalue { i32, i32, i32, i32 } %574, 0, !dbg !60
+  %663 = bitcast i32 %662 to float, !dbg !60
+  %664 = extractvalue { i32, i32, i32, i32 } %545, 0, !dbg !56
+  %665 = bitcast i32 %664 to float, !dbg !56
+  %666 = fadd float %665, %663, !dbg !64
+  %667 = fsub float %666, %624, !dbg !65
+  %668 = extractvalue { i32, i32, i32, i32 } %573, 3, !dbg !60
+  %669 = bitcast i32 %668 to float, !dbg !60
+  %670 = extractvalue { i32, i32, i32, i32 } %544, 3, !dbg !56
+  %671 = bitcast i32 %670 to float, !dbg !56
+  %672 = fadd float %671, %669, !dbg !64
+  %673 = fmul float %565, %569, !dbg !44
+  %674 = fadd float %436, %673, !dbg !45
+  %675 = fsub float %672, %674, !dbg !65
+  %676 = extractvalue { i32, i32, i32, i32 } %573, 2, !dbg !60
+  %677 = bitcast i32 %676 to float, !dbg !60
+  %678 = extractvalue { i32, i32, i32, i32 } %544, 2, !dbg !56
+  %679 = bitcast i32 %678 to float, !dbg !56
+  %680 = fadd float %679, %677, !dbg !64
+  %681 = fsub float %680, %674, !dbg !65
+  %682 = extractvalue { i32, i32, i32, i32 } %573, 1, !dbg !60
+  %683 = bitcast i32 %682 to float, !dbg !60
+  %684 = extractvalue { i32, i32, i32, i32 } %544, 1, !dbg !56
+  %685 = bitcast i32 %684 to float, !dbg !56
+  %686 = fadd float %685, %683, !dbg !64
+  %687 = fsub float %686, %674, !dbg !65
+  %688 = extractvalue { i32, i32, i32, i32 } %573, 0, !dbg !60
+  %689 = bitcast i32 %688 to float, !dbg !60
+  %690 = extractvalue { i32, i32, i32, i32 } %544, 0, !dbg !56
+  %691 = bitcast i32 %690 to float, !dbg !56
+  %692 = fadd float %691, %689, !dbg !64
+  %693 = fsub float %692, %674, !dbg !65
+  %694 = extractvalue { i32, i32, i32, i32 } %572, 3, !dbg !60
+  %695 = bitcast i32 %694 to float, !dbg !60
+  %696 = extractvalue { i32, i32, i32, i32 } %543, 3, !dbg !56
+  %697 = bitcast i32 %696 to float, !dbg !56
+  %698 = fadd float %697, %695, !dbg !64
+  %699 = fsub float %698, %674, !dbg !65
+  %700 = extractvalue { i32, i32, i32, i32 } %572, 2, !dbg !60
+  %701 = bitcast i32 %700 to float, !dbg !60
+  %702 = extractvalue { i32, i32, i32, i32 } %543, 2, !dbg !56
+  %703 = bitcast i32 %702 to float, !dbg !56
+  %704 = fadd float %703, %701, !dbg !64
+  %705 = fsub float %704, %674, !dbg !65
+  %706 = extractvalue { i32, i32, i32, i32 } %572, 1, !dbg !60
+  %707 = bitcast i32 %706 to float, !dbg !60
+  %708 = extractvalue { i32, i32, i32, i32 } %543, 1, !dbg !56
+  %709 = bitcast i32 %708 to float, !dbg !56
+  %710 = fadd float %709, %707, !dbg !64
+  %711 = fsub float %710, %674, !dbg !65
+  %712 = extractvalue { i32, i32, i32, i32 } %572, 0, !dbg !60
+  %713 = bitcast i32 %712 to float, !dbg !60
+  %714 = extractvalue { i32, i32, i32, i32 } %543, 0, !dbg !56
+  %715 = bitcast i32 %714 to float, !dbg !56
+  %716 = fadd float %715, %713, !dbg !64
+  %717 = fsub float %716, %674, !dbg !65
+  %718 = fmul float %717, %.0.i, !dbg !66
+  %719 = fmul float %711, %.0.i, !dbg !66
+  %720 = fmul float %705, %.0.i, !dbg !66
+  %721 = fmul float %699, %.0.i, !dbg !66
+  %722 = fmul float %693, %.0.i, !dbg !66
+  %723 = fmul float %687, %.0.i, !dbg !66
+  %724 = fmul float %681, %.0.i, !dbg !66
+  %725 = fmul float %675, %.0.i, !dbg !66
+  %726 = fmul float %667, %.0.i23, !dbg !66
+  %727 = fmul float %661, %.0.i23, !dbg !66
+  %728 = fmul float %655, %.0.i23, !dbg !66
+  %729 = fmul float %649, %.0.i23, !dbg !66
+  %730 = fmul float %643, %.0.i23, !dbg !66
+  %731 = fmul float %637, %.0.i23, !dbg !66
+  %732 = fmul float %631, %.0.i23, !dbg !66
+  %733 = fmul float %625, %.0.i23, !dbg !66
+  %734 = getelementptr float, ptr addrspace(3) @global_smem, i64 %547, !dbg !67
+  store i32 %549, ptr addrspace(3) %734, align 4, !dbg !67
+  tail call void @llvm.nvvm.barrier0(), !dbg !67
+  %735 = getelementptr float, ptr addrspace(3) @global_smem, i64 %109, !dbg !67
+  %736 = load float, ptr addrspace(3) %735, align 32, !dbg !67
+  %737 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 1, !dbg !67
+  %738 = load float, ptr addrspace(3) %737, align 4, !dbg !67
+  %739 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 2, !dbg !67
+  %740 = load float, ptr addrspace(3) %739, align 8, !dbg !67
+  %741 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 3, !dbg !67
+  %742 = load float, ptr addrspace(3) %741, align 4, !dbg !67
+  %743 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 4, !dbg !67
+  %744 = load float, ptr addrspace(3) %743, align 16, !dbg !67
+  %745 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 5, !dbg !67
+  %746 = load float, ptr addrspace(3) %745, align 4, !dbg !67
+  %747 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 6, !dbg !67
+  %748 = load float, ptr addrspace(3) %747, align 8, !dbg !67
+  %749 = getelementptr inbounds <8 x float>, ptr addrspace(3) %735, i64 0, i64 7, !dbg !67
+  %750 = load float, ptr addrspace(3) %749, align 4, !dbg !67
+  %751 = fmul float %718, %736, !dbg !67
+  %752 = fmul float %719, %738, !dbg !67
+  %753 = fmul float %720, %740, !dbg !67
+  %754 = fmul float %721, %742, !dbg !67
+  %755 = fmul float %722, %744, !dbg !67
+  %756 = fmul float %723, %746, !dbg !67
+  %757 = fmul float %724, %748, !dbg !67
+  %758 = fmul float %725, %750, !dbg !67
+  %759 = fmul float %726, %736, !dbg !67
+  %760 = fmul float %727, %738, !dbg !67
+  %761 = fmul float %728, %740, !dbg !67
+  %762 = fmul float %729, %742, !dbg !67
+  %763 = fmul float %730, %744, !dbg !67
+  %764 = fmul float %731, %746, !dbg !67
+  %765 = fmul float %732, %748, !dbg !67
+  %766 = fmul float %733, %750, !dbg !67
+  %767 = shl i32 %17, 8, !dbg !68
+  %768 = shl i32 %18, 8, !dbg !68
+  %769 = or i32 %767, %13, !dbg !69
+  %770 = or i32 %768, %13, !dbg !69
+  %771 = sext i32 %769 to i64, !dbg !70
+  %772 = getelementptr i16, ptr addrspace(1) %4, i64 %771, !dbg !70
+  %773 = sext i32 %770 to i64, !dbg !70
+  %774 = getelementptr i16, ptr addrspace(1) %4, i64 %773, !dbg !70
+  %775 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %751) #6, !dbg !71
+  %776 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %752) #6, !dbg !71
+  %777 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %753) #6, !dbg !71
+  %778 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %754) #6, !dbg !71
+  %779 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %755) #6, !dbg !71
+  %780 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %756) #6, !dbg !71
+  %781 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %757) #6, !dbg !71
+  %782 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %758) #6, !dbg !71
+  %783 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %759) #6, !dbg !71
+  %784 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %760) #6, !dbg !71
+  %785 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %761) #6, !dbg !71
+  %786 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %762) #6, !dbg !71
+  %787 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %763) #6, !dbg !71
+  %788 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %764) #6, !dbg !71
+  %789 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %765) #6, !dbg !71
+  %790 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %766) #6, !dbg !71
+  %791 = insertelement <2 x i16> undef, i16 %775, i64 0, !dbg !71
+  %792 = insertelement <2 x i16> %791, i16 %776, i64 1, !dbg !71
+  %793 = bitcast <2 x i16> %792 to i32, !dbg !71
+  %794 = insertelement <2 x i16> undef, i16 %777, i64 0, !dbg !71
+  %795 = insertelement <2 x i16> %794, i16 %778, i64 1, !dbg !71
+  %796 = bitcast <2 x i16> %795 to i32, !dbg !71
+  %797 = insertelement <2 x i16> undef, i16 %779, i64 0, !dbg !71
+  %798 = insertelement <2 x i16> %797, i16 %780, i64 1, !dbg !71
+  %799 = bitcast <2 x i16> %798 to i32, !dbg !71
+  %800 = insertelement <2 x i16> undef, i16 %781, i64 0, !dbg !71
+  %801 = insertelement <2 x i16> %800, i16 %782, i64 1, !dbg !71
+  %802 = bitcast <2 x i16> %801 to i32, !dbg !71
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %793, i32 %796, i32 %799, i32 %802, ptr addrspace(1) %772, i1 true) #6, !dbg !71
+  %803 = insertelement <2 x i16> undef, i16 %783, i64 0, !dbg !71
+  %804 = insertelement <2 x i16> %803, i16 %784, i64 1, !dbg !71
+  %805 = bitcast <2 x i16> %804 to i32, !dbg !71
+  %806 = insertelement <2 x i16> undef, i16 %785, i64 0, !dbg !71
+  %807 = insertelement <2 x i16> %806, i16 %786, i64 1, !dbg !71
+  %808 = bitcast <2 x i16> %807 to i32, !dbg !71
+  %809 = insertelement <2 x i16> undef, i16 %787, i64 0, !dbg !71
+  %810 = insertelement <2 x i16> %809, i16 %788, i64 1, !dbg !71
+  %811 = bitcast <2 x i16> %810 to i32, !dbg !71
+  %812 = insertelement <2 x i16> undef, i16 %789, i64 0, !dbg !71
+  %813 = insertelement <2 x i16> %812, i16 %790, i64 1, !dbg !71
+  %814 = bitcast <2 x i16> %813 to i32, !dbg !71
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %805, i32 %808, i32 %811, i32 %814, ptr addrspace(1) %774, i1 true) #6, !dbg !71
+  ret void, !dbg !72
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #3 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #5
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cgx5lxpuexpindj4dsmjz5x42uhyy7iskevq7ovzpwagb3t5powj.py", directory: "/tmp/torchinductor_root/gx")
+!4 = !{ptr @triton__0d1d2d3d4d5de6de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5de6de, !"maxntidx", i32 256}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5de6de", linkageName: "triton__0d1d2d3d4d5de6de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 22, column: 44, scope: !7)
+!11 = !DILocation(line: 24, column: 33, scope: !7)
+!12 = !DILocation(line: 21, column: 28, scope: !7)
+!13 = !DILocation(line: 21, column: 33, scope: !7)
+!14 = !DILocation(line: 22, column: 23, scope: !7)
+!15 = !DILocation(line: 26, column: 30, scope: !7)
+!16 = !DILocation(line: 26, column: 35, scope: !7)
+!17 = !DILocation(line: 27, column: 18, scope: !7)
+!18 = !DILocation(line: 35, column: 44, scope: !7)
+!19 = !DILocation(line: 35, column: 40, scope: !7)
+!20 = !DILocation(line: 35, column: 34, scope: !7)
+!21 = !DILocation(line: 35, column: 50, scope: !7)
+!22 = !DILocation(line: 36, column: 22, scope: !7)
+!23 = !DILocation(line: 37, column: 22, scope: !7)
+!24 = !DILocation(line: 38, column: 36, scope: !7)
+!25 = !DILocation(line: 39, column: 40, scope: !7)
+!26 = !DILocation(line: 39, column: 55, scope: !7)
+!27 = !DILocation(line: 40, column: 44, scope: !7)
+!28 = !DILocation(line: 40, column: 40, scope: !7)
+!29 = !DILocation(line: 40, column: 34, scope: !7)
+!30 = !DILocation(line: 40, column: 52, scope: !7)
+!31 = !DILocation(line: 41, column: 22, scope: !7)
+!32 = !DILocation(line: 98, column: 22, scope: !33, inlinedAt: !35)
+!33 = distinct !DILexicalBlockFile(scope: !7, file: !34, discriminator: 0)
+!34 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!35 = !DILocation(line: 44, column: 38, scope: !33)
+!36 = !DILocation(line: 101, column: 30, scope: !33, inlinedAt: !35)
+!37 = !DILocation(line: 101, column: 22, scope: !33, inlinedAt: !35)
+!38 = !DILocation(line: 101, column: 13, scope: !33, inlinedAt: !35)
+!39 = !DILocation(line: 108, column: 21, scope: !40, inlinedAt: !41)
+!40 = distinct !DILexicalBlockFile(scope: !33, file: !34, discriminator: 0)
+!41 = !DILocation(line: 120, column: 46, scope: !40, inlinedAt: !42)
+!42 = !DILocation(line: 50, column: 41, scope: !40)
+!43 = !DILocation(line: 110, column: 60, scope: !40, inlinedAt: !41)
+!44 = !DILocation(line: 112, column: 25, scope: !40, inlinedAt: !41)
+!45 = !DILocation(line: 112, column: 17, scope: !40, inlinedAt: !41)
+!46 = !DILocation(line: 113, column: 15, scope: !40, inlinedAt: !41)
+!47 = !DILocation(line: 113, column: 30, scope: !40, inlinedAt: !41)
+!48 = !DILocation(line: 113, column: 49, scope: !40, inlinedAt: !41)
+!49 = !DILocation(line: 113, column: 22, scope: !40, inlinedAt: !41)
+!50 = !DILocation(line: 113, column: 38, scope: !40, inlinedAt: !41)
+!51 = !DILocation(line: 120, column: 46, scope: !33, inlinedAt: !52)
+!52 = !DILocation(line: 50, column: 41, scope: !33)
+!53 = !DILocation(line: 109, column: 28, scope: !40, inlinedAt: !41)
+!54 = !DILocation(line: 110, column: 39, scope: !40, inlinedAt: !41)
+!55 = !DILocation(line: 110, column: 49, scope: !40, inlinedAt: !41)
+!56 = !DILocation(line: 59, column: 51, scope: !7)
+!57 = !DILocation(line: 60, column: 35, scope: !7)
+!58 = !DILocation(line: 60, column: 40, scope: !7)
+!59 = !DILocation(line: 64, column: 57, scope: !7)
+!60 = !DILocation(line: 65, column: 54, scope: !7)
+!61 = !DILocation(line: 69, column: 23, scope: !7)
+!62 = !DILocation(line: 71, column: 24, scope: !7)
+!63 = !DILocation(line: 72, column: 30, scope: !7)
+!64 = !DILocation(line: 66, column: 24, scope: !7)
+!65 = !DILocation(line: 67, column: 24, scope: !7)
+!66 = !DILocation(line: 73, column: 24, scope: !7)
+!67 = !DILocation(line: 74, column: 24, scope: !7)
+!68 = !DILocation(line: 76, column: 39, scope: !7)
+!69 = !DILocation(line: 76, column: 35, scope: !7)
+!70 = !DILocation(line: 76, column: 29, scope: !7)
+!71 = !DILocation(line: 76, column: 52, scope: !7)
+!72 = !DILocation(line: 55, column: 4, scope: !7)

.triton/dump/345a87a492fd703c73ab83265a21fcb6/triton_.ptx

@@ -0,0 +1,1654 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5de6de
+.extern .func __assertfail
+(
+	.param .b64 __assertfail_param_0,
+	.param .b64 __assertfail_param_1,
+	.param .b32 __assertfail_param_2,
+	.param .b64 __assertfail_param_3,
+	.param .b64 __assertfail_param_4
+)
+;
+.global .align 1 .b8 assertFunc_1[25] = {95, 99, 97, 108, 108, 95, 119, 105, 116, 104, 95, 102, 114, 97, 109, 101, 115, 95, 114, 101, 109, 111, 118, 101, 100};
+.global .align 1 .b8 assertFile_1[38] = {60, 102, 114, 111, 122, 101, 110, 32, 105, 109, 112, 111, 114, 116, 108, 105, 98, 46, 95, 98, 111, 111, 116, 115, 116, 114, 97, 112, 95, 101, 120, 116, 101, 114, 110, 97, 108, 62};
+.global .align 1 .b8 assertMessage_1[39] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 49, 51, 32, 60, 32, 53, 48, 50, 53, 55};
+.global .align 1 .b8 assertFunc_0[25] = {95, 99, 97, 108, 108, 95, 119, 105, 116, 104, 95, 102, 114, 97, 109, 101, 115, 95, 114, 101, 109, 111, 118, 101, 100};
+.global .align 1 .b8 assertFile_0[38] = {60, 102, 114, 111, 122, 101, 110, 32, 105, 109, 112, 111, 114, 116, 108, 105, 98, 46, 95, 98, 111, 111, 116, 115, 116, 114, 97, 112, 95, 101, 120, 116, 101, 114, 110, 97, 108, 62};
+.global .align 1 .b8 assertMessage_0[38] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 51, 32, 60, 32, 53, 48, 50, 53, 55};
+.extern .shared .align 1 .b8 global_smem[];
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};
+
+.visible .entry triton__0d1d2d3d4d5de6de(
+	.param .u64 triton__0d1d2d3d4d5de6de_param_0,
+	.param .u64 triton__0d1d2d3d4d5de6de_param_1,
+	.param .u64 triton__0d1d2d3d4d5de6de_param_2,
+	.param .u64 triton__0d1d2d3d4d5de6de_param_3,
+	.param .u64 triton__0d1d2d3d4d5de6de_param_4,
+	.param .u32 triton__0d1d2d3d4d5de6de_param_5,
+	.param .u32 triton__0d1d2d3d4d5de6de_param_6
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<117>;
+	.reg .b16 	%rs<17>;
+	.reg .b32 	%r<375>;
+	.reg .f32 	%f<423>;
+	.reg .b64 	%rd<113>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd13, [triton__0d1d2d3d4d5de6de_param_3];
+	ld.param.u64 	%rd12, [triton__0d1d2d3d4d5de6de_param_1];
+	ld.param.u64 	%rd53, [triton__0d1d2d3d4d5de6de_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r59, %tid.x;
+	ld.param.u64 	%rd54, [triton__0d1d2d3d4d5de6de_param_2];
+	bfe.u32 	%r60, %r59, 5, 3;
+	and.b32  	%r61, %r59, 15;
+	.loc	1 24 33
+	shl.b32 	%r62, %r59, 3;
+	and.b32  	%r1, %r62, 248;
+	and.b32  	%r2, %r59, 255;
+	.loc	1 21 28
+	mov.u32 %r26, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r63, %r26, 4;
+	.loc	1 22 23
+	or.b32  	%r3, %r63, %r60;
+	or.b32  	%r4, %r3, 8;
+	or.b32  	%r64, %r63, %r61;
+	.loc	1 26 30
+	mul.wide.s32 	%rd55, %r3, 8;
+	add.s64 	%rd16, %rd53, %rd55;
+	add.s64 	%rd32, %rd16, 64;
+	mul.wide.s32 	%rd56, %r64, 8;
+	add.s64 	%rd48, %rd53, %rd56;
+	mov.pred 	%p93, -1;
+	.loc	1 26 35
+	mov.u64 %rd15, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd15 }, [ %rd16 + 0 ];
+	mov.u64 %rd17, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd17 }, [ %rd16 + 0 ];
+	mov.u64 %rd19, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd19 }, [ %rd16 + 0 ];
+	mov.u64 %rd21, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd21 }, [ %rd16 + 0 ];
+	mov.u64 %rd23, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd23 }, [ %rd16 + 0 ];
+	mov.u64 %rd25, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd25 }, [ %rd16 + 0 ];
+	mov.u64 %rd27, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd27 }, [ %rd16 + 0 ];
+	mov.u64 %rd29, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd29 }, [ %rd16 + 0 ];
+	mov.u64 %rd31, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd31 }, [ %rd32 + 0 ];
+	mov.u64 %rd33, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd33 }, [ %rd32 + 0 ];
+	mov.u64 %rd35, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd35 }, [ %rd32 + 0 ];
+	mov.u64 %rd37, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd37 }, [ %rd32 + 0 ];
+	mov.u64 %rd39, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd39 }, [ %rd32 + 0 ];
+	mov.u64 %rd41, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd41 }, [ %rd32 + 0 ];
+	mov.u64 %rd43, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd43 }, [ %rd32 + 0 ];
+	mov.u64 %rd45, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd45 }, [ %rd32 + 0 ];
+	mov.u64 %rd47, 0x0;
+	@%p93 ld.global.L1::evict_last.b64 { %rd47 }, [ %rd48 + 0 ];
+	.loc	1 27 18
+	bfe.s32 	%r65, %r26, 27, 1;
+	shr.u32 	%r66, %r65, 23;
+	add.s32 	%r67, %r3, %r66;
+	and.b32  	%r68, %r67, 16776704;
+	sub.s32 	%r69, %r3, %r68;
+	add.s32 	%r70, %r4, %r66;
+	and.b32  	%r71, %r70, 16776704;
+	sub.s32 	%r72, %r4, %r71;
+	.loc	1 35 44
+	shl.b32 	%r73, %r69, 8;
+	shl.b32 	%r74, %r72, 8;
+	.loc	1 35 40
+	or.b32  	%r75, %r73, %r1;
+	or.b32  	%r76, %r74, %r1;
+	.loc	1 35 34
+	mul.wide.s32 	%rd57, %r75, 4;
+	add.s64 	%rd80, %rd54, %rd57;
+	cvt.s64.s32 	%rd58, %r73;
+	cvt.u64.u32 	%rd59, %r1;
+	or.b64  	%rd60, %rd58, %rd59;
+	shl.b64 	%rd61, %rd60, 2;
+	add.s64 	%rd62, %rd54, %rd61;
+	add.s64 	%rd81, %rd62, 16;
+	mul.wide.s32 	%rd63, %r76, 4;
+	add.s64 	%rd82, %rd54, %rd63;
+	cvt.s64.s32 	%rd64, %r74;
+	or.b64  	%rd65, %rd64, %rd59;
+	shl.b64 	%rd66, %rd65, 2;
+	add.s64 	%rd67, %rd54, %rd66;
+	add.s64 	%rd83, %rd67, 16;
+	mov.b32 	%r257, 0;
+	.loc	1 35 50
+	mov.u32 %r27, 0x0;
+	mov.u32 %r28, 0x0;
+	mov.u32 %r29, 0x0;
+	mov.u32 %r30, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r27, %r28, %r29, %r30 }, [ %rd80 + 0 ];
+	@!%p93 mov.u32 %r27, %r257;
+	@!%p93 mov.u32 %r28, %r257;
+	@!%p93 mov.u32 %r29, %r257;
+	@!%p93 mov.u32 %r30, %r257;
+	mov.b32 	%f1, %r27;
+	mov.b32 	%f2, %r28;
+	mov.b32 	%f3, %r29;
+	mov.b32 	%f4, %r30;
+	mov.u32 %r35, 0x0;
+	mov.u32 %r36, 0x0;
+	mov.u32 %r37, 0x0;
+	mov.u32 %r38, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r35, %r36, %r37, %r38 }, [ %rd81 + 0 ];
+	@!%p93 mov.u32 %r35, %r257;
+	@!%p93 mov.u32 %r36, %r257;
+	@!%p93 mov.u32 %r37, %r257;
+	@!%p93 mov.u32 %r38, %r257;
+	mov.b32 	%f5, %r35;
+	mov.b32 	%f6, %r36;
+	mov.b32 	%f7, %r37;
+	mov.b32 	%f8, %r38;
+	mov.u32 %r43, 0x0;
+	mov.u32 %r44, 0x0;
+	mov.u32 %r45, 0x0;
+	mov.u32 %r46, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r43, %r44, %r45, %r46 }, [ %rd82 + 0 ];
+	@!%p93 mov.u32 %r43, %r257;
+	@!%p93 mov.u32 %r44, %r257;
+	@!%p93 mov.u32 %r45, %r257;
+	@!%p93 mov.u32 %r46, %r257;
+	mov.b32 	%f9, %r43;
+	mov.b32 	%f10, %r44;
+	mov.b32 	%f11, %r45;
+	mov.b32 	%f12, %r46;
+	mov.u32 %r51, 0x0;
+	mov.u32 %r52, 0x0;
+	mov.u32 %r53, 0x0;
+	mov.u32 %r54, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r51, %r52, %r53, %r54 }, [ %rd83 + 0 ];
+	@!%p93 mov.u32 %r51, %r257;
+	@!%p93 mov.u32 %r52, %r257;
+	@!%p93 mov.u32 %r53, %r257;
+	@!%p93 mov.u32 %r54, %r257;
+	mov.b32 	%f13, %r51;
+	mov.b32 	%f14, %r52;
+	mov.b32 	%f15, %r53;
+	mov.b32 	%f16, %r54;
+	.loc	1 36 22
+	add.s64 	%rd68, %rd47, 50257;
+	.loc	1 37 22
+	setp.lt.s64 	%p38, %rd47, 0;
+	.loc	1 38 36
+	selp.b64 	%rd7, %rd68, %rd47, %p38;
+	.loc	1 39 40
+	setp.lt.u64 	%p39, %rd7, 50257;
+	mov.b32 	%r374, 883;
+	mov.u64 	%rd112, 1;
+	.loc	1 39 55
+	@%p39 bra 	$L__BB0_2;
+	mov.u64 	%rd69, assertMessage_0;
+	cvta.global.u64 	%rd70, %rd69;
+	mov.u64 	%rd71, assertFile_0;
+	cvta.global.u64 	%rd72, %rd71;
+	mov.u64 	%rd73, assertFunc_0;
+	cvta.global.u64 	%rd74, %rd73;
+	{ // callseq 8, 0
+	.reg .b32 temp_param_reg;
+	.param .b64 param0;
+	st.param.b64 	[param0+0], %rd70;
+	.param .b64 param1;
+	st.param.b64 	[param1+0], %rd72;
+	.param .b32 param2;
+	st.param.b32 	[param2+0], %r374;
+	.param .b64 param3;
+	st.param.b64 	[param3+0], %rd74;
+	.param .b64 param4;
+	st.param.b64 	[param4+0], %rd112;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 8
+$L__BB0_2:
+	.loc	1 0 55
+	ld.param.u64 	%rd14, [triton__0d1d2d3d4d5de6de_param_4];
+	.loc	1 37 22
+	setp.lt.s64 	%p83, %rd31, 0;
+	setp.lt.s64 	%p84, %rd15, 0;
+	.loc	1 40 44
+	shl.b64 	%rd85, %rd15, 8;
+	add.s64 	%rd86, %rd85, 12865792;
+	selp.b64 	%rd87, %rd86, %rd85, %p84;
+	shl.b64 	%rd88, %rd31, 8;
+	add.s64 	%rd89, %rd88, 12865792;
+	selp.b64 	%rd90, %rd89, %rd88, %p83;
+	.loc	1 40 40
+	or.b64  	%rd92, %rd87, %rd59;
+	or.b64  	%rd93, %rd90, %rd59;
+	.loc	1 40 34
+	shl.b64 	%rd94, %rd92, 2;
+	add.s64 	%rd104, %rd12, %rd94;
+	add.s64 	%rd105, %rd104, 16;
+	shl.b64 	%rd95, %rd93, 2;
+	add.s64 	%rd106, %rd12, %rd95;
+	add.s64 	%rd107, %rd106, 16;
+	.loc	1 40 52
+	mov.u32 %r78, 0x0;
+	mov.u32 %r79, 0x0;
+	mov.u32 %r80, 0x0;
+	mov.u32 %r81, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r78, %r79, %r80, %r81 }, [ %rd104 + 0 ];
+	@!%p93 mov.u32 %r78, %r257;
+	@!%p93 mov.u32 %r79, %r257;
+	@!%p93 mov.u32 %r80, %r257;
+	@!%p93 mov.u32 %r81, %r257;
+	mov.b32 	%f27, %r78;
+	mov.b32 	%f28, %r79;
+	mov.b32 	%f29, %r80;
+	mov.b32 	%f30, %r81;
+	mov.u32 %r86, 0x0;
+	mov.u32 %r87, 0x0;
+	mov.u32 %r88, 0x0;
+	mov.u32 %r89, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r86, %r87, %r88, %r89 }, [ %rd105 + 0 ];
+	@!%p93 mov.u32 %r86, %r257;
+	@!%p93 mov.u32 %r87, %r257;
+	@!%p93 mov.u32 %r88, %r257;
+	@!%p93 mov.u32 %r89, %r257;
+	mov.b32 	%f31, %r86;
+	mov.b32 	%f32, %r87;
+	mov.b32 	%f33, %r88;
+	mov.b32 	%f34, %r89;
+	mov.u32 %r94, 0x0;
+	mov.u32 %r95, 0x0;
+	mov.u32 %r96, 0x0;
+	mov.u32 %r97, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r94, %r95, %r96, %r97 }, [ %rd106 + 0 ];
+	@!%p93 mov.u32 %r94, %r257;
+	@!%p93 mov.u32 %r95, %r257;
+	@!%p93 mov.u32 %r96, %r257;
+	@!%p93 mov.u32 %r97, %r257;
+	mov.b32 	%f35, %r94;
+	mov.b32 	%f36, %r95;
+	mov.b32 	%f37, %r96;
+	mov.b32 	%f38, %r97;
+	mov.u32 %r102, 0x0;
+	mov.u32 %r103, 0x0;
+	mov.u32 %r104, 0x0;
+	mov.u32 %r105, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r102, %r103, %r104, %r105 }, [ %rd107 + 0 ];
+	@!%p93 mov.u32 %r102, %r257;
+	@!%p93 mov.u32 %r103, %r257;
+	@!%p93 mov.u32 %r104, %r257;
+	@!%p93 mov.u32 %r105, %r257;
+	mov.b32 	%f39, %r102;
+	mov.b32 	%f40, %r103;
+	mov.b32 	%f41, %r104;
+	mov.b32 	%f42, %r105;
+	.loc	1 41 22
+	add.f32 	%f43, %f1, %f27;
+	add.f32 	%f44, %f2, %f28;
+	add.f32 	%f45, %f3, %f29;
+	add.f32 	%f46, %f4, %f30;
+	add.f32 	%f47, %f5, %f31;
+	add.f32 	%f48, %f6, %f32;
+	add.f32 	%f49, %f7, %f33;
+	add.f32 	%f50, %f8, %f34;
+	add.f32 	%f51, %f9, %f35;
+	add.f32 	%f52, %f10, %f36;
+	add.f32 	%f53, %f11, %f37;
+	add.f32 	%f54, %f12, %f38;
+	add.f32 	%f55, %f13, %f39;
+	add.f32 	%f56, %f14, %f40;
+	add.f32 	%f57, %f15, %f41;
+	add.f32 	%f58, %f16, %f42;
+$L__tmp1:
+	.loc	2 98 22
+	add.f32 	%f59, %f43, 0f00000000;
+	add.f32 	%f60, %f44, 0f00000000;
+	add.f32 	%f61, %f45, 0f00000000;
+	add.f32 	%f62, %f46, 0f00000000;
+	add.f32 	%f63, %f47, 0f00000000;
+	add.f32 	%f64, %f48, 0f00000000;
+	add.f32 	%f65, %f49, 0f00000000;
+	add.f32 	%f66, %f50, 0f00000000;
+	add.f32 	%f67, %f51, 0f00000000;
+	add.f32 	%f68, %f52, 0f00000000;
+	add.f32 	%f69, %f53, 0f00000000;
+	add.f32 	%f70, %f54, 0f00000000;
+	add.f32 	%f71, %f55, 0f00000000;
+	add.f32 	%f72, %f56, 0f00000000;
+	add.f32 	%f73, %f57, 0f00000000;
+	add.f32 	%f74, %f58, 0f00000000;
+	.loc	2 101 30
+	sub.f32 	%f75, %f43, %f59;
+	sub.f32 	%f76, %f44, %f60;
+	sub.f32 	%f77, %f45, %f61;
+	sub.f32 	%f78, %f46, %f62;
+	sub.f32 	%f79, %f47, %f63;
+	sub.f32 	%f80, %f48, %f64;
+	sub.f32 	%f81, %f49, %f65;
+	sub.f32 	%f82, %f50, %f66;
+	sub.f32 	%f83, %f51, %f67;
+	sub.f32 	%f84, %f52, %f68;
+	sub.f32 	%f85, %f53, %f69;
+	sub.f32 	%f86, %f54, %f70;
+	sub.f32 	%f87, %f55, %f71;
+	sub.f32 	%f88, %f56, %f72;
+	sub.f32 	%f89, %f57, %f73;
+	sub.f32 	%f90, %f58, %f74;
+	.loc	2 101 13
+	fma.rn.f32 	%f91, %f43, %f75, 0f00000000;
+	fma.rn.f32 	%f92, %f44, %f76, 0f00000000;
+	fma.rn.f32 	%f93, %f45, %f77, 0f00000000;
+	fma.rn.f32 	%f94, %f46, %f78, 0f00000000;
+	fma.rn.f32 	%f95, %f47, %f79, 0f00000000;
+	fma.rn.f32 	%f96, %f48, %f80, 0f00000000;
+	fma.rn.f32 	%f97, %f49, %f81, 0f00000000;
+	fma.rn.f32 	%f98, %f50, %f82, 0f00000000;
+	fma.rn.f32 	%f99, %f51, %f83, 0f00000000;
+	fma.rn.f32 	%f100, %f52, %f84, 0f00000000;
+	fma.rn.f32 	%f101, %f53, %f85, 0f00000000;
+	fma.rn.f32 	%f102, %f54, %f86, 0f00000000;
+	fma.rn.f32 	%f103, %f55, %f87, 0f00000000;
+	fma.rn.f32 	%f104, %f56, %f88, 0f00000000;
+	fma.rn.f32 	%f105, %f57, %f89, 0f00000000;
+	fma.rn.f32 	%f106, %f58, %f90, 0f00000000;
+$L__tmp2:
+	.loc	2 108 21
+	sub.f32 	%f107, %f60, %f59;
+	mov.b32 	%r111, 1065353216;
+	mov.b32 	%r112, 1073741824;
+	.loc	2 110 60
+	div.full.f32 %r110, %r111, %r112;
+	mov.b32 	%f108, %r110;
+	.loc	2 112 17
+	fma.rn.f32 	%f109, %f108, %f107, %f59;
+	.loc	2 113 15
+	add.f32 	%f110, %f91, %f92;
+	.loc	2 113 30
+	mul.f32 	%f111, %f107, %f107;
+	.loc	2 113 22
+	fma.rn.f32 	%f112, %f108, %f111, %f110;
+	.loc	2 108 21
+	sub.f32 	%f113, %f61, %f109;
+	mov.b32 	%r115, 1077936128;
+	.loc	2 110 60
+	div.full.f32 %r113, %r111, %r115;
+	mov.b32 	%f114, %r113;
+	.loc	2 112 17
+	fma.rn.f32 	%f115, %f114, %f113, %f109;
+	.loc	2 113 15
+	add.f32 	%f116, %f93, %f112;
+	.loc	2 113 30
+	mul.f32 	%f117, %f113, %f113;
+	.loc	2 113 38
+	fma.rn.f32 	%f118, %f113, %f113, %f117;
+	.loc	2 113 22
+	fma.rn.f32 	%f119, %f114, %f118, %f116;
+	.loc	2 108 21
+	sub.f32 	%f120, %f62, %f115;
+	mov.b32 	%r118, 1082130432;
+	.loc	2 110 60
+	div.full.f32 %r116, %r111, %r118;
+	mov.b32 	%f121, %r116;
+	.loc	2 112 17
+	fma.rn.f32 	%f122, %f121, %f120, %f115;
+	.loc	2 113 15
+	add.f32 	%f123, %f94, %f119;
+	.loc	2 113 30
+	mul.f32 	%f124, %f120, %f120;
+	.loc	2 113 38
+	mul.f32 	%f125, %f124, 0f40400000;
+	.loc	2 113 22
+	fma.rn.f32 	%f126, %f121, %f125, %f123;
+	.loc	2 108 21
+	sub.f32 	%f127, %f63, %f122;
+	mov.b32 	%r121, 1084227584;
+	.loc	2 110 60
+	div.full.f32 %r119, %r111, %r121;
+	mov.b32 	%f128, %r119;
+	.loc	2 112 17
+	fma.rn.f32 	%f129, %f128, %f127, %f122;
+	.loc	2 113 15
+	add.f32 	%f130, %f95, %f126;
+	.loc	2 113 30
+	mul.f32 	%f131, %f127, %f127;
+	.loc	2 113 38
+	mul.f32 	%f132, %f131, 0f40800000;
+	.loc	2 113 22
+	fma.rn.f32 	%f133, %f128, %f132, %f130;
+	.loc	2 108 21
+	sub.f32 	%f134, %f64, %f129;
+	mov.b32 	%r124, 1086324736;
+	.loc	2 110 60
+	div.full.f32 %r122, %r111, %r124;
+	mov.b32 	%f135, %r122;
+	.loc	2 112 17
+	fma.rn.f32 	%f136, %f135, %f134, %f129;
+	.loc	2 113 15
+	add.f32 	%f137, %f96, %f133;
+	.loc	2 113 30
+	mul.f32 	%f138, %f134, %f134;
+	.loc	2 113 38
+	mul.f32 	%f139, %f138, 0f40A00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f140, %f135, %f139, %f137;
+	.loc	2 108 21
+	sub.f32 	%f141, %f65, %f136;
+	mov.b32 	%r127, 1088421888;
+	.loc	2 110 60
+	div.full.f32 %r125, %r111, %r127;
+	mov.b32 	%f142, %r125;
+	.loc	2 112 17
+	fma.rn.f32 	%f143, %f142, %f141, %f136;
+	.loc	2 113 15
+	add.f32 	%f144, %f97, %f140;
+	.loc	2 113 30
+	mul.f32 	%f145, %f141, %f141;
+	.loc	2 113 38
+	mul.f32 	%f146, %f145, 0f40C00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f147, %f142, %f146, %f144;
+	.loc	2 108 21
+	sub.f32 	%f148, %f66, %f143;
+	mov.b32 	%r130, 1090519040;
+	.loc	2 110 60
+	div.full.f32 %r128, %r111, %r130;
+	mov.b32 	%f149, %r128;
+	.loc	2 112 17
+	fma.rn.f32 	%f150, %f149, %f148, %f143;
+	.loc	2 113 15
+	add.f32 	%f151, %f98, %f147;
+	.loc	2 113 30
+	mul.f32 	%f152, %f148, %f148;
+	.loc	2 113 38
+	mul.f32 	%f153, %f152, 0f40E00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f154, %f149, %f153, %f151;
+	.loc	2 108 21
+	sub.f32 	%f155, %f68, %f67;
+	.loc	2 110 60
+	div.full.f32 %r131, %r111, %r112;
+	mov.b32 	%f156, %r131;
+	.loc	2 112 17
+	fma.rn.f32 	%f157, %f155, %f156, %f67;
+	.loc	2 113 15
+	add.f32 	%f158, %f99, %f100;
+	.loc	2 113 30
+	mul.f32 	%f159, %f155, %f155;
+	.loc	2 113 22
+	fma.rn.f32 	%f160, %f159, %f156, %f158;
+	.loc	2 108 21
+	sub.f32 	%f161, %f69, %f157;
+	.loc	2 110 60
+	div.full.f32 %r134, %r111, %r115;
+	mov.b32 	%f162, %r134;
+	.loc	2 112 17
+	fma.rn.f32 	%f163, %f162, %f161, %f157;
+	.loc	2 113 15
+	add.f32 	%f164, %f101, %f160;
+	.loc	2 113 30
+	mul.f32 	%f165, %f161, %f161;
+	.loc	2 113 38
+	fma.rn.f32 	%f166, %f161, %f161, %f165;
+	.loc	2 113 22
+	fma.rn.f32 	%f167, %f162, %f166, %f164;
+	.loc	2 108 21
+	sub.f32 	%f168, %f70, %f163;
+	.loc	2 110 60
+	div.full.f32 %r137, %r111, %r118;
+	mov.b32 	%f169, %r137;
+	.loc	2 112 17
+	fma.rn.f32 	%f170, %f169, %f168, %f163;
+	.loc	2 113 15
+	add.f32 	%f171, %f102, %f167;
+	.loc	2 113 30
+	mul.f32 	%f172, %f168, %f168;
+	.loc	2 113 38
+	mul.f32 	%f173, %f172, 0f40400000;
+	.loc	2 113 22
+	fma.rn.f32 	%f174, %f169, %f173, %f171;
+	.loc	2 108 21
+	sub.f32 	%f175, %f71, %f170;
+	.loc	2 110 60
+	div.full.f32 %r140, %r111, %r121;
+	mov.b32 	%f176, %r140;
+	.loc	2 112 17
+	fma.rn.f32 	%f177, %f176, %f175, %f170;
+	.loc	2 113 15
+	add.f32 	%f178, %f103, %f174;
+	.loc	2 113 30
+	mul.f32 	%f179, %f175, %f175;
+	.loc	2 113 38
+	mul.f32 	%f180, %f179, 0f40800000;
+	.loc	2 113 22
+	fma.rn.f32 	%f181, %f176, %f180, %f178;
+	.loc	2 108 21
+	sub.f32 	%f182, %f72, %f177;
+	.loc	2 110 60
+	div.full.f32 %r143, %r111, %r124;
+	mov.b32 	%f183, %r143;
+	.loc	2 112 17
+	fma.rn.f32 	%f184, %f183, %f182, %f177;
+	.loc	2 113 15
+	add.f32 	%f185, %f104, %f181;
+	.loc	2 113 30
+	mul.f32 	%f186, %f182, %f182;
+	.loc	2 113 38
+	mul.f32 	%f187, %f186, 0f40A00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f188, %f183, %f187, %f185;
+	.loc	2 108 21
+	sub.f32 	%f189, %f73, %f184;
+	.loc	2 110 60
+	div.full.f32 %r146, %r111, %r127;
+	mov.b32 	%f190, %r146;
+	.loc	2 112 17
+	fma.rn.f32 	%f191, %f190, %f189, %f184;
+	.loc	2 113 15
+	add.f32 	%f192, %f105, %f188;
+	.loc	2 113 30
+	mul.f32 	%f193, %f189, %f189;
+	.loc	2 113 38
+	mul.f32 	%f194, %f193, 0f40C00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f195, %f190, %f194, %f192;
+	.loc	2 108 21
+	sub.f32 	%f196, %f74, %f191;
+	.loc	2 110 60
+	div.full.f32 %r149, %r111, %r130;
+	mov.b32 	%f197, %r149;
+	.loc	2 112 17
+	fma.rn.f32 	%f198, %f197, %f196, %f191;
+	.loc	2 113 15
+	add.f32 	%f199, %f106, %f195;
+	.loc	2 113 30
+	mul.f32 	%f200, %f196, %f196;
+	.loc	2 113 38
+	mul.f32 	%f201, %f200, 0f40E00000;
+	.loc	2 113 22
+	fma.rn.f32 	%f202, %f197, %f201, %f199;
+$L__tmp3:
+	.loc	2 120 46
+	mov.b32 	%r216, %f150;
+	shfl.sync.bfly.b32	%r217, %r216, 16, 31, -1;
+	mov.b32 	%f203, %r217;
+	mov.b32 	%r218, %f154;
+	shfl.sync.bfly.b32	%r219, %r218, 16, 31, -1;
+	mov.b32 	%f204, %r219;
+	shfl.sync.bfly.b32	%r153, %r130, 16, 31, -1;
+	mov.b32 	%f205, %r153;
+$L__tmp4:
+	.loc	2 108 21
+	sub.f32 	%f206, %f203, %f150;
+	.loc	2 109 28
+	add.f32 	%f207, %f205, 0f41000000;
+	.loc	2 110 39
+	setp.eq.f32 	%p85, %f207, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r154, %f207;
+	div.full.f32 %r152, %r153, %r154;
+	mov.b32 	%f208, %r152;
+	.loc	2 110 49
+	selp.f32 	%f209, 0f00000000, %f208, %p85;
+	.loc	2 112 17
+	fma.rn.f32 	%f210, %f209, %f206, %f150;
+	.loc	2 113 15
+	add.f32 	%f211, %f154, %f204;
+	.loc	2 113 30
+	mul.f32 	%f212, %f206, %f206;
+	.loc	2 113 38
+	mul.f32 	%f213, %f212, 0f41000000;
+	.loc	2 113 22
+	fma.rn.f32 	%f214, %f209, %f213, %f211;
+$L__tmp5:
+	.loc	2 120 46
+	mov.b32 	%r220, %f210;
+	shfl.sync.bfly.b32	%r221, %r220, 8, 31, -1;
+	mov.b32 	%f215, %r221;
+	mov.b32 	%r222, %f214;
+	shfl.sync.bfly.b32	%r223, %r222, 8, 31, -1;
+	mov.b32 	%f216, %r223;
+	shfl.sync.bfly.b32	%r156, %r154, 8, 31, -1;
+	mov.b32 	%f217, %r156;
+$L__tmp6:
+	.loc	2 108 21
+	sub.f32 	%f218, %f215, %f210;
+	.loc	2 109 28
+	add.f32 	%f219, %f207, %f217;
+	.loc	2 110 39
+	setp.eq.f32 	%p86, %f219, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r157, %f219;
+	div.full.f32 %r155, %r156, %r157;
+	mov.b32 	%f220, %r155;
+	.loc	2 110 49
+	selp.f32 	%f221, 0f00000000, %f220, %p86;
+	.loc	2 112 17
+	fma.rn.f32 	%f222, %f221, %f218, %f210;
+	.loc	2 113 15
+	add.f32 	%f223, %f214, %f216;
+	.loc	2 113 30
+	mul.f32 	%f224, %f218, %f218;
+	.loc	2 113 38
+	mul.f32 	%f225, %f207, %f224;
+	.loc	2 113 22
+	fma.rn.f32 	%f226, %f221, %f225, %f223;
+$L__tmp7:
+	.loc	2 120 46
+	mov.b32 	%r224, %f222;
+	shfl.sync.bfly.b32	%r225, %r224, 4, 31, -1;
+	mov.b32 	%f227, %r225;
+	mov.b32 	%r226, %f226;
+	shfl.sync.bfly.b32	%r227, %r226, 4, 31, -1;
+	mov.b32 	%f228, %r227;
+	shfl.sync.bfly.b32	%r159, %r157, 4, 31, -1;
+	mov.b32 	%f229, %r159;
+$L__tmp8:
+	.loc	2 108 21
+	sub.f32 	%f230, %f227, %f222;
+	.loc	2 109 28
+	add.f32 	%f231, %f219, %f229;
+	.loc	2 110 39
+	setp.eq.f32 	%p87, %f231, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r160, %f231;
+	div.full.f32 %r158, %r159, %r160;
+	mov.b32 	%f232, %r158;
+	.loc	2 110 49
+	selp.f32 	%f233, 0f00000000, %f232, %p87;
+	.loc	2 112 17
+	fma.rn.f32 	%f234, %f230, %f233, %f222;
+	.loc	2 113 15
+	add.f32 	%f235, %f226, %f228;
+	.loc	2 113 30
+	mul.f32 	%f236, %f230, %f230;
+	.loc	2 113 38
+	mul.f32 	%f237, %f219, %f236;
+	.loc	2 113 22
+	fma.rn.f32 	%f238, %f233, %f237, %f235;
+$L__tmp9:
+	.loc	2 120 46
+	mov.b32 	%r228, %f234;
+	shfl.sync.bfly.b32	%r229, %r228, 2, 31, -1;
+	mov.b32 	%f239, %r229;
+	mov.b32 	%r230, %f238;
+	shfl.sync.bfly.b32	%r231, %r230, 2, 31, -1;
+	mov.b32 	%f240, %r231;
+	shfl.sync.bfly.b32	%r162, %r160, 2, 31, -1;
+	mov.b32 	%f241, %r162;
+$L__tmp10:
+	.loc	2 108 21
+	sub.f32 	%f242, %f239, %f234;
+	.loc	2 109 28
+	add.f32 	%f17, %f231, %f241;
+	.loc	2 110 39
+	setp.eq.f32 	%p88, %f17, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r163, %f17;
+	div.full.f32 %r161, %r162, %r163;
+	mov.b32 	%f243, %r161;
+	.loc	2 110 49
+	selp.f32 	%f244, 0f00000000, %f243, %p88;
+	.loc	2 112 17
+	fma.rn.f32 	%f18, %f242, %f244, %f234;
+	.loc	2 113 15
+	add.f32 	%f245, %f238, %f240;
+	.loc	2 113 30
+	mul.f32 	%f246, %f242, %f242;
+	.loc	2 113 38
+	mul.f32 	%f247, %f231, %f246;
+	.loc	2 113 22
+	fma.rn.f32 	%f19, %f244, %f247, %f245;
+$L__tmp11:
+	.loc	2 120 46
+	mov.b32 	%r232, %f18;
+	shfl.sync.bfly.b32	%r5, %r232, 1, 31, -1;
+	mov.b32 	%r233, %f19;
+	shfl.sync.bfly.b32	%r6, %r233, 1, 31, -1;
+	shfl.sync.bfly.b32	%r165, %r163, 1, 31, -1;
+	mov.b32 	%f248, %r165;
+$L__tmp12:
+	.loc	2 109 28
+	add.f32 	%f20, %f17, %f248;
+	.loc	2 110 60
+	mov.b32 	%r166, %f20;
+	div.full.f32 %r164, %r165, %r166;
+	mov.b32 	%f21, %r164;
+$L__tmp13:
+	.loc	2 120 46
+	mov.b32 	%r234, %f198;
+	shfl.sync.bfly.b32	%r235, %r234, 16, 31, -1;
+	mov.b32 	%f249, %r235;
+	mov.b32 	%r236, %f202;
+	shfl.sync.bfly.b32	%r237, %r236, 16, 31, -1;
+	mov.b32 	%f250, %r237;
+	shfl.sync.bfly.b32	%r168, %r130, 16, 31, -1;
+	mov.b32 	%f251, %r168;
+$L__tmp14:
+	.loc	2 108 21
+	sub.f32 	%f252, %f249, %f198;
+	.loc	2 109 28
+	add.f32 	%f253, %f251, 0f41000000;
+	.loc	2 110 39
+	setp.eq.f32 	%p89, %f253, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r169, %f253;
+	div.full.f32 %r167, %r168, %r169;
+	mov.b32 	%f254, %r167;
+	.loc	2 110 49
+	selp.f32 	%f255, 0f00000000, %f254, %p89;
+	.loc	2 112 17
+	fma.rn.f32 	%f256, %f252, %f255, %f198;
+	.loc	2 113 15
+	add.f32 	%f257, %f202, %f250;
+	.loc	2 113 30
+	mul.f32 	%f258, %f252, %f252;
+	.loc	2 113 38
+	mul.f32 	%f259, %f258, 0f41000000;
+	.loc	2 113 22
+	fma.rn.f32 	%f260, %f259, %f255, %f257;
+$L__tmp15:
+	.loc	2 120 46
+	mov.b32 	%r238, %f256;
+	shfl.sync.bfly.b32	%r239, %r238, 8, 31, -1;
+	mov.b32 	%f261, %r239;
+	mov.b32 	%r240, %f260;
+	shfl.sync.bfly.b32	%r241, %r240, 8, 31, -1;
+	mov.b32 	%f262, %r241;
+	shfl.sync.bfly.b32	%r171, %r169, 8, 31, -1;
+	mov.b32 	%f263, %r171;
+$L__tmp16:
+	.loc	2 108 21
+	sub.f32 	%f264, %f261, %f256;
+	.loc	2 109 28
+	add.f32 	%f265, %f253, %f263;
+	.loc	2 110 39
+	setp.eq.f32 	%p90, %f265, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r172, %f265;
+	div.full.f32 %r170, %r171, %r172;
+	mov.b32 	%f266, %r170;
+	.loc	2 110 49
+	selp.f32 	%f267, 0f00000000, %f266, %p90;
+	.loc	2 112 17
+	fma.rn.f32 	%f268, %f264, %f267, %f256;
+	.loc	2 113 15
+	add.f32 	%f269, %f260, %f262;
+	.loc	2 113 30
+	mul.f32 	%f270, %f264, %f264;
+	.loc	2 113 38
+	mul.f32 	%f271, %f253, %f270;
+	.loc	2 113 22
+	fma.rn.f32 	%f272, %f267, %f271, %f269;
+$L__tmp17:
+	.loc	2 120 46
+	mov.b32 	%r242, %f268;
+	shfl.sync.bfly.b32	%r243, %r242, 4, 31, -1;
+	mov.b32 	%f273, %r243;
+	mov.b32 	%r244, %f272;
+	shfl.sync.bfly.b32	%r245, %r244, 4, 31, -1;
+	mov.b32 	%f274, %r245;
+	shfl.sync.bfly.b32	%r174, %r172, 4, 31, -1;
+	mov.b32 	%f275, %r174;
+$L__tmp18:
+	.loc	2 108 21
+	sub.f32 	%f276, %f273, %f268;
+	.loc	2 109 28
+	add.f32 	%f277, %f265, %f275;
+	.loc	2 110 39
+	setp.eq.f32 	%p91, %f277, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r175, %f277;
+	div.full.f32 %r173, %r174, %r175;
+	mov.b32 	%f278, %r173;
+	.loc	2 110 49
+	selp.f32 	%f279, 0f00000000, %f278, %p91;
+	.loc	2 112 17
+	fma.rn.f32 	%f280, %f276, %f279, %f268;
+	.loc	2 113 15
+	add.f32 	%f281, %f272, %f274;
+	.loc	2 113 30
+	mul.f32 	%f282, %f276, %f276;
+	.loc	2 113 38
+	mul.f32 	%f283, %f265, %f282;
+	.loc	2 113 22
+	fma.rn.f32 	%f284, %f279, %f283, %f281;
+$L__tmp19:
+	.loc	2 120 46
+	mov.b32 	%r246, %f280;
+	shfl.sync.bfly.b32	%r247, %r246, 2, 31, -1;
+	mov.b32 	%f285, %r247;
+	mov.b32 	%r248, %f284;
+	shfl.sync.bfly.b32	%r249, %r248, 2, 31, -1;
+	mov.b32 	%f286, %r249;
+	shfl.sync.bfly.b32	%r177, %r175, 2, 31, -1;
+	mov.b32 	%f287, %r177;
+$L__tmp20:
+	.loc	2 108 21
+	sub.f32 	%f288, %f285, %f280;
+	.loc	2 109 28
+	add.f32 	%f22, %f277, %f287;
+	.loc	2 110 39
+	setp.eq.f32 	%p92, %f22, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r178, %f22;
+	div.full.f32 %r176, %r177, %r178;
+	mov.b32 	%f289, %r176;
+	.loc	2 110 49
+	selp.f32 	%f290, 0f00000000, %f289, %p92;
+	.loc	2 112 17
+	fma.rn.f32 	%f23, %f288, %f290, %f280;
+	.loc	2 113 15
+	add.f32 	%f291, %f284, %f286;
+	.loc	2 113 30
+	mul.f32 	%f292, %f288, %f288;
+	.loc	2 113 38
+	mul.f32 	%f293, %f277, %f292;
+	.loc	2 113 22
+	fma.rn.f32 	%f24, %f290, %f293, %f291;
+$L__tmp21:
+	.loc	2 120 46
+	mov.b32 	%r250, %f23;
+	shfl.sync.bfly.b32	%r7, %r250, 1, 31, -1;
+	mov.b32 	%r251, %f24;
+	shfl.sync.bfly.b32	%r8, %r251, 1, 31, -1;
+	shfl.sync.bfly.b32	%r180, %r178, 1, 31, -1;
+	mov.b32 	%f294, %r180;
+$L__tmp22:
+	.loc	2 109 28
+	add.f32 	%f25, %f22, %f294;
+	.loc	2 110 60
+	mov.b32 	%r181, %f25;
+	div.full.f32 %r179, %r180, %r181;
+	mov.b32 	%f26, %r179;
+$L__tmp23:
+	.loc	1 59 51
+	mov.u32 %r182, 0x0;
+	mov.u32 %r183, 0x0;
+	mov.u32 %r184, 0x0;
+	mov.u32 %r185, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r182, %r183, %r184, %r185 }, [ %rd80 + 0 ];
+	@!%p93 mov.u32 %r182, %r257;
+	@!%p93 mov.u32 %r183, %r257;
+	@!%p93 mov.u32 %r184, %r257;
+	@!%p93 mov.u32 %r185, %r257;
+	mov.u32 %r190, 0x0;
+	mov.u32 %r191, 0x0;
+	mov.u32 %r192, 0x0;
+	mov.u32 %r193, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r190, %r191, %r192, %r193 }, [ %rd81 + 0 ];
+	@!%p93 mov.u32 %r190, %r257;
+	@!%p93 mov.u32 %r191, %r257;
+	@!%p93 mov.u32 %r192, %r257;
+	@!%p93 mov.u32 %r193, %r257;
+	mov.u32 %r198, 0x0;
+	mov.u32 %r199, 0x0;
+	mov.u32 %r200, 0x0;
+	mov.u32 %r201, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r198, %r199, %r200, %r201 }, [ %rd82 + 0 ];
+	@!%p93 mov.u32 %r198, %r257;
+	@!%p93 mov.u32 %r199, %r257;
+	@!%p93 mov.u32 %r200, %r257;
+	@!%p93 mov.u32 %r201, %r257;
+	mov.u32 %r206, 0x0;
+	mov.u32 %r207, 0x0;
+	mov.u32 %r208, 0x0;
+	mov.u32 %r209, 0x0;
+	@%p93 ld.global.L1::evict_last.v4.b32 { %r206, %r207, %r208, %r209 }, [ %rd83 + 0 ];
+	@!%p93 mov.u32 %r206, %r257;
+	@!%p93 mov.u32 %r207, %r257;
+	@!%p93 mov.u32 %r208, %r257;
+	@!%p93 mov.u32 %r209, %r257;
+	.loc	1 60 35
+	mul.wide.u32 	%rd96, %r2, 4;
+	add.s64 	%rd84, %rd13, %rd96;
+	.loc	1 60 40
+	mov.u32 %r214, 0x0;
+	@%p93 ld.global.L1::evict_last.b32 { %r214 }, [ %rd84 + 0 ];
+	@!%p93 mov.u32 %r214, %r257;
+	.loc	1 64 57
+	@%p39 bra 	$L__BB0_4;
+	mov.u64 	%rd97, assertMessage_1;
+	cvta.global.u64 	%rd98, %rd97;
+	mov.u64 	%rd99, assertFile_1;
+	cvta.global.u64 	%rd100, %rd99;
+	mov.u64 	%rd101, assertFunc_1;
+	cvta.global.u64 	%rd102, %rd101;
+	{ // callseq 9, 0
+	.reg .b32 temp_param_reg;
+	.param .b64 param0;
+	st.param.b64 	[param0+0], %rd98;
+	.param .b64 param1;
+	st.param.b64 	[param1+0], %rd100;
+	.param .b32 param2;
+	st.param.b32 	[param2+0], %r374;
+	.param .b64 param3;
+	st.param.b64 	[param3+0], %rd102;
+	.param .b64 param4;
+	st.param.b64 	[param4+0], %rd112;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 9
+$L__BB0_4:
+$L__tmp24:
+	.loc	2 120 46
+	mov.b32 	%f295, %r8;
+$L__tmp25:
+	.loc	2 113 15
+	add.f32 	%f296, %f24, %f295;
+$L__tmp26:
+	.loc	2 120 46
+	mov.b32 	%f297, %r7;
+$L__tmp27:
+	.loc	2 108 21
+	sub.f32 	%f298, %f297, %f23;
+	.loc	2 113 30
+	mul.f32 	%f299, %f298, %f298;
+	.loc	2 113 38
+	mul.f32 	%f300, %f22, %f299;
+	.loc	2 110 39
+	setp.eq.f32 	%p115, %f25, 0f00000000;
+	.loc	2 110 49
+	selp.f32 	%f301, 0f00000000, %f26, %p115;
+	.loc	2 113 22
+	fma.rn.f32 	%f302, %f301, %f300, %f296;
+$L__tmp28:
+	.loc	2 120 46
+	mov.b32 	%f303, %r6;
+$L__tmp29:
+	.loc	2 113 15
+	add.f32 	%f304, %f19, %f303;
+$L__tmp30:
+	.loc	2 120 46
+	mov.b32 	%f305, %r5;
+$L__tmp31:
+	.loc	2 108 21
+	sub.f32 	%f306, %f305, %f18;
+	.loc	2 113 30
+	mul.f32 	%f307, %f306, %f306;
+	.loc	2 113 38
+	mul.f32 	%f308, %f17, %f307;
+	.loc	2 110 39
+	setp.eq.f32 	%p116, %f20, 0f00000000;
+	.loc	2 110 49
+	selp.f32 	%f309, 0f00000000, %f21, %p116;
+	.loc	2 113 22
+	fma.rn.f32 	%f310, %f309, %f308, %f304;
+$L__tmp32:
+	.loc	1 65 54
+	mov.u32 %r253, 0x0;
+	mov.u32 %r254, 0x0;
+	mov.u32 %r255, 0x0;
+	mov.u32 %r256, 0x0;
+	@%p93 ld.global.L1::evict_first.v4.b32 { %r253, %r254, %r255, %r256 }, [ %rd104 + 0 ];
+	@!%p93 mov.u32 %r253, %r257;
+	@!%p93 mov.u32 %r254, %r257;
+	@!%p93 mov.u32 %r255, %r257;
+	@!%p93 mov.u32 %r256, %r257;
+	mov.u32 %r261, 0x0;
+	mov.u32 %r262, 0x0;
+	mov.u32 %r263, 0x0;
+	mov.u32 %r264, 0x0;
+	@%p93 ld.global.L1::evict_first.v4.b32 { %r261, %r262, %r263, %r264 }, [ %rd105 + 0 ];
+	@!%p93 mov.u32 %r261, %r257;
+	@!%p93 mov.u32 %r262, %r257;
+	@!%p93 mov.u32 %r263, %r257;
+	@!%p93 mov.u32 %r264, %r257;
+	mov.u32 %r269, 0x0;
+	mov.u32 %r270, 0x0;
+	mov.u32 %r271, 0x0;
+	mov.u32 %r272, 0x0;
+	@%p93 ld.global.L1::evict_first.v4.b32 { %r269, %r270, %r271, %r272 }, [ %rd106 + 0 ];
+	@!%p93 mov.u32 %r269, %r257;
+	@!%p93 mov.u32 %r270, %r257;
+	@!%p93 mov.u32 %r271, %r257;
+	@!%p93 mov.u32 %r272, %r257;
+	mov.u32 %r277, 0x0;
+	mov.u32 %r278, 0x0;
+	mov.u32 %r279, 0x0;
+	mov.u32 %r280, 0x0;
+	@%p93 ld.global.L1::evict_first.v4.b32 { %r277, %r278, %r279, %r280 }, [ %rd107 + 0 ];
+	@!%p93 mov.u32 %r277, %r257;
+	@!%p93 mov.u32 %r278, %r257;
+	@!%p93 mov.u32 %r279, %r257;
+	@!%p93 mov.u32 %r280, %r257;
+	.loc	1 69 23
+	mov.b32 	%r286, %f310;
+	mov.b32 	%r287, 1132462080;
+	div.full.f32 %r285, %r286, %r287;
+	mov.b32 	%f311, %r285;
+	mov.b32 	%r310, %f302;
+	div.full.f32 %r309, %r310, %r287;
+	mov.b32 	%f312, %r309;
+	.loc	1 71 24
+	add.f32 	%f313, %f311, 0f3727C5AC;
+	add.f32 	%f314, %f312, 0f3727C5AC;
+	.loc	1 72 30
+	rsqrt.approx.ftz.f32 	%f315, %f313;
+	rsqrt.approx.ftz.f32 	%f316, %f314;
+	.loc	1 65 54
+	mov.b32 	%f317, %r280;
+	.loc	1 59 51
+	mov.b32 	%f318, %r209;
+	.loc	1 66 24
+	add.f32 	%f319, %f318, %f317;
+$L__tmp33:
+	.loc	2 112 17
+	fma.rn.f32 	%f320, %f298, %f301, %f23;
+$L__tmp34:
+	.loc	1 67 24
+	sub.f32 	%f321, %f319, %f320;
+	.loc	1 65 54
+	mov.b32 	%f322, %r279;
+	.loc	1 59 51
+	mov.b32 	%f323, %r208;
+	.loc	1 66 24
+	add.f32 	%f324, %f323, %f322;
+	.loc	1 67 24
+	sub.f32 	%f325, %f324, %f320;
+	.loc	1 65 54
+	mov.b32 	%f326, %r278;
+	.loc	1 59 51
+	mov.b32 	%f327, %r207;
+	.loc	1 66 24
+	add.f32 	%f328, %f327, %f326;
+	.loc	1 67 24
+	sub.f32 	%f329, %f328, %f320;
+	.loc	1 65 54
+	mov.b32 	%f330, %r277;
+	.loc	1 59 51
+	mov.b32 	%f331, %r206;
+	.loc	1 66 24
+	add.f32 	%f332, %f331, %f330;
+	.loc	1 67 24
+	sub.f32 	%f333, %f332, %f320;
+	.loc	1 65 54
+	mov.b32 	%f334, %r272;
+	.loc	1 59 51
+	mov.b32 	%f335, %r201;
+	.loc	1 66 24
+	add.f32 	%f336, %f335, %f334;
+	.loc	1 67 24
+	sub.f32 	%f337, %f336, %f320;
+	.loc	1 65 54
+	mov.b32 	%f338, %r271;
+	.loc	1 59 51
+	mov.b32 	%f339, %r200;
+	.loc	1 66 24
+	add.f32 	%f340, %f339, %f338;
+	.loc	1 67 24
+	sub.f32 	%f341, %f340, %f320;
+	.loc	1 65 54
+	mov.b32 	%f342, %r270;
+	.loc	1 59 51
+	mov.b32 	%f343, %r199;
+	.loc	1 66 24
+	add.f32 	%f344, %f343, %f342;
+	.loc	1 67 24
+	sub.f32 	%f345, %f344, %f320;
+	.loc	1 65 54
+	mov.b32 	%f346, %r269;
+	.loc	1 59 51
+	mov.b32 	%f347, %r198;
+	.loc	1 66 24
+	add.f32 	%f348, %f347, %f346;
+	.loc	1 67 24
+	sub.f32 	%f349, %f348, %f320;
+	.loc	1 65 54
+	mov.b32 	%f350, %r264;
+	.loc	1 59 51
+	mov.b32 	%f351, %r193;
+	.loc	1 66 24
+	add.f32 	%f352, %f351, %f350;
+$L__tmp35:
+	.loc	2 112 17
+	fma.rn.f32 	%f353, %f306, %f309, %f18;
+$L__tmp36:
+	.loc	1 67 24
+	sub.f32 	%f354, %f352, %f353;
+	.loc	1 65 54
+	mov.b32 	%f355, %r263;
+	.loc	1 59 51
+	mov.b32 	%f356, %r192;
+	.loc	1 66 24
+	add.f32 	%f357, %f356, %f355;
+	.loc	1 67 24
+	sub.f32 	%f358, %f357, %f353;
+	.loc	1 65 54
+	mov.b32 	%f359, %r262;
+	.loc	1 59 51
+	mov.b32 	%f360, %r191;
+	.loc	1 66 24
+	add.f32 	%f361, %f360, %f359;
+	.loc	1 67 24
+	sub.f32 	%f362, %f361, %f353;
+	.loc	1 65 54
+	mov.b32 	%f363, %r261;
+	.loc	1 59 51
+	mov.b32 	%f364, %r190;
+	.loc	1 66 24
+	add.f32 	%f365, %f364, %f363;
+	.loc	1 67 24
+	sub.f32 	%f366, %f365, %f353;
+	.loc	1 65 54
+	mov.b32 	%f367, %r256;
+	.loc	1 59 51
+	mov.b32 	%f368, %r185;
+	.loc	1 66 24
+	add.f32 	%f369, %f368, %f367;
+	.loc	1 67 24
+	sub.f32 	%f370, %f369, %f353;
+	.loc	1 65 54
+	mov.b32 	%f371, %r255;
+	.loc	1 59 51
+	mov.b32 	%f372, %r184;
+	.loc	1 66 24
+	add.f32 	%f373, %f372, %f371;
+	.loc	1 67 24
+	sub.f32 	%f374, %f373, %f353;
+	.loc	1 65 54
+	mov.b32 	%f375, %r254;
+	.loc	1 59 51
+	mov.b32 	%f376, %r183;
+	.loc	1 66 24
+	add.f32 	%f377, %f376, %f375;
+	.loc	1 67 24
+	sub.f32 	%f378, %f377, %f353;
+	.loc	1 65 54
+	mov.b32 	%f379, %r253;
+	.loc	1 59 51
+	mov.b32 	%f380, %r182;
+	.loc	1 66 24
+	add.f32 	%f381, %f380, %f379;
+	.loc	1 67 24
+	sub.f32 	%f382, %f381, %f353;
+	.loc	1 73 24
+	mul.f32 	%f383, %f382, %f315;
+	mul.f32 	%f384, %f378, %f315;
+	mul.f32 	%f385, %f374, %f315;
+	mul.f32 	%f386, %f370, %f315;
+	mul.f32 	%f387, %f366, %f315;
+	mul.f32 	%f388, %f362, %f315;
+	mul.f32 	%f389, %f358, %f315;
+	mul.f32 	%f390, %f354, %f315;
+	mul.f32 	%f391, %f349, %f316;
+	mul.f32 	%f392, %f345, %f316;
+	mul.f32 	%f393, %f341, %f316;
+	mul.f32 	%f394, %f337, %f316;
+	mul.f32 	%f395, %f333, %f316;
+	mul.f32 	%f396, %f329, %f316;
+	mul.f32 	%f397, %f325, %f316;
+	mul.f32 	%f398, %f321, %f316;
+	.loc	1 74 24
+	shl.b32 	%r357, %r2, 2;
+	mov.u32 	%r358, global_smem;
+	add.s32 	%r359, %r358, %r357;
+	st.shared.u32 	[%r359], %r214;
+	bar.sync 	0;
+	shl.b32 	%r360, %r1, 2;
+	add.s32 	%r361, %r358, %r360;
+	ld.shared.v4.f32 	{%f399, %f400, %f401, %f402}, [%r361];
+	ld.shared.v4.f32 	{%f403, %f404, %f405, %f406}, [%r361+16];
+	mul.f32 	%f407, %f383, %f399;
+	mul.f32 	%f408, %f384, %f400;
+	mul.f32 	%f409, %f385, %f401;
+	mul.f32 	%f410, %f386, %f402;
+	mul.f32 	%f411, %f387, %f403;
+	mul.f32 	%f412, %f388, %f404;
+	mul.f32 	%f413, %f389, %f405;
+	mul.f32 	%f414, %f390, %f406;
+	mul.f32 	%f415, %f391, %f399;
+	mul.f32 	%f416, %f392, %f400;
+	mul.f32 	%f417, %f393, %f401;
+	mul.f32 	%f418, %f394, %f402;
+	mul.f32 	%f419, %f395, %f403;
+	mul.f32 	%f420, %f396, %f404;
+	mul.f32 	%f421, %f397, %f405;
+	mul.f32 	%f422, %f398, %f406;
+	.loc	1 76 39
+	shl.b32 	%r362, %r3, 8;
+	shl.b32 	%r363, %r4, 8;
+	.loc	1 76 35
+	or.b32  	%r364, %r362, %r1;
+	or.b32  	%r365, %r363, %r1;
+	.loc	1 76 29
+	mul.wide.s32 	%rd110, %r364, 2;
+	add.s64 	%rd108, %rd14, %rd110;
+	mul.wide.s32 	%rd111, %r365, 2;
+	add.s64 	%rd109, %rd14, %rd111;
+	.loc	1 76 52
+	mov.b32 	%r333, %f407;
+	cvt.rn.bf16.f32 %rs1, %r333;
+	mov.b32 	%r334, %f408;
+	cvt.rn.bf16.f32 %rs2, %r334;
+	mov.b32 	%r335, %f409;
+	cvt.rn.bf16.f32 %rs3, %r335;
+	mov.b32 	%r336, %f410;
+	cvt.rn.bf16.f32 %rs4, %r336;
+	mov.b32 	%r337, %f411;
+	cvt.rn.bf16.f32 %rs5, %r337;
+	mov.b32 	%r338, %f412;
+	cvt.rn.bf16.f32 %rs6, %r338;
+	mov.b32 	%r339, %f413;
+	cvt.rn.bf16.f32 %rs7, %r339;
+	mov.b32 	%r340, %f414;
+	cvt.rn.bf16.f32 %rs8, %r340;
+	mov.b32 	%r341, %f415;
+	cvt.rn.bf16.f32 %rs9, %r341;
+	mov.b32 	%r342, %f416;
+	cvt.rn.bf16.f32 %rs10, %r342;
+	mov.b32 	%r343, %f417;
+	cvt.rn.bf16.f32 %rs11, %r343;
+	mov.b32 	%r344, %f418;
+	cvt.rn.bf16.f32 %rs12, %r344;
+	mov.b32 	%r345, %f419;
+	cvt.rn.bf16.f32 %rs13, %r345;
+	mov.b32 	%r346, %f420;
+	cvt.rn.bf16.f32 %rs14, %r346;
+	mov.b32 	%r347, %f421;
+	cvt.rn.bf16.f32 %rs15, %r347;
+	mov.b32 	%r348, %f422;
+	cvt.rn.bf16.f32 %rs16, %r348;
+	mov.b32 	%r366, {%rs1, %rs2};
+	mov.b32 	%r367, {%rs3, %rs4};
+	mov.b32 	%r368, {%rs5, %rs6};
+	mov.b32 	%r369, {%rs7, %rs8};
+	@%p93 st.global.v4.b32 [ %rd108 + 0 ], { %r366, %r367, %r368, %r369 };
+	mov.b32 	%r370, {%rs9, %rs10};
+	mov.b32 	%r371, {%rs11, %rs12};
+	mov.b32 	%r372, {%rs13, %rs14};
+	mov.b32 	%r373, {%rs15, %rs16};
+	@%p93 st.global.v4.b32 [ %rd109 + 0 ], { %r370, %r371, %r372, %r373 };
+	.loc	1 55 4
+	ret;
+$L__tmp37:
+$L__func_end0:
+
+}
+	// .globl	__nv_rsqrtf
+.visible .func  (.param .b32 func_retval0) __nv_rsqrtf(
+	.param .b32 __nv_rsqrtf_param_0
+)
+{
+	.reg .f32 	%f<3>;
+$L__func_begin1:
+
+	ld.param.f32 	%f1, [__nv_rsqrtf_param_0];
+	rsqrt.approx.ftz.f32 	%f2, %f1;
+	st.param.f32 	[func_retval0+0], %f2;
+	ret;
+$L__func_end1:
+
+}
+	.file	1 "/tmp/torchinductor_root/gx/cgx5lxpuexpindj4dsmjz5x42uhyy7iskevq7ovzpwagb3t5powj.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
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+	}
+	.section	.debug_info
+	{
+.b32 298
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+.b64 $L__tmp1
+.b64 $L__tmp2
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+.b64 $L__tmp3
+.b64 $L__tmp31
+.b8 2
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+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
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+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 302
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/345a87a492fd703c73ab83265a21fcb6/triton_.ttgir

@@ -0,0 +1,125 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 8], threadsPerWarp = [1, 32], warpsPerCTA = [8, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [8, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked2 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 8], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5de6de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<512> : tensor<16x1xi32, #blocked>
+    %cst_0 = arith.constant dense<256> : tensor<1x256xi32, #blocked>
+    %cst_1 = arith.constant dense<256> : tensor<16x1xi32, #blocked>
+    %cst_2 = arith.constant dense<1.000000e+00> : tensor<1x256xf32, #blocked>
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<1x256xf32, #blocked>
+    %cst_4 = arith.constant dense<256> : tensor<16x1xi64, #blocked>
+    %cst_5 = arith.constant dense<50257> : tensor<16x1xi64, #blocked>
+    %cst_6 = arith.constant dense<0> : tensor<16x1xi64, #blocked>
+    %cst_7 = arith.constant dense<0> : tensor<16x1xi64, #blocked1>
+    %cst_8 = arith.constant dense<50257> : tensor<16x1xi64, #blocked1>
+    %cst_9 = arith.constant 0.000000e+00 : f32
+    %cst_10 = arith.constant dense<0.000000e+00> : tensor<1x256xf32, #blocked2>
+    %cst_11 = arith.constant dense<256> : tensor<1x256xi32, #blocked2>
+    %cst_12 = arith.constant dense<9.99999974E-6> : tensor<16x1xf32, #blocked>
+    %cst_13 = arith.constant dense<2.560000e+02> : tensor<16x1xf32, #blocked>
+    %cst_14 = arith.constant dense<0.000000e+00> : tensor<16x256xf32, #blocked>
+    %c16_i32 = arith.constant 16 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c16_i32 : i32
+    %2 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %3 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xi32, #blocked>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<16x1xi32, #blocked1>
+    %6 = tt.splat %1 : (i32) -> tensor<16x1xi32, #blocked>
+    %7 = tt.splat %1 : (i32) -> tensor<16x1xi32, #blocked1>
+    %8 = arith.addi %6, %4 : tensor<16x1xi32, #blocked>
+    %9 = arith.addi %7, %5 : tensor<16x1xi32, #blocked1>
+    %10 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %11 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #triton_gpu.slice<{dim = 0, parent = #blocked2}>>
+    %12 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<256xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x256xi32, #blocked>
+    %13 = tt.expand_dims %11 {axis = 0 : i32} : (tensor<256xi32, #triton_gpu.slice<{dim = 0, parent = #blocked2}>>) -> tensor<1x256xi32, #blocked2>
+    %14 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>, #blocked>
+    %15 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>, #blocked1>
+    %16 = tt.addptr %14, %8 : tensor<16x1x!tt.ptr<i64, 1>, #blocked>, tensor<16x1xi32, #blocked>
+    %17 = tt.addptr %15, %9 : tensor<16x1x!tt.ptr<i64, 1>, #blocked1>, tensor<16x1xi32, #blocked1>
+    %18 = tt.load %16 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64, #blocked>
+    %19 = tt.load %17 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64, #blocked1>
+    %20 = arith.remsi %8, %cst : tensor<16x1xi32, #blocked>
+    %21 = arith.cmpi slt, %12, %cst_0 : tensor<1x256xi32, #blocked>
+    %22 = arith.cmpi slt, %13, %cst_11 : tensor<1x256xi32, #blocked2>
+    %23 = arith.muli %20, %cst_1 : tensor<16x1xi32, #blocked>
+    %24 = tt.broadcast %12 : (tensor<1x256xi32, #blocked>) -> tensor<16x256xi32, #blocked>
+    %25 = tt.broadcast %23 : (tensor<16x1xi32, #blocked>) -> tensor<16x256xi32, #blocked>
+    %26 = arith.addi %24, %25 : tensor<16x256xi32, #blocked>
+    %27 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<16x256x!tt.ptr<f32, 1>, #blocked>
+    %28 = tt.addptr %27, %26 : tensor<16x256x!tt.ptr<f32, 1>, #blocked>, tensor<16x256xi32, #blocked>
+    %29 = tt.broadcast %21 : (tensor<1x256xi1, #blocked>) -> tensor<16x256xi1, #blocked>
+    %30 = tt.load %28, %29, %cst_14 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32, #blocked>
+    %31 = arith.addi %18, %cst_5 : tensor<16x1xi64, #blocked>
+    %32 = arith.addi %19, %cst_8 : tensor<16x1xi64, #blocked1>
+    %33 = arith.cmpi slt, %18, %cst_6 : tensor<16x1xi64, #blocked>
+    %34 = arith.cmpi slt, %19, %cst_7 : tensor<16x1xi64, #blocked1>
+    %35 = arith.select %33, %31, %18 : tensor<16x1xi1, #blocked>, tensor<16x1xi64, #blocked>
+    %36 = arith.select %34, %32, %19 : tensor<16x1xi1, #blocked1>, tensor<16x1xi64, #blocked1>
+    %37 = arith.cmpi sge, %36, %cst_7 : tensor<16x1xi64, #blocked1>
+    %38 = arith.cmpi slt, %36, %cst_8 : tensor<16x1xi64, #blocked1>
+    %39 = arith.andi %37, %38 : tensor<16x1xi1, #blocked1>
+    tt.assert %39, "index out of bounds: 0 <= tmp3 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<16x1xi1, #blocked1>
+    %40 = arith.muli %35, %cst_4 : tensor<16x1xi64, #blocked>
+    %41 = tt.broadcast %40 : (tensor<16x1xi64, #blocked>) -> tensor<16x256xi64, #blocked>
+    %42 = arith.extsi %12 : tensor<1x256xi32, #blocked> to tensor<1x256xi64, #blocked>
+    %43 = tt.broadcast %42 : (tensor<1x256xi64, #blocked>) -> tensor<16x256xi64, #blocked>
+    %44 = arith.addi %43, %41 : tensor<16x256xi64, #blocked>
+    %45 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<16x256x!tt.ptr<f32, 1>, #blocked>
+    %46 = tt.addptr %45, %44 : tensor<16x256x!tt.ptr<f32, 1>, #blocked>, tensor<16x256xi64, #blocked>
+    %47 = tt.load %46, %29, %cst_14 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32, #blocked>
+    %48 = arith.addf %47, %30 : tensor<16x256xf32, #blocked>
+    %49 = arith.addf %48, %cst_14 : tensor<16x256xf32, #blocked>
+    %50 = arith.subf %48, %49 : tensor<16x256xf32, #blocked>
+    %51 = arith.mulf %48, %50 : tensor<16x256xf32, #blocked>
+    %52 = arith.addf %51, %cst_14 : tensor<16x256xf32, #blocked>
+    %53 = arith.select %29, %49, %cst_14 : tensor<16x256xi1, #blocked>, tensor<16x256xf32, #blocked>
+    %54 = arith.select %29, %52, %cst_14 : tensor<16x256xi1, #blocked>, tensor<16x256xf32, #blocked>
+    %55 = arith.select %21, %cst_2, %cst_3 : tensor<1x256xi1, #blocked>, tensor<1x256xf32, #blocked>
+    %56 = tt.broadcast %55 : (tensor<1x256xf32, #blocked>) -> tensor<16x256xf32, #blocked>
+    %57:3 = "tt.reduce"(%53, %54, %56) <{axis = 1 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32, %arg9: f32, %arg10: f32, %arg11: f32, %arg12: f32):
+      %82 = arith.subf %arg10, %arg7 : f32
+      %83 = arith.addf %arg9, %arg12 : f32
+      %84 = arith.cmpf oeq, %83, %cst_9 : f32
+      %85 = arith.divf %arg12, %83 : f32
+      %86 = arith.select %84, %cst_9, %85 : f32
+      %87 = arith.mulf %82, %86 : f32
+      %88 = arith.addf %arg7, %87 : f32
+      %89 = arith.addf %arg8, %arg11 : f32
+      %90 = arith.mulf %82, %82 : f32
+      %91 = arith.mulf %90, %arg9 : f32
+      %92 = arith.mulf %91, %86 : f32
+      %93 = arith.addf %89, %92 : f32
+      tt.reduce.return %88, %93, %83 : f32, f32, f32
+    }) : (tensor<16x256xf32, #blocked>, tensor<16x256xf32, #blocked>, tensor<16x256xf32, #blocked>) -> (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>, tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>, tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>)
+    %58 = tt.expand_dims %57#0 {axis = 1 : i32} : (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xf32, #blocked>
+    %59 = tt.expand_dims %57#1 {axis = 1 : i32} : (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xf32, #blocked>
+    %60 = tt.load %28, %29, %cst_14 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32, #blocked>
+    %61 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<1x256x!tt.ptr<f32, 1>, #blocked2>
+    %62 = tt.addptr %61, %13 : tensor<1x256x!tt.ptr<f32, 1>, #blocked2>, tensor<1x256xi32, #blocked2>
+    %63 = tt.load %62, %22, %cst_10 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1x256xf32, #blocked2>
+    tt.assert %39, "index out of bounds: 0 <= tmp13 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<16x1xi1, #blocked1>
+    %64 = tt.load %46, %29, %cst_14 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<16x256xf32, #blocked>
+    %65 = arith.addf %64, %60 : tensor<16x256xf32, #blocked>
+    %66 = tt.broadcast %58 : (tensor<16x1xf32, #blocked>) -> tensor<16x256xf32, #blocked>
+    %67 = arith.subf %65, %66 : tensor<16x256xf32, #blocked>
+    %68 = arith.divf %59, %cst_13 : tensor<16x1xf32, #blocked>
+    %69 = arith.addf %68, %cst_12 : tensor<16x1xf32, #blocked>
+    %70 = tt.extern_elementwise %69 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (tensor<16x1xf32, #blocked>) -> tensor<16x1xf32, #blocked>
+    %71 = tt.broadcast %70 : (tensor<16x1xf32, #blocked>) -> tensor<16x256xf32, #blocked>
+    %72 = arith.mulf %67, %71 : tensor<16x256xf32, #blocked>
+    %73 = triton_gpu.convert_layout %63 : (tensor<1x256xf32, #blocked2>) -> tensor<1x256xf32, #blocked>
+    %74 = tt.broadcast %73 : (tensor<1x256xf32, #blocked>) -> tensor<16x256xf32, #blocked>
+    %75 = arith.mulf %72, %74 : tensor<16x256xf32, #blocked>
+    %76 = arith.muli %8, %cst_1 : tensor<16x1xi32, #blocked>
+    %77 = tt.broadcast %76 : (tensor<16x1xi32, #blocked>) -> tensor<16x256xi32, #blocked>
+    %78 = arith.addi %24, %77 : tensor<16x256xi32, #blocked>
+    %79 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<16x256x!tt.ptr<bf16, 1>, #blocked>
+    %80 = tt.addptr %79, %78 : tensor<16x256x!tt.ptr<bf16, 1>, #blocked>, tensor<16x256xi32, #blocked>
+    %81 = arith.truncf %75 : tensor<16x256xf32, #blocked> to tensor<16x256xbf16, #blocked>
+    tt.store %80, %81, %29 {cache = 1 : i32, evict = 1 : i32} : tensor<16x256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/345a87a492fd703c73ab83265a21fcb6/triton_.ttir

@@ -0,0 +1,104 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5de6de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<1.000000e+00> : tensor<1x256xf32>
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1x256xf32>
+    %cst_1 = arith.constant 0.000000e+00 : f32
+    %cst_2 = arith.constant dense<256> : tensor<16x1xi64>
+    %cst_3 = arith.constant dense<50257> : tensor<16x1xi64>
+    %cst_4 = arith.constant dense<0> : tensor<16x1xi64>
+    %cst_5 = arith.constant dense<9.99999974E-6> : tensor<16x1xf32>
+    %cst_6 = arith.constant dense<2.560000e+02> : tensor<16x1xf32>
+    %cst_7 = arith.constant dense<0.000000e+00> : tensor<16x256xf32>
+    %cst_8 = arith.constant dense<256> : tensor<16x1xi32>
+    %cst_9 = arith.constant dense<256> : tensor<1x256xi32>
+    %cst_10 = arith.constant dense<512> : tensor<16x1xi32>
+    %c16_i32 = arith.constant 16 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c16_i32 : i32
+    %2 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32>
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<16xi32>) -> tensor<16x1xi32>
+    %4 = tt.splat %1 : (i32) -> tensor<16x1xi32>
+    %5 = arith.addi %4, %3 : tensor<16x1xi32>
+    %6 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %7 = tt.expand_dims %6 {axis = 0 : i32} : (tensor<256xi32>) -> tensor<1x256xi32>
+    %8 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>>
+    %9 = tt.addptr %8, %5 : tensor<16x1x!tt.ptr<i64, 1>>, tensor<16x1xi32>
+    %10 = tt.load %9 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64>
+    %11 = arith.remsi %5, %cst_10 : tensor<16x1xi32>
+    %12 = arith.cmpi slt, %7, %cst_9 : tensor<1x256xi32>
+    %13 = arith.muli %11, %cst_8 : tensor<16x1xi32>
+    %14 = tt.broadcast %7 : (tensor<1x256xi32>) -> tensor<16x256xi32>
+    %15 = tt.broadcast %13 : (tensor<16x1xi32>) -> tensor<16x256xi32>
+    %16 = arith.addi %14, %15 : tensor<16x256xi32>
+    %17 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<16x256x!tt.ptr<f32, 1>>
+    %18 = tt.addptr %17, %16 : tensor<16x256x!tt.ptr<f32, 1>>, tensor<16x256xi32>
+    %19 = tt.broadcast %12 : (tensor<1x256xi1>) -> tensor<16x256xi1>
+    %20 = tt.load %18, %19, %cst_7 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32>
+    %21 = arith.addi %10, %cst_3 : tensor<16x1xi64>
+    %22 = arith.cmpi slt, %10, %cst_4 : tensor<16x1xi64>
+    %23 = arith.select %22, %21, %10 : tensor<16x1xi1>, tensor<16x1xi64>
+    %24 = arith.cmpi sge, %23, %cst_4 : tensor<16x1xi64>
+    %25 = arith.cmpi slt, %23, %cst_3 : tensor<16x1xi64>
+    %26 = arith.andi %24, %25 : tensor<16x1xi1>
+    tt.assert %26, "index out of bounds: 0 <= tmp3 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<16x1xi1>
+    %27 = arith.muli %23, %cst_2 : tensor<16x1xi64>
+    %28 = tt.broadcast %27 : (tensor<16x1xi64>) -> tensor<16x256xi64>
+    %29 = arith.extsi %7 : tensor<1x256xi32> to tensor<1x256xi64>
+    %30 = tt.broadcast %29 : (tensor<1x256xi64>) -> tensor<16x256xi64>
+    %31 = arith.addi %30, %28 : tensor<16x256xi64>
+    %32 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<16x256x!tt.ptr<f32, 1>>
+    %33 = tt.addptr %32, %31 : tensor<16x256x!tt.ptr<f32, 1>>, tensor<16x256xi64>
+    %34 = tt.load %33, %19, %cst_7 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32>
+    %35 = arith.addf %34, %20 : tensor<16x256xf32>
+    %36 = arith.addf %35, %cst_7 : tensor<16x256xf32>
+    %37 = arith.subf %35, %36 : tensor<16x256xf32>
+    %38 = arith.mulf %35, %37 : tensor<16x256xf32>
+    %39 = arith.addf %38, %cst_7 : tensor<16x256xf32>
+    %40 = arith.select %19, %36, %cst_7 : tensor<16x256xi1>, tensor<16x256xf32>
+    %41 = arith.select %19, %39, %cst_7 : tensor<16x256xi1>, tensor<16x256xf32>
+    %42 = arith.select %12, %cst, %cst_0 : tensor<1x256xi1>, tensor<1x256xf32>
+    %43 = tt.broadcast %42 : (tensor<1x256xf32>) -> tensor<16x256xf32>
+    %44:3 = "tt.reduce"(%40, %41, %43) <{axis = 1 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32, %arg9: f32, %arg10: f32, %arg11: f32, %arg12: f32):
+      %68 = arith.subf %arg10, %arg7 : f32
+      %69 = arith.addf %arg9, %arg12 : f32
+      %70 = arith.cmpf oeq, %69, %cst_1 : f32
+      %71 = arith.divf %arg12, %69 : f32
+      %72 = arith.select %70, %cst_1, %71 : f32
+      %73 = arith.mulf %68, %72 : f32
+      %74 = arith.addf %arg7, %73 : f32
+      %75 = arith.addf %arg8, %arg11 : f32
+      %76 = arith.mulf %68, %68 : f32
+      %77 = arith.mulf %76, %arg9 : f32
+      %78 = arith.mulf %77, %72 : f32
+      %79 = arith.addf %75, %78 : f32
+      tt.reduce.return %74, %79, %69 : f32, f32, f32
+    }) : (tensor<16x256xf32>, tensor<16x256xf32>, tensor<16x256xf32>) -> (tensor<16xf32>, tensor<16xf32>, tensor<16xf32>)
+    %45 = tt.expand_dims %44#0 {axis = 1 : i32} : (tensor<16xf32>) -> tensor<16x1xf32>
+    %46 = tt.expand_dims %44#1 {axis = 1 : i32} : (tensor<16xf32>) -> tensor<16x1xf32>
+    %47 = tt.load %18, %19, %cst_7 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x256xf32>
+    %48 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<1x256x!tt.ptr<f32, 1>>
+    %49 = tt.addptr %48, %7 : tensor<1x256x!tt.ptr<f32, 1>>, tensor<1x256xi32>
+    %50 = tt.load %49, %12, %cst_0 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1x256xf32>
+    tt.assert %26, "index out of bounds: 0 <= tmp13 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<16x1xi1>
+    %51 = tt.load %33, %19, %cst_7 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<16x256xf32>
+    %52 = arith.addf %51, %47 : tensor<16x256xf32>
+    %53 = tt.broadcast %45 : (tensor<16x1xf32>) -> tensor<16x256xf32>
+    %54 = arith.subf %52, %53 : tensor<16x256xf32>
+    %55 = arith.divf %46, %cst_6 : tensor<16x1xf32>
+    %56 = arith.addf %55, %cst_5 : tensor<16x1xf32>
+    %57 = tt.extern_elementwise %56 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (tensor<16x1xf32>) -> tensor<16x1xf32>
+    %58 = tt.broadcast %57 : (tensor<16x1xf32>) -> tensor<16x256xf32>
+    %59 = arith.mulf %54, %58 : tensor<16x256xf32>
+    %60 = tt.broadcast %50 : (tensor<1x256xf32>) -> tensor<16x256xf32>
+    %61 = arith.mulf %59, %60 : tensor<16x256xf32>
+    %62 = arith.muli %5, %cst_8 : tensor<16x1xi32>
+    %63 = tt.broadcast %62 : (tensor<16x1xi32>) -> tensor<16x256xi32>
+    %64 = arith.addi %14, %63 : tensor<16x256xi32>
+    %65 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<16x256x!tt.ptr<bf16, 1>>
+    %66 = tt.addptr %65, %64 : tensor<16x256x!tt.ptr<bf16, 1>>, tensor<16x256xi32>
+    %67 = arith.truncf %61 : tensor<16x256xf32> to tensor<16x256xbf16>
+    tt.store %66, %67, %19 {cache = 1 : i32, evict = 1 : i32} : tensor<16x256xbf16>
+    tt.return
+  }
+}

.triton/dump/3cd3b6d7993c56f7d0340d40c84f737c/triton_.llir

@@ -0,0 +1,355 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@assertFunc_1 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_1 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_1 = internal constant [39 x i8] c"index out of bounds: 0 <= tmp16 < 50257"
+@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp3 < 50257"
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr
+
+define void @triton__0d1d2d3d4d5d6de7de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, i32 %6, i32 %7) local_unnamed_addr !dbg !7 {
+  %9 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %10 = lshr i32 %9, 2, !dbg !10
+  %11 = and i32 %10, 63, !dbg !10
+  %12 = and i32 %9, 63, !dbg !10
+  %13 = and i32 %9, 3, !dbg !11
+  %14 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #5, !dbg !12
+  %15 = shl i32 %14, 6, !dbg !13
+  %16 = or i32 %15, %11, !dbg !14
+  %17 = or i32 %15, %12, !dbg !14
+  %18 = sext i32 %16 to i64, !dbg !15
+  %19 = getelementptr i64, ptr addrspace(1) %0, i64 %18, !dbg !15
+  %20 = sext i32 %17 to i64, !dbg !15
+  %21 = getelementptr i64, ptr addrspace(1) %0, i64 %20, !dbg !15
+  %22 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %19, i1 true) #5, !dbg !16
+  %23 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %21, i1 true) #5, !dbg !16
+  %24 = srem i32 %16, 512, !dbg !17
+  %25 = shl nsw i32 %24, 8, !dbg !18
+  %26 = shl i32 %16, 8, !dbg !19
+  %27 = add i64 %23, 50257, !dbg !20
+  %28 = icmp slt i64 %22, 0, !dbg !21
+  %29 = icmp slt i64 %23, 0, !dbg !21
+  %30 = select i1 %29, i64 %27, i64 %23, !dbg !22
+  %.fr8 = freeze i64 %30, !dbg !23
+  %31 = icmp ugt i64 %.fr8, 50256, !dbg !23
+  %32 = shl i64 %22, 8, !dbg !24
+  %33 = add i64 %32, 12865792, !dbg !24
+  %34 = select i1 %28, i64 %33, i64 %32, !dbg !24
+  %35 = getelementptr float, ptr addrspace(1) %1, i64 %34
+  br i1 %31, label %.split.us, label %.split, !dbg !25
+
+.split.us:                                        ; preds = %8, %.split.us
+  %36 = phi float [ %58, %.split.us ], [ 0.000000e+00, %8 ]
+  %37 = phi float [ %63, %.split.us ], [ 0.000000e+00, %8 ]
+  %38 = phi float [ %60, %.split.us ], [ 0.000000e+00, %8 ]
+  %39 = phi i32 [ %64, %.split.us ], [ 0, %8 ]
+  %40 = or i32 %39, %13, !dbg !26
+  %41 = add i32 %40, %25, !dbg !27
+  %42 = sext i32 %41 to i64, !dbg !28
+  %43 = getelementptr float, ptr addrspace(1) %2, i64 %42, !dbg !28
+  %44 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %43, i1 true, i32 0, i1 true) #5, !dbg !29
+  %45 = bitcast i32 %44 to float, !dbg !29
+  %46 = add i32 %40, %26, !dbg !30
+  %47 = sext i32 %46 to i64, !dbg !31
+  %48 = getelementptr i16, ptr addrspace(1) %3, i64 %47, !dbg !31
+  %49 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %48, i1 true, i16 0, i1 true) #5, !dbg !32
+  %50 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %49) #5, !dbg !33
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !25
+  %51 = zext nneg i32 %40 to i64, !dbg !34
+  %52 = getelementptr float, ptr addrspace(1) %35, i64 %51, !dbg !35
+  %53 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %52, i1 true, i32 0, i1 true) #5, !dbg !36
+  %54 = bitcast i32 %53 to float, !dbg !36
+  %55 = fadd float %45, %54, !dbg !37
+  %56 = fadd float %50, %55, !dbg !38
+  %57 = fsub float %56, %38, !dbg !39
+  %58 = fadd float %36, 1.000000e+00, !dbg !43
+  %59 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %57, float %58) #5, !dbg !44
+  %60 = fadd float %38, %59, !dbg !45
+  %61 = fsub float %56, %60, !dbg !46
+  %62 = fmul float %57, %61, !dbg !47
+  %63 = fadd float %37, %62, !dbg !48
+  %64 = add nuw nsw i32 %39, 4, !dbg !49
+  %65 = icmp ult i32 %39, 252, !dbg !49
+  br i1 %65, label %.split.us, label %.split5.us, !dbg !49
+
+.split:                                           ; preds = %8, %.split
+  %66 = phi float [ %88, %.split ], [ 0.000000e+00, %8 ]
+  %67 = phi float [ %93, %.split ], [ 0.000000e+00, %8 ]
+  %68 = phi float [ %90, %.split ], [ 0.000000e+00, %8 ]
+  %69 = phi i32 [ %94, %.split ], [ 0, %8 ]
+  %70 = or i32 %69, %13, !dbg !26
+  %71 = add i32 %70, %25, !dbg !27
+  %72 = sext i32 %71 to i64, !dbg !28
+  %73 = getelementptr float, ptr addrspace(1) %2, i64 %72, !dbg !28
+  %74 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %73, i1 true, i32 0, i1 true) #5, !dbg !29
+  %75 = bitcast i32 %74 to float, !dbg !29
+  %76 = add i32 %70, %26, !dbg !30
+  %77 = sext i32 %76 to i64, !dbg !31
+  %78 = getelementptr i16, ptr addrspace(1) %3, i64 %77, !dbg !31
+  %79 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %78, i1 true, i16 0, i1 true) #5, !dbg !32
+  %80 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %79) #5, !dbg !33
+  %81 = zext nneg i32 %70 to i64, !dbg !34
+  %82 = getelementptr float, ptr addrspace(1) %35, i64 %81, !dbg !35
+  %83 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %82, i1 true, i32 0, i1 true) #5, !dbg !36
+  %84 = bitcast i32 %83 to float, !dbg !36
+  %85 = fadd float %75, %84, !dbg !37
+  %86 = fadd float %80, %85, !dbg !38
+  %87 = fsub float %86, %68, !dbg !39
+  %88 = fadd float %66, 1.000000e+00, !dbg !43
+  %89 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %87, float %88) #5, !dbg !44
+  %90 = fadd float %68, %89, !dbg !45
+  %91 = fsub float %86, %90, !dbg !46
+  %92 = fmul float %87, %91, !dbg !47
+  %93 = fadd float %67, %92, !dbg !48
+  %94 = add nuw nsw i32 %69, 4, !dbg !49
+  %95 = icmp ult i32 %69, 252, !dbg !49
+  br i1 %95, label %.split, label %.split5.us, !dbg !49
+
+.split5.us:                                       ; preds = %.split, %.split.us
+  %.us-phi = phi float [ %60, %.split.us ], [ %90, %.split ]
+  %.us-phi6 = phi float [ %63, %.split.us ], [ %93, %.split ]
+  %.us-phi7 = phi float [ %58, %.split.us ], [ %88, %.split ]
+  %96 = bitcast float %.us-phi to i32, !dbg !50
+  %97 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %96, i32 2, i32 31), !dbg !50
+  %98 = bitcast i32 %97 to float, !dbg !50
+  %99 = bitcast float %.us-phi6 to i32, !dbg !50
+  %100 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %99, i32 2, i32 31), !dbg !50
+  %101 = bitcast i32 %100 to float, !dbg !50
+  %102 = bitcast float %.us-phi7 to i32, !dbg !50
+  %103 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %102, i32 2, i32 31), !dbg !50
+  %104 = bitcast i32 %103 to float, !dbg !50
+  %105 = fsub float %98, %.us-phi, !dbg !52
+  %106 = fadd float %.us-phi7, %104, !dbg !56
+  %107 = fcmp oeq float %106, 0.000000e+00, !dbg !57
+  %108 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %104, float %106) #5, !dbg !58
+  %109 = select i1 %107, float 0.000000e+00, float %108, !dbg !59
+  %110 = fmul float %105, %109, !dbg !60
+  %111 = fadd float %.us-phi, %110, !dbg !61
+  %112 = fadd float %.us-phi6, %101, !dbg !62
+  %113 = fmul float %105, %105, !dbg !63
+  %114 = fmul float %.us-phi7, %113, !dbg !64
+  %115 = fmul float %114, %109, !dbg !65
+  %116 = fadd float %112, %115, !dbg !66
+  %117 = bitcast float %111 to i32, !dbg !50
+  %118 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %117, i32 1, i32 31), !dbg !50
+  %119 = bitcast i32 %118 to float, !dbg !50
+  %120 = bitcast float %116 to i32, !dbg !50
+  %121 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %120, i32 1, i32 31), !dbg !50
+  %122 = bitcast i32 %121 to float, !dbg !50
+  %123 = bitcast float %106 to i32, !dbg !50
+  %124 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %123, i32 1, i32 31), !dbg !50
+  %125 = bitcast i32 %124 to float, !dbg !50
+  %126 = fsub float %119, %111, !dbg !52
+  %127 = fadd float %106, %125, !dbg !56
+  %128 = fcmp oeq float %127, 0.000000e+00, !dbg !57
+  %129 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %125, float %127) #5, !dbg !58
+  %130 = select i1 %128, float 0.000000e+00, float %129, !dbg !59
+  %131 = fmul float %126, %130, !dbg !60
+  %132 = fadd float %111, %131, !dbg !61
+  %133 = fadd float %116, %122, !dbg !62
+  %134 = fmul float %126, %126, !dbg !63
+  %135 = fmul float %106, %134, !dbg !64
+  %136 = fmul float %130, %135, !dbg !65
+  %137 = fadd float %133, %136, !dbg !66
+  %138 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %137, float 2.560000e+02) #5, !dbg !67
+  %139 = fadd float %138, 0x3EE4F8B580000000, !dbg !68
+  br label %140, !dbg !69
+
+140:                                              ; preds = %.split5.us, %__nv_rsqrtf.exit
+  %141 = phi i32 [ 0, %.split5.us ], [ %174, %__nv_rsqrtf.exit ]
+  %142 = or i32 %141, %13, !dbg !70
+  %143 = add i32 %142, %25, !dbg !71
+  %144 = sext i32 %143 to i64, !dbg !72
+  %145 = getelementptr float, ptr addrspace(1) %2, i64 %144, !dbg !72
+  %146 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %145, i1 true, i32 0, i1 true) #5, !dbg !73
+  %147 = bitcast i32 %146 to float, !dbg !73
+  %148 = add i32 %142, %26, !dbg !74
+  %149 = sext i32 %148 to i64, !dbg !75
+  %150 = getelementptr i16, ptr addrspace(1) %3, i64 %149, !dbg !75
+  %151 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %150, i1 true, i16 0, i1 true) #5, !dbg !76
+  %152 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %151) #5, !dbg !77
+  %153 = zext nneg i32 %142 to i64, !dbg !78
+  %154 = getelementptr float, ptr addrspace(1) %4, i64 %153, !dbg !78
+  %155 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %154, i1 true, i32 0, i1 true) #5, !dbg !79
+  %156 = bitcast i32 %155 to float, !dbg !79
+  br i1 %31, label %157, label %158, !dbg !80
+
+157:                                              ; preds = %140
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 883, ptr nonnull @assertFunc_1, i64 1), !dbg !80
+  br label %158, !dbg !80
+
+158:                                              ; preds = %157, %140
+  %159 = getelementptr float, ptr addrspace(1) %35, i64 %153, !dbg !81
+  %160 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %159, i1 true, i32 0, i1 true) #5, !dbg !82
+  %161 = bitcast i32 %160 to float, !dbg !82
+  %162 = fadd float %147, %161, !dbg !83
+  %163 = fadd float %152, %162, !dbg !84
+  %164 = fsub float %163, %132, !dbg !85
+  %165 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !86
+  %.not.i = icmp eq i32 %165, 0, !dbg !86
+  br i1 %.not.i, label %168, label %166, !dbg !86
+
+166:                                              ; preds = %158
+  %167 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %139), !dbg !86
+  br label %__nv_rsqrtf.exit, !dbg !86
+
+168:                                              ; preds = %158
+  %169 = tail call float @llvm.nvvm.rsqrt.approx.f(float %139), !dbg !86
+  br label %__nv_rsqrtf.exit, !dbg !86
+
+__nv_rsqrtf.exit:                                 ; preds = %166, %168
+  %.0.i = phi float [ %167, %166 ], [ %169, %168 ], !dbg !86
+  %170 = fmul float %164, %.0.i, !dbg !87
+  %171 = fmul float %170, %156, !dbg !88
+  %172 = getelementptr i16, ptr addrspace(1) %5, i64 %149, !dbg !89
+  %173 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %171) #5, !dbg !90
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %173, ptr addrspace(1) %172, i1 true) #5, !dbg !90
+  %174 = add nuw nsw i32 %141, 4, !dbg !69
+  %175 = icmp ult i32 %141, 252, !dbg !69
+  br i1 %175, label %140, label %176, !dbg !69
+
+176:                                              ; preds = %__nv_rsqrtf.exit
+  ret void, !dbg !91
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_rsqrtf(float %x) local_unnamed_addr #2 {
+  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5
+  %.not = icmp eq i32 %1, 0
+  br i1 %.not, label %4, label %2
+
+2:                                                ; preds = %0
+  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
+  br label %6
+
+4:                                                ; preds = %0
+  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
+  br label %6
+
+6:                                                ; preds = %4, %2
+  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
+  ret float %.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #3
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #4
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cpn3lawg65lpi63gv6c6pn4oikhg6qva2h2qjdpxe6qj4lvttwez.py", directory: "/tmp/torchinductor_root/pn")
+!4 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2d3d4d5d6de7de, !"maxntidx", i32 256}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6de7de", linkageName: "triton__0d1d2d3d4d5d6de7de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 22, column: 44, scope: !7)
+!11 = !DILocation(line: 24, column: 33, scope: !7)
+!12 = !DILocation(line: 21, column: 28, scope: !7)
+!13 = !DILocation(line: 21, column: 33, scope: !7)
+!14 = !DILocation(line: 22, column: 23, scope: !7)
+!15 = !DILocation(line: 26, column: 30, scope: !7)
+!16 = !DILocation(line: 26, column: 35, scope: !7)
+!17 = !DILocation(line: 27, column: 18, scope: !7)
+!18 = !DILocation(line: 35, column: 44, scope: !7)
+!19 = !DILocation(line: 36, column: 44, scope: !7)
+!20 = !DILocation(line: 37, column: 22, scope: !7)
+!21 = !DILocation(line: 38, column: 22, scope: !7)
+!22 = !DILocation(line: 39, column: 36, scope: !7)
+!23 = !DILocation(line: 40, column: 40, scope: !7)
+!24 = !DILocation(line: 41, column: 44, scope: !7)
+!25 = !DILocation(line: 40, column: 55, scope: !7)
+!26 = !DILocation(line: 32, column: 27, scope: !7)
+!27 = !DILocation(line: 35, column: 40, scope: !7)
+!28 = !DILocation(line: 35, column: 34, scope: !7)
+!29 = !DILocation(line: 35, column: 50, scope: !7)
+!30 = !DILocation(line: 36, column: 40, scope: !7)
+!31 = !DILocation(line: 36, column: 34, scope: !7)
+!32 = !DILocation(line: 36, column: 50, scope: !7)
+!33 = !DILocation(line: 36, column: 101, scope: !7)
+!34 = !DILocation(line: 41, column: 40, scope: !7)
+!35 = !DILocation(line: 41, column: 34, scope: !7)
+!36 = !DILocation(line: 41, column: 52, scope: !7)
+!37 = !DILocation(line: 42, column: 22, scope: !7)
+!38 = !DILocation(line: 44, column: 22, scope: !7)
+!39 = !DILocation(line: 96, column: 20, scope: !40, inlinedAt: !42)
+!40 = distinct !DILexicalBlockFile(scope: !7, file: !41, discriminator: 0)
+!41 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!42 = !DILocation(line: 47, column: 41, scope: !40)
+!43 = !DILocation(line: 97, column: 26, scope: !40, inlinedAt: !42)
+!44 = !DILocation(line: 98, column: 30, scope: !40, inlinedAt: !42)
+!45 = !DILocation(line: 98, column: 22, scope: !40, inlinedAt: !42)
+!46 = !DILocation(line: 101, column: 30, scope: !40, inlinedAt: !42)
+!47 = !DILocation(line: 101, column: 22, scope: !40, inlinedAt: !42)
+!48 = !DILocation(line: 50, column: 50, scope: !7)
+!49 = !DILocation(line: 31, column: 36, scope: !7)
+!50 = !DILocation(line: 120, column: 46, scope: !40, inlinedAt: !51)
+!51 = !DILocation(line: 53, column: 44, scope: !40)
+!52 = !DILocation(line: 108, column: 21, scope: !53, inlinedAt: !54)
+!53 = distinct !DILexicalBlockFile(scope: !40, file: !41, discriminator: 0)
+!54 = !DILocation(line: 120, column: 46, scope: !53, inlinedAt: !55)
+!55 = !DILocation(line: 53, column: 44, scope: !53)
+!56 = !DILocation(line: 109, column: 28, scope: !53, inlinedAt: !54)
+!57 = !DILocation(line: 110, column: 39, scope: !53, inlinedAt: !54)
+!58 = !DILocation(line: 110, column: 60, scope: !53, inlinedAt: !54)
+!59 = !DILocation(line: 110, column: 49, scope: !53, inlinedAt: !54)
+!60 = !DILocation(line: 112, column: 25, scope: !53, inlinedAt: !54)
+!61 = !DILocation(line: 112, column: 17, scope: !53, inlinedAt: !54)
+!62 = !DILocation(line: 113, column: 15, scope: !53, inlinedAt: !54)
+!63 = !DILocation(line: 113, column: 30, scope: !53, inlinedAt: !54)
+!64 = !DILocation(line: 113, column: 38, scope: !53, inlinedAt: !54)
+!65 = !DILocation(line: 113, column: 49, scope: !53, inlinedAt: !54)
+!66 = !DILocation(line: 113, column: 22, scope: !53, inlinedAt: !54)
+!67 = !DILocation(line: 75, column: 24, scope: !7)
+!68 = !DILocation(line: 77, column: 24, scope: !7)
+!69 = !DILocation(line: 58, column: 36, scope: !7)
+!70 = !DILocation(line: 59, column: 27, scope: !7)
+!71 = !DILocation(line: 62, column: 41, scope: !7)
+!72 = !DILocation(line: 62, column: 35, scope: !7)
+!73 = !DILocation(line: 62, column: 51, scope: !7)
+!74 = !DILocation(line: 63, column: 41, scope: !7)
+!75 = !DILocation(line: 63, column: 35, scope: !7)
+!76 = !DILocation(line: 63, column: 51, scope: !7)
+!77 = !DILocation(line: 63, column: 103, scope: !7)
+!78 = !DILocation(line: 64, column: 35, scope: !7)
+!79 = !DILocation(line: 64, column: 40, scope: !7)
+!80 = !DILocation(line: 68, column: 57, scope: !7)
+!81 = !DILocation(line: 69, column: 35, scope: !7)
+!82 = !DILocation(line: 69, column: 54, scope: !7)
+!83 = !DILocation(line: 70, column: 24, scope: !7)
+!84 = !DILocation(line: 72, column: 24, scope: !7)
+!85 = !DILocation(line: 73, column: 24, scope: !7)
+!86 = !DILocation(line: 78, column: 30, scope: !7)
+!87 = !DILocation(line: 79, column: 24, scope: !7)
+!88 = !DILocation(line: 80, column: 24, scope: !7)
+!89 = !DILocation(line: 82, column: 29, scope: !7)
+!90 = !DILocation(line: 82, column: 52, scope: !7)
+!91 = !DILocation(line: 58, column: 4, scope: !7)

.triton/dump/4710f23a3addbad00b260d7a02366fe0/triton_.ttgir

@@ -0,0 +1,39 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d34e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg3: i32, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0> : tensor<1x8xi64, #blocked>
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1x8xf32, #blocked>
+    %cst_1 = arith.constant dense<8> : tensor<1x8xi32, #blocked>
+    %c0_i32 = arith.constant 0 : i32
+    %0 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %1 = tt.expand_dims %0 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x8xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst_1 : tensor<1x8xi32, #blocked>
+    %3 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<1x8x!tt.ptr<f32, 1>, #blocked>
+    %4 = tt.addptr %3, %1 : tensor<1x8x!tt.ptr<f32, 1>, #blocked>, tensor<1x8xi32, #blocked>
+    %5 = tt.load %4, %2, %cst_0 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1x8xf32, #blocked>
+    %6 = tt.splat %arg2 : (!tt.ptr<i64, 1>) -> tensor<1x8x!tt.ptr<i64, 1>, #blocked>
+    %7 = tt.addptr %6, %1 : tensor<1x8x!tt.ptr<i64, 1>, #blocked>, tensor<1x8xi32, #blocked>
+    %8 = tt.load %7, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1x8xi64, #blocked>
+    %9 = arith.select %2, %5, %cst_0 : tensor<1x8xi1, #blocked>, tensor<1x8xf32, #blocked>
+    %10 = "tt.reduce"(%9) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %19 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %19 : f32
+    }) : (tensor<1x8xf32, #blocked>) -> tensor<1xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %11 = tt.expand_dims %10 {axis = 1 : i32} : (tensor<1xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<1x1xf32, #blocked>
+    %12 = arith.select %2, %8, %cst : tensor<1x8xi1, #blocked>, tensor<1x8xi64, #blocked>
+    %13 = "tt.reduce"(%12) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: i64, %arg6: i64):
+      %19 = arith.addi %arg5, %arg6 : i64
+      tt.reduce.return %19 : i64
+    }) : (tensor<1x8xi64, #blocked>) -> tensor<1xi64, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %14 = tt.expand_dims %13 {axis = 1 : i32} : (tensor<1xi64, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<1x1xi64, #blocked>
+    %15 = arith.sitofp %14 : tensor<1x1xi64, #blocked> to tensor<1x1xf32, #blocked>
+    %16 = arith.divf %11, %15 : tensor<1x1xf32, #blocked>
+    gpu.barrier
+    %17 = tt.addptr %arg0, %c0_i32 : !tt.ptr<f32, 1>, i32
+    %18 = tt.splat %17 : (!tt.ptr<f32, 1>) -> tensor<1x1x!tt.ptr<f32, 1>, #blocked>
+    tt.store %18, %16 {cache = 1 : i32, evict = 1 : i32} : tensor<1x1xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/53075505618c3af0ef6ce61f3300cdcb/triton_.ptx

@@ -0,0 +1,2004 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6de7de
+.extern .func __assertfail
+(
+	.param .b64 __assertfail_param_0,
+	.param .b64 __assertfail_param_1,
+	.param .b32 __assertfail_param_2,
+	.param .b64 __assertfail_param_3,
+	.param .b64 __assertfail_param_4
+)
+;
+.global .align 1 .b8 assertFunc_1[25] = {95, 99, 97, 108, 108, 95, 119, 105, 116, 104, 95, 102, 114, 97, 109, 101, 115, 95, 114, 101, 109, 111, 118, 101, 100};
+.global .align 1 .b8 assertFile_1[38] = {60, 102, 114, 111, 122, 101, 110, 32, 105, 109, 112, 111, 114, 116, 108, 105, 98, 46, 95, 98, 111, 111, 116, 115, 116, 114, 97, 112, 95, 101, 120, 116, 101, 114, 110, 97, 108, 62};
+.global .align 1 .b8 assertMessage_1[39] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 49, 54, 32, 60, 32, 53, 48, 50, 53, 55};
+.global .align 1 .b8 assertFunc_0[25] = {95, 99, 97, 108, 108, 95, 119, 105, 116, 104, 95, 102, 114, 97, 109, 101, 115, 95, 114, 101, 109, 111, 118, 101, 100};
+.global .align 1 .b8 assertFile_0[38] = {60, 102, 114, 111, 122, 101, 110, 32, 105, 109, 112, 111, 114, 116, 108, 105, 98, 46, 95, 98, 111, 111, 116, 115, 116, 114, 97, 112, 95, 101, 120, 116, 101, 114, 110, 97, 108, 62};
+.global .align 1 .b8 assertMessage_0[38] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 51, 32, 60, 32, 53, 48, 50, 53, 55};
+.extern .shared .align 1 .b8 global_smem[];
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};
+
+.visible .entry triton__0d1d2d3d4d5d6de7de(
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6de7de_param_5,
+	.param .u32 triton__0d1d2d3d4d5d6de7de_param_6,
+	.param .u32 triton__0d1d2d3d4d5d6de7de_param_7
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<157>;
+	.reg .b16 	%rs<49>;
+	.reg .b32 	%r<474>;
+	.reg .f32 	%f<678>;
+	.reg .b64 	%rd<118>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6de7de_param_5];
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6de7de_param_4];
+	ld.param.u64 	%rd14, [triton__0d1d2d3d4d5d6de7de_param_3];
+	ld.param.u64 	%rd52, [triton__0d1d2d3d4d5d6de7de_param_0];
+	ld.param.u64 	%rd53, [triton__0d1d2d3d4d5d6de7de_param_1];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r12, %tid.x;
+	ld.param.u64 	%rd54, [triton__0d1d2d3d4d5d6de7de_param_2];
+	bfe.u32 	%r1, %r12, 3, 5;
+	and.b32  	%r2, %r12, 63;
+	.loc	1 24 33
+	shl.b32 	%r13, %r12, 3;
+	and.b32  	%r3, %r13, 56;
+	.loc	1 31 36
+	shr.u32 	%r4, %r12, 6;
+	.loc	1 21 28
+	mov.u32 %r10, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r14, %r10, 6;
+	.loc	1 22 23
+	or.b32  	%r15, %r14, %r1;
+	or.b32  	%r16, %r15, 32;
+	or.b32  	%r17, %r14, %r2;
+	.loc	1 26 30
+	mul.wide.s32 	%rd55, %r15, 8;
+	add.s64 	%rd18, %rd52, %rd55;
+	add.s64 	%rd34, %rd18, 256;
+	mul.wide.s32 	%rd56, %r17, 8;
+	add.s64 	%rd50, %rd52, %rd56;
+	mov.pred 	%p1, -1;
+	.loc	1 26 35
+	mov.u64 %rd17, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd17 }, [ %rd18 + 0 ];
+	mov.u64 %rd19, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd19 }, [ %rd18 + 0 ];
+	mov.u64 %rd21, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd21 }, [ %rd18 + 0 ];
+	mov.u64 %rd23, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd23 }, [ %rd18 + 0 ];
+	mov.u64 %rd25, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd25 }, [ %rd18 + 0 ];
+	mov.u64 %rd27, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd27 }, [ %rd18 + 0 ];
+	mov.u64 %rd29, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd29 }, [ %rd18 + 0 ];
+	mov.u64 %rd31, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd31 }, [ %rd18 + 0 ];
+	mov.u64 %rd33, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd33 }, [ %rd34 + 0 ];
+	mov.u64 %rd35, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd35 }, [ %rd34 + 0 ];
+	mov.u64 %rd37, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd37 }, [ %rd34 + 0 ];
+	mov.u64 %rd39, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd39 }, [ %rd34 + 0 ];
+	mov.u64 %rd41, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd41 }, [ %rd34 + 0 ];
+	mov.u64 %rd43, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd43 }, [ %rd34 + 0 ];
+	mov.u64 %rd45, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd45 }, [ %rd34 + 0 ];
+	mov.u64 %rd47, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd47 }, [ %rd34 + 0 ];
+	mov.u64 %rd49, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd49 }, [ %rd50 + 0 ];
+	.loc	1 27 18
+	bfe.s32 	%r18, %r10, 25, 1;
+	shr.u32 	%r19, %r18, 23;
+	add.s32 	%r20, %r15, %r19;
+	and.b32  	%r21, %r20, 16776704;
+	sub.s32 	%r22, %r15, %r21;
+	add.s32 	%r23, %r16, %r19;
+	and.b32  	%r24, %r23, 16776704;
+	sub.s32 	%r25, %r16, %r24;
+	.loc	1 35 44
+	shl.b32 	%r26, %r22, 8;
+	shl.b32 	%r27, %r25, 8;
+	.loc	1 37 22
+	add.s64 	%rd57, %rd49, 50257;
+	.loc	1 38 22
+	setp.lt.s64 	%p18, %rd17, 0;
+	setp.lt.s64 	%p19, %rd33, 0;
+	setp.lt.s64 	%p20, %rd49, 0;
+	.loc	1 39 36
+	selp.b64 	%rd1, %rd57, %rd49, %p20;
+	.loc	1 41 44
+	shl.b64 	%rd58, %rd17, 8;
+	add.s64 	%rd59, %rd58, 12865792;
+	selp.b64 	%rd60, %rd59, %rd58, %p18;
+	shl.b64 	%rd61, %rd33, 8;
+	add.s64 	%rd62, %rd61, 12865792;
+	selp.b64 	%rd63, %rd62, %rd61, %p19;
+	.loc	1 31 36
+	and.b32  	%r28, %r12, 7;
+	mul.wide.u32 	%rd2, %r28, 32;
+	shl.b64 	%rd64, %rd63, 2;
+	or.b64  	%rd65, %rd2, %rd64;
+	add.s64 	%rd3, %rd53, %rd65;
+	shl.b64 	%rd66, %rd60, 2;
+	or.b64  	%rd67, %rd2, %rd66;
+	add.s64 	%rd4, %rd53, %rd67;
+	or.b32  	%r29, %r27, %r3;
+	mul.wide.s32 	%rd68, %r29, 4;
+	add.s64 	%rd5, %rd54, %rd68;
+	or.b32  	%r30, %r26, %r3;
+	mul.wide.s32 	%rd69, %r30, 4;
+	add.s64 	%rd6, %rd54, %rd69;
+	shl.b32 	%r31, %r10, 14;
+	shl.b32 	%r32, %r1, 8;
+	or.b32  	%r33, %r31, %r32;
+	or.b32  	%r5, %r33, %r3;
+	mov.f32 	%f614, 0f00000000;
+	mov.u64 	%rd116, 0;
+	mov.b32 	%r472, -64;
+	mov.f32 	%f615, %f614;
+	mov.f32 	%f616, %f614;
+	mov.f32 	%f617, %f614;
+	mov.f32 	%f618, %f614;
+	mov.f32 	%f619, %f614;
+	mov.f32 	%f620, %f614;
+	mov.f32 	%f621, %f614;
+	mov.f32 	%f622, %f614;
+	mov.f32 	%f623, %f614;
+	mov.f32 	%f624, %f614;
+	mov.f32 	%f625, %f614;
+	mov.f32 	%f626, %f614;
+	mov.f32 	%f627, %f614;
+	mov.f32 	%f628, %f614;
+	mov.f32 	%f629, %f614;
+	mov.f32 	%f630, %f614;
+	mov.f32 	%f631, %f614;
+	mov.f32 	%f632, %f614;
+	mov.f32 	%f633, %f614;
+	mov.f32 	%f634, %f614;
+	mov.f32 	%f635, %f614;
+	mov.f32 	%f636, %f614;
+	mov.f32 	%f637, %f614;
+	mov.f32 	%f638, %f614;
+	mov.f32 	%f639, %f614;
+	mov.f32 	%f640, %f614;
+	mov.f32 	%f641, %f614;
+	mov.f32 	%f642, %f614;
+	mov.f32 	%f643, %f614;
+	mov.f32 	%f644, %f614;
+	mov.f32 	%f645, %f614;
+	mov.f32 	%f646, %f614;
+	mov.f32 	%f647, %f614;
+	mov.f32 	%f648, %f614;
+	mov.f32 	%f649, %f614;
+	mov.f32 	%f650, %f614;
+	mov.f32 	%f651, %f614;
+	mov.f32 	%f652, %f614;
+	mov.f32 	%f653, %f614;
+	mov.f32 	%f654, %f614;
+	mov.f32 	%f655, %f614;
+	mov.f32 	%f656, %f614;
+	mov.f32 	%f657, %f614;
+	mov.f32 	%f658, %f614;
+	mov.f32 	%f659, %f614;
+	mov.f32 	%f660, %f614;
+	mov.f32 	%f661, %f614;
+	mov.f32 	%f662, %f614;
+	mov.f32 	%f663, %f614;
+	mov.f32 	%f664, %f614;
+	mov.f32 	%f665, %f614;
+	mov.f32 	%f666, %f614;
+	mov.f32 	%f667, %f614;
+	mov.f32 	%f668, %f614;
+	mov.f32 	%f669, %f614;
+	mov.f32 	%f670, %f614;
+	mov.f32 	%f671, %f614;
+	mov.f32 	%f672, %f614;
+	mov.f32 	%f673, %f614;
+	mov.f32 	%f674, %f614;
+	mov.f32 	%f675, %f614;
+	mov.f32 	%f676, %f614;
+	mov.f32 	%f677, %f614;
+	bra.uni 	$L__BB0_1;
+$L__BB0_3:
+	.loc	1 41 40
+	add.s64 	%rd85, %rd4, %rd116;
+	.loc	1 41 34
+	add.s64 	%rd86, %rd85, 16;
+	add.s64 	%rd87, %rd3, %rd116;
+	.loc	1 41 52
+	add.s64 	%rd88, %rd87, 16;
+	mov.u32 %r102, 0x0;
+	mov.u32 %r103, 0x0;
+	mov.u32 %r104, 0x0;
+	mov.u32 %r105, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r102, %r103, %r104, %r105 }, [ %rd85 + 0 ];
+	@!%p1 mov.u32 %r102, %r411;
+	@!%p1 mov.u32 %r103, %r411;
+	@!%p1 mov.u32 %r104, %r411;
+	@!%p1 mov.u32 %r105, %r411;
+	mov.b32 	%f206, %r102;
+	mov.b32 	%f207, %r103;
+	mov.b32 	%f208, %r104;
+	mov.b32 	%f209, %r105;
+	mov.u32 %r110, 0x0;
+	mov.u32 %r111, 0x0;
+	mov.u32 %r112, 0x0;
+	mov.u32 %r113, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r110, %r111, %r112, %r113 }, [ %rd86 + 0 ];
+	@!%p1 mov.u32 %r110, %r411;
+	@!%p1 mov.u32 %r111, %r411;
+	@!%p1 mov.u32 %r112, %r411;
+	@!%p1 mov.u32 %r113, %r411;
+	mov.b32 	%f210, %r110;
+	mov.b32 	%f211, %r111;
+	mov.b32 	%f212, %r112;
+	mov.b32 	%f213, %r113;
+	mov.u32 %r118, 0x0;
+	mov.u32 %r119, 0x0;
+	mov.u32 %r120, 0x0;
+	mov.u32 %r121, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r118, %r119, %r120, %r121 }, [ %rd87 + 0 ];
+	@!%p1 mov.u32 %r118, %r411;
+	@!%p1 mov.u32 %r119, %r411;
+	@!%p1 mov.u32 %r120, %r411;
+	@!%p1 mov.u32 %r121, %r411;
+	mov.b32 	%f214, %r118;
+	mov.b32 	%f215, %r119;
+	mov.b32 	%f216, %r120;
+	mov.b32 	%f217, %r121;
+	mov.u32 %r126, 0x0;
+	mov.u32 %r127, 0x0;
+	mov.u32 %r128, 0x0;
+	mov.u32 %r129, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r126, %r127, %r128, %r129 }, [ %rd88 + 0 ];
+	@!%p1 mov.u32 %r126, %r411;
+	@!%p1 mov.u32 %r127, %r411;
+	@!%p1 mov.u32 %r128, %r411;
+	@!%p1 mov.u32 %r129, %r411;
+	mov.b32 	%f218, %r126;
+	mov.b32 	%f219, %r127;
+	mov.b32 	%f220, %r128;
+	mov.b32 	%f221, %r129;
+	.loc	1 42 22
+	add.f32 	%f222, %f65, %f206;
+	add.f32 	%f223, %f66, %f207;
+	add.f32 	%f224, %f67, %f208;
+	add.f32 	%f225, %f68, %f209;
+	add.f32 	%f226, %f69, %f210;
+	add.f32 	%f227, %f70, %f211;
+	add.f32 	%f228, %f71, %f212;
+	add.f32 	%f229, %f72, %f213;
+	add.f32 	%f230, %f73, %f214;
+	add.f32 	%f231, %f74, %f215;
+	add.f32 	%f232, %f75, %f216;
+	add.f32 	%f233, %f76, %f217;
+	add.f32 	%f234, %f77, %f218;
+	add.f32 	%f235, %f78, %f219;
+	add.f32 	%f236, %f79, %f220;
+	add.f32 	%f237, %f80, %f221;
+	.loc	1 44 22
+	add.f32 	%f238, %f81, %f222;
+	add.f32 	%f239, %f82, %f223;
+	add.f32 	%f240, %f83, %f224;
+	add.f32 	%f241, %f84, %f225;
+	add.f32 	%f242, %f85, %f226;
+	add.f32 	%f243, %f86, %f227;
+	add.f32 	%f244, %f87, %f228;
+	add.f32 	%f245, %f88, %f229;
+	add.f32 	%f246, %f89, %f230;
+	add.f32 	%f247, %f90, %f231;
+	add.f32 	%f248, %f91, %f232;
+	add.f32 	%f249, %f92, %f233;
+	add.f32 	%f250, %f93, %f234;
+	add.f32 	%f251, %f94, %f235;
+	add.f32 	%f252, %f95, %f236;
+	add.f32 	%f253, %f96, %f237;
+$L__tmp1:
+	.loc	2 96 20
+	sub.f32 	%f254, %f238, %f662;
+	sub.f32 	%f255, %f239, %f663;
+	sub.f32 	%f256, %f240, %f664;
+	sub.f32 	%f257, %f241, %f665;
+	sub.f32 	%f258, %f242, %f666;
+	sub.f32 	%f259, %f243, %f667;
+	sub.f32 	%f260, %f244, %f668;
+	sub.f32 	%f261, %f245, %f669;
+	sub.f32 	%f262, %f246, %f670;
+	sub.f32 	%f263, %f247, %f671;
+	sub.f32 	%f264, %f248, %f672;
+	sub.f32 	%f265, %f249, %f673;
+	sub.f32 	%f266, %f250, %f674;
+	sub.f32 	%f267, %f251, %f675;
+	sub.f32 	%f268, %f252, %f676;
+	sub.f32 	%f269, %f253, %f677;
+	.loc	2 97 26
+	add.f32 	%f614, %f614, 0f3F800000;
+	add.f32 	%f615, %f615, 0f3F800000;
+	add.f32 	%f616, %f616, 0f3F800000;
+	add.f32 	%f617, %f617, 0f3F800000;
+	add.f32 	%f618, %f618, 0f3F800000;
+	add.f32 	%f619, %f619, 0f3F800000;
+	add.f32 	%f620, %f620, 0f3F800000;
+	add.f32 	%f621, %f621, 0f3F800000;
+	add.f32 	%f622, %f622, 0f3F800000;
+	add.f32 	%f623, %f623, 0f3F800000;
+	add.f32 	%f624, %f624, 0f3F800000;
+	add.f32 	%f625, %f625, 0f3F800000;
+	add.f32 	%f626, %f626, 0f3F800000;
+	add.f32 	%f627, %f627, 0f3F800000;
+	add.f32 	%f628, %f628, 0f3F800000;
+	add.f32 	%f629, %f629, 0f3F800000;
+	add.f32 	%f630, %f630, 0f3F800000;
+	add.f32 	%f631, %f631, 0f3F800000;
+	add.f32 	%f632, %f632, 0f3F800000;
+	add.f32 	%f633, %f633, 0f3F800000;
+	add.f32 	%f634, %f634, 0f3F800000;
+	add.f32 	%f635, %f635, 0f3F800000;
+	add.f32 	%f636, %f636, 0f3F800000;
+	add.f32 	%f637, %f637, 0f3F800000;
+	add.f32 	%f638, %f638, 0f3F800000;
+	add.f32 	%f639, %f639, 0f3F800000;
+	add.f32 	%f640, %f640, 0f3F800000;
+	add.f32 	%f641, %f641, 0f3F800000;
+	add.f32 	%f642, %f642, 0f3F800000;
+	add.f32 	%f643, %f643, 0f3F800000;
+	add.f32 	%f644, %f644, 0f3F800000;
+	add.f32 	%f645, %f645, 0f3F800000;
+	.loc	2 98 30
+	mov.b32 	%r135, %f254;
+	mov.b32 	%r136, %f614;
+	div.full.f32 %r134, %r135, %r136;
+	mov.b32 	%f270, %r134;
+	mov.b32 	%r138, %f255;
+	mov.b32 	%r139, %f615;
+	div.full.f32 %r137, %r138, %r139;
+	mov.b32 	%f271, %r137;
+	mov.b32 	%r141, %f256;
+	mov.b32 	%r142, %f616;
+	div.full.f32 %r140, %r141, %r142;
+	mov.b32 	%f272, %r140;
+	mov.b32 	%r144, %f257;
+	mov.b32 	%r145, %f617;
+	div.full.f32 %r143, %r144, %r145;
+	mov.b32 	%f273, %r143;
+	mov.b32 	%r147, %f258;
+	mov.b32 	%r148, %f618;
+	div.full.f32 %r146, %r147, %r148;
+	mov.b32 	%f274, %r146;
+	mov.b32 	%r150, %f259;
+	mov.b32 	%r151, %f619;
+	div.full.f32 %r149, %r150, %r151;
+	mov.b32 	%f275, %r149;
+	mov.b32 	%r153, %f260;
+	mov.b32 	%r154, %f620;
+	div.full.f32 %r152, %r153, %r154;
+	mov.b32 	%f276, %r152;
+	mov.b32 	%r156, %f261;
+	mov.b32 	%r157, %f621;
+	div.full.f32 %r155, %r156, %r157;
+	mov.b32 	%f277, %r155;
+	mov.b32 	%r159, %f262;
+	mov.b32 	%r160, %f622;
+	div.full.f32 %r158, %r159, %r160;
+	mov.b32 	%f278, %r158;
+	mov.b32 	%r162, %f263;
+	mov.b32 	%r163, %f623;
+	div.full.f32 %r161, %r162, %r163;
+	mov.b32 	%f279, %r161;
+	mov.b32 	%r165, %f264;
+	mov.b32 	%r166, %f624;
+	div.full.f32 %r164, %r165, %r166;
+	mov.b32 	%f280, %r164;
+	mov.b32 	%r168, %f265;
+	mov.b32 	%r169, %f625;
+	div.full.f32 %r167, %r168, %r169;
+	mov.b32 	%f281, %r167;
+	mov.b32 	%r171, %f266;
+	mov.b32 	%r172, %f626;
+	div.full.f32 %r170, %r171, %r172;
+	mov.b32 	%f282, %r170;
+	mov.b32 	%r174, %f267;
+	mov.b32 	%r175, %f627;
+	div.full.f32 %r173, %r174, %r175;
+	mov.b32 	%f283, %r173;
+	mov.b32 	%r177, %f268;
+	mov.b32 	%r178, %f628;
+	div.full.f32 %r176, %r177, %r178;
+	mov.b32 	%f284, %r176;
+	mov.b32 	%r180, %f269;
+	mov.b32 	%r181, %f629;
+	div.full.f32 %r179, %r180, %r181;
+	mov.b32 	%f285, %r179;
+	.loc	2 98 22
+	add.f32 	%f662, %f662, %f270;
+	add.f32 	%f663, %f663, %f271;
+	add.f32 	%f664, %f664, %f272;
+	add.f32 	%f665, %f665, %f273;
+	add.f32 	%f666, %f666, %f274;
+	add.f32 	%f667, %f667, %f275;
+	add.f32 	%f668, %f668, %f276;
+	add.f32 	%f669, %f669, %f277;
+	add.f32 	%f670, %f670, %f278;
+	add.f32 	%f671, %f671, %f279;
+	add.f32 	%f672, %f672, %f280;
+	add.f32 	%f673, %f673, %f281;
+	add.f32 	%f674, %f674, %f282;
+	add.f32 	%f675, %f675, %f283;
+	add.f32 	%f676, %f676, %f284;
+	add.f32 	%f677, %f677, %f285;
+	.loc	2 101 30
+	sub.f32 	%f286, %f238, %f662;
+	sub.f32 	%f287, %f239, %f663;
+	sub.f32 	%f288, %f240, %f664;
+	sub.f32 	%f289, %f241, %f665;
+	sub.f32 	%f290, %f242, %f666;
+	sub.f32 	%f291, %f243, %f667;
+	sub.f32 	%f292, %f244, %f668;
+	sub.f32 	%f293, %f245, %f669;
+	sub.f32 	%f294, %f246, %f670;
+	sub.f32 	%f295, %f247, %f671;
+	sub.f32 	%f296, %f248, %f672;
+	sub.f32 	%f297, %f249, %f673;
+	sub.f32 	%f298, %f250, %f674;
+	sub.f32 	%f299, %f251, %f675;
+	sub.f32 	%f300, %f252, %f676;
+	sub.f32 	%f301, %f253, %f677;
+$L__tmp2:
+	.loc	1 50 50
+	fma.rn.f32 	%f646, %f254, %f286, %f646;
+	fma.rn.f32 	%f647, %f255, %f287, %f647;
+	fma.rn.f32 	%f648, %f256, %f288, %f648;
+	fma.rn.f32 	%f649, %f257, %f289, %f649;
+	fma.rn.f32 	%f650, %f258, %f290, %f650;
+	fma.rn.f32 	%f651, %f259, %f291, %f651;
+	fma.rn.f32 	%f652, %f260, %f292, %f652;
+	fma.rn.f32 	%f653, %f261, %f293, %f653;
+	fma.rn.f32 	%f654, %f262, %f294, %f654;
+	fma.rn.f32 	%f655, %f263, %f295, %f655;
+	fma.rn.f32 	%f656, %f264, %f296, %f656;
+	fma.rn.f32 	%f657, %f265, %f297, %f657;
+	fma.rn.f32 	%f658, %f266, %f298, %f658;
+	fma.rn.f32 	%f659, %f267, %f299, %f659;
+	fma.rn.f32 	%f660, %f268, %f300, %f660;
+	fma.rn.f32 	%f661, %f269, %f301, %f661;
+	.loc	1 31 36
+	add.s64 	%rd116, %rd116, 256;
+	add.s32 	%r472, %r472, 64;
+	setp.lt.u32 	%p72, %r472, 192;
+	@%p72 bra 	$L__BB0_1;
+	bra.uni 	$L__BB0_4;
+$L__BB0_1:
+	.loc	1 40 40
+	setp.lt.u64 	%p51, %rd1, 50257;
+	.loc	1 35 34
+	add.s64 	%rd70, %rd6, %rd116;
+	add.s64 	%rd71, %rd70, 16;
+	add.s64 	%rd72, %rd5, %rd116;
+	.loc	1 35 50
+	add.s64 	%rd73, %rd72, 16;
+	mov.b32 	%r411, 0;
+	mov.u32 %r34, 0x0;
+	mov.u32 %r35, 0x0;
+	mov.u32 %r36, 0x0;
+	mov.u32 %r37, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r34, %r35, %r36, %r37 }, [ %rd70 + 0 ];
+	@!%p1 mov.u32 %r34, %r411;
+	@!%p1 mov.u32 %r35, %r411;
+	@!%p1 mov.u32 %r36, %r411;
+	@!%p1 mov.u32 %r37, %r411;
+	mov.b32 	%f65, %r34;
+	mov.b32 	%f66, %r35;
+	mov.b32 	%f67, %r36;
+	mov.b32 	%f68, %r37;
+	mov.u32 %r42, 0x0;
+	mov.u32 %r43, 0x0;
+	mov.u32 %r44, 0x0;
+	mov.u32 %r45, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r42, %r43, %r44, %r45 }, [ %rd71 + 0 ];
+	@!%p1 mov.u32 %r42, %r411;
+	@!%p1 mov.u32 %r43, %r411;
+	@!%p1 mov.u32 %r44, %r411;
+	@!%p1 mov.u32 %r45, %r411;
+	mov.b32 	%f69, %r42;
+	mov.b32 	%f70, %r43;
+	mov.b32 	%f71, %r44;
+	mov.b32 	%f72, %r45;
+	mov.u32 %r50, 0x0;
+	mov.u32 %r51, 0x0;
+	mov.u32 %r52, 0x0;
+	mov.u32 %r53, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r50, %r51, %r52, %r53 }, [ %rd72 + 0 ];
+	@!%p1 mov.u32 %r50, %r411;
+	@!%p1 mov.u32 %r51, %r411;
+	@!%p1 mov.u32 %r52, %r411;
+	@!%p1 mov.u32 %r53, %r411;
+	mov.b32 	%f73, %r50;
+	mov.b32 	%f74, %r51;
+	mov.b32 	%f75, %r52;
+	mov.b32 	%f76, %r53;
+	mov.u32 %r58, 0x0;
+	mov.u32 %r59, 0x0;
+	mov.u32 %r60, 0x0;
+	mov.u32 %r61, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r58, %r59, %r60, %r61 }, [ %rd73 + 0 ];
+	@!%p1 mov.u32 %r58, %r411;
+	@!%p1 mov.u32 %r59, %r411;
+	@!%p1 mov.u32 %r60, %r411;
+	@!%p1 mov.u32 %r61, %r411;
+	mov.b32 	%f77, %r58;
+	mov.b32 	%f78, %r59;
+	mov.b32 	%f79, %r60;
+	mov.b32 	%f80, %r61;
+	.loc	1 36 40
+	add.s32 	%r98, %r5, %r472;
+	add.s32 	%r99, %r98, 64;
+	.loc	1 36 34
+	add.s32 	%r100, %r98, 8256;
+	mul.wide.s32 	%rd76, %r99, 2;
+	add.s64 	%rd74, %rd14, %rd76;
+	mul.wide.s32 	%rd77, %r100, 2;
+	add.s64 	%rd75, %rd14, %rd77;
+	.loc	1 36 50
+	mov.u32 %r66, 0x0;
+	mov.u32 %r67, 0x0;
+	mov.u32 %r68, 0x0;
+	mov.u32 %r69, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r66, %r67, %r68, %r69 }, [ %rd74 + 0 ];
+	@!%p1 mov.u32 %r66, %r411;
+	@!%p1 mov.u32 %r67, %r411;
+	@!%p1 mov.u32 %r68, %r411;
+	@!%p1 mov.u32 %r69, %r411;
+	cvt.u16.u32 	%rs1, %r66;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r66; }
+	cvt.u16.u32 	%rs3, %r67;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs4}, %r67; }
+	cvt.u16.u32 	%rs5, %r68;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r68; }
+	cvt.u16.u32 	%rs7, %r69;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r69; }
+	mov.u32 %r74, 0x0;
+	mov.u32 %r75, 0x0;
+	mov.u32 %r76, 0x0;
+	mov.u32 %r77, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r74, %r75, %r76, %r77 }, [ %rd75 + 0 ];
+	@!%p1 mov.u32 %r74, %r411;
+	@!%p1 mov.u32 %r75, %r411;
+	@!%p1 mov.u32 %r76, %r411;
+	@!%p1 mov.u32 %r77, %r411;
+	cvt.u16.u32 	%rs9, %r74;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r74; }
+	cvt.u16.u32 	%rs11, %r75;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs12}, %r75; }
+	cvt.u16.u32 	%rs13, %r76;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs14}, %r76; }
+	cvt.u16.u32 	%rs15, %r77;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs16}, %r77; }
+	.loc	1 36 101
+	cvt.f32.bf16 %r82, %rs1;
+	mov.b32 	%f81, %r82;
+	cvt.f32.bf16 %r83, %rs2;
+	mov.b32 	%f82, %r83;
+	cvt.f32.bf16 %r84, %rs3;
+	mov.b32 	%f83, %r84;
+	cvt.f32.bf16 %r85, %rs4;
+	mov.b32 	%f84, %r85;
+	cvt.f32.bf16 %r86, %rs5;
+	mov.b32 	%f85, %r86;
+	cvt.f32.bf16 %r87, %rs6;
+	mov.b32 	%f86, %r87;
+	cvt.f32.bf16 %r88, %rs7;
+	mov.b32 	%f87, %r88;
+	cvt.f32.bf16 %r89, %rs8;
+	mov.b32 	%f88, %r89;
+	cvt.f32.bf16 %r90, %rs9;
+	mov.b32 	%f89, %r90;
+	cvt.f32.bf16 %r91, %rs10;
+	mov.b32 	%f90, %r91;
+	cvt.f32.bf16 %r92, %rs11;
+	mov.b32 	%f91, %r92;
+	cvt.f32.bf16 %r93, %rs12;
+	mov.b32 	%f92, %r93;
+	cvt.f32.bf16 %r94, %rs13;
+	mov.b32 	%f93, %r94;
+	cvt.f32.bf16 %r95, %rs14;
+	mov.b32 	%f94, %r95;
+	cvt.f32.bf16 %r96, %rs15;
+	mov.b32 	%f95, %r96;
+	cvt.f32.bf16 %r97, %rs16;
+	mov.b32 	%f96, %r97;
+	mov.b32 	%r471, 883;
+	mov.u64 	%rd115, 1;
+	.loc	1 40 55
+	@%p51 bra 	$L__BB0_3;
+	mov.u64 	%rd78, assertMessage_0;
+	cvta.global.u64 	%rd79, %rd78;
+	mov.u64 	%rd80, assertFile_0;
+	cvta.global.u64 	%rd81, %rd80;
+	mov.u64 	%rd82, assertFunc_0;
+	cvta.global.u64 	%rd83, %rd82;
+	{ // callseq 6, 0
+	.reg .b32 temp_param_reg;
+	.param .b64 param0;
+	st.param.b64 	[param0+0], %rd79;
+	.param .b64 param1;
+	st.param.b64 	[param1+0], %rd81;
+	.param .b32 param2;
+	st.param.b32 	[param2+0], %r471;
+	.param .b64 param3;
+	st.param.b64 	[param3+0], %rd83;
+	.param .b64 param4;
+	st.param.b64 	[param4+0], %rd115;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 6
+	bra.uni 	$L__BB0_3;
+$L__BB0_4:
+	.loc	1 31 36
+	and.b32  	%r291, %r4, 3;
+	mad.lo.s32 	%r292, %r291, 72, %r2;
+	shl.b32 	%r293, %r292, 2;
+	mov.u32 	%r294, global_smem;
+	add.s32 	%r295, %r294, %r293;
+	st.shared.f32 	[%r295], %f630;
+	st.shared.f32 	[%r295+1152], %f631;
+	st.shared.f32 	[%r295+2304], %f632;
+	st.shared.f32 	[%r295+3456], %f633;
+	st.shared.f32 	[%r295+4608], %f634;
+	st.shared.f32 	[%r295+5760], %f635;
+	st.shared.f32 	[%r295+6912], %f636;
+	st.shared.f32 	[%r295+8064], %f637;
+	bar.sync 	0;
+	mad.lo.s32 	%r296, %r1, 72, %r3;
+	shl.b32 	%r297, %r296, 2;
+	add.s32 	%r298, %r294, %r297;
+	ld.shared.v4.f32 	{%f302, %f303, %f304, %f305}, [%r298];
+	ld.shared.v4.f32 	{%f306, %f307, %f308, %f309}, [%r298+16];
+	bar.sync 	0;
+	st.shared.f32 	[%r295], %f638;
+	st.shared.f32 	[%r295+1152], %f639;
+	st.shared.f32 	[%r295+2304], %f640;
+	st.shared.f32 	[%r295+3456], %f641;
+	st.shared.f32 	[%r295+4608], %f642;
+	st.shared.f32 	[%r295+5760], %f643;
+	st.shared.f32 	[%r295+6912], %f644;
+	st.shared.f32 	[%r295+8064], %f645;
+	bar.sync 	0;
+	ld.shared.v4.f32 	{%f310, %f311, %f312, %f313}, [%r298];
+	ld.shared.v4.f32 	{%f314, %f315, %f316, %f317}, [%r298+16];
+$L__tmp3:
+	.loc	2 108 21
+	sub.f32 	%f318, %f663, %f662;
+	.loc	2 109 28
+	add.f32 	%f319, %f302, %f303;
+	.loc	2 110 39
+	setp.eq.f32 	%p73, %f319, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r183, %f303;
+	mov.b32 	%r184, %f319;
+	div.full.f32 %r182, %r183, %r184;
+	mov.b32 	%f320, %r182;
+	.loc	2 110 49
+	selp.f32 	%f321, 0f00000000, %f320, %p73;
+	.loc	2 112 17
+	fma.rn.f32 	%f322, %f318, %f321, %f662;
+	.loc	2 113 15
+	add.f32 	%f323, %f646, %f647;
+	.loc	2 113 30
+	mul.f32 	%f324, %f318, %f318;
+	.loc	2 113 38
+	mul.f32 	%f325, %f324, %f302;
+	.loc	2 113 22
+	fma.rn.f32 	%f326, %f325, %f321, %f323;
+	.loc	2 108 21
+	sub.f32 	%f327, %f664, %f322;
+	.loc	2 109 28
+	add.f32 	%f328, %f304, %f319;
+	.loc	2 110 39
+	setp.eq.f32 	%p74, %f328, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r187, %f328;
+	mov.b32 	%r186, %f304;
+	div.full.f32 %r185, %r186, %r187;
+	mov.b32 	%f329, %r185;
+	.loc	2 110 49
+	selp.f32 	%f330, 0f00000000, %f329, %p74;
+	.loc	2 112 17
+	fma.rn.f32 	%f331, %f330, %f327, %f322;
+	.loc	2 113 15
+	add.f32 	%f332, %f648, %f326;
+	.loc	2 113 30
+	mul.f32 	%f333, %f327, %f327;
+	.loc	2 113 38
+	mul.f32 	%f334, %f319, %f333;
+	.loc	2 113 22
+	fma.rn.f32 	%f335, %f330, %f334, %f332;
+	.loc	2 108 21
+	sub.f32 	%f336, %f665, %f331;
+	.loc	2 109 28
+	add.f32 	%f337, %f305, %f328;
+	.loc	2 110 39
+	setp.eq.f32 	%p75, %f337, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r190, %f337;
+	mov.b32 	%r189, %f305;
+	div.full.f32 %r188, %r189, %r190;
+	mov.b32 	%f338, %r188;
+	.loc	2 110 49
+	selp.f32 	%f339, 0f00000000, %f338, %p75;
+	.loc	2 112 17
+	fma.rn.f32 	%f340, %f339, %f336, %f331;
+	.loc	2 113 15
+	add.f32 	%f341, %f649, %f335;
+	.loc	2 113 30
+	mul.f32 	%f342, %f336, %f336;
+	.loc	2 113 38
+	mul.f32 	%f343, %f328, %f342;
+	.loc	2 113 22
+	fma.rn.f32 	%f344, %f339, %f343, %f341;
+	.loc	2 108 21
+	sub.f32 	%f345, %f666, %f340;
+	.loc	2 109 28
+	add.f32 	%f346, %f306, %f337;
+	.loc	2 110 39
+	setp.eq.f32 	%p76, %f346, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r193, %f346;
+	mov.b32 	%r192, %f306;
+	div.full.f32 %r191, %r192, %r193;
+	mov.b32 	%f347, %r191;
+	.loc	2 110 49
+	selp.f32 	%f348, 0f00000000, %f347, %p76;
+	.loc	2 112 17
+	fma.rn.f32 	%f349, %f348, %f345, %f340;
+	.loc	2 113 15
+	add.f32 	%f350, %f650, %f344;
+	.loc	2 113 30
+	mul.f32 	%f351, %f345, %f345;
+	.loc	2 113 38
+	mul.f32 	%f352, %f337, %f351;
+	.loc	2 113 22
+	fma.rn.f32 	%f353, %f348, %f352, %f350;
+	.loc	2 108 21
+	sub.f32 	%f354, %f667, %f349;
+	.loc	2 109 28
+	add.f32 	%f355, %f307, %f346;
+	.loc	2 110 39
+	setp.eq.f32 	%p77, %f355, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r196, %f355;
+	mov.b32 	%r195, %f307;
+	div.full.f32 %r194, %r195, %r196;
+	mov.b32 	%f356, %r194;
+	.loc	2 110 49
+	selp.f32 	%f357, 0f00000000, %f356, %p77;
+	.loc	2 112 17
+	fma.rn.f32 	%f358, %f357, %f354, %f349;
+	.loc	2 113 15
+	add.f32 	%f359, %f651, %f353;
+	.loc	2 113 30
+	mul.f32 	%f360, %f354, %f354;
+	.loc	2 113 38
+	mul.f32 	%f361, %f346, %f360;
+	.loc	2 113 22
+	fma.rn.f32 	%f362, %f357, %f361, %f359;
+	.loc	2 108 21
+	sub.f32 	%f363, %f668, %f358;
+	.loc	2 109 28
+	add.f32 	%f364, %f308, %f355;
+	.loc	2 110 39
+	setp.eq.f32 	%p78, %f364, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r199, %f364;
+	mov.b32 	%r198, %f308;
+	div.full.f32 %r197, %r198, %r199;
+	mov.b32 	%f365, %r197;
+	.loc	2 110 49
+	selp.f32 	%f366, 0f00000000, %f365, %p78;
+	.loc	2 112 17
+	fma.rn.f32 	%f367, %f366, %f363, %f358;
+	.loc	2 113 15
+	add.f32 	%f368, %f652, %f362;
+	.loc	2 113 30
+	mul.f32 	%f369, %f363, %f363;
+	.loc	2 113 38
+	mul.f32 	%f370, %f355, %f369;
+	.loc	2 113 22
+	fma.rn.f32 	%f371, %f366, %f370, %f368;
+	.loc	2 108 21
+	sub.f32 	%f372, %f669, %f367;
+	.loc	2 109 28
+	add.f32 	%f373, %f309, %f364;
+	.loc	2 110 39
+	setp.eq.f32 	%p79, %f373, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r202, %f373;
+	mov.b32 	%r201, %f309;
+	div.full.f32 %r200, %r201, %r202;
+	mov.b32 	%f374, %r200;
+	.loc	2 110 49
+	selp.f32 	%f375, 0f00000000, %f374, %p79;
+	.loc	2 112 17
+	fma.rn.f32 	%f376, %f375, %f372, %f367;
+	.loc	2 113 15
+	add.f32 	%f377, %f653, %f371;
+	.loc	2 113 30
+	mul.f32 	%f378, %f372, %f372;
+	.loc	2 113 38
+	mul.f32 	%f379, %f364, %f378;
+	.loc	2 113 22
+	fma.rn.f32 	%f380, %f375, %f379, %f377;
+	.loc	2 108 21
+	sub.f32 	%f381, %f671, %f670;
+	.loc	2 109 28
+	add.f32 	%f382, %f310, %f311;
+	.loc	2 110 39
+	setp.eq.f32 	%p80, %f382, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r204, %f311;
+	mov.b32 	%r205, %f382;
+	div.full.f32 %r203, %r204, %r205;
+	mov.b32 	%f383, %r203;
+	.loc	2 110 49
+	selp.f32 	%f384, 0f00000000, %f383, %p80;
+	.loc	2 112 17
+	fma.rn.f32 	%f385, %f381, %f384, %f670;
+	.loc	2 113 15
+	add.f32 	%f386, %f654, %f655;
+	.loc	2 113 30
+	mul.f32 	%f387, %f381, %f381;
+	.loc	2 113 38
+	mul.f32 	%f388, %f387, %f310;
+	.loc	2 113 22
+	fma.rn.f32 	%f389, %f388, %f384, %f386;
+	.loc	2 108 21
+	sub.f32 	%f390, %f672, %f385;
+	.loc	2 109 28
+	add.f32 	%f391, %f312, %f382;
+	.loc	2 110 39
+	setp.eq.f32 	%p81, %f391, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r208, %f391;
+	mov.b32 	%r207, %f312;
+	div.full.f32 %r206, %r207, %r208;
+	mov.b32 	%f392, %r206;
+	.loc	2 110 49
+	selp.f32 	%f393, 0f00000000, %f392, %p81;
+	.loc	2 112 17
+	fma.rn.f32 	%f394, %f393, %f390, %f385;
+	.loc	2 113 15
+	add.f32 	%f395, %f656, %f389;
+	.loc	2 113 30
+	mul.f32 	%f396, %f390, %f390;
+	.loc	2 113 38
+	mul.f32 	%f397, %f382, %f396;
+	.loc	2 113 22
+	fma.rn.f32 	%f398, %f393, %f397, %f395;
+	.loc	2 108 21
+	sub.f32 	%f399, %f673, %f394;
+	.loc	2 109 28
+	add.f32 	%f400, %f313, %f391;
+	.loc	2 110 39
+	setp.eq.f32 	%p82, %f400, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r211, %f400;
+	mov.b32 	%r210, %f313;
+	div.full.f32 %r209, %r210, %r211;
+	mov.b32 	%f401, %r209;
+	.loc	2 110 49
+	selp.f32 	%f402, 0f00000000, %f401, %p82;
+	.loc	2 112 17
+	fma.rn.f32 	%f403, %f402, %f399, %f394;
+	.loc	2 113 15
+	add.f32 	%f404, %f657, %f398;
+	.loc	2 113 30
+	mul.f32 	%f405, %f399, %f399;
+	.loc	2 113 38
+	mul.f32 	%f406, %f391, %f405;
+	.loc	2 113 22
+	fma.rn.f32 	%f407, %f402, %f406, %f404;
+	.loc	2 108 21
+	sub.f32 	%f408, %f674, %f403;
+	.loc	2 109 28
+	add.f32 	%f409, %f314, %f400;
+	.loc	2 110 39
+	setp.eq.f32 	%p83, %f409, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r214, %f409;
+	mov.b32 	%r213, %f314;
+	div.full.f32 %r212, %r213, %r214;
+	mov.b32 	%f410, %r212;
+	.loc	2 110 49
+	selp.f32 	%f411, 0f00000000, %f410, %p83;
+	.loc	2 112 17
+	fma.rn.f32 	%f412, %f411, %f408, %f403;
+	.loc	2 113 15
+	add.f32 	%f413, %f658, %f407;
+	.loc	2 113 30
+	mul.f32 	%f414, %f408, %f408;
+	.loc	2 113 38
+	mul.f32 	%f415, %f400, %f414;
+	.loc	2 113 22
+	fma.rn.f32 	%f416, %f411, %f415, %f413;
+	.loc	2 108 21
+	sub.f32 	%f417, %f675, %f412;
+	.loc	2 109 28
+	add.f32 	%f418, %f315, %f409;
+	.loc	2 110 39
+	setp.eq.f32 	%p84, %f418, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r217, %f418;
+	mov.b32 	%r216, %f315;
+	div.full.f32 %r215, %r216, %r217;
+	mov.b32 	%f419, %r215;
+	.loc	2 110 49
+	selp.f32 	%f420, 0f00000000, %f419, %p84;
+	.loc	2 112 17
+	fma.rn.f32 	%f421, %f420, %f417, %f412;
+	.loc	2 113 15
+	add.f32 	%f422, %f659, %f416;
+	.loc	2 113 30
+	mul.f32 	%f423, %f417, %f417;
+	.loc	2 113 38
+	mul.f32 	%f424, %f409, %f423;
+	.loc	2 113 22
+	fma.rn.f32 	%f425, %f420, %f424, %f422;
+	.loc	2 108 21
+	sub.f32 	%f426, %f676, %f421;
+	.loc	2 109 28
+	add.f32 	%f427, %f316, %f418;
+	.loc	2 110 39
+	setp.eq.f32 	%p85, %f427, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r220, %f427;
+	mov.b32 	%r219, %f316;
+	div.full.f32 %r218, %r219, %r220;
+	mov.b32 	%f428, %r218;
+	.loc	2 110 49
+	selp.f32 	%f429, 0f00000000, %f428, %p85;
+	.loc	2 112 17
+	fma.rn.f32 	%f430, %f429, %f426, %f421;
+	.loc	2 113 15
+	add.f32 	%f431, %f660, %f425;
+	.loc	2 113 30
+	mul.f32 	%f432, %f426, %f426;
+	.loc	2 113 38
+	mul.f32 	%f433, %f418, %f432;
+	.loc	2 113 22
+	fma.rn.f32 	%f434, %f429, %f433, %f431;
+	.loc	2 108 21
+	sub.f32 	%f435, %f677, %f430;
+	.loc	2 109 28
+	add.f32 	%f436, %f317, %f427;
+	.loc	2 110 39
+	setp.eq.f32 	%p86, %f436, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r223, %f436;
+	mov.b32 	%r222, %f317;
+	div.full.f32 %r221, %r222, %r223;
+	mov.b32 	%f437, %r221;
+	.loc	2 110 49
+	selp.f32 	%f438, 0f00000000, %f437, %p86;
+	.loc	2 112 17
+	fma.rn.f32 	%f439, %f438, %f435, %f430;
+	.loc	2 113 15
+	add.f32 	%f440, %f661, %f434;
+	.loc	2 113 30
+	mul.f32 	%f441, %f435, %f435;
+	.loc	2 113 38
+	mul.f32 	%f442, %f427, %f441;
+	.loc	2 113 22
+	fma.rn.f32 	%f443, %f438, %f442, %f440;
+$L__tmp4:
+	.loc	2 120 46
+	mov.b32 	%r299, %f376;
+	shfl.sync.bfly.b32	%r300, %r299, 4, 31, -1;
+	mov.b32 	%f444, %r300;
+	mov.b32 	%r301, %f380;
+	shfl.sync.bfly.b32	%r302, %r301, 4, 31, -1;
+	mov.b32 	%f445, %r302;
+	shfl.sync.bfly.b32	%r225, %r202, 4, 31, -1;
+	mov.b32 	%f446, %r225;
+$L__tmp5:
+	.loc	2 108 21
+	sub.f32 	%f447, %f444, %f376;
+	.loc	2 109 28
+	add.f32 	%f448, %f373, %f446;
+	.loc	2 110 39
+	setp.eq.f32 	%p87, %f448, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r226, %f448;
+	div.full.f32 %r224, %r225, %r226;
+	mov.b32 	%f449, %r224;
+	.loc	2 110 49
+	selp.f32 	%f450, 0f00000000, %f449, %p87;
+	.loc	2 112 17
+	fma.rn.f32 	%f451, %f450, %f447, %f376;
+	.loc	2 113 15
+	add.f32 	%f452, %f380, %f445;
+	.loc	2 113 30
+	mul.f32 	%f453, %f447, %f447;
+	.loc	2 113 38
+	mul.f32 	%f454, %f373, %f453;
+	.loc	2 113 22
+	fma.rn.f32 	%f455, %f450, %f454, %f452;
+$L__tmp6:
+	.loc	2 120 46
+	mov.b32 	%r303, %f451;
+	shfl.sync.bfly.b32	%r304, %r303, 2, 31, -1;
+	mov.b32 	%f456, %r304;
+	mov.b32 	%r305, %f455;
+	shfl.sync.bfly.b32	%r306, %r305, 2, 31, -1;
+	mov.b32 	%f457, %r306;
+	shfl.sync.bfly.b32	%r228, %r226, 2, 31, -1;
+	mov.b32 	%f458, %r228;
+$L__tmp7:
+	.loc	2 108 21
+	sub.f32 	%f459, %f456, %f451;
+	.loc	2 109 28
+	add.f32 	%f460, %f448, %f458;
+	.loc	2 110 39
+	setp.eq.f32 	%p88, %f460, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r229, %f460;
+	div.full.f32 %r227, %r228, %r229;
+	mov.b32 	%f461, %r227;
+	.loc	2 110 49
+	selp.f32 	%f462, 0f00000000, %f461, %p88;
+	.loc	2 112 17
+	fma.rn.f32 	%f463, %f462, %f459, %f451;
+	.loc	2 113 15
+	add.f32 	%f464, %f455, %f457;
+	.loc	2 113 30
+	mul.f32 	%f465, %f459, %f459;
+	.loc	2 113 38
+	mul.f32 	%f466, %f448, %f465;
+	.loc	2 113 22
+	fma.rn.f32 	%f467, %f462, %f466, %f464;
+$L__tmp8:
+	.loc	2 120 46
+	mov.b32 	%r307, %f463;
+	shfl.sync.bfly.b32	%r308, %r307, 1, 31, -1;
+	mov.b32 	%f468, %r308;
+	mov.b32 	%r309, %f467;
+	shfl.sync.bfly.b32	%r310, %r309, 1, 31, -1;
+	mov.b32 	%f469, %r310;
+	shfl.sync.bfly.b32	%r231, %r229, 1, 31, -1;
+	mov.b32 	%f470, %r231;
+$L__tmp9:
+	.loc	2 108 21
+	sub.f32 	%f471, %f468, %f463;
+	.loc	2 109 28
+	add.f32 	%f472, %f460, %f470;
+	.loc	2 110 39
+	setp.eq.f32 	%p89, %f472, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r232, %f472;
+	div.full.f32 %r230, %r231, %r232;
+	mov.b32 	%f473, %r230;
+	.loc	2 110 49
+	selp.f32 	%f474, 0f00000000, %f473, %p89;
+	.loc	2 112 17
+	fma.rn.f32 	%f161, %f471, %f474, %f463;
+	.loc	2 113 15
+	add.f32 	%f475, %f467, %f469;
+	.loc	2 113 30
+	mul.f32 	%f476, %f471, %f471;
+	.loc	2 113 38
+	mul.f32 	%f477, %f460, %f476;
+	.loc	2 113 22
+	fma.rn.f32 	%f478, %f474, %f477, %f475;
+$L__tmp10:
+	.loc	2 120 46
+	mov.b32 	%r311, %f439;
+	shfl.sync.bfly.b32	%r312, %r311, 4, 31, -1;
+	mov.b32 	%f479, %r312;
+	mov.b32 	%r313, %f443;
+	shfl.sync.bfly.b32	%r314, %r313, 4, 31, -1;
+	mov.b32 	%f480, %r314;
+	shfl.sync.bfly.b32	%r234, %r223, 4, 31, -1;
+	mov.b32 	%f481, %r234;
+$L__tmp11:
+	.loc	2 108 21
+	sub.f32 	%f482, %f479, %f439;
+	.loc	2 109 28
+	add.f32 	%f483, %f436, %f481;
+	.loc	2 110 39
+	setp.eq.f32 	%p90, %f483, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r235, %f483;
+	div.full.f32 %r233, %r234, %r235;
+	mov.b32 	%f484, %r233;
+	.loc	2 110 49
+	selp.f32 	%f485, 0f00000000, %f484, %p90;
+	.loc	2 112 17
+	fma.rn.f32 	%f486, %f482, %f485, %f439;
+	.loc	2 113 15
+	add.f32 	%f487, %f443, %f480;
+	.loc	2 113 30
+	mul.f32 	%f488, %f482, %f482;
+	.loc	2 113 38
+	mul.f32 	%f489, %f436, %f488;
+	.loc	2 113 22
+	fma.rn.f32 	%f490, %f489, %f485, %f487;
+$L__tmp12:
+	.loc	2 120 46
+	mov.b32 	%r315, %f486;
+	shfl.sync.bfly.b32	%r316, %r315, 2, 31, -1;
+	mov.b32 	%f491, %r316;
+	mov.b32 	%r317, %f490;
+	shfl.sync.bfly.b32	%r318, %r317, 2, 31, -1;
+	mov.b32 	%f492, %r318;
+	shfl.sync.bfly.b32	%r237, %r235, 2, 31, -1;
+	mov.b32 	%f493, %r237;
+$L__tmp13:
+	.loc	2 108 21
+	sub.f32 	%f494, %f491, %f486;
+	.loc	2 109 28
+	add.f32 	%f495, %f483, %f493;
+	.loc	2 110 39
+	setp.eq.f32 	%p91, %f495, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r238, %f495;
+	div.full.f32 %r236, %r237, %r238;
+	mov.b32 	%f496, %r236;
+	.loc	2 110 49
+	selp.f32 	%f497, 0f00000000, %f496, %p91;
+	.loc	2 112 17
+	fma.rn.f32 	%f498, %f494, %f497, %f486;
+	.loc	2 113 15
+	add.f32 	%f499, %f490, %f492;
+	.loc	2 113 30
+	mul.f32 	%f500, %f494, %f494;
+	.loc	2 113 38
+	mul.f32 	%f501, %f483, %f500;
+	.loc	2 113 22
+	fma.rn.f32 	%f502, %f497, %f501, %f499;
+$L__tmp14:
+	.loc	2 120 46
+	mov.b32 	%r319, %f498;
+	shfl.sync.bfly.b32	%r320, %r319, 1, 31, -1;
+	mov.b32 	%f503, %r320;
+	mov.b32 	%r321, %f502;
+	shfl.sync.bfly.b32	%r322, %r321, 1, 31, -1;
+	mov.b32 	%f504, %r322;
+	shfl.sync.bfly.b32	%r240, %r238, 1, 31, -1;
+	mov.b32 	%f505, %r240;
+$L__tmp15:
+	.loc	2 108 21
+	sub.f32 	%f506, %f503, %f498;
+	.loc	2 109 28
+	add.f32 	%f507, %f495, %f505;
+	.loc	2 110 39
+	setp.eq.f32 	%p92, %f507, 0f00000000;
+	.loc	2 110 60
+	mov.b32 	%r241, %f507;
+	div.full.f32 %r239, %r240, %r241;
+	mov.b32 	%f508, %r239;
+	.loc	2 110 49
+	selp.f32 	%f509, 0f00000000, %f508, %p92;
+	.loc	2 112 17
+	fma.rn.f32 	%f162, %f506, %f509, %f498;
+	.loc	2 113 15
+	add.f32 	%f510, %f502, %f504;
+	.loc	2 113 30
+	mul.f32 	%f511, %f506, %f506;
+	.loc	2 113 38
+	mul.f32 	%f512, %f495, %f511;
+	.loc	2 113 22
+	fma.rn.f32 	%f513, %f509, %f512, %f510;
+$L__tmp16:
+	.loc	1 75 24
+	mov.b32 	%r243, %f478;
+	mov.b32 	%r244, 1132462080;
+	div.full.f32 %r242, %r243, %r244;
+	mov.b32 	%f514, %r242;
+	mov.b32 	%r267, %f513;
+	div.full.f32 %r266, %r267, %r244;
+	mov.b32 	%f515, %r266;
+	.loc	1 77 24
+	add.f32 	%f163, %f514, 0f3727C5AC;
+	add.f32 	%f164, %f515, 0f3727C5AC;
+	.loc	1 58 36
+	add.s64 	%rd9, %rd15, %rd2;
+	mov.u64 	%rd117, 0;
+	mov.b32 	%r473, -64;
+	rsqrt.approx.ftz.f32 	%f580, %f163;
+	rsqrt.approx.ftz.f32 	%f581, %f164;
+	bra.uni 	$L__BB0_5;
+$L__BB0_7:
+	.loc	1 69 35
+	add.s64 	%rd107, %rd4, %rd117;
+	add.s64 	%rd108, %rd107, 16;
+	add.s64 	%rd109, %rd3, %rd117;
+	.loc	1 69 54
+	add.s64 	%rd110, %rd109, 16;
+	mov.u32 %r407, 0x0;
+	mov.u32 %r408, 0x0;
+	mov.u32 %r409, 0x0;
+	mov.u32 %r410, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r407, %r408, %r409, %r410 }, [ %rd107 + 0 ];
+	@!%p1 mov.u32 %r407, %r411;
+	@!%p1 mov.u32 %r408, %r411;
+	@!%p1 mov.u32 %r409, %r411;
+	@!%p1 mov.u32 %r410, %r411;
+	mov.b32 	%f516, %r407;
+	mov.b32 	%f517, %r408;
+	mov.b32 	%f518, %r409;
+	mov.b32 	%f519, %r410;
+	mov.u32 %r415, 0x0;
+	mov.u32 %r416, 0x0;
+	mov.u32 %r417, 0x0;
+	mov.u32 %r418, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r415, %r416, %r417, %r418 }, [ %rd108 + 0 ];
+	@!%p1 mov.u32 %r415, %r411;
+	@!%p1 mov.u32 %r416, %r411;
+	@!%p1 mov.u32 %r417, %r411;
+	@!%p1 mov.u32 %r418, %r411;
+	mov.b32 	%f520, %r415;
+	mov.b32 	%f521, %r416;
+	mov.b32 	%f522, %r417;
+	mov.b32 	%f523, %r418;
+	mov.u32 %r423, 0x0;
+	mov.u32 %r424, 0x0;
+	mov.u32 %r425, 0x0;
+	mov.u32 %r426, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r423, %r424, %r425, %r426 }, [ %rd109 + 0 ];
+	@!%p1 mov.u32 %r423, %r411;
+	@!%p1 mov.u32 %r424, %r411;
+	@!%p1 mov.u32 %r425, %r411;
+	@!%p1 mov.u32 %r426, %r411;
+	mov.b32 	%f524, %r423;
+	mov.b32 	%f525, %r424;
+	mov.b32 	%f526, %r425;
+	mov.b32 	%f527, %r426;
+	mov.u32 %r431, 0x0;
+	mov.u32 %r432, 0x0;
+	mov.u32 %r433, 0x0;
+	mov.u32 %r434, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r431, %r432, %r433, %r434 }, [ %rd110 + 0 ];
+	@!%p1 mov.u32 %r431, %r411;
+	@!%p1 mov.u32 %r432, %r411;
+	@!%p1 mov.u32 %r433, %r411;
+	@!%p1 mov.u32 %r434, %r411;
+	mov.b32 	%f528, %r431;
+	mov.b32 	%f529, %r432;
+	mov.b32 	%f530, %r433;
+	mov.b32 	%f531, %r434;
+	.loc	1 70 24
+	add.f32 	%f532, %f165, %f516;
+	add.f32 	%f533, %f166, %f517;
+	add.f32 	%f534, %f167, %f518;
+	add.f32 	%f535, %f168, %f519;
+	add.f32 	%f536, %f169, %f520;
+	add.f32 	%f537, %f170, %f521;
+	add.f32 	%f538, %f171, %f522;
+	add.f32 	%f539, %f172, %f523;
+	add.f32 	%f540, %f173, %f524;
+	add.f32 	%f541, %f174, %f525;
+	add.f32 	%f542, %f175, %f526;
+	add.f32 	%f543, %f176, %f527;
+	add.f32 	%f544, %f177, %f528;
+	add.f32 	%f545, %f178, %f529;
+	add.f32 	%f546, %f179, %f530;
+	add.f32 	%f547, %f180, %f531;
+	.loc	1 72 24
+	add.f32 	%f548, %f181, %f532;
+	add.f32 	%f549, %f182, %f533;
+	add.f32 	%f550, %f183, %f534;
+	add.f32 	%f551, %f184, %f535;
+	add.f32 	%f552, %f185, %f536;
+	add.f32 	%f553, %f186, %f537;
+	add.f32 	%f554, %f187, %f538;
+	add.f32 	%f555, %f188, %f539;
+	add.f32 	%f556, %f189, %f540;
+	add.f32 	%f557, %f190, %f541;
+	add.f32 	%f558, %f191, %f542;
+	add.f32 	%f559, %f192, %f543;
+	add.f32 	%f560, %f193, %f544;
+	add.f32 	%f561, %f194, %f545;
+	add.f32 	%f562, %f195, %f546;
+	add.f32 	%f563, %f196, %f547;
+	.loc	1 73 24
+	sub.f32 	%f564, %f548, %f161;
+	sub.f32 	%f565, %f549, %f161;
+	sub.f32 	%f566, %f550, %f161;
+	sub.f32 	%f567, %f551, %f161;
+	sub.f32 	%f568, %f552, %f161;
+	sub.f32 	%f569, %f553, %f161;
+	sub.f32 	%f570, %f554, %f161;
+	sub.f32 	%f571, %f555, %f161;
+	sub.f32 	%f572, %f556, %f162;
+	sub.f32 	%f573, %f557, %f162;
+	sub.f32 	%f574, %f558, %f162;
+	sub.f32 	%f575, %f559, %f162;
+	sub.f32 	%f576, %f560, %f162;
+	sub.f32 	%f577, %f561, %f162;
+	sub.f32 	%f578, %f562, %f162;
+	sub.f32 	%f579, %f563, %f162;
+	.loc	1 79 24
+	mul.f32 	%f582, %f564, %f580;
+	mul.f32 	%f583, %f565, %f580;
+	mul.f32 	%f584, %f566, %f580;
+	mul.f32 	%f585, %f567, %f580;
+	mul.f32 	%f586, %f568, %f580;
+	mul.f32 	%f587, %f569, %f580;
+	mul.f32 	%f588, %f570, %f580;
+	mul.f32 	%f589, %f571, %f580;
+	mul.f32 	%f590, %f572, %f581;
+	mul.f32 	%f591, %f573, %f581;
+	mul.f32 	%f592, %f574, %f581;
+	mul.f32 	%f593, %f575, %f581;
+	mul.f32 	%f594, %f576, %f581;
+	mul.f32 	%f595, %f577, %f581;
+	mul.f32 	%f596, %f578, %f581;
+	mul.f32 	%f597, %f579, %f581;
+	.loc	1 80 24
+	mul.f32 	%f598, %f582, %f197;
+	mul.f32 	%f599, %f583, %f198;
+	mul.f32 	%f600, %f584, %f199;
+	mul.f32 	%f601, %f585, %f200;
+	mul.f32 	%f602, %f586, %f201;
+	mul.f32 	%f603, %f587, %f202;
+	mul.f32 	%f604, %f588, %f203;
+	mul.f32 	%f605, %f589, %f204;
+	mul.f32 	%f606, %f590, %f197;
+	mul.f32 	%f607, %f591, %f198;
+	mul.f32 	%f608, %f592, %f199;
+	mul.f32 	%f609, %f593, %f200;
+	mul.f32 	%f610, %f594, %f201;
+	mul.f32 	%f611, %f595, %f202;
+	mul.f32 	%f612, %f596, %f203;
+	mul.f32 	%f613, %f597, %f204;
+	.loc	1 82 29
+	shl.b64 	%rd113, %rd11, 1;
+	add.s64 	%rd111, %rd16, %rd113;
+	shl.b64 	%rd114, %rd12, 1;
+	add.s64 	%rd112, %rd16, %rd114;
+	.loc	1 82 52
+	mov.b32 	%r439, %f598;
+	cvt.rn.bf16.f32 %rs33, %r439;
+	mov.b32 	%r440, %f599;
+	cvt.rn.bf16.f32 %rs34, %r440;
+	mov.b32 	%r441, %f600;
+	cvt.rn.bf16.f32 %rs35, %r441;
+	mov.b32 	%r442, %f601;
+	cvt.rn.bf16.f32 %rs36, %r442;
+	mov.b32 	%r443, %f602;
+	cvt.rn.bf16.f32 %rs37, %r443;
+	mov.b32 	%r444, %f603;
+	cvt.rn.bf16.f32 %rs38, %r444;
+	mov.b32 	%r445, %f604;
+	cvt.rn.bf16.f32 %rs39, %r445;
+	mov.b32 	%r446, %f605;
+	cvt.rn.bf16.f32 %rs40, %r446;
+	mov.b32 	%r447, %f606;
+	cvt.rn.bf16.f32 %rs41, %r447;
+	mov.b32 	%r448, %f607;
+	cvt.rn.bf16.f32 %rs42, %r448;
+	mov.b32 	%r449, %f608;
+	cvt.rn.bf16.f32 %rs43, %r449;
+	mov.b32 	%r450, %f609;
+	cvt.rn.bf16.f32 %rs44, %r450;
+	mov.b32 	%r451, %f610;
+	cvt.rn.bf16.f32 %rs45, %r451;
+	mov.b32 	%r452, %f611;
+	cvt.rn.bf16.f32 %rs46, %r452;
+	mov.b32 	%r453, %f612;
+	cvt.rn.bf16.f32 %rs47, %r453;
+	mov.b32 	%r454, %f613;
+	cvt.rn.bf16.f32 %rs48, %r454;
+	mov.b32 	%r463, {%rs33, %rs34};
+	mov.b32 	%r464, {%rs35, %rs36};
+	mov.b32 	%r465, {%rs37, %rs38};
+	mov.b32 	%r466, {%rs39, %rs40};
+	@%p1 st.global.v4.b32 [ %rd111 + 0 ], { %r463, %r464, %r465, %r466 };
+	mov.b32 	%r467, {%rs41, %rs42};
+	mov.b32 	%r468, {%rs43, %rs44};
+	mov.b32 	%r469, {%rs45, %rs46};
+	mov.b32 	%r470, {%rs47, %rs48};
+	@%p1 st.global.v4.b32 [ %rd112 + 0 ], { %r467, %r468, %r469, %r470 };
+	.loc	1 58 36
+	add.s64 	%rd117, %rd117, 256;
+	add.s32 	%r473, %r473, 64;
+	setp.lt.u32 	%p156, %r473, 192;
+	@%p156 bra 	$L__BB0_5;
+	bra.uni 	$L__BB0_8;
+$L__BB0_5:
+	.loc	1 62 35
+	add.s64 	%rd90, %rd6, %rd117;
+	add.s64 	%rd91, %rd90, 16;
+	add.s64 	%rd92, %rd5, %rd117;
+	.loc	1 62 51
+	add.s64 	%rd93, %rd92, 16;
+	mov.u32 %r323, 0x0;
+	mov.u32 %r324, 0x0;
+	mov.u32 %r325, 0x0;
+	mov.u32 %r326, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r323, %r324, %r325, %r326 }, [ %rd90 + 0 ];
+	@!%p1 mov.u32 %r323, %r411;
+	@!%p1 mov.u32 %r324, %r411;
+	@!%p1 mov.u32 %r325, %r411;
+	@!%p1 mov.u32 %r326, %r411;
+	mov.b32 	%f165, %r323;
+	mov.b32 	%f166, %r324;
+	mov.b32 	%f167, %r325;
+	mov.b32 	%f168, %r326;
+	mov.u32 %r331, 0x0;
+	mov.u32 %r332, 0x0;
+	mov.u32 %r333, 0x0;
+	mov.u32 %r334, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r331, %r332, %r333, %r334 }, [ %rd91 + 0 ];
+	@!%p1 mov.u32 %r331, %r411;
+	@!%p1 mov.u32 %r332, %r411;
+	@!%p1 mov.u32 %r333, %r411;
+	@!%p1 mov.u32 %r334, %r411;
+	mov.b32 	%f169, %r331;
+	mov.b32 	%f170, %r332;
+	mov.b32 	%f171, %r333;
+	mov.b32 	%f172, %r334;
+	mov.u32 %r339, 0x0;
+	mov.u32 %r340, 0x0;
+	mov.u32 %r341, 0x0;
+	mov.u32 %r342, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r339, %r340, %r341, %r342 }, [ %rd92 + 0 ];
+	@!%p1 mov.u32 %r339, %r411;
+	@!%p1 mov.u32 %r340, %r411;
+	@!%p1 mov.u32 %r341, %r411;
+	@!%p1 mov.u32 %r342, %r411;
+	mov.b32 	%f173, %r339;
+	mov.b32 	%f174, %r340;
+	mov.b32 	%f175, %r341;
+	mov.b32 	%f176, %r342;
+	mov.u32 %r347, 0x0;
+	mov.u32 %r348, 0x0;
+	mov.u32 %r349, 0x0;
+	mov.u32 %r350, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r347, %r348, %r349, %r350 }, [ %rd93 + 0 ];
+	@!%p1 mov.u32 %r347, %r411;
+	@!%p1 mov.u32 %r348, %r411;
+	@!%p1 mov.u32 %r349, %r411;
+	@!%p1 mov.u32 %r350, %r411;
+	mov.b32 	%f177, %r347;
+	mov.b32 	%f178, %r348;
+	mov.b32 	%f179, %r349;
+	mov.b32 	%f180, %r350;
+	.loc	1 63 41
+	add.s32 	%r403, %r5, %r473;
+	add.s32 	%r404, %r403, 64;
+	.loc	1 63 35
+	add.s32 	%r405, %r403, 8256;
+	cvt.s64.s32 	%rd11, %r404;
+	mul.wide.s32 	%rd98, %r404, 2;
+	add.s64 	%rd94, %rd14, %rd98;
+	cvt.s64.s32 	%rd12, %r405;
+	mul.wide.s32 	%rd99, %r405, 2;
+	add.s64 	%rd95, %rd14, %rd99;
+	.loc	1 63 51
+	mov.u32 %r355, 0x0;
+	mov.u32 %r356, 0x0;
+	mov.u32 %r357, 0x0;
+	mov.u32 %r358, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r355, %r356, %r357, %r358 }, [ %rd94 + 0 ];
+	@!%p1 mov.u32 %r355, %r411;
+	@!%p1 mov.u32 %r356, %r411;
+	@!%p1 mov.u32 %r357, %r411;
+	@!%p1 mov.u32 %r358, %r411;
+	cvt.u16.u32 	%rs17, %r355;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs18}, %r355; }
+	cvt.u16.u32 	%rs19, %r356;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs20}, %r356; }
+	cvt.u16.u32 	%rs21, %r357;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs22}, %r357; }
+	cvt.u16.u32 	%rs23, %r358;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs24}, %r358; }
+	mov.u32 %r363, 0x0;
+	mov.u32 %r364, 0x0;
+	mov.u32 %r365, 0x0;
+	mov.u32 %r366, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r363, %r364, %r365, %r366 }, [ %rd95 + 0 ];
+	@!%p1 mov.u32 %r363, %r411;
+	@!%p1 mov.u32 %r364, %r411;
+	@!%p1 mov.u32 %r365, %r411;
+	@!%p1 mov.u32 %r366, %r411;
+	cvt.u16.u32 	%rs25, %r363;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs26}, %r363; }
+	cvt.u16.u32 	%rs27, %r364;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs28}, %r364; }
+	cvt.u16.u32 	%rs29, %r365;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs30}, %r365; }
+	cvt.u16.u32 	%rs31, %r366;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs32}, %r366; }
+	.loc	1 63 103
+	cvt.f32.bf16 %r371, %rs17;
+	mov.b32 	%f181, %r371;
+	cvt.f32.bf16 %r372, %rs18;
+	mov.b32 	%f182, %r372;
+	cvt.f32.bf16 %r373, %rs19;
+	mov.b32 	%f183, %r373;
+	cvt.f32.bf16 %r374, %rs20;
+	mov.b32 	%f184, %r374;
+	cvt.f32.bf16 %r375, %rs21;
+	mov.b32 	%f185, %r375;
+	cvt.f32.bf16 %r376, %rs22;
+	mov.b32 	%f186, %r376;
+	cvt.f32.bf16 %r377, %rs23;
+	mov.b32 	%f187, %r377;
+	cvt.f32.bf16 %r378, %rs24;
+	mov.b32 	%f188, %r378;
+	cvt.f32.bf16 %r379, %rs25;
+	mov.b32 	%f189, %r379;
+	cvt.f32.bf16 %r380, %rs26;
+	mov.b32 	%f190, %r380;
+	cvt.f32.bf16 %r381, %rs27;
+	mov.b32 	%f191, %r381;
+	cvt.f32.bf16 %r382, %rs28;
+	mov.b32 	%f192, %r382;
+	cvt.f32.bf16 %r383, %rs29;
+	mov.b32 	%f193, %r383;
+	cvt.f32.bf16 %r384, %rs30;
+	mov.b32 	%f194, %r384;
+	cvt.f32.bf16 %r385, %rs31;
+	mov.b32 	%f195, %r385;
+	cvt.f32.bf16 %r386, %rs32;
+	mov.b32 	%f196, %r386;
+	.loc	1 64 35
+	add.s64 	%rd96, %rd9, %rd117;
+	.loc	1 64 40
+	add.s64 	%rd97, %rd96, 16;
+	mov.u32 %r387, 0x0;
+	mov.u32 %r388, 0x0;
+	mov.u32 %r389, 0x0;
+	mov.u32 %r390, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r387, %r388, %r389, %r390 }, [ %rd96 + 0 ];
+	@!%p1 mov.u32 %r387, %r411;
+	@!%p1 mov.u32 %r388, %r411;
+	@!%p1 mov.u32 %r389, %r411;
+	@!%p1 mov.u32 %r390, %r411;
+	mov.b32 	%f197, %r387;
+	mov.b32 	%f198, %r388;
+	mov.b32 	%f199, %r389;
+	mov.b32 	%f200, %r390;
+	mov.u32 %r395, 0x0;
+	mov.u32 %r396, 0x0;
+	mov.u32 %r397, 0x0;
+	mov.u32 %r398, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r395, %r396, %r397, %r398 }, [ %rd97 + 0 ];
+	@!%p1 mov.u32 %r395, %r411;
+	@!%p1 mov.u32 %r396, %r411;
+	@!%p1 mov.u32 %r397, %r411;
+	@!%p1 mov.u32 %r398, %r411;
+	mov.b32 	%f201, %r395;
+	mov.b32 	%f202, %r396;
+	mov.b32 	%f203, %r397;
+	mov.b32 	%f204, %r398;
+	.loc	1 68 57
+	@%p51 bra 	$L__BB0_7;
+	mov.u64 	%rd100, assertMessage_1;
+	cvta.global.u64 	%rd101, %rd100;
+	mov.u64 	%rd102, assertFile_1;
+	cvta.global.u64 	%rd103, %rd102;
+	mov.u64 	%rd104, assertFunc_1;
+	cvta.global.u64 	%rd105, %rd104;
+	{ // callseq 7, 0
+	.reg .b32 temp_param_reg;
+	.param .b64 param0;
+	st.param.b64 	[param0+0], %rd101;
+	.param .b64 param1;
+	st.param.b64 	[param1+0], %rd103;
+	.param .b32 param2;
+	st.param.b32 	[param2+0], %r471;
+	.param .b64 param3;
+	st.param.b64 	[param3+0], %rd105;
+	.param .b64 param4;
+	st.param.b64 	[param4+0], %rd115;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 7
+	bra.uni 	$L__BB0_7;
+$L__BB0_8:
+	.loc	1 58 4
+	ret;
+$L__tmp17:
+$L__func_end0:
+
+}
+	// .globl	__nv_rsqrtf
+.visible .func  (.param .b32 func_retval0) __nv_rsqrtf(
+	.param .b32 __nv_rsqrtf_param_0
+)
+{
+	.reg .f32 	%f<3>;
+$L__func_begin1:
+
+	ld.param.f32 	%f1, [__nv_rsqrtf_param_0];
+	rsqrt.approx.ftz.f32 	%f2, %f1;
+	st.param.f32 	[func_retval0+0], %f2;
+	ret;
+$L__func_end1:
+
+}
+	.file	1 "/tmp/torchinductor_root/pn/cpn3lawg65lpi63gv6c6pn4oikhg6qva2h2qjdpxe6qj4lvttwez.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/torch/_inductor/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 32
+.b8 11
+.b8 0
+.b8 0
+.b8 3
+.b8 46
+.b8 1
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 49
+.b8 19
+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 1
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 302
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 112
+.b8 110
+.b8 51
+.b8 108
+.b8 97
+.b8 119
+.b8 103
+.b8 54
+.b8 53
+.b8 108
+.b8 112
+.b8 105
+.b8 54
+.b8 51
+.b8 103
+.b8 118
+.b8 54
+.b8 99
+.b8 54
+.b8 112
+.b8 110
+.b8 52
+.b8 111
+.b8 105
+.b8 107
+.b8 104
+.b8 103
+.b8 54
+.b8 113
+.b8 118
+.b8 97
+.b8 50
+.b8 104
+.b8 50
+.b8 113
+.b8 106
+.b8 100
+.b8 112
+.b8 120
+.b8 101
+.b8 54
+.b8 113
+.b8 106
+.b8 52
+.b8 108
+.b8 118
+.b8 116
+.b8 116
+.b8 119
+.b8 101
+.b8 122
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 112
+.b8 110
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp2
+.b8 2
+.b8 47
+.b8 41
+.b8 5
+.b32 125
+.b64 $L__tmp3
+.b64 $L__tmp16
+.b8 2
+.b8 53
+.b8 44
+.b8 4
+.b32 125
+.b64 $L__tmp3
+.b64 $L__tmp16
+.b8 2
+.b8 120
+.b8 46
+.b8 0
+.b8 4
+.b32 125
+.b64 $L__tmp4
+.b64 $L__tmp15
+.b8 2
+.b8 53
+.b8 44
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 306
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 101
+.b8 55
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 306
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/cde66a00b7594f6428e4f4dcdfa88537/triton_.ttgir

@@ -0,0 +1,154 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 8], threadsPerWarp = [2, 16], warpsPerCTA = [8, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [8, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked2 = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [2, 4], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5de6de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg6: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<512> : tensor<16x1xi32, #blocked>
+    %cst_0 = arith.constant dense<256> : tensor<1x128xi32, #blocked>
+    %cst_1 = arith.constant dense<256> : tensor<16x1xi32, #blocked>
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<16x128xf32, #blocked>
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<1x128xf32, #blocked>
+    %cst_4 = arith.constant dense<1.000000e+00> : tensor<16x128xf32, #blocked>
+    %cst_5 = arith.constant dense<256> : tensor<16x1xi64, #blocked>
+    %cst_6 = arith.constant dense<0> : tensor<16x1xi64, #blocked>
+    %cst_7 = arith.constant dense<50257> : tensor<16x1xi64, #blocked>
+    %cst_8 = arith.constant dense<50257> : tensor<16x1xi64, #blocked1>
+    %cst_9 = arith.constant dense<0> : tensor<16x1xi64, #blocked1>
+    %c0_i32 = arith.constant 0 : i32
+    %c128_i32 = arith.constant 128 : i32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_10 = arith.constant dense<1.000000e+00> : tensor<16x128xf32, #blocked2>
+    %cst_11 = arith.constant 0.000000e+00 : f32
+    %cst_12 = arith.constant dense<0.000000e+00> : tensor<16x128xf32, #blocked2>
+    %cst_13 = arith.constant dense<256> : tensor<1x128xi32, #blocked2>
+    %cst_14 = arith.constant dense<9.99999974E-6> : tensor<16x1xf32, #blocked>
+    %cst_15 = arith.constant dense<2.560000e+02> : tensor<16x1xf32, #blocked>
+    %c16_i32 = arith.constant 16 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c16_i32 : i32
+    %2 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %3 = tt.make_range {end = 16 : i32, start = 0 : i32} : tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xi32, #blocked>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<16xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<16x1xi32, #blocked1>
+    %6 = tt.splat %1 : (i32) -> tensor<16x1xi32, #blocked>
+    %7 = tt.splat %1 : (i32) -> tensor<16x1xi32, #blocked1>
+    %8 = arith.addi %6, %4 : tensor<16x1xi32, #blocked>
+    %9 = arith.addi %7, %5 : tensor<16x1xi32, #blocked1>
+    %10 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %11 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked2}>>
+    %12 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x128xi32, #blocked>
+    %13 = tt.expand_dims %11 {axis = 0 : i32} : (tensor<128xi32, #triton_gpu.slice<{dim = 0, parent = #blocked2}>>) -> tensor<1x128xi32, #blocked2>
+    %14 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>, #blocked>
+    %15 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<16x1x!tt.ptr<i64, 1>, #blocked1>
+    %16 = tt.addptr %14, %8 : tensor<16x1x!tt.ptr<i64, 1>, #blocked>, tensor<16x1xi32, #blocked>
+    %17 = tt.addptr %15, %9 : tensor<16x1x!tt.ptr<i64, 1>, #blocked1>, tensor<16x1xi32, #blocked1>
+    %18 = tt.load %16 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64, #blocked>
+    %19 = tt.load %17 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x1xi64, #blocked1>
+    %20 = arith.remsi %8, %cst : tensor<16x1xi32, #blocked>
+    %21 = arith.muli %20, %cst_1 : tensor<16x1xi32, #blocked>
+    %22 = tt.broadcast %21 : (tensor<16x1xi32, #blocked>) -> tensor<16x128xi32, #blocked>
+    %23 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<16x128x!tt.ptr<f32, 1>, #blocked>
+    %24 = arith.addi %18, %cst_7 : tensor<16x1xi64, #blocked>
+    %25 = arith.addi %19, %cst_8 : tensor<16x1xi64, #blocked1>
+    %26 = arith.cmpi slt, %18, %cst_6 : tensor<16x1xi64, #blocked>
+    %27 = arith.cmpi slt, %19, %cst_9 : tensor<16x1xi64, #blocked1>
+    %28 = arith.select %26, %24, %18 : tensor<16x1xi1, #blocked>, tensor<16x1xi64, #blocked>
+    %29 = arith.select %27, %25, %19 : tensor<16x1xi1, #blocked1>, tensor<16x1xi64, #blocked1>
+    %30 = arith.cmpi sge, %29, %cst_9 : tensor<16x1xi64, #blocked1>
+    %31 = arith.cmpi slt, %29, %cst_8 : tensor<16x1xi64, #blocked1>
+    %32 = arith.andi %30, %31 : tensor<16x1xi1, #blocked1>
+    %33 = arith.muli %28, %cst_5 : tensor<16x1xi64, #blocked>
+    %34 = tt.broadcast %33 : (tensor<16x1xi64, #blocked>) -> tensor<16x128xi64, #blocked>
+    %35 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<16x128x!tt.ptr<f32, 1>, #blocked>
+    %36:4 = scf.for %arg7 = %c0_i32 to %c256_i32 step %c128_i32 iter_args(%arg8 = %cst_2, %arg9 = %cst_2, %arg10 = %cst_12, %arg11 = %cst_2) -> (tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked2>, tensor<16x128xf32, #blocked>)  : i32 {
+      %48 = tt.splat %arg7 : (i32) -> tensor<1x128xi32, #blocked>
+      %49 = tt.splat %arg7 : (i32) -> tensor<1x128xi32, #blocked2>
+      %50 = arith.addi %48, %12 : tensor<1x128xi32, #blocked>
+      %51 = arith.addi %49, %13 : tensor<1x128xi32, #blocked2>
+      %52 = arith.cmpi slt, %50, %cst_0 : tensor<1x128xi32, #blocked>
+      %53 = arith.cmpi slt, %51, %cst_13 : tensor<1x128xi32, #blocked2>
+      %54 = tt.broadcast %50 : (tensor<1x128xi32, #blocked>) -> tensor<16x128xi32, #blocked>
+      %55 = arith.addi %54, %22 : tensor<16x128xi32, #blocked>
+      %56 = tt.addptr %23, %55 : tensor<16x128x!tt.ptr<f32, 1>, #blocked>, tensor<16x128xi32, #blocked>
+      %57 = tt.broadcast %52 : (tensor<1x128xi1, #blocked>) -> tensor<16x128xi1, #blocked>
+      %58 = tt.broadcast %53 : (tensor<1x128xi1, #blocked2>) -> tensor<16x128xi1, #blocked2>
+      %59 = tt.load %56, %57, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x128xf32, #blocked>
+      tt.assert %32, "index out of bounds: 0 <= tmp3 < 50257", "/usr/local/lib/python3.10/dist-packages/torch/_inductor/codecache.py", "<module>", 1892 : tensor<16x1xi1, #blocked1>
+      %60 = arith.extsi %50 : tensor<1x128xi32, #blocked> to tensor<1x128xi64, #blocked>
+      %61 = tt.broadcast %60 : (tensor<1x128xi64, #blocked>) -> tensor<16x128xi64, #blocked>
+      %62 = arith.addi %61, %34 : tensor<16x128xi64, #blocked>
+      %63 = tt.addptr %35, %62 : tensor<16x128x!tt.ptr<f32, 1>, #blocked>, tensor<16x128xi64, #blocked>
+      %64 = tt.load %63, %57, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x128xf32, #blocked>
+      %65 = arith.addf %64, %59 : tensor<16x128xf32, #blocked>
+      %66 = arith.subf %65, %arg8 : tensor<16x128xf32, #blocked>
+      %67 = arith.addf %arg11, %cst_4 : tensor<16x128xf32, #blocked>
+      %68 = arith.addf %arg10, %cst_10 : tensor<16x128xf32, #blocked2>
+      %69 = arith.divf %66, %67 : tensor<16x128xf32, #blocked>
+      %70 = arith.addf %arg8, %69 : tensor<16x128xf32, #blocked>
+      %71 = arith.subf %65, %70 : tensor<16x128xf32, #blocked>
+      %72 = arith.mulf %66, %71 : tensor<16x128xf32, #blocked>
+      %73 = arith.addf %arg9, %72 : tensor<16x128xf32, #blocked>
+      %74 = arith.select %57, %70, %arg8 : tensor<16x128xi1, #blocked>, tensor<16x128xf32, #blocked>
+      %75 = arith.select %57, %73, %arg9 : tensor<16x128xi1, #blocked>, tensor<16x128xf32, #blocked>
+      %76 = arith.select %57, %67, %arg11 : tensor<16x128xi1, #blocked>, tensor<16x128xf32, #blocked>
+      %77 = arith.select %58, %68, %arg10 : tensor<16x128xi1, #blocked2>, tensor<16x128xf32, #blocked2>
+      scf.yield %74, %75, %77, %76 : tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked2>, tensor<16x128xf32, #blocked>
+    }
+    %37 = triton_gpu.convert_layout %36#2 : (tensor<16x128xf32, #blocked2>) -> tensor<16x128xf32, #blocked>
+    %38:3 = "tt.reduce"(%36#0, %36#1, %37) <{axis = 1 : i32}> ({
+    ^bb0(%arg7: f32, %arg8: f32, %arg9: f32, %arg10: f32, %arg11: f32, %arg12: f32):
+      %48 = arith.subf %arg10, %arg7 : f32
+      %49 = arith.addf %arg9, %arg12 : f32
+      %50 = arith.cmpf oeq, %49, %cst_11 : f32
+      %51 = arith.divf %arg12, %49 : f32
+      %52 = arith.select %50, %cst_11, %51 : f32
+      %53 = arith.mulf %48, %52 : f32
+      %54 = arith.addf %arg7, %53 : f32
+      %55 = arith.addf %arg8, %arg11 : f32
+      %56 = arith.mulf %48, %48 : f32
+      %57 = arith.mulf %56, %arg9 : f32
+      %58 = arith.mulf %57, %52 : f32
+      %59 = arith.addf %55, %58 : f32
+      tt.reduce.return %54, %59, %49 : f32, f32, f32
+    }) : (tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked>, tensor<16x128xf32, #blocked>) -> (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>, tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>, tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>)
+    %39 = tt.expand_dims %38#0 {axis = 1 : i32} : (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xf32, #blocked>
+    %40 = tt.expand_dims %38#1 {axis = 1 : i32} : (tensor<16xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<16x1xf32, #blocked>
+    %41 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<1x128x!tt.ptr<f32, 1>, #blocked>
+    %42 = tt.broadcast %39 : (tensor<16x1xf32, #blocked>) -> tensor<16x128xf32, #blocked>
+    %43 = arith.divf %40, %cst_15 : tensor<16x1xf32, #blocked>
+    %44 = arith.addf %43, %cst_14 : tensor<16x1xf32, #blocked>
+    %45 = arith.muli %8, %cst_1 : tensor<16x1xi32, #blocked>
+    %46 = tt.broadcast %45 : (tensor<16x1xi32, #blocked>) -> tensor<16x128xi32, #blocked>
+    %47 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<16x128x!tt.ptr<bf16, 1>, #blocked>
+    scf.for %arg7 = %c0_i32 to %c256_i32 step %c128_i32  : i32 {
+      %48 = tt.splat %arg7 : (i32) -> tensor<1x128xi32, #blocked>
+      %49 = arith.addi %48, %12 : tensor<1x128xi32, #blocked>
+      %50 = arith.cmpi slt, %49, %cst_0 : tensor<1x128xi32, #blocked>
+      %51 = tt.broadcast %49 : (tensor<1x128xi32, #blocked>) -> tensor<16x128xi32, #blocked>
+      %52 = arith.addi %51, %22 : tensor<16x128xi32, #blocked>
+      %53 = tt.addptr %23, %52 : tensor<16x128x!tt.ptr<f32, 1>, #blocked>, tensor<16x128xi32, #blocked>
+      %54 = tt.broadcast %50 : (tensor<1x128xi1, #blocked>) -> tensor<16x128xi1, #blocked>
+      %55 = tt.load %53, %54, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<16x128xf32, #blocked>
+      %56 = tt.addptr %41, %49 : tensor<1x128x!tt.ptr<f32, 1>, #blocked>, tensor<1x128xi32, #blocked>
+      %57 = tt.load %56, %50, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1x128xf32, #blocked>
+      tt.assert %32, "index out of bounds: 0 <= tmp13 < 50257", "/usr/local/lib/python3.10/dist-packages/torch/_inductor/codecache.py", "<module>", 1892 : tensor<16x1xi1, #blocked1>
+      %58 = arith.extsi %49 : tensor<1x128xi32, #blocked> to tensor<1x128xi64, #blocked>
+      %59 = tt.broadcast %58 : (tensor<1x128xi64, #blocked>) -> tensor<16x128xi64, #blocked>
+      %60 = arith.addi %59, %34 : tensor<16x128xi64, #blocked>
+      %61 = tt.addptr %35, %60 : tensor<16x128x!tt.ptr<f32, 1>, #blocked>, tensor<16x128xi64, #blocked>
+      %62 = tt.load %61, %54, %cst_2 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<16x128xf32, #blocked>
+      %63 = arith.addf %62, %55 : tensor<16x128xf32, #blocked>
+      %64 = arith.subf %63, %42 : tensor<16x128xf32, #blocked>
+      %65 = tt.extern_elementwise %44 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (tensor<16x1xf32, #blocked>) -> tensor<16x1xf32, #blocked>
+      %66 = tt.broadcast %65 : (tensor<16x1xf32, #blocked>) -> tensor<16x128xf32, #blocked>
+      %67 = arith.mulf %64, %66 : tensor<16x128xf32, #blocked>
+      %68 = tt.broadcast %57 : (tensor<1x128xf32, #blocked>) -> tensor<16x128xf32, #blocked>
+      %69 = arith.mulf %67, %68 : tensor<16x128xf32, #blocked>
+      %70 = arith.addi %51, %46 : tensor<16x128xi32, #blocked>
+      %71 = tt.addptr %47, %70 : tensor<16x128x!tt.ptr<bf16, 1>, #blocked>, tensor<16x128xi32, #blocked>
+      %72 = arith.truncf %69 : tensor<16x128xf32, #blocked> to tensor<16x128xbf16, #blocked>
+      tt.store %71, %72, %54 {cache = 1 : i32, evict = 1 : i32} : tensor<16x128xbf16, #blocked>
+    }
+    tt.return
+  }
+}

wandb/run-20240926_055222-14kj2390/run-14kj2390.wandb

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a41d34844187b603a549bc59bb4411ea5dc13a1b984865be55df2318b2e7a8c3
+size 28769629

wandb/run-20240926_124123-zc6s8e8w/run-zc6s8e8w.wandb

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:fb8a97e2da032f4f531a370d36d1202e0c3415accd568812cc10f04ca7663010
+size 28283808

wandb/run-20240926_192831-378lr5yg/run-378lr5yg.wandb

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+oid sha256:6072638d705ca84f37480a4e2d52557f77495381d8a7857a0fe95ba3c6b6d88b
+size 28266657

wandb/run-20240927_021423-clesd0p8/run-clesd0p8.wandb

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+version https://git-lfs.github.com/spec/v1
+oid sha256:80ce69a6ed252398eac1d3fc86876dd099d2ecff12750606bc8be6129112bf24
+size 27656192