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Datasets:
AWfaw
/
ai-hdlcoder-dataset

Tasks:
Text Generation
Modalities:
Text
Formats:
json
Sub-tasks:
language-modeling
Languages:
code
Size:
100K - 1M
Libraries:
Datasets
Dask
License:
Dataset card Viewer Files
AWfaw commited on
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1 Parent(s): 2e8c1da

Update README.md

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  1. README.md +15 -46
README.md CHANGED
@@ -35,52 +35,21 @@ The dataset is created for research purposes and consists of source code from a
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  ### Data Instances
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  ```python
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- [
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- [
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- {
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- "name": "repo_name",
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- "mode": "NULLABLE",
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- "type": "STRING",
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- "description": null,
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- "fields": []
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- },
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- {
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- "name": "path",
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- "mode": "NULLABLE",
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- "type": "STRING",
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- "description": null,
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- "fields": []
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- },
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- {
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- "name": "copies",
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- "mode": "NULLABLE",
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- "type": "INTEGER",
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- "description": null,
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- "fields": []
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- },
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- {
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- "name": "size",
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- "mode": "NULLABLE",
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- "type": "INTEGER",
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- "description": null,
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- "fields": []
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- },
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- {
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- "name": "content",
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- "mode": "NULLABLE",
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- "type": "STRING",
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- "description": null,
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- "fields": []
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- },
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- {
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- "name": "license",
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- "mode": "NULLABLE",
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- "type": "STRING",
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- "description": null,
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- "fields": []
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- }
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- ]
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- ]
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  ```
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  ### Data Fields
 
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  ### Data Instances
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  ```python
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+ {
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+ "repo_name": "sebgod/linguist",
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+ "path": "samples/VHDL/foo.vhd",
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+ "copies": "91",
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+ "size": "217",
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+ "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
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+ "license": "mit"
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+ }, {
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+ "repo_name": "cybernet14/linguist",
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+ "path": "samples/VHDL/foo.vhd",
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+ "copies": "91",
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+ "size": "217",
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+ "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
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+ "license": "mit"
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+ }
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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  ```
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  ### Data Fields