Datasets:

AWfaw

/

ai-hdlcoder-dataset

like 0

franz/pocl

examples/accel/rtl/firmware_imem_pkg.vhdl

2

17707

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.ffaccel_imem_mau.all; package ffaccel_imem_image is type std_logic_imem_matrix is array (natural range <>) of std_logic_vector(IMEMMAUWIDTH-1 downto 0); constant imem_array : std_logic_imem_matrix := ( "0000000001001010000000000011111111000101010", "0000101110001010110000000000000001011001010", "0000101100000000000000100110000000001000100", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000100000001000000000000011011001011", "0000000000010000100101111111111111111111111", "0000000000000000101101111111111111111111111", "0000000001010000110101111111111111111111111", "0000000000011001110000100000000001110110011", "0000101100001001000000000000000000011001101", "0010100011011010100101111111111111111111111", "0010100010000111100101111111111111111111111", "0000000000001001100000000000000001101010000", "0101111111111111111101111111111111111111111", "0000111010000100111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110110001010000000001111110000000100001", "0101111111111111111101111111111111111111111", "0000101100000000111000100110000000000110001", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000111111110100001", "0101111111111111111101111111111111111111111", "0000101100000001001000100110000000001010000", "0000000000010100010101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000100001001011", "0001000000001001100001000000000001101010000", "0101111111111111111101111111111111111111111", "0001111010000100111101111111111111111111111", "0000000000100100010000100000000010011010000", "0000001110000100000000100000000001111010000", "0000101100001001000101111111111111111111111", "0000101100000110000001000000101011001001011", "0010000000110100010010100000000010011010000", "0101111111111111111101111111111111111111111", "0000101010000001000010100110000000001001000", "0101111111111111111001000000111001011001011", "0001000010000100000001100000000001111010000", "0101111111111111111101111111111111111111111", "0001101100000001001001100110000000000110000", "0000100001101010000101111111111111111111111", "0000100010010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000010000100000000100000000001111010000", "0000100001010001001101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000010100001001011", "0001000100000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001010000000000000000000010101011", "0101111111111111111101111111111111111111111", "0000101100001001000000100110000000001010000", "0000000000010100001001000000101000101001011", "0101111111111111111101111111111111111111111", "0000101100000001001101111111111111111111111", "0001000000000100010001100000000010011010000", "0000000100000100000000100000000001111010000", "0101111111111111111101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011001011001011", "0001000110000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001000110000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011110101001011", "0001001000000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001000000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000100011111001011", "0001001010000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001010000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100010100110000001000000101001001001011", "0001000000000100010001100000000010011010000", "0101111111111111111101111111111111111111111", "0001101100001001000010100100000000000111000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0010000000000100010010100000000010001010000", "0000000000000100010000100000000010011010000", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000001101111001011", "0001000010000100000001100000000001111010000", "0001100001010001001101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000011000100000000100000000001111010000", "0000000100000100000000100000000001111010000", "0000101100000110000000100000000001111010000", "0000101100000110000000000000001000000100000", "0000100001111010000101111111111111111111111", "0000101010000001001000100110000000000110000", "0101111111111111111000000000001010000100000", "0000100010011010000000100100000000000100110", "0000101100000110000000100100000000000001101", "0000000101000100000000100000000001111010000", "0000000000100100010000100000000011011010000", "0000101010000001100000100110000000000110000", "0000101010000111000000100110000000001001000", "0000000010000100000000100100000000001010000", "0000101010001010000000110010000000000100110", "0000101100000111000000100000000011001010000", "0000110000000001010000000000000001000100000", "0101111111111111111101111111111111111111111", "0000111000000001001000100110000000000111000", "0000110000000001011001000001010110101001011", "0101111111111111111101111111111111111111111", "0000110000000001100101111111111111111111111", "0001000000000100010001100000000010011010000", "0000100001001010000101111111111111111111111", "0000100011010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000000000100010000100000000010011010000", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000011111110100000000100000000010011010000", "0000100010100111000101111111111111111111111", "0000101100000001001000100000000011000111000", "0000101100001010000000000000000000000100010", "0000110000001010000101111111111111111111111", "0000110000000100000000100110000000001001000", "0000000001000100000000100000000010101010000", "0000101100001010100000100000000011001010000", "0000101100000001010000000000000001000100000", "0000100010110111100000100000000010111010000", "0000101100000001100000000000000001000100000", "0101111111111111111010000000110101001001011", "0000101100000001011101111111111111111111111", "0010011111110100000010100000000010011010000", "0010100010100111000101111111111111111111111", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000111110111001011", "0001000100000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000000111101001001011", "0101111111111111111101111111111111111111111", "0010000100000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001000100011001011", "0001000110000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001000010101001011", "0101111111111111111101111111111111111111111", "0010000110000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001001111001011", "0001001000000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001000001001011", "0101111111111111111101111111111111111111111", "0010001000000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001111111001011", "0001001010000100000001100000000001111010000", "0001100001000001101010100000000010010110000", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001101101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0000001010000100000000100000000001111010000", "0000100001000001101101111111111111111111111", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010010110000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001010100001001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010100111000000100000000010101010000", "0000100011000111000000000000000001000100000", "0000100010011010000000011111111111110100000", "0000110000001010000000100110000000000001010", "0000110000000100110000100110000000000001001", "0000101100001010000000100000000001010100010", "0000000001000100000000100000000011001010000", "0000101100001001000000100000000010111010000", "0000111000001010100000100000000010110111100", "0000101100000001100000000000000001000100000", "0101111111111111111010000001011000101001011", "0000101100000001011101111111111111111111111", "0010100010100111000010100000000010101010000", "0010000001000100000010100000000011000111000", "0000100001000001101000000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000000100010000100000000010001010000"); end ffaccel_imem_image;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gaisler/ddr/ddrrec.vhd

2

19211

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- File: ddrrec.vhd -- Author: David Lindh - Gaisler Research -- Description: DDR-RAM memory controller interface records ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library gaisler; use grlib.devices.all; use gaisler.memctrl.all; library techmap; use techmap.gencomp.all; use techmap.allmem.all; package ddrrec is ------------------------------------------------------------------------------- -- Options ------------------------------------------------------------------------------- -- This can be changed constant buffersize : integer := 4; -- Data buffer size, 2,4,8.,.-1024 (8 word) bursts ------------------------------------------------------------------------------- -- Data sizes, should not haveto be changed ------------------------------------------------------------------------------- type dm_arr is array(4 to 16) of integer; constant dmvector : dm_arr := (2,others => 1); constant maxdqsize : integer := 64; constant maxdmsize : integer := 16; constant maxstrobesize : integer := 16; constant adrbits : integer := 16; -- BA + row/col address -1 (2+14-1) constant ahbadr : integer := 32; -- AHB addressbits constant ahbdata : integer := 32; -- AHB databits constant bufferadr : integer := log2(buffersize)+2; constant ddrcfg_reset : std_logic_vector(31 downto 0):= '1' & --refresh "00" & -- CAS "00" & -- Memcmd "10" & -- Burst length '0' & -- Auto Precharge "11" & -- Read prediction "00" & -- Write protection x"00000"; --Memory commands (RAS, CAS, WE) constant CMD_READ : std_logic_vector(2 downto 0) := "101"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "100"; constant CMD_NOP : std_logic_vector(2 downto 0) := "111"; constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "011"; constant CMD_BT : std_logic_vector(2 downto 0) := "110"; constant CMD_PRE : std_logic_vector(2 downto 0) := "010"; constant CMD_AR : std_logic_vector(2 downto 0) := "001"; constant CMD_LMR : std_logic_vector(2 downto 0) := "000"; constant BANK0 : std_logic_vector(1 downto 0) := "10"; constant BANK1 : std_logic_vector(1 downto 0) := "01"; constant BANK01 : std_logic_vector(1 downto 0) := "00"; type burst_mask_type is array (buffersize-1 downto 0) of integer range 1 to 8; type two_burst_mask_type is array (1 downto 0) of burst_mask_type; type two_buf_adr_type is array (1 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0); type two_buf_data_type is array (1 downto 0) of std_logic_vector((bufferadr-1) downto 0); type pre_row_type is array (7 downto 0) of std_logic_vector(adrbits-1 downto 0); type two_ddr_adr_type is array (1 downto 0) of std_logic_vector(adrbits-1 downto 0); type two_ddr_bank_type is array (1 downto 0) of std_logic_vector(1 downto 0); type two_pre_bank_type is array (1 downto 0) of integer range 0 to 7; type blwaittype is array (6 downto 0) of integer range 2 to 8; type mlwaittype is array (1 downto 0) of integer range 1 to 8; type bufwaittype is array (6 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0); type ahbwaittype is array (6 downto 0) of integer range 0 to 1; ------------------------------------------------------------------------------- -- Records ------------------------------------------------------------------------------- -- APB controller type apb_ctrl_in_type is record apbsi : apb_slv_in_type; apb_cmd_done : std_ulogic; ready : std_ulogic; end record; type apb_ctrl_out_type is record apbso : apb_slv_out_type; ddrcfg_reg : std_logic_vector(31 downto 0); end record; ------------------------------------------------------------------------------- -- Sync ram dp (data-fifo) type syncram_dp_in_type is record address1 : std_logic_vector((bufferadr -1) downto 0); datain1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); enable1 : std_ulogic; write1 : std_ulogic; address2 : std_logic_vector((bufferadr-1) downto 0); datain2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); enable2 : std_ulogic; write2 : std_ulogic; end record; type syncram_dp_out_type is record dataout1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); dataout2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); end record; type two_syncram_dp_out_type is array (1 downto 0) of syncram_dp_out_type; type two_syncram_dp_in_type is array (1 downto 0) of syncram_dp_in_type; ------------------------------------------------------------------------------- -- Sync ram 2p (adr-fifo) type syncram_2p_in_type is record renable : std_ulogic; raddress : std_logic_vector((log2(buffersize) -1) downto 0); write : std_ulogic; waddress : std_logic_vector((log2(buffersize)-1) downto 0); datain : std_logic_vector((ahbadr-1+1) downto 0); end record; type syncram_2p_out_type is record dataout : std_logic_vector((ahbadr-1+1) downto 0); end record; ----------------------------------------------------------------------------- -- High speed interface towards memory type hs_in_type is record bl : integer range 2 to 8; ml : integer range 1 to 8; cas : std_logic_vector(1 downto 0); buf : std_logic_vector((log2(buffersize)-1) downto 0); ahb : integer range 0 to 1; cs : std_logic_vector(1 downto 0); adr : std_logic_vector(adrbits-1 downto 0); cmd : std_logic_vector(2 downto 0); cmd_valid : std_ulogic; dsramso : two_syncram_dp_out_type; ddso : ddrmem_out_type; end record; type hs_out_type is record hs_busy : std_ulogic; cmdDone : two_buf_adr_type; dsramsi : two_syncram_dp_in_type; ddsi : ddrmem_in_type; end record; ----------------------------------------------------------------------------- -- AHB controller type ahb_ctrl_in_type is record ahbsi : ahb_slv_in_type; asramsi : syncram_2p_in_type; dsramsi : syncram_dp_in_type; burstlength : integer range 2 to 8; r_predict : std_ulogic; w_prot : std_ulogic; locked : std_ulogic; rw_cmd_done : std_logic_vector((log2(buffersize) -1) downto 0); end record; type ahb_ctrl_out_type is record ahbso : ahb_slv_out_type; asramso : syncram_2p_out_type; dsramso : syncram_dp_out_type; rw_cmd_valid : std_logic_vector((log2(buffersize) -1) downto 0); w_data_valid : std_logic_vector((log2(buffersize) -1) downto 0); burst_dm : burst_mask_type; end record; type two_ahb_ctrl_out_type is array (1 downto 0) of ahb_ctrl_out_type; type two_ahb_ctrl_in_type is array (1 downto 0) of ahb_ctrl_in_type; ----------------------------------------------------------------------------- -- Main controller type main_ctrl_in_type is record apbctrlso : apb_ctrl_out_type; ahbctrlso : two_ahb_ctrl_out_type; hsso : hs_out_type; end record; type main_ctrl_out_type is record apbctrlsi : apb_ctrl_in_type; ahbctrlsi : two_ahb_ctrl_in_type; hssi : hs_in_type; end record; ------------------------------------------------------------------------------- -- DDRCFG register type config_out_type is record refresh : std_ulogic; cas : std_logic_vector(1 downto 0); memcmd : std_logic_vector(1 downto 0); bl : std_logic_vector(1 downto 0); autopre : std_ulogic; r_predict : std_logic_vector(1 downto 0); w_prot : std_logic_vector(1 downto 0); ready : std_ulogic; end record; ------------------------------------------------------------------------------- -- State machines ------------------------------------------------------------------------------- type apbcycletype is (idle, refresh, cmd, wait_lmr1, wait_lmr2, cmdlmr, cmdDone, cmdDone2); type timercycletype is (t1, t2, t3, t4); type initcycletype is (idle, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11); type maincycletype is (init, idle, pre1, act1, w1, r1, rw, c1, c2); type rwcycletype is (idle, r, w); type cmdbuffercycletype is (no_cmd, new_cmd); type cmdcycletype is(idle, hold); ----------------------------------------------------------------------------- -- AHB - Local variables type ahb_reg_type is record readcounter : integer range 0 to 8; writecounter : integer range 0 to 8; blockburstlength : integer range 0 to 8; hready : std_ulogic; hresp : std_logic_vector(1 downto 0); rwadrbuffer : std_logic_vector((ahbadr-1) downto 0); use_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0); pre_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0); pre_read_adr : std_logic_vector((ahbadr-1) downto 0); pre_read_valid : std_ulogic; use_write_buffer : std_logic_vector((log2(buffersize)-1) downto 0); rw_cmd_valid : std_logic_vector((log2(buffersize)-1) downto 0); w_data_valid : std_logic_vector((log2(buffersize)-1) downto 0); sync_adr : std_logic_vector((bufferadr-1) downto 0); sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); sync_write : std_ulogic; sync_busy : std_ulogic; sync_busy_adr : std_logic_vector((bufferadr-1) downto 0); sync2_adr : std_logic_vector((log2(buffersize)-1) downto 0); sync2_wdata : std_logic_vector((ahbadr-1+1) downto 0); sync2_write : std_ulogic; sync2_busy : std_ulogic; doRead : std_ulogic; doWrite : std_ulogic; new_burst : std_ulogic; startp : integer range 0 to 7; ahbstartp : integer range 0 to 7; even_odd_write : integer range 0 to 1; burst_hsize : integer range 1 to 8; offset : std_logic_vector(2 downto 0); ahboffset : std_logic_vector(2 downto 0); read_data : std_logic_vector(maxdqsize-1 downto 0); cur_hrdata : std_logic_vector((ahbdata-1) downto 0); cur_hready : std_ulogic; cur_hresp : std_logic_vector(1 downto 0); prev_retry : std_ulogic; prev_error : std_ulogic; burst_dm : burst_mask_type; end record; ------------------------------------------------------------------------------- -- APB controller - Local variables type apb_reg_type is record ddrcfg_reg : std_logic_vector(31 downto 0); end record; ------------------------------------------------------------------------------- -- High speed RW - Local variables type rw_reg_type is record cbufstate : cmdbuffercycletype; cmdstate : cmdcycletype; rwstate : rwcycletype; cur_buf : two_buf_adr_type; cur_ahb : integer range 0 to 1; use_bl : integer range 2 to 8; use_ml : integer range 1 to 8; use_buf : std_logic_vector((log2(buffersize)-1) downto 0); use_ahb : integer range 0 to 1; use_cas : std_ulogic; rw_cmd : std_logic_vector(2 downto 0); rw_bl : integer range 2 to 8; rw_cas : integer range 2 to 3; next_bl : integer range 2 to 8; next_ml : integer range 1 to 8; next_buf : std_logic_vector((log2(buffersize)-1) downto 0); next_ahb : integer range 0 to 1; next_cas : std_logic_vector(1 downto 0); next_adr : std_logic_vector(adrbits-1 downto 0); next_cs : std_logic_vector(1 downto 0); next_cmd : std_logic_vector(2 downto 0); set_cmd : std_logic_vector(2 downto 0); set_adr : std_logic_vector(adrbits-1 downto 0); set_cs : std_logic_vector(1 downto 0); set_cke : std_ulogic; hs_busy : std_ulogic; cmdDone : two_buf_adr_type; begin_read : std_ulogic; begin_write : std_ulogic; dq_dqs_oe : std_ulogic; w_ce : std_ulogic; r_ce : std_ulogic; cnt : integer range 0 to 8; holdcnt : integer range 0 to 31; r2wholdcnt : integer range 0 to 15; act2precnt : integer range 0 to 15; wait_time : integer range 0 to 31; readwait : std_logic_vector(6 downto 0); writewait : std_logic_vector(1 downto 0); bufwait : bufwaittype; ahbwait : ahbwaittype; blwait : blwaittype; mlwait : mlwaittype; caswait : std_logic_vector(6 downto 0); dm1_o : std_logic_vector((maxdmsize-1) downto 0); dm2_o : std_logic_vector((maxdmsize-1) downto 0); dqs1_o : std_ulogic; sync_adr : two_buf_data_type; sync_write : std_logic_vector(1 downto 0); sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0); end record; ------------------------------------------------------------------------------- -- High speed CMD - Local variables type cmd_reg_type is record cur_cmd : std_logic_vector(2 downto 0); cur_cs : std_logic_vector(1 downto 0); cur_adr : std_logic_vector(adrbits-1 downto 0); next_cmd : std_logic_vector(2 downto 0); next_cs : std_logic_vector(1 downto 0); next_adr : std_logic_vector(adrbits-1 downto 0); end record; ------------------------------------------------------------------------------- -- Main controller - Local variables type main_reg_type is record -- For main controller mainstate : maincycletype; loadcmdbuffer : std_ulogic; cmdbufferdata : std_logic_vector(2 downto 0); adrbufferdata : std_logic_vector(adrbits-1 downto 0); use_ahb : integer range 0 to 1; use_bl : integer range 2 to 8; use_cas : std_logic_vector(1 downto 0); use_buf : std_logic_vector((log2(buffersize)-1) downto 0); burstlength : integer range 2 to 8; rw_cmd_done : two_buf_adr_type; lmradr : std_logic_vector(adrbits-1 downto 0); memCmdDone : std_ulogic; lockAHB : std_logic_vector(1 downto 0); pre_row : pre_row_type; pre_chg : std_logic_vector(7 downto 0); pre_bankadr : two_pre_bank_type; sync2_adr : two_buf_adr_type; -- For init statemachine initstate : initcycletype; doMemInit : std_ulogic; memInitDone : std_ulogic; initDelay : integer range 0 to 255; cs : std_logic_vector(1 downto 0); -- For address calculator coladdress : two_ddr_adr_type; tmpcoladdress : two_ddr_adr_type; rowaddress : two_ddr_adr_type; addressrange : integer range 0 to 31; tmpcolbits : integer range 0 to 15; colbits : integer range 0 to 15; rowbits : integer range 0 to 15; bankselect : two_ddr_bank_type; intbankbits : two_ddr_bank_type; -- For refresh timer statemachine timerstate : timercycletype; doRefresh : std_ulogic; refreshDone : std_ulogic; refreshTime : integer range 0 to 4095; maxRefreshTime : integer range 0 to 32767; idlecnt : integer range 0 to 10; refreshcnt : integer range 0 to 65535; -- For DDRCFG register (APB) apbstate : apbcycletype; apb_cmd_done : std_ulogic; ready : std_ulogic; ddrcfg : config_out_type; end record; ------------------------------------------------------------------------------- -- Components ------------------------------------------------------------------------------- component ahb_slv generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f80#; sepclk : integer := 0; dqsize : integer := 64; dmsize : integer := 8; tech : integer := virtex2); port ( rst : in std_ulogic; hclk : in std_ulogic; clk0 : in std_ulogic; csi : in ahb_ctrl_in_type; cso : out ahb_ctrl_out_type); end component; component ddr_in generic ( tech : integer); port ( Q1 : out std_ulogic; Q2 : out std_ulogic; C1 : in std_ulogic; C2 : in std_ulogic; CE : in std_ulogic; -- DQS : in std_logic; -- used for lattice -- DDRCLKPOL: in std_logic; -- used for lattice D : in std_ulogic; R : in std_ulogic; S : in std_ulogic); end component; component ddr_out generic ( tech : integer); port ( Q : out std_ulogic; C1 : in std_ulogic; C2 : in std_ulogic; CE : in std_ulogic; D1 : in std_ulogic; D2 : in std_ulogic; R : in std_ulogic; S : in std_ulogic); end component; component hs generic( tech : in integer; dqsize : in integer; dmsize : in integer; strobesize: in integer; clkperiod : in integer); port ( rst : in std_ulogic; clk0 : in std_ulogic; clk90 : in std_ulogic; clk180 : in std_ulogic; clk270 : in std_ulogic; hclk : in std_ulogic; hssi : in hs_in_type; hsso : out hs_out_type); end component; end ddrrec;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gaisler/misc/gptimer.in.vhd

6

487

-- Modular timer constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; constant CFG_GPT_SW : integer := CONFIG_GPT_SW; constant CFG_GPT_TW : integer := CONFIG_GPT_TW; constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/hynix/ddr2/components.vhd

2

1857

---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2007 GAISLER RESEARCH -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- See the file COPYING for the full details of the license. -- ----------------------------------------------------------------------------- -- Package: components -- File: components.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: Component declaration of Hynix RAM ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.HY5PS121621F_PACK.all; package components is component HY5PS121621F generic ( TimingCheckFlag : boolean := TRUE; PUSCheckFlag : boolean := FALSE; Part_Number : PART_NUM_TYPE := B400); Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z'); LDQS : inout std_logic := 'Z'; LDQSB : inout std_logic := 'Z'; UDQS : inout std_logic := 'Z'; UDQSB : inout std_logic := 'Z'; LDM : in std_logic; WEB : in std_logic; CASB : in std_logic; RASB : in std_logic; CSB : in std_logic; BA : in std_logic_vector(1 downto 0); ADDR : in std_logic_vector(12 downto 0); CKE : in std_logic; CLK : in std_logic; CLKB : in std_logic; UDM : in std_logic ); End component; end; -- pragma translate_on

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/grlib/sparc/cpu_disas.vhd

2

4248

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: cpu_disas -- File: cpu_disas.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: SPARC disassembler according to SPARC V8 manual ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; use grlib.sparc.all; use grlib.sparc_disas.all; entity cpu_disas is port ( clk : in std_ulogic; rstn : in std_ulogic; dummy : out std_ulogic; inst : in std_logic_vector(31 downto 0); pc : in std_logic_vector(31 downto 2); result: in std_logic_vector(31 downto 0); index : in std_logic_vector(3 downto 0); wreg : in std_ulogic; annul : in std_ulogic; holdn : in std_ulogic; pv : in std_ulogic; trap : in std_ulogic; disas : in std_ulogic); end; architecture behav of cpu_disas is begin dummy <= '1'; trc : process(clk) variable valid : boolean; variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable fpins, fpld : boolean; variable iindex : integer; begin iindex := conv_integer(index); op := inst(31 downto 30); op3 := inst(24 downto 19); fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2)); fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR)); valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0'))); valid := valid and (holdn = '1'); if rising_edge(clk) and (rstn = '1') then print_insn (iindex, pc(31 downto 2) & "00", inst, result, valid, trap = '1', wreg = '1', false); end if; end process; end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; use grlib.sparc.all; use grlib.sparc_disas.all; entity fpu_disas is port ( clk : in std_ulogic; rstn : in std_ulogic; dummy : out std_ulogic; wr2inst : in std_logic_vector(31 downto 0); wr2pc : in std_logic_vector(31 downto 2); divinst : in std_logic_vector(31 downto 0); divpc : in std_logic_vector(31 downto 2); dbg_wrdata: in std_logic_vector(63 downto 0); index : in std_logic_vector(3 downto 0); dbg_wren : in std_logic_vector(1 downto 0); resv : in std_ulogic; ld : in std_ulogic; rdwr : in std_ulogic; ccwr : in std_ulogic; rdd : in std_ulogic; div_valid : in std_ulogic; holdn : in std_ulogic; disas : in std_ulogic); end; architecture behav of fpu_disas is begin dummy <= '1'; trc : process(clk) variable valid : boolean; variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable fpins, fpld : boolean; variable iindex : integer; begin iindex := conv_integer(index); if rising_edge(clk) and (rstn = '1') then valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1'); print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata, (rdd = '1'), valid, false, (dbg_wren /= "00")); print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata, (rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00")); end if; end process; end; -- pragma translate_on

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gaisler/pci/pcidma.vhd

2

3814

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: pci_dma -- File: pci_dma.vhd -- Author: Jiri Gaisler - Gaisler Research -- Modified: Alf Vaerneus - Gaisler Research -- Description: PCI master and target interface with DMA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.pci.all; use gaisler.pcilib.all; entity pcidma is generic ( memtech : integer := DEFMEMTECH; dmstndx : integer := 0; dapbndx : integer := 0; dapbaddr : integer := 0; dapbmask : integer := 16#fff#; blength : integer := 16; mstndx : integer := 0; abits : integer := 21; dmaabits : integer := 26; fifodepth : integer := 3; -- FIFO depth device_id : integer := 0; -- PCI device ID vendor_id : integer := 0; -- PCI vendor ID slvndx : integer := 0; apbndx : integer := 0; apbaddr : integer := 0; apbmask : integer := 16#fff#; haddr : integer := 16#F00#; hmask : integer := 16#F00#; ioaddr : integer := 16#000#; nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks oepol : integer := 0; endian : integer := 0; -- 0 little, 1 big class_code: integer := 16#0B4000#; rev : integer := 0; irq : integer := 0; scanen : integer := 0 ); port( rst : in std_logic; clk : in std_logic; pciclk : in std_logic; pcii : in pci_in_type; pcio : out pci_out_type; dapbo : out apb_slv_out_type; dahbmo : out ahb_mst_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ahbmi : in ahb_mst_in_type; ahbmo : out ahb_mst_out_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of pcidma is signal ahbsi2 : ahb_slv_in_type; signal ahbso2 : ahb_slv_out_type; begin dma : dmactrl generic map (hindex => dmstndx, slvindex => slvndx, pindex => dapbndx, paddr => dapbaddr, blength => blength) port map (rst, clk, apbi, dapbo, ahbmi, dahbmo, ahbsi, ahbso, ahbsi2, ahbso2); pci : pci_mtf generic map (memtech => memtech, hmstndx => mstndx, dmamst => dmstndx, fifodepth => fifodepth, device_id => device_id, vendor_id => vendor_id, hslvndx => slvndx, pindex => apbndx, paddr => apbaddr, irq => irq, haddr => haddr, hmask => hmask, ioaddr => ioaddr, abits => abits, dmaabits => dmaabits, nsync => nsync, oepol => oepol, endian => endian, class_code => class_code, rev => rev, scanen => scanen) port map (rst, clk, pciclk, pcii, pcio, apbi, apbo, ahbmi, ahbmo, ahbsi2, ahbso2); end;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/hynix/ddr2/HY5PS121621F_PACK.vhd

3

17071

------------------------------------------------------ -- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM -- -- -- -- Packages for HY5PS121621F.vhd -- -- -- -- HHHH HHHH -- -- HHHH HHHH -- -- ,O0O. ,O0 .HH ,O0 .HH -- -- (O000O)(000 )H(000 )H Hynix -- -- `O0O' `O0 'HH `O0 'HH -- -- HHHH HHHH Semiconductor -- -- HHHH HHHH -- ------------------------------------------------------ --------------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; library grlib; use grlib.stdlib.all; --USE IEEE.STD_LOGIC_ARITH.all; --USE IEEE.STD_LOGIC_UNSIGNED.all; --------------------------------------------------------------------------------------------------- package HY5PS121621F_PACK is --------------------------------------------------------------------------------------------------- constant NUM_OF_MROPCODE : integer := 13; constant NUM_OF_ROW_ADD : integer := 13; constant NUM_OF_COL_ADD : integer := 10; constant NUM_OF_BANK_ADD : integer := 2; constant WORD_SIZE : integer := 16; constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD; constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD; constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD; constant NUM_OF_BUFFERS : integer := 3; type PART_NUM_TYPE is (B400, B533, B667, B800); type PART_NUM is array (B400 to B800) of time; constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns); constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns); constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns); constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns); constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns); constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns); constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns); constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns); constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns); constant tRRD : time := 10 ns; constant tREF : time := 64 ms; constant tRFC : time := 75 ns; constant tRTP : time := 7.5 ns; constant tXSNR : time := tRFC + 10 ns; constant tXP : integer := 2; constant tCKE : integer := 3; constant tXARD : integer := 2; constant tXARDS : integer := 2; constant tXSRD : integer := 200; constant tPUS : time := 200 us; type STATE_TYPE is ( PWRDN, PWRUP, SLFREF, IDLE, RACT, READ, WRITE); type COMMAND_TYPE is ( DSEL, NOP, MRS, EMRS1, EMRS2, EMRS3, ACT, RD, RDAP, WR, WRAP, PCG, PCGA, AREF, SREF, SREX, PDEN, PDEX, ERROR, ILLEGAL); type BURST_MODE_TYPE is ( SEQUENTIAL, INTERLEAVE); type OCD_DRIVE_MODE_TYPE is ( CAL_EXIT, DRIVE1, DRIVE0, ADJUST, CAL_DEFAULT); subtype CL_TYPE is integer range 0 to 6; subtype BL_TYPE is integer range 4 to 8; subtype TWR_TYPE is integer range 2 to 6; type DLL_RST is ( RST, NORST); type MODE_REGISTER is record CAS_LATENCY : CL_TYPE; BURST_MODE : BURST_MODE_TYPE; BURST_LENGTH : BL_TYPE; DLL_STATE : DLL_RST; SAPD : std_logic; TWR : TWR_TYPE; end record; type EMR_TYPE is record DLL_EN : std_logic; AL : CL_TYPE; QOFF : std_logic; DQSB_ENB : std_logic; RDQS_EN : std_logic; OCD_PGM : OCD_DRIVE_MODE_TYPE; end record; type EMR2_TYPE is record SREF_HOT : std_logic; end record; type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time; type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0); type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0); subtype COL_DATA_TYPE is integer range 0 to 65535; type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE; type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE; type RAM_PNTR is ACCESS ROW_DATA_TYPE; type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE; type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR; subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0); type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE; type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0); type CKE_TYPE is array (integer range -1 to 0) of std_logic; subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0); procedure COMMAND_DECODE ( variable CSB, RASB, CASB, WEB, A10 : in std_logic; variable Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0); variable CKE : in CKE_TYPE; variable COMMAND : out COMMAND_TYPE; variable BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0); variable State : in STATE_TYPE); procedure MODE_REGISTER_SET ( MROPCODE : in MROPCODE_TYPE; MR : out MODE_REGISTER); procedure EXT_MODE_REGISTER_SET ( MROPCODE : in MROPCODE_TYPE; EMR : out EMR_TYPE); procedure EXT_MODE_REGISTER_SET2 ( MROPCODE : in MROPCODE_TYPE; EMR : out EMR2_TYPE); function REMAINDER ( val0 : in integer; val1 : in integer) return integer; function XOR_FUNC ( val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector; function CHAR_TO_STD_LOGIC ( c : in character) return std_logic; function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT; end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package --------------------------------------------------------------------------------------------------- package body HY5PS121621F_PACK is --------------------------------------------------------------------------------------------------- procedure COMMAND_DECODE ( variable CSB, RASB, CASB, WEB, A10 : in std_logic; variable Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0); variable CKE : in CKE_TYPE; variable COMMAND : out COMMAND_TYPE; variable BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0); variable State : in STATE_TYPE) Is begin case CKE (-1) is when '1' => case CKE (0) is when '0' => if (BankState = "0000") then if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then COMMAND := SREF; elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then COMMAND := PDEN; else COMMAND := ILLEGAL; end if; elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then COMMAND := PDEN; else COMMAND := ILLEGAL; end if; when '1' => if (CSB = '1') then COMMAND := DSEL; elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then COMMAND := NOP; elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then if (A10 = '0') then COMMAND := RD; else COMMAND := RDAP; end if; elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then if (A10 = '0') then COMMAND := WR; else COMMAND := WRAP; end if; elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then COMMAND := ACT; elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then if (A10 = '0') then COMMAND := PCG; else COMMAND := PCGA; end if; elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then COMMAND := AREF; elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then if (BankState = "0000") then if (Bank_Add = "00") then COMMAND := MRS; elsif (Bank_Add = "01") then COMMAND := EMRS1; elsif (Bank_Add = "10") then COMMAND := EMRS2; elsif (Bank_Add = "11") then COMMAND := EMRS3; end if; else COMMAND := ILLEGAL; end if; end if; when others => COMMAND := ERROR; end case; when '0' => case CKE (0) is when '0' => COMMAND := NOP; when '1' => if (State = PWRUP) then COMMAND := NOP; elsif (CSB = '1') then if (State = SLFREF) then COMMAND := SREX; elsif (State = PWRDN) then COMMAND := PDEX; end if; elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then if (State = SLFREF) then COMMAND := SREX; elsif (State = PWRDN) then COMMAND := PDEX; end if; else COMMAND := ERROR; end if; when others => COMMAND := ERROR; end case; when others => COMMAND := ERROR; end case; end COMMAND_DECODE; ------------------------------------------------------------------------------------------------ procedure MODE_REGISTER_SET ( MROPCODE : in MROPCODE_TYPE; MR : out MODE_REGISTER) is begin if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then MR.CAS_LATENCY := 2; elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then MR.CAS_LATENCY := 3; elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then MR.CAS_LATENCY := 4; elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then MR.CAS_LATENCY := 5; elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then MR.CAS_LATENCY := 6; else assert false report "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!" severity WARNING; end if; if MROPCODE(3) = '0' then MR.BURST_MODE := SEQUENTIAL; elsif MROPCODE(3) = '1' then MR.BURST_MODE := INTERLEAVE; end if; if MROPCODE(8) = '0' then MR.DLL_STATE := NORST; elsif MROPCODE(8) = '1' then MR.DLL_STATE := RST; end if; if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then MR.BURST_LENGTH := 4; elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then MR.BURST_LENGTH := 8; else assert false report "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!" severity ERROR; end if; if MROPCODE(12) = '0' then MR.SAPD := '0'; elsif MROPCODE(12) = '1' then MR.SAPD := '1'; end if; if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then MR.TWR := 2; elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then MR.TWR := 3; elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then MR.TWR := 4; elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then MR.TWR := 5; elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then MR.TWR := 6; else assert false report "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!" severity ERROR; end if; end MODE_REGISTER_SET; ------------------------------------------------------------------------------------------------ procedure EXT_MODE_REGISTER_SET ( MROPCODE : in MROPCODE_TYPE; EMR : out EMR_TYPE) is begin if (MROPCODE(0) = '0') then EMR.DLL_EN := '1'; elsif (MROPCODE(0) = '1') then EMR.DLL_EN := '0'; end if; if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then EMR.AL := 0; elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then EMR.AL := 1; elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then EMR.AL := 2; elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then EMR.AL := 3; elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then EMR.AL := 4; elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then EMR.AL := 5; else assert false report "ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!" severity WARNING; end if; if MROPCODE(12) = '0' then EMR.QOFF := '0'; elsif MROPCODE(12) = '1' then EMR.QOFF := '1'; end if; if MROPCODE(10) = '0' then EMR.DQSB_ENB := '0'; elsif MROPCODE(10) = '1' then EMR.DQSB_ENB := '1'; end if; if MROPCODE(11) = '0' then EMR.RDQS_EN := '0'; elsif MROPCODE(11) = '1' then EMR.RDQS_EN := '1'; end if; if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then EMR.OCD_PGM := CAL_EXIT; elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then EMR.OCD_PGM := DRIVE1; elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then EMR.OCD_PGM := DRIVE0; elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then EMR.OCD_PGM := ADJUST; elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then EMR.OCD_PGM := CAL_DEFAULT; else assert false report "ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!" severity ERROR; end if; end EXT_MODE_REGISTER_SET; ------------------------------------------------------------------------------------------------ procedure EXT_MODE_REGISTER_SET2 ( MROPCODE : in MROPCODE_TYPE; EMR : out EMR2_TYPE) is begin if (MROPCODE(7) = '0') then EMR.SREF_HOT := '0'; elsif (MROPCODE(7) = '1') then EMR.SREF_HOT := '1'; end if; end EXT_MODE_REGISTER_SET2; ------------------------------------------------------------------------------------------------ function REMAINDER (val0 : in integer; val1 : in integer) return integer is variable Result : integer; begin Result := val0; loop exit when Result < val1; Result := Result - val1; end loop; return Result; end REMAINDER; ------------------------------------------------------------------------------------------------ function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is variable Result : std_logic_vector(2 downto 0); variable j : integer := 0; begin for i in val0'RANGE LOOP if (val0(i) /= val1(i)) then Result(i) := '1'; else Result(i) := '0'; end if; j := j + 1; end loop; return Result((j - 1) downto 0); end XOR_FUNC; ------------------------------------------------------------------------------------------------ function CHAR_TO_STD_LOGIC ( c : in character) return std_logic is variable r : std_logic; begin case c is when '0' => r := '0'; when 'L' => r := 'L'; when '1' => r := '1'; when 'H' => r := 'H'; when 'W' => r := 'W'; when 'Z' => r := 'Z'; when 'U' => r := 'U'; when '-' => r := '-'; when others => r := 'X'; end case; return r; end CHAR_TO_STD_LOGIC; ------------------------------------------------------------------------------------------------ function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is variable Result: BIT; begin case V is when '0' | 'L' => Result := '0'; when '1' | 'H' => Result := '1'; when 'X' | 'W' | 'Z' | 'U' | '-' => Result := '0'; end case; return Result; end STD_LOGIC_TO_BIT; ------------------------------------------------------------------------------------------------ end HY5PS121621F_PACK;

mit

lxp32/lxp32-cpu

rtl/lxp32c_top.vhd

1

3182

--------------------------------------------------------------------- -- LXP32C CPU top-level module (C-series, with instruction cache) -- -- Part of the LXP32 CPU -- -- Copyright (c) 2016 by Alex I. Kuznetsov -- -- This version uses Wishbone B3 interface for the instruction bus -- (IBUS). It is designed for high-latency program memory, such as -- external SDRAM chips. -- -- Parameters: -- DBUS_RMW: Use RMW cycle instead of SEL_O() signal -- for byte-granular access to data bus -- DIVIDER_EN: enable divider -- IBUS_BURST_SIZE: size of the burst -- IBUS_PREFETCH_SIZE: initiate read burst if number of words -- left in the buffer is less than specified -- MUL_ARCH: multiplier architecture ("dsp", "opt" -- or "seq") -- START_ADDR: address in program memory where execution -- starts --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity lxp32c_top is generic( DBUS_RMW: boolean:=false; DIVIDER_EN: boolean:=true; IBUS_BURST_SIZE: integer:=16; IBUS_PREFETCH_SIZE: integer:=32; MUL_ARCH: string:="dsp"; START_ADDR: std_logic_vector(31 downto 0):=(others=>'0') ); port( clk_i: in std_logic; rst_i: in std_logic; ibus_cyc_o: out std_logic; ibus_stb_o: out std_logic; ibus_cti_o: out std_logic_vector(2 downto 0); ibus_bte_o: out std_logic_vector(1 downto 0); ibus_ack_i: in std_logic; ibus_adr_o: out std_logic_vector(29 downto 0); ibus_dat_i: in std_logic_vector(31 downto 0); dbus_cyc_o: out std_logic; dbus_stb_o: out std_logic; dbus_we_o: out std_logic; dbus_sel_o: out std_logic_vector(3 downto 0); dbus_ack_i: in std_logic; dbus_adr_o: out std_logic_vector(31 downto 2); dbus_dat_o: out std_logic_vector(31 downto 0); dbus_dat_i: in std_logic_vector(31 downto 0); irq_i: in std_logic_vector(7 downto 0) ); end entity; architecture rtl of lxp32c_top is signal lli_re: std_logic; signal lli_adr: std_logic_vector(29 downto 0); signal lli_dat: std_logic_vector(31 downto 0); signal lli_busy: std_logic; begin cpu_inst: entity work.lxp32_cpu(rtl) generic map( DBUS_RMW=>DBUS_RMW, DIVIDER_EN=>DIVIDER_EN, MUL_ARCH=>MUL_ARCH, START_ADDR=>START_ADDR ) port map( clk_i=>clk_i, rst_i=>rst_i, lli_re_o=>lli_re, lli_adr_o=>lli_adr, lli_dat_i=>lli_dat, lli_busy_i=>lli_busy, dbus_cyc_o=>dbus_cyc_o, dbus_stb_o=>dbus_stb_o, dbus_we_o=>dbus_we_o, dbus_sel_o=>dbus_sel_o, dbus_ack_i=>dbus_ack_i, dbus_adr_o=>dbus_adr_o, dbus_dat_o=>dbus_dat_o, dbus_dat_i=>dbus_dat_i, irq_i=>irq_i ); icache_inst: entity work.lxp32_icache(rtl) generic map( BURST_SIZE=>IBUS_BURST_SIZE, PREFETCH_SIZE=>IBUS_PREFETCH_SIZE ) port map( clk_i=>clk_i, rst_i=>rst_i, lli_re_i=>lli_re, lli_adr_i=>lli_adr, lli_dat_o=>lli_dat, lli_busy_o=>lli_busy, wbm_cyc_o=>ibus_cyc_o, wbm_stb_o=>ibus_stb_o, wbm_cti_o=>ibus_cti_o, wbm_bte_o=>ibus_bte_o, wbm_ack_i=>ibus_ack_i, wbm_adr_o=>ibus_adr_o, wbm_dat_i=>ibus_dat_i ); end architecture;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gaisler/misc/svgactrl.vhd

2

21077

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: Vga Controller -- File: vga_controller.vhd -- Author: Hans Soderlund -- Description: Vga Controller main file ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.misc.all; entity svgactrl is generic( length : integer := 384; -- Fifo-length part : integer := 128; -- Fifo-part lenght memtech : integer := DEFMEMTECH; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; hindex : integer := 0; hirq : integer := 0; clk0 : integer := 40000; clk1 : integer := 20000; clk2 : integer := 15385; clk3 : integer := 0; burstlen : integer range 2 to 8 := 8 ); port ( rst : in std_logic; clk : in std_logic; vgaclk : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; vgao : out apbvga_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; clk_sel : out std_logic_vector(1 downto 0) ); end ; architecture rtl of svgactrl is constant REVISION : amba_version_type := 0; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0), 1 => apb_iobar(paddr, pmask)); type RegisterType is array (1 to 5) of std_logic_vector(31 downto 0); type state_type is (running, not_running, reset); type read_type is record read_pointer : integer range 0 to length ; read_pointer_out : integer range 0 to length ; sync : std_logic_vector(2 downto 0); data_out : std_logic_vector(23 downto 0); lock : std_logic; index : std_logic_vector(1 downto 0); mem_index : integer; read_pointer_clut : std_logic_vector(7 downto 0); hcounter : std_logic_vector(15 downto 0); vcounter : std_logic_vector(15 downto 0); fifo_ren : std_logic; fifo_en : std_logic; hsync : std_logic ; vsync : std_logic ; csync : std_logic ; blank : std_logic ; hsync2 : std_logic ; vsync2 : std_logic ; csync2 : std_logic ; blank2 : std_logic ; end record; type control_type is record int_reg : RegisterType; state : state_type; enable : std_logic; reset : std_logic; sync_c : std_logic_vector(2 downto 0); sync_w : std_logic_vector(2 downto 0); write_pointer_clut : std_logic_vector(7 downto 0); datain_clut : std_logic_vector(23 downto 0); write_en_clut : std_logic; adress : std_logic_vector(31 downto 0); start : std_logic; write_pointer : integer range 0 to length; ram_address : integer range 0 to length; data : std_logic_vector(31 downto 0); level : integer range 0 to part + 1; status : integer range 0 to 3; hpolarity : std_ulogic; vpolarity : std_ulogic; func : std_logic_vector(1 downto 0); clk_sel : std_logic_vector(1 downto 0); end record; type sync_regs is record s1 : std_logic_vector(2 downto 0); s2 : std_logic_vector(2 downto 0); s3 : std_logic_vector(2 downto 0); end record; signal t,tin : read_type; signal r,rin : control_type; signal sync_w : sync_regs; signal sync_ra : sync_regs; signal sync_rb : sync_regs; signal sync_c : sync_regs; signal read_status : std_logic_vector(2 downto 0); signal write_status : std_logic_vector(2 downto 0); signal write_en : std_logic; signal res_mod :std_logic; signal en_mod : std_logic; signal fifo_en : std_logic; signal dmai : ahb_dma_in_type; signal dmao : ahb_dma_out_type; signal equal : std_logic; signal hmax : std_logic_vector(15 downto 0); signal hfporch : std_logic_vector(15 downto 0); signal hsyncpulse : std_logic_vector(15 downto 0); signal hvideo : std_logic_vector(15 downto 0); signal vmax : std_logic_vector(15 downto 0); signal vfporch : std_logic_vector(15 downto 0); signal vsyncpulse : std_logic_vector(15 downto 0); signal vvideo : std_logic_vector(15 downto 0); signal write_pointer_clut : std_logic_vector(7 downto 0); signal read_pointer_clut : std_logic_vector(7 downto 0); signal read_pointer_fifo : std_logic_vector(9 downto 0); signal write_pointer_fifo : std_logic_vector(9 downto 0); signal datain_clut : std_logic_vector(23 downto 0); signal dataout_clut : std_logic_vector(23 downto 0); signal dataout_fifo : std_logic_vector(31 downto 0); signal datain_fifo : std_logic_vector(31 downto 0); signal write_en_clut, read_en_clut : std_logic; signal vcc : std_logic; signal read_en_fifo, write_en_fifo : std_logic; begin vcc <= '1'; ram0 : syncram_2p generic map (tech => memtech, abits => 10, dbits => 32, sepclk => 1) port map (vgaclk, read_en_fifo, read_pointer_fifo, dataout_fifo,clk, write_en_fifo, write_pointer_fifo, datain_fifo); clutram : syncram_2p generic map (tech => memtech, abits => 8, dbits => 24, sepclk => 1) port map (vgaclk, read_en_clut, read_pointer_clut, dataout_clut, clk, write_en_clut, write_pointer_clut,datain_clut); ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER, GAISLER_SVGACTRL, 0, 3, 1) port map (rst, clk, dmai, dmao, ahbi, ahbo); apbo.pirq <= (others => '0'); apbo.pindex <= pindex; apbo.pconfig <= pconfig; control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod, sync_w) variable v: control_type; variable rdata : std_logic_vector(31 downto 0); variable mem_sel : integer; variable apbwrite : std_logic; variable we_fifo : std_logic; begin v := r; v.write_en_clut := '0'; rdata := (others =>'0'); mem_sel := conv_integer(apbi.paddr(5 downto 2)); we_fifo := '0'; -- Control part. This part handles the apb-accesses and stores the internal registers ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable; case apbi.paddr(5 downto 2) is when "0000" => if apbwrite = '1' then v.enable := apbi.pwdata(0); v.reset := apbi.pwdata(1); v.hpolarity := apbi.pwdata(8); v.vpolarity := apbi.pwdata(9); v.func := apbi.pwdata(5 downto 4); v.clk_sel := apbi.pwdata(7 downto 6); end if; rdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel & r.func & fifo_en & '0' & r.reset & r.enable; when "1010" => if apbwrite = '1' then v.datain_clut := apbi.pwdata(23 downto 0); v.write_pointer_clut := apbi.pwdata(31 downto 24); v.write_en_clut := '1'; end if; when "0001" => if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if; rdata := r.int_reg(1); when "0010" => if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if; rdata := r.int_reg(2); when "0011" => if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if; rdata := r.int_reg(3); when "0100" => if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if; rdata := r.int_reg(4); when "0101" => if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if; rdata := r.int_reg(5); when "0110" => rdata := conv_std_logic_vector(clk0,32); when "0111" => rdata := conv_std_logic_vector(clk1,32); when "1000" => rdata := conv_std_logic_vector(clk2,32); when "1001" => rdata := conv_std_logic_vector(clk3,32); when others => end case; ------------------------------------------ ----------- Control state machine -------- case r.state is when running => if r.enable = '0' then v.sync_c := "011"; v.state := not_running; end if; when not_running => if r.enable = '1' then v.sync_c := "001"; v.state := reset; end if; when reset => if sync_c.s3 = "001" then v.sync_c := "010"; v.state := running; end if; end case; ----------------------------------------- ----------- Control reset part----------- if r.reset = '1' or rst = '0' then v.state := not_running; v.enable := '0'; v.int_reg := (others => (others => '0')); v.sync_c := "011"; v.reset := '0'; v.clk_sel := "00"; end if; ------------------------------------------------------------------------------ -- Write part. This part reads from the memory framebuffer and places the data -- in the designated fifo specified from the generic. ------------------------------------------------------------------------------- v.start := '0'; if write_en = '0' then if (r.start or not dmao.active) = '1' then v.start := '1'; end if; if dmao.ready = '1' then ------------ AHB access part ----------- ---------- and Fifo write part --------- v.data := dmao.rdata(31 downto 0); v.ram_address := v.write_pointer; v.write_pointer := v.write_pointer +1; we_fifo := '1'; if v.write_pointer = length then v.write_pointer := 0; end if; v.level := v.level +1; if dmao.haddr = (9 downto 0 => '0') then v.adress := (v.adress(31 downto 10) + 1) & dmao.haddr; else v.adress := v.adress(31 downto 10) & dmao.haddr; end if; if (dmao.haddr(burstlen+1 downto 0) = ((burstlen+1 downto 2 => '1') & "00")) then v.start := '0'; end if; end if; ---------------------------------------- v.sync_w := v.sync_w and read_status; ------------ Fifo sync part ------------ if v.level >= (part -1) then if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part then v.level := 0; if r.status = 0 then v.sync_w(2) := '1'; else v.sync_w(r.status -1) := '1'; end if; v.status := v.status + 1; if v.status = 3 then v.status := 0; end if; else v.start := '0'; end if; end if; end if; ------------------------------------------ ------------ Write reset part ------------ if res_mod = '0' or write_en = '1' then if dmao.active = '0' then v.adress := r.int_reg(5); end if; v.start := '0'; v.sync_w := "000"; v.status := 1; v.ram_address := 0; v.write_pointer := 0; v.level := 0; end if; ------------------------------------------ if (r.start and dmao.active and not dmao.ready) = '1' then v.start := '1'; end if; -- Assertions rin <= v; sync_c.s1 <= v.sync_c; sync_w.s1 <= r.sync_w; res_mod <= sync_c.s3(1); en_mod <= sync_c.s3(0); write_status <= sync_w.s3; hvideo <= r.int_reg(1)(15 downto 0); vvideo <= r.int_reg(1)(31 downto 16); hfporch <= r.int_reg(2)(15 downto 0); vfporch <= r.int_reg(2)(31 downto 16); hsyncpulse <= r.int_reg(3)(15 downto 0); vsyncpulse <= r.int_reg(3)(31 downto 16); hmax <= r.int_reg(4)(15 downto 0); vmax <= r.int_reg(4)(31 downto 16); apbo.prdata <= rdata; dmai.wdata <= (others => '0'); dmai.burst <= '1'; dmai.irq <= '0'; dmai.size <= "10"; dmai.write <= '0'; dmai.busy <= '0'; dmai.start <= r.start and r.enable; dmai.address <= r.adress; write_pointer_fifo <= conv_std_logic_vector(v.ram_address,10); write_pointer_clut <= r.write_pointer_clut; datain_fifo <= v.data; datain_clut <= r.datain_clut; write_en_clut <= r.write_en_clut; clk_sel <= r.clk_sel; write_en_fifo <= we_fifo; end process; read_proc : process(t,res_mod,en_mod,write_status,dataout_fifo,sync_rb,dataout_clut, vmax, hmax, hvideo, hfporch, hsyncpulse, vvideo, vfporch, vsyncpulse, sync_ra, r) variable v : read_type; variable inc_pointer : std_logic; begin v := t; v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync; v.blank2 := t.blank; -- Syncsignals generation functions. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- if en_mod = '0' then -- vertical counter if (t.vcounter = vmax ) and (t.hcounter = hmax ) then v.vcounter := (others => '0'); elsif t.hcounter = hmax then v.vcounter := t.vcounter +1; end if; -- horizontal counter if t.hcounter < hmax then v.hcounter := t.hcounter +1; else v.hcounter := (others => '0'); end if; -- generate hsync if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch -1)) then v.hsync := r.hpolarity; else v.hsync := not r.hpolarity; end if; -- generate vsync if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then v.vsync := r.vpolarity; else v.vsync := not r.vpolarity; end if; --generate csync & blank signal v.csync := not (v.hsync xor v.vsync); v.blank := not t.fifo_ren; --generate fifo_ren -signal if (t.hcounter = (hmax -1) and t.vcounter = vmax) or (t.hcounter = (hmax -1 ) and t.vcounter < vvideo) then v.fifo_ren := '0'; elsif t.hcounter = (hvideo -1) and t.vcounter <= vvideo then v.fifo_ren := '1'; end if; --generate fifo_en -signal if t.vcounter = vmax then v.fifo_en := '0'; elsif t.vcounter = vvideo and t.hcounter = (hvideo -1) then v.fifo_en := '1'; end if; end if; if r.func /= "01" then -- do not delay strobes when not using CLUT v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync; v.blank2 := v.blank; end if; -- Sync reset part --------- if res_mod = '0' then v.hcounter := hmax; v.vcounter := vmax - 1; v.hsync := r.hpolarity; v.vsync := r.vpolarity; v.blank := '0'; v.fifo_ren := '1'; v.fifo_en := '1'; end if; -- Read from fifo. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- inc_pointer := '0'; if t.fifo_en = '0' then ------------ Fifo sync part ------------ if (v.read_pointer_out = 0 or v.read_pointer_out = part or v.read_pointer_out = (part + part)) and t.fifo_ren = '0' and v.index = "00" then case t.sync is when "111" | "011" => if write_status(0) = '1' then v.sync := "110"; v.lock := '0'; else v.lock := '1'; end if; when "110" => if write_status(1) = '1' then v.sync := "101"; v.lock := '0'; else v.lock := '1'; end if; when "101" => if write_status(2) = '1' then v.sync := "011"; v.lock := '0'; else v.lock := '1'; end if; when others => null; end case; end if; ------------------------------------------ ------------ Fifo read part ------------- ------------ and CLUT access ------------- if t.fifo_ren = '0' and v.lock = '0' then case r.func is when "01" => if t.index = "00" then v.read_pointer_clut := dataout_fifo(31 downto 24); v.index := "01"; elsif t.index = "01" then v.read_pointer_clut := dataout_fifo(23 downto 16); v.index := "10"; elsif t.index = "10" then v.read_pointer_clut := dataout_fifo(15 downto 8); v.index := "11"; else v.read_pointer_clut := dataout_fifo(7 downto 0); v.index := "00"; inc_pointer := '1'; end if; v.data_out := dataout_clut; when "10" => if t.index = "00" then v.data_out := dataout_fifo(31 downto 27) & "000" & dataout_fifo(26 downto 21) & "00" & dataout_fifo(20 downto 16) & "000"; v.index := "01"; else v.data_out := dataout_fifo(15 downto 11) & "000" & dataout_fifo(10 downto 5) & "00" & dataout_fifo(4 downto 0) & "000"; v.index := "00"; inc_pointer := '1'; end if; when "11" => v.data_out := dataout_fifo(23 downto 0); v.index := "00"; inc_pointer := '1'; when others => v.data_out := (23 downto 0 => '1'); v.index := "00"; inc_pointer := '1'; end case; else v.data_out := (others => '0'); end if; if inc_pointer = '1' then v.read_pointer_out := t.read_pointer; v.read_pointer := t.read_pointer + 1; if v.read_pointer = length then v.read_pointer := 0; end if; if v.read_pointer_out = length then v.read_pointer_out := 0; end if; end if; else v.data_out := (others => '0'); end if; ------------------------------------------ ------------ Fifo read reset part ------- if res_mod = '0' or t.fifo_en = '1' then v.sync := "111"; v.read_pointer_out := 0; v.read_pointer := 1; v.data_out := (others => '0'); v.lock := '1'; v.index := "00"; v.read_pointer_clut := (others => '0'); end if; ------------------------------------------ tin <= v; sync_ra.s1 <= t.sync; sync_rb.s1 <= t.fifo_en & "00"; read_status <= sync_ra.s3; write_en <= sync_rb.s3(2); fifo_en <= t.fifo_en; read_pointer_clut <= v.read_pointer_clut; read_pointer_fifo <= conv_std_logic_vector(v.read_pointer_out,10); read_en_fifo <= not v.fifo_ren; read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0); vgao.video_out_r <= t.data_out(23 downto 16); vgao.video_out_g <= t.data_out(15 downto 8); vgao.video_out_b <= t.data_out(7 downto 0); vgao.hsync <= t.hsync2; vgao.vsync <= t.vsync2; vgao.comp_sync <= t.csync2; vgao.blank <= t.blank2; end process; proc_clk : process(clk) begin if rising_edge(clk) then r <= rin; -- Control sync_ra.s2 <= sync_ra.s1; -- Write sync_ra.s3 <= sync_ra.s2; -- Write sync_rb.s2 <= sync_rb.s1; -- Write sync_rb.s3 <= sync_rb.s2; -- Write end if; end process; proc_vgaclk : process(vgaclk) begin if rising_edge(vgaclk) then t <= tin; -- Read sync_c.s2 <= sync_c.s1; -- Control sync_c.s3 <= sync_c.s2; -- Control sync_w.s2 <= sync_w.s1; -- Read sync_w.s3 <= sync_w.s2; -- Read end if; end process; end ;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gleichmann/ahb2hpi/ahb2hpi.vhd

2

14317

------------------------------------------------------------------------------- -- Title : AHB2HPI bus bridge -- Project : LEON3MINI ------------------------------------------------------------------------------- -- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $ ------------------------------------------------------------------------------- -- Author : Thomas Ameseder -- Company : Gleichmann Electronics -- Created : 2005-08-19 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: -- -- This module implements an AHB slave that communicates with a -- Host Peripheral Interface (HPI) device such as the CY7C67300 USB controller. -- Supports Big Endian and Little Endian. -- -- Restrictions: Do not use a data width other than 16 at the moment. ------------------------------------------------------------------------------- -- Copyright (c) 2005 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; entity ahb2hpi is generic ( counter_width : integer := 4; data_width : integer := 16; address_width : integer := 2; hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff# ); port ( -- AHB port HCLK : in std_ulogic; HRESETn : in std_ulogic; ahbso : out ahb_slv_out_type; ahbsi : in ahb_slv_in_type; -- HPI port ADDR : out std_logic_vector(address_width-1 downto 0); DATA : inout std_logic_vector(data_width-1 downto 0); nCS : out std_ulogic; nWR : out std_ulogic; nRD : out std_ulogic; INT : in std_ulogic; -- debug port dbg_equal : out std_ulogic ); end ahb2hpi; architecture rtl of ahb2hpi is constant CONFIGURATION_VERSION : integer := 0; constant VERSION : integer := 0; constant INTERRUPT_NUMBER : integer := 5; -- register file address is the base address plus the -- ahb memory space reserved for the device itself -- its size is 64 bytes as defined with 16#fff# for its -- mask below constant REGFILE_ADDRESS : integer := 16#340#; -- big endian/little endian architecture selection constant BIG_ENDIAN : boolean := true; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_HPI, CONFIGURATION_VERSION, VERSION, INTERRUPT_NUMBER), 4 => ahb_iobar(haddr, hmask), 5 => ahb_iobar(REGFILE_ADDRESS, 16#fff#), others => (others => '0')); type reg_type is record hwrite : std_ulogic; hready : std_ulogic; hsel : std_ulogic; addr : std_logic_vector(address_width-1 downto 0); counter : unsigned(counter_width-1 downto 0); Din : std_logic_vector(data_width-1 downto 0); Dout : std_logic_vector(data_width-1 downto 0); nWR, nRD, nCS : std_ulogic; INT : std_ulogic; ctrlreg : std_logic_vector(data_width-1 downto 0); data_acquisition : std_ulogic; end record; -- combinatorial, registered and -- double-registered signals signal c, r, rr : reg_type; -- signals for probing input and output data signal in_data_probe, out_data_probe : std_logic_vector(data_width-1 downto 0); signal equality_probe : std_ulogic; -- signal data_acquisition : std_ulogic; -- keep registers for debug purposes attribute syn_preserve: boolean; attribute syn_preserve of in_data_probe, out_data_probe, equality_probe : signal is true; begin comb : process (INT, DATA, HRESETn, ahbsi, r, rr) variable v : reg_type; -- register fields variable tAtoCSlow : unsigned(1 downto 0); -- address to chip select (CS) low variable tCStoCTRLlow : unsigned(1 downto 0); -- CS low to control (read/write) low variable tCTRLlowDvalid : unsigned(1 downto 0); -- control (read) low to data valid variable tCTRLlow : unsigned(1 downto 0); -- control low to control high variable tCTRLhighCShigh : unsigned(1 downto 0); -- control high to CS high variable tCShighREC : unsigned(1 downto 0); -- CS high to next CS recovery variable tCNT : unsigned(counter_width-1 downto 0); -- timing counter begin -- assign values from the register in the beginning -- lateron, assign new values by looking at the new -- inputs from the bus v := r; -- data_acquisition <= '0'; if HRESETn = '0' then v.hwrite := '0'; v.hready := '1'; v.hsel := '0'; v.addr := (others => '-'); v.counter := conv_unsigned(0, counter_width); v.Din := (others => '-'); v.Dout := (others => '-'); v.nWR := '1'; v.nRD := '1'; v.nCS := '1'; v.INT := '0'; -- bit 12 is reserved for the interrupt v.ctrlreg(15 downto 13) := (others => '0'); v.ctrlreg(11 downto 0) := (others => '0'); -- v.data_acquisition := '0'; end if; -- assert data_acquisition for not longer than one cycle v.data_acquisition := '0'; -- bit 12 of control register holds registered interrupt v.ctrlreg(12) := INT; v.INT := INT; -- assign register fields to signals tAtoCSlow := (unsigned(r.ctrlreg(11 downto 10))); tCStoCTRLlow := (unsigned(r.ctrlreg(9 downto 8))); tCTRLlowDvalid := (unsigned(r.ctrlreg(7 downto 6))); tCTRLlow := (unsigned(r.ctrlreg(5 downto 4))); tCTRLhighCShigh := (unsigned(r.ctrlreg(3 downto 2))); tCShighREC := (unsigned(r.ctrlreg(1 downto 0))); tCNT := conv_unsigned(conv_unsigned(0, counter_width) + tAtoCSlow + tCStoCTRLlow + tCTRLlow + tCTRLhighCShigh + tCShighREC + '1', counter_width); -- is bus free to use? if ahbsi.hready = '1' then -- gets selected when HSEL signal for the right slave -- is asserted and the transfer type is SEQ or NONSEQ v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1); else v.hsel := '0'; end if; -- a valid cycle starts, so all relevant bus signals -- are registered and the timer is started if v.hsel = '1' and v.counter = conv_unsigned(0, counter_width) then v.hwrite := ahbsi.hwrite and v.hsel; v.hready := '0'; v.counter := conv_unsigned(tCNT, counter_width); v.nWR := '1'; --not v.hwrite; v.nRD := '1'; --v.hwrite; v.nCS := '1'; if (conv_integer(ahbsi.haddr(19 downto 8)) = REGFILE_ADDRESS) then if ahbsi.haddr(7 downto 0) = X"00" then -- disable HPI signals, read/write register data -- and manage AHB handshake if v.hwrite = '1' then -- take data from AHB write data bus but skip interrupt bit if BIG_ENDIAN then -- v.ctrlreg := ahbsi.hwdata(31 downto 31-data_width+1); v.ctrlreg(15 downto 13) := ahbsi.hwdata(31 downto 29); v.ctrlreg(11 downto 0) := ahbsi.hwdata(27 downto 16); else -- v.ctrlreg := ahbsi.hwdata(31-data_width downto 0); v.ctrlreg(15 downto 13) := ahbsi.hwdata(15 downto 13); v.ctrlreg(11 downto 0) := ahbsi.hwdata(11 downto 0); end if; else v.Din := v.ctrlreg; end if; end if; -- go to last cycle which signals ahb ready v.counter := conv_unsigned(0, counter_width); --(tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC); else -- the LSB of 16-bit AHB addresses is always zero, -- so the address is shifted in order to be able -- to access data with a short* in C v.addr := ahbsi.haddr(address_width downto 1); -- v.size := ahbsi.hsize(1 downto 0); -- fetch input data according to the AMBA specification -- for big/little endian architectures -- only relevant for 16-bit accesses if v.addr(0) = '0' then if BIG_ENDIAN then v.Dout := ahbsi.hwdata(31 downto 31-data_width+1); else v.Dout := ahbsi.hwdata(31-data_width downto 0); end if; else if BIG_ENDIAN then v.Dout := ahbsi.hwdata(31-data_width downto 0); else v.Dout := ahbsi.hwdata(31 downto 31-data_width+1); end if; end if; end if; end if; -- check if counter has just been re-initialized; if so, -- decrement it until it reaches zero and set control signals -- accordingly if v.counter > conv_unsigned(0, counter_width) then if v.counter = (tCNT - tAtoCSlow) then v.nCS := '0'; end if; if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow) then v.nWR := not v.hwrite; v.nRD := v.hwrite; end if; if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlowDvalid) then if v.nRD = '0' then v.Din := DATA; v.data_acquisition := '1'; -- in_data_probe <= DATA; end if; end if; if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow) then v.nWR := '1'; v.nRD := '1'; end if; if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh) then v.nCS := '1'; end if; if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC) then v.hready := '1'; end if; -- note: since the counter is queried and immediately -- decremented afterwards, the value in hardware -- is one lower than given in the if statement v.counter := v.counter - 1; else v.hready := '1'; end if; -- assign variable to a signal c <= v; -- HPI outputs ADDR <= r.addr; nCS <= r.nCS; nWR <= r.nWR; nRD <= r.nRD; -- three-state buffer: drive bus during a write cycle -- and hold data for one more clock cycle, then -- shut off from the bus if ((r.nCS = '0' and r.nWR = '0') or (rr.nCS = '0' and r.nWR = '0') or (r.nCS = '0' and rr.nWR = '0') or (rr.nCS = '0' and rr.nWR = '0')) then DATA <= r.Dout; else DATA <= (others => 'Z'); end if; -- output data is assigned to the both the high and the -- low word of the 32-bit data bus ahbso.hrdata(31 downto 31-data_width+1) <= r.Din; ahbso.hrdata(31-data_width downto 0) <= r.Din; --(others => '-'); -- if v.addr(0) = '0' then -- if BIG_ENDIAN then -- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din; -- ahbso.hrdata(31-data_width downto 0) <= (others => '-'); -- else -- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-'); -- ahbso.hrdata(31-data_width downto 0) <= r.Din; -- end if; -- else -- if BIG_ENDIAN then -- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-'); -- ahbso.hrdata(31-data_width downto 0) <= r.Din; -- else -- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din; -- ahbso.hrdata(31-data_width downto 0) <= (others => '-'); -- end if; -- end if; ahbso.hready <= r.hready; ahbso.hirq <= (INTERRUPT_NUMBER => r.ctrlreg(12), others => '0'); -- propagate registered interrupt -- ahbso.hirq <= (others => '0'); -- ahbso.hirq(INTERRUPT_NUMBER) <= r.ctrlreg(12); end process comb; -- constant AHB outputs ahbso.hresp <= "00"; -- answer OK by default ahbso.hsplit <= (others => '0'); -- no SPLIT transactions ahbso.hcache <= '0'; -- cacheable yes/no ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; reg : process (HCLK) begin if rising_edge(HCLK) then r <= c; rr <= r; end if; end process; --------------------------------------------------------------------------------------- -- DEBUG SECTION for triggering on read/write inconsistency -- use a C program that writes data AND reads it immediately afterwards -- dbg_equal start with being '0' after reset, then goes high during the transaction -- it should not have a falling edge during the transactions -- -> trigger on that event -- note regarding HPI data transactions: -- the address is written first before writing/reading at address B"10" -- the data register is at address B"00" --------------------------------------------------------------------------------------- -- read at the rising edge of the read signal -- (before the next read data is received) -- data_acquisition <= '1' when rr.nrd = '1' and r.nrd = '0' else -- '0'; -- read data to compare to in_data_probe <= r.din; check_data : process (HCLK, HRESETn) begin if HRESETn = '0' then out_data_probe <= (others => '0'); equality_probe <= '0'; elsif rising_edge(HCLK) then -- is data being written to the *data* register? if r.nwr = '0' and r.ncs = '0' and r.addr = "00" then out_data_probe <= r.dout; end if; if r.data_acquisition = '1' then if in_data_probe = out_data_probe then equality_probe <= '1'; else equality_probe <= '0'; end if; end if; end if; end process; dbg_equal <= equality_probe; -- pragma translate_off bootmsg : report_version generic map ("ahb2hpi" & tost(hindex) & ": AHB-to-HPI Bridge, irq " & tost(INTERRUPT_NUMBER)); -- pragma translate_on end rtl;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/cypress/ssram/package_utility.vhd

6

2040

--**************************************************************** --** MODEL : package_utility ** --** COMPANY : Cypress Semiconductor ** --** REVISION: 1.0 Created new package utility model ** --** ** --**************************************************************** Library ieee,work; Use ieee.std_logic_1164.all; -- Use IEEE.Std_Logic_Arith.all; use ieee.numeric_std.all; -- Use IEEE.std_logic_TextIO.all; --- Use work.package_timing.all; Library Std; Use STD.TextIO.all; Package package_utility is FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; End; -- package package_utility Package body package_utility is ------------------------------------------------------------------------------------------------ --Converts string into std_logic_vector ------------------------------------------------------------------------------------------------ FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); BEGIN FOR i IN S'RANGE LOOP IF S(i) = '0' THEN result(i) := '0'; ELSIF S(i) = '1' THEN result(i) := '1'; ELSIF S(i) = 'X' THEN result(i) := 'X'; ELSE result(i) := 'Z'; END IF; END LOOP; RETURN result; END convert_string; ------------------------------------------------------------------------------------------------ --Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------ FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS VARIABLE result : INTEGER := 0; BEGIN FOR i IN S'RANGE LOOP IF S(i) = '1' THEN result := result + (2**i); ELSIF S(i) = '0' THEN result := result; ELSE result := 0; END IF; END LOOP; RETURN result; END CONV_INTEGER1; end package_utility;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/micron/ddr/mt46v16m16.vhd

2

60967

----------------------------------------------------------------------------------------- -- -- File Name: MT46V16M16.VHD -- Version: 3.1 -- Date: January 14th, 2002 -- Model: Behavioral -- Simulator: NCDesktop - http://www.cadence.com -- ModelSim PE - http://www.model.com -- -- Dependencies: None -- -- Email: modelsupport@micron.com -- Company: Micron Technology, Inc. -- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) -- -- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) -- -- Limitation: Doesn't model internal refresh counter -- -- Note: -- -- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY -- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY -- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR -- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. -- -- Copyright (c) 1998 Micron Semiconductor Products, Inc. -- All rights researved -- -- Rev Author Date Changes -- --- ---------------------------- ---------- ------------------------------------- -- 2.1 SH 01/14/2002 - Fix Burst_counter -- Micron Technology, Inc. -- -- 2.0 SH 11/08/2001 - Second release -- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE -- 3.1 Craig Hanson cahanson 05/28/2003 - update all models to release version 3.1 -- @micron.com (no changes to this model) ----------------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; LIBRARY WORK; USE WORK.MTI_PKG.ALL; use std.textio.all; library grlib; use grlib.stdlib.all; library gaisler; use gaisler.sim.all; ENTITY MT46V16M16 IS GENERIC ( -- Timing for -75Z CL2 tCK : TIME := 7.500 ns; tCH : TIME := 3.375 ns; -- 0.45*tCK tCL : TIME := 3.375 ns; -- 0.45*tCK tDH : TIME := 0.500 ns; tDS : TIME := 0.500 ns; tIH : TIME := 0.900 ns; tIS : TIME := 0.900 ns; tMRD : TIME := 15.000 ns; tRAS : TIME := 40.000 ns; tRAP : TIME := 20.000 ns; tRC : TIME := 65.000 ns; tRFC : TIME := 75.000 ns; tRCD : TIME := 20.000 ns; tRP : TIME := 20.000 ns; tRRD : TIME := 15.000 ns; tWR : TIME := 15.000 ns; addr_bits : INTEGER := 13; data_bits : INTEGER := 16; cols_bits : INTEGER := 9; index : INTEGER := 0; fname : string := "sdram.srec"; -- File to read from bbits : INTEGER := 16 ); PORT ( Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); Clk : IN STD_LOGIC; Clk_n : IN STD_LOGIC; Cke : IN STD_LOGIC; Cs_n : IN STD_LOGIC; Ras_n : IN STD_LOGIC; Cas_n : IN STD_LOGIC; We_n : IN STD_LOGIC; Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ); END MT46V16M16; ARCHITECTURE behave OF MT46V16M16 IS -- Array for Read pipeline TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); -- Array for Write pipeline TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); -- Array for Auto Precharge TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; -- Array for Manual Precharge TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; -- Array for Burst Terminate TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; -- Array for Memory Access TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); TYPE Array_ram_pntr IS ACCESS Array_ram_type; TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; -- Data pair SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); -- Mode Register SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); -- Command Decode Variables SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; -- Burst Length Decode Variables SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; -- Cas Latency Decode Variables SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; -- Internal Control Signals SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; -- System Clock SIGNAL Sys_clk : STD_LOGIC := '0'; -- Dqs buffer SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; BEGIN -- Strip the strength Cs_in <= To_X01 (Cs_n); Ras_in <= To_X01 (Ras_n); Cas_in <= To_X01 (Cas_n); We_in <= To_X01 (We_n); -- Commands Decode Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); -- Burst Length Decode Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); -- CAS Latency Decode Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); -- Dqs buffer Dqs <= Dqs_out; -- -- System Clock -- int_clk : PROCESS (Clk, Clk_n) VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; begin IF Clk = '1' AND Clk_n = '0' THEN ClkZ := '1'; CkeZ := Cke; ELSIF Clk = '0' AND Clk_n = '1' THEN ClkZ := '0'; END IF; Sys_clk <= CkeZ AND ClkZ; END PROCESS; -- -- Main Process -- state_register : PROCESS -- Precharge Variables VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; -- Activate Variables VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; -- Data IO variables VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; -- Internal address mux variables VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); -- DLL Reset variables VARIABLE DLL_enable : STD_LOGIC := '0'; VARIABLE DLL_reset : STD_LOGIC := '0'; VARIABLE DLL_done : STD_LOGIC := '0'; VARIABLE DLL_count : INTEGER := 0; -- Timing Check VARIABLE MRD_chk : TIME := 0 ns; VARIABLE RFC_chk : TIME := 0 ns; VARIABLE RRD_chk : TIME := 0 ns; VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; -- Read pipeline variables VARIABLE Read_cmnd : Array_Read_cmnd; VARIABLE Read_bank : Array_Read_bank; VARIABLE Read_cols : Array_Read_cols; -- Write pipeline variables VARIABLE Write_cmnd : Array_Write_cmnd; VARIABLE Write_bank : Array_Write_bank; VARIABLE Write_cols : Array_Write_cols; -- Auto Precharge variables VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); -- Manual Precharge variables VARIABLE A10_precharge : Array_A10_precharge; VARIABLE Bank_precharge : Array_Bank_precharge; VARIABLE Cmnd_precharge : Array_Cmnd_precharge; -- Burst Terminate variable VARIABLE Cmnd_bst : Array_Cmnd_bst; -- Memory Banks VARIABLE Bank0 : Array_ram_stor; VARIABLE Bank1 : Array_ram_stor; VARIABLE Bank2 : Array_ram_stor; VARIABLE Bank3 : Array_ram_stor; -- Burst Counter VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); -- Internal Dqs initialize VARIABLE Dqs_int : STD_LOGIC := '0'; -- Data buffer for DM Mask VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); -- Load and Dumb variables FILE file_load : TEXT open read_mode is fname; -- Data load FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump VARIABLE Bank_Load : std_logic_vector ( 1 DOWNTO 0); VARIABLE rows_load : std_logic_vector (12 DOWNTO 0); VARIABLE cols_load : std_logic_vector ( 8 DOWNTO 0); VARIABLE data_load : std_logic_vector (15 DOWNTO 0); VARIABLE i, j : INTEGER; VARIABLE good_load : BOOLEAN; VARIABLE l : LINE; variable file_loaded : boolean := false; variable dump : std_logic := '0'; variable ch : character; variable rectype : std_logic_vector(3 downto 0); variable recaddr : std_logic_vector(31 downto 0); variable reclen : std_logic_vector(7 downto 0); variable recdata : std_logic_vector(0 to 16*8-1); -- -- Initialize empty rows -- PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS VARIABLE i, j : INTEGER := 0; BEGIN IF Bank = "00" THEN IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros FOR j IN (data_bits - 1) DOWNTO 0 LOOP Bank0 (Row_index) (i) (j) := '0'; END LOOP; END LOOP; END IF; ELSIF Bank = "01" THEN IF Bank1 (Row_index) = NULL THEN Bank1 (Row_index) := NEW Array_ram_type; FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP FOR j IN (data_bits - 1) DOWNTO 0 LOOP Bank1 (Row_index) (i) (j) := '0'; END LOOP; END LOOP; END IF; ELSIF Bank = "10" THEN IF Bank2 (Row_index) = NULL THEN Bank2 (Row_index) := NEW Array_ram_type; FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP FOR j IN (data_bits - 1) DOWNTO 0 LOOP Bank2 (Row_index) (i) (j) := '0'; END LOOP; END LOOP; END IF; ELSIF Bank = "11" THEN IF Bank3 (Row_index) = NULL THEN Bank3 (Row_index) := NEW Array_ram_type; FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP FOR j IN (data_bits - 1) DOWNTO 0 LOOP Bank3 (Row_index) (i) (j) := '0'; END LOOP; END LOOP; END IF; END IF; END; -- -- Burst Counter -- PROCEDURE Burst_decode IS VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN -- Advance burst counter Burst_counter := Burst_counter + 1; -- Burst Type IF Mode_reg (3) = '0' THEN Cols_temp := Cols_addr + 1; ELSIF Mode_reg (3) = '1' THEN Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); END IF; -- Burst Length IF Burst_length_2 = '1' THEN Cols_addr (0) := Cols_temp (0); ELSIF Burst_length_4 = '1' THEN Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); ELSIF Burst_length_8 = '1' THEN Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); ELSE Cols_addr := Cols_temp; END IF; -- Data counter IF Burst_length_2 = '1' THEN IF conv_integer(Burst_counter) >= 2 THEN IF Data_in_enable = '1' THEN Data_in_enable := '0'; ELSIF Data_out_enable = '1' THEN Data_out_enable := '0'; END IF; END IF; ELSIF Burst_length_4 = '1' THEN IF conv_integer(Burst_counter) >= 4 THEN IF Data_in_enable = '1' THEN Data_in_enable := '0'; ELSIF Data_out_enable = '1' THEN Data_out_enable := '0'; END IF; END IF; ELSIF Burst_length_8 = '1' THEN IF conv_integer(Burst_counter) >= 8 THEN IF Data_in_enable = '1' THEN Data_in_enable := '0'; ELSIF Data_out_enable = '1' THEN Data_out_enable := '0'; END IF; END IF; END IF; END; BEGIN WAIT ON Sys_clk; -- -- Manual Precharge Pipeline -- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN -- A10 Precharge Pipeline A10_precharge(0) := A10_precharge(1); A10_precharge(1) := A10_precharge(2); A10_precharge(2) := A10_precharge(3); A10_precharge(3) := A10_precharge(4); A10_precharge(4) := A10_precharge(5); A10_precharge(5) := A10_precharge(6); A10_precharge(6) := A10_precharge(7); A10_precharge(7) := A10_precharge(8); A10_precharge(8) := '0'; -- Bank Precharge Pipeline Bank_precharge(0) := Bank_precharge(1); Bank_precharge(1) := Bank_precharge(2); Bank_precharge(2) := Bank_precharge(3); Bank_precharge(3) := Bank_precharge(4); Bank_precharge(4) := Bank_precharge(5); Bank_precharge(5) := Bank_precharge(6); Bank_precharge(6) := Bank_precharge(7); Bank_precharge(7) := Bank_precharge(8); Bank_precharge(8) := "00"; -- Command Precharge Pipeline Cmnd_precharge(0) := Cmnd_precharge(1); Cmnd_precharge(1) := Cmnd_precharge(2); Cmnd_precharge(2) := Cmnd_precharge(3); Cmnd_precharge(3) := Cmnd_precharge(4); Cmnd_precharge(4) := Cmnd_precharge(5); Cmnd_precharge(5) := Cmnd_precharge(6); Cmnd_precharge(6) := Cmnd_precharge(7); Cmnd_precharge(7) := Cmnd_precharge(8); Cmnd_precharge(8) := '0'; -- Terminate Read if same bank or all banks IF ((Cmnd_precharge (0) = '1') AND (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND (Data_out_enable = '1')) THEN Data_out_enable := '0'; END IF; END IF; -- -- Burst Terminate Pipeline -- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN -- Burst Terminate pipeline Cmnd_bst (0) := Cmnd_bst (1); Cmnd_bst (1) := Cmnd_bst (2); Cmnd_bst (2) := Cmnd_bst (3); Cmnd_bst (3) := Cmnd_bst (4); Cmnd_bst (4) := Cmnd_bst (5); Cmnd_bst (5) := Cmnd_bst (6); Cmnd_bst (6) := Cmnd_bst (7); Cmnd_bst (7) := Cmnd_bst (8); Cmnd_bst (8) := '0'; -- Terminate current Read IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN Data_out_enable := '0'; END IF; END IF; -- -- Dq and Dqs Drivers -- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN -- Read Command Pipeline Read_cmnd (0) := Read_cmnd (1); Read_cmnd (1) := Read_cmnd (2); Read_cmnd (2) := Read_cmnd (3); Read_cmnd (3) := Read_cmnd (4); Read_cmnd (4) := Read_cmnd (5); Read_cmnd (5) := Read_cmnd (6); Read_cmnd (6) := Read_cmnd (7); Read_cmnd (7) := Read_cmnd (8); Read_cmnd (8) := '0'; -- Read Bank Pipeline Read_bank (0) := Read_bank (1); Read_bank (1) := Read_bank (2); Read_bank (2) := Read_bank (3); Read_bank (3) := Read_bank (4); Read_bank (4) := Read_bank (5); Read_bank (5) := Read_bank (6); Read_bank (6) := Read_bank (7); Read_bank (7) := Read_bank (8); Read_bank (8) := "00"; -- Read Column Pipeline Read_cols (0) := Read_cols (1); Read_cols (1) := Read_cols (2); Read_cols (2) := Read_cols (3); Read_cols (3) := Read_cols (4); Read_cols (4) := Read_cols (5); Read_cols (5) := Read_cols (6); Read_cols (6) := Read_cols (7); Read_cols (7) := Read_cols (8); Read_cols (8) := (OTHERS => '0'); -- Initialize Read command IF Read_cmnd (0) = '1' THEN Data_out_enable := '1'; Bank_addr := Read_bank (0); Cols_addr := Read_cols (0); Cols_brst := Cols_addr (2 DOWNTO 0); Burst_counter := (OTHERS => '0'); -- Row address mux CASE Bank_addr IS WHEN "00" => Rows_addr := B0_row_addr; WHEN "01" => Rows_addr := B1_row_addr; WHEN "10" => Rows_addr := B2_row_addr; WHEN OTHERS => Rows_addr := B3_row_addr; END CASE; END IF; -- Toggle Dqs during Read command IF Data_out_enable = '1' THEN Dqs_int := '0'; IF Dqs_out = "00" THEN Dqs_out <= "11"; ELSIF Dqs_out = "11" THEN Dqs_out <= "00"; ELSE Dqs_out <= "00"; END IF; ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN Dqs_out <= "ZZ"; END IF; -- Initialize Dqs for Read command IF Read_cmnd (2) = '1' THEN IF Data_out_enable = '0' THEN Dqs_int := '1'; Dqs_out <= "00"; END IF; END IF; -- Read Latch IF Data_out_enable = '1' THEN -- Initialize Memory Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); -- Output Data CASE Bank_addr IS WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); END CASE; -- Increase Burst Counter Burst_decode; ELSE Dq <= (OTHERS => 'Z'); END IF; END IF; -- -- Write FIFO and DM Mask Logic -- IF Sys_clk'EVENT AND Sys_clk = '1' THEN -- Write command pipeline Write_cmnd (0) := Write_cmnd (1); Write_cmnd (1) := Write_cmnd (2); Write_cmnd (2) := '0'; -- Write command pipeline Write_bank (0) := Write_bank (1); Write_bank (1) := Write_bank (2); Write_bank (2) := "00"; -- Write column pipeline Write_cols (0) := Write_cols (1); Write_cols (1) := Write_cols (2); Write_cols (2) := (OTHERS => '0'); -- Initialize Write command IF Write_cmnd (0) = '1' THEN Data_in_enable := '1'; Bank_addr := Write_bank (0); Cols_addr := Write_cols (0); Cols_brst := Cols_addr (2 DOWNTO 0); Burst_counter := (OTHERS => '0'); -- Row address mux CASE Bank_addr IS WHEN "00" => Rows_addr := B0_row_addr; WHEN "01" => Rows_addr := B1_row_addr; WHEN "10" => Rows_addr := B2_row_addr; WHEN OTHERS => Rows_addr := B3_row_addr; END CASE; END IF; -- Write data IF Data_in_enable = '1' THEN -- Initialize memory Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); -- Write first data IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN -- Data Buffer CASE Bank_addr IS WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); END CASE; -- Perform DM Mask IF Dm_pair (0) = '0' THEN Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); END IF; IF Dm_pair (1) = '0' THEN Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); END IF; -- Write Data CASE Bank_addr IS WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; END CASE; END IF; -- Increase Burst Counter Burst_decode; -- Write second data IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN -- Data Buffer CASE Bank_addr IS WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); END CASE; -- Perform DM Mask IF Dm_pair (2) = '0' THEN Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); END IF; IF Dm_pair (3) = '0' THEN Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); END IF; -- Write Data CASE Bank_addr IS WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; END CASE; END IF; -- Increase Burst Counter Burst_decode; -- tWR start and tWTR check IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN CASE Bank_addr IS WHEN "00" => WR_chk0 := NOW; WHEN "01" => WR_chk1 := NOW; WHEN "10" => WR_chk2 := NOW; WHEN OTHERS => WR_chk3 := NOW; END CASE; -- tWTR check ASSERT (Read_enable = '0') REPORT "tWTR violation during Read" SEVERITY WARNING; END IF; END IF; END IF; -- -- Auto Precharge Calculation -- IF Sys_clk'EVENT AND Sys_clk = '1' THEN -- Precharge counter IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN Count_precharge (0) := Count_precharge (0) + 1; END IF; IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN Count_precharge (1) := Count_precharge (1) + 1; END IF; IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN Count_precharge (2) := Count_precharge (2) + 1; END IF; IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN Count_precharge (3) := Count_precharge (3) + 1; END IF; -- Read with AutoPrecharge Calculation -- The device start internal precharge when: -- 1. Meet tRAS requirement -- 2. BL/2 cycles after command IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN Pc_b0 := '1'; Act_b0 := '0'; RP_chk0 := NOW; Read_precharge(0) := '0'; END IF; END IF; IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN Pc_b1 := '1'; Act_b1 := '0'; RP_chk1 := NOW; Read_precharge(1) := '0'; END IF; END IF; IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN Pc_b2 := '1'; Act_b2 := '0'; RP_chk2 := NOW; Read_precharge(2) := '0'; END IF; END IF; IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN Pc_b3 := '1'; Act_b3 := '0'; RP_chk3 := NOW; Read_precharge(3) := '0'; END IF; END IF; -- Write with AutoPrecharge Calculation -- The device start internal precharge when: -- 1. Meet tRAS requirement -- 2. Two clock after last burst -- Since tWR is time base, the model will compensate tRP IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN Pc_b0 := '1'; Act_b0 := '0'; RP_chk0 := NOW - ((2 * tCK) - tWR); Write_precharge(0) := '0'; END IF; END IF; IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN Pc_b1 := '1'; Act_b1 := '0'; RP_chk1 := NOW - ((2 * tCK) - tWR); Write_precharge(1) := '0'; END IF; END IF; IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN Pc_b2 := '1'; Act_b2 := '0'; RP_chk2 := NOW - ((2 * tCK) - tWR); Write_precharge(2) := '0'; END IF; END IF; IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN Pc_b3 := '1'; Act_b3 := '0'; RP_chk3 := NOW - ((2 * tCK) - tWR); Write_precharge(3) := '0'; END IF; END IF; END IF; -- -- DLL Counter -- IF Sys_clk'EVENT AND Sys_clk = '1' THEN IF (DLL_Reset = '1' AND DLL_done = '0') THEN DLL_count := DLL_count + 1; IF (DLL_count >= 200) THEN DLL_done := '1'; END IF; END IF; END IF; -- -- Control Logic -- IF Sys_clk'EVENT AND Sys_clk = '1' THEN -- Auto Refresh IF Aref_enable = '1' THEN -- Auto Refresh to Auto Refresh ASSERT (NOW - RFC_chk >= tRFC) REPORT "tRFC violation during Auto Refresh" SEVERITY WARNING; -- Precharge to Auto Refresh ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) REPORT "tRP violation during Auto Refresh" SEVERITY WARNING; -- Precharge to Auto Refresh ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') REPORT "All banks must be Precharge before Auto Refresh" SEVERITY WARNING; -- Record current tRFC time RFC_chk := NOW; END IF; -- Extended Load Mode Register IF Ext_mode_enable = '1' THEN IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN IF (Addr (0) = '0') THEN DLL_enable := '1'; ELSE DLL_enable := '0'; END IF; END IF; -- Precharge to EMR ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') REPORT "All bank must be Precharged before Extended Mode Register" SEVERITY WARNING; -- Precharge to EMR ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) REPORT "tRP violation during Extended Load Register" SEVERITY WARNING; -- LMR/EMR to EMR ASSERT (NOW - MRD_chk >= tMRD) REPORT "tMRD violation during Extended Mode Register" SEVERITY WARNING; -- Record current tMRD time MRD_chk := NOW; END IF; -- Load Mode Register IF Mode_reg_enable = '1' THEN -- Register mode Mode_reg <= Addr; -- DLL Reset IF (DLL_enable = '1' AND Addr (8) = '1') THEN DLL_reset := '1'; DLL_done := '0'; DLL_count := 0; ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN ASSERT (FALSE) REPORT "DLL is ENABLE: DLL RESET is require" SEVERITY WARNING; ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN ASSERT (FALSE) REPORT "DLL is DISABLE: DLL RESET will be ignored" SEVERITY WARNING; END IF; -- Precharge to LMR ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') REPORT "All bank must be Precharged before Load Mode Register" SEVERITY WARNING; -- Precharge to EMR ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) REPORT "tRP violation during Load Mode Register" SEVERITY WARNING; -- LMR/ELMR to LMR ASSERT (NOW - MRD_chk >= tMRD) REPORT "tMRD violation during Load Mode Register" SEVERITY WARNING; -- Check for invalid Burst Length ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 (Addr (2 DOWNTO 0) = "011")) -- BL = 8 REPORT "Invalid Burst Length during Load Mode Register" SEVERITY WARNING; -- Check for invalid CAS Latency ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 REPORT "Invalid CAS Latency during Load Mode Register" SEVERITY WARNING; -- Record current tMRD time MRD_chk := NOW; END IF; -- Active Block (latch Bank and Row Address) IF Active_enable = '1' THEN -- Activate an OPEN bank can corrupt data ASSERT ((Ba = "00" AND Act_b0 = '0') OR (Ba = "01" AND Act_b1 = '0') OR (Ba = "10" AND Act_b2 = '0') OR (Ba = "11" AND Act_b3 = '0')) REPORT "Bank is already activated - data can be corrupted" SEVERITY WARNING; -- Activate Bank 0 IF Ba = "00" AND Pc_b0 = '1' THEN -- Activate to Activate (same bank) ASSERT (NOW - RC_chk0 >= tRC) REPORT "tRC violation during Activate Bank 0" SEVERITY WARNING; -- Precharge to Active ASSERT (NOW - RP_chk0 >= tRP) REPORT "tRP violation during Activate Bank 0" SEVERITY WARNING; -- Record Variables for checking violation Act_b0 := '1'; Pc_b0 := '0'; B0_row_addr := Addr; RC_chk0 := NOW; RCD_chk0 := NOW; RAS_chk0 := NOW; RAP_chk0 := NOW; END IF; -- Activate Bank 1 IF Ba = "01" AND Pc_b1 = '1' THEN -- Activate to Activate (same bank) ASSERT (NOW - RC_chk1 >= tRC) REPORT "tRC violation during Activate Bank 1" SEVERITY WARNING; -- Precharge to Active ASSERT (NOW - RP_chk1 >= tRP) REPORT "tRP violation during Activate Bank 1" SEVERITY WARNING; -- Record Variables for checking violation Act_b1 := '1'; Pc_b1 := '0'; B1_row_addr := Addr; RC_chk1 := NOW; RCD_chk1 := NOW; RAS_chk1 := NOW; RAP_chk1 := NOW; END IF; -- Activate Bank 2 IF Ba = "10" AND Pc_b2 = '1' THEN -- Activate to Activate (same bank) ASSERT (NOW - RC_chk2 >= tRC) REPORT "tRC violation during Activate Bank 2" SEVERITY WARNING; -- Precharge to Active ASSERT (NOW - RP_chk2 >= tRP) REPORT "tRP violation during Activate Bank 2" SEVERITY WARNING; -- Record Variables for checking violation Act_b2 := '1'; Pc_b2 := '0'; B2_row_addr := Addr; RC_chk2 := NOW; RCD_chk2 := NOW; RAS_chk2 := NOW; RAP_chk2 := NOW; END IF; -- Activate Bank 3 IF Ba = "11" AND Pc_b3 = '1' THEN -- Activate to Activate (same bank) ASSERT (NOW - RC_chk3 >= tRC) REPORT "tRC violation during Activate Bank 3" SEVERITY WARNING; -- Precharge to Active ASSERT (NOW - RP_chk3 >= tRP) REPORT "tRP violation during Activate Bank 3" SEVERITY WARNING; -- Record Variables for checking violation Act_b3 := '1'; Pc_b3 := '0'; B3_row_addr := Addr; RC_chk3 := NOW; RCD_chk3 := NOW; RAS_chk3 := NOW; RAP_chk3 := NOW; END IF; -- Activate Bank A to Activate Bank B IF (Prev_bank /= Ba) THEN ASSERT (NOW - RRD_chk >= tRRD) REPORT "tRRD violation during Activate" SEVERITY WARNING; END IF; -- AutoRefresh to Activate ASSERT (NOW - RFC_chk >= tRFC) REPORT "tRFC violation during Activate" SEVERITY WARNING; -- Record Variables for Checking Violation RRD_chk := NOW; Prev_bank := Ba; END IF; -- Precharge Block - Consider NOP if bank already precharged or in process of precharging IF Prech_enable = '1' THEN -- EMR or LMR to Precharge ASSERT (NOW - MRD_chk >= tMRD) REPORT "tMRD violation during Precharge" SEVERITY WARNING; -- Precharge Bank 0 IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN Act_b0 := '0'; Pc_b0 := '1'; RP_chk0 := NOW; -- Activate to Precharge bank 0 ASSERT (NOW - RAS_chk0 >= tRAS) REPORT "tRAS violation during Precharge" SEVERITY WARNING; -- tWR violation check for Write ASSERT (NOW - WR_chk0 >= tWR) REPORT "tWR violation during Precharge" SEVERITY WARNING; END IF; -- Precharge Bank 1 IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN Act_b1 := '0'; Pc_b1 := '1'; RP_chk1 := NOW; -- Activate to Precharge ASSERT (NOW - RAS_chk1 >= tRAS) REPORT "tRAS violation during Precharge" SEVERITY WARNING; -- tWR violation check for Write ASSERT (NOW - WR_chk1 >= tWR) REPORT "tWR violation during Precharge" SEVERITY WARNING; END IF; -- Precharge Bank 2 IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN Act_b2 := '0'; Pc_b2 := '1'; RP_chk2 := NOW; -- Activate to Precharge ASSERT (NOW - RAS_chk2 >= tRAS) REPORT "tRAS violation during Precharge" SEVERITY WARNING; -- tWR violation check for Write ASSERT (NOW - WR_chk2 >= tWR) REPORT "tWR violation during Precharge" SEVERITY WARNING; END IF; -- Precharge Bank 3 IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN Act_b3 := '0'; Pc_b3 := '1'; RP_chk3 := NOW; -- Activate to Precharge ASSERT (NOW - RAS_chk3 >= tRAS) REPORT "tRAS violation during Precharge" SEVERITY WARNING; -- tWR violation check for Write ASSERT (NOW - WR_chk3 >= tWR) REPORT "tWR violation during Precharge" SEVERITY WARNING; END IF; -- Pipeline for READ IF CAS_latency_15 = '1' THEN A10_precharge (3) := Addr(10); Bank_precharge (3) := Ba; Cmnd_precharge (3) := '1'; ELSIF CAS_latency_2 = '1' THEN A10_precharge (4) := Addr(10); Bank_precharge (4) := Ba; Cmnd_precharge (4) := '1'; ELSIF CAS_latency_25 = '1' THEN A10_precharge (5) := Addr(10); Bank_precharge (5) := Ba; Cmnd_precharge (5) := '1'; ELSIF CAS_latency_3 = '1' THEN A10_precharge (6) := Addr(10); Bank_precharge (6) := Ba; Cmnd_precharge (6) := '1'; ELSIF CAS_latency_4 = '1' THEN A10_precharge (8) := Addr(10); Bank_precharge (8) := Ba; Cmnd_precharge (8) := '1'; END IF; END IF; -- Burst Terminate IF Burst_term = '1' THEN -- Pipeline for Read IF CAS_latency_15 = '1' THEN Cmnd_bst (3) := '1'; ELSIF CAS_latency_2 = '1' THEN Cmnd_bst (4) := '1'; ELSIF CAS_latency_25 = '1' THEN Cmnd_bst (5) := '1'; ELSIF CAS_latency_3 = '1' THEN Cmnd_bst (6) := '1'; ELSIF CAS_latency_4 = '1' THEN Cmnd_bst (8) := '1'; END IF; -- Terminate Write ASSERT (Data_in_enable = '0') REPORT "It's illegal to Burst Terminate a Write" SEVERITY WARNING; -- Terminate Read with Auto Precharge ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND Read_precharge (2) = '0' AND Read_precharge (3) = '0') REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" SEVERITY WARNING; END IF; -- Read Command IF Read_enable = '1' THEN -- CAS Latency Pipeline IF Cas_latency_15 = '1' THEN Read_cmnd (3) := '1'; Read_bank (3) := Ba; Read_cols (3) := Addr (8 DOWNTO 0); ELSIF Cas_latency_2 = '1' THEN Read_cmnd (4) := '1'; Read_bank (4) := Ba; Read_cols (4) := Addr (8 DOWNTO 0); ELSIF Cas_latency_25 = '1' THEN Read_cmnd (5) := '1'; Read_bank (5) := Ba; Read_cols (5) := Addr (8 DOWNTO 0); ELSIF Cas_latency_3 = '1' THEN Read_cmnd (6) := '1'; Read_bank (6) := Ba; Read_cols (6) := Addr (8 DOWNTO 0); ELSIF Cas_latency_4 = '1' THEN Read_cmnd (8) := '1'; Read_bank (8) := Ba; Read_cols (8) := Addr (8 DOWNTO 0); END IF; -- Write to Read: Terminate Write Immediately IF Data_in_enable = '1' THEN Data_in_enable := '0'; END IF; -- Interrupting a Read with Auto Precharge (same bank only) ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') REPORT "It's illegal to interrupt a Read with Auto Precharge" SEVERITY WARNING; -- Activate to Read ASSERT ((Ba = "00" AND Act_b0 = '1') OR (Ba = "01" AND Act_b1 = '1') OR (Ba = "10" AND Act_b2 = '1') OR (Ba = "11" AND Act_b3 = '1')) REPORT "Bank is not Activated for Read" SEVERITY WARNING; -- Activate to Read without Auto Precharge IF Addr (10) = '0' THEN ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) REPORT "tRCD violation during Read" SEVERITY WARNING; END IF; -- Activate to Read with Auto Precharge IF Addr (10) = '1' THEN ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) REPORT "tRAP violation during Read" SEVERITY WARNING; END IF; -- Auto precharge IF Addr (10) = '1' THEN Read_precharge (Conv_INTEGER(Ba)) := '1'; Count_precharge (Conv_INTEGER(Ba)) := 0; END IF; -- DLL Check IF (DLL_reset = '1') THEN ASSERT (DLL_done = '1') REPORT "DLL RESET not complete" SEVERITY WARNING; END IF; END IF; -- Write Command IF Write_enable = '1' THEN -- Pipeline for Write Write_cmnd (2) := '1'; Write_bank (2) := Ba; Write_cols (2) := Addr (8 DOWNTO 0); -- Interrupting a Write with Auto Precharge (same bank only) ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') REPORT "It's illegal to interrupt a Write with Auto Precharge" SEVERITY WARNING; -- Activate to Write ASSERT ((Ba = "00" AND Act_b0 = '1') OR (Ba = "01" AND Act_b1 = '1') OR (Ba = "10" AND Act_b2 = '1') OR (Ba = "11" AND Act_b3 = '1')) REPORT "Bank is not Activated for Write" SEVERITY WARNING; -- Activate to Write ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) REPORT "tRCD violation during Write" SEVERITY WARNING; -- Auto precharge IF Addr (10) = '1' THEN Write_precharge (Conv_INTEGER(Ba)) := '1'; Count_precharge (Conv_INTEGER(Ba)) := 0; END IF; END IF; END IF; IF not file_loaded THEN --' file_loaded := true; WHILE NOT endfile(file_load) LOOP readline(file_load, l); read(l, ch); if (ch /= 'S') or (ch /= 's') then hexread(l, rectype); hexread(l, reclen); recaddr := (others => '0'); case rectype is when "0001" => hexread(l, recaddr(15 downto 0)); when "0010" => hexread(l, recaddr(23 downto 0)); when "0011" => hexread(l, recaddr); when "0111" => hexread(l, recaddr); -- if (index = 0) then print("Start address : " & tost(recaddr)); end if; next; when others => next; end case; case bbits is when 64 => -- 64-bit bank with four 16-bit DDRs recaddr(31 downto 27) := (others => '0'); hexread(l, recdata); Bank_Load := recaddr(26 downto 25); Rows_Load := recaddr(24 downto 12); Cols_Load := recaddr(11 downto 3); Init_mem (Bank_Load, To_Integer(Rows_Load)); IF Bank_Load = "00" THEN for i in 0 to 1 loop Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); end loop; ELSIF Bank_Load = "01" THEN for i in 0 to 3 loop Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); end loop; ELSIF Bank_Load = "10" THEN for i in 0 to 3 loop Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); end loop; ELSIF Bank_Load = "11" THEN for i in 0 to 3 loop Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); end loop; END IF; when 32 => -- 32-bit bank with two 16-bit DDRs recaddr(31 downto 26) := (others => '0'); hexread(l, recdata); Bank_Load := recaddr(25 downto 24); Rows_Load := recaddr(23 downto 11); Cols_Load := recaddr(10 downto 2); Init_mem (Bank_Load, To_Integer(Rows_Load)); IF Bank_Load = "00" THEN for i in 0 to 3 loop Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); end loop; ELSIF Bank_Load = "01" THEN for i in 0 to 3 loop Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); end loop; ELSIF Bank_Load = "10" THEN for i in 0 to 3 loop Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); end loop; ELSIF Bank_Load = "11" THEN for i in 0 to 3 loop Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); end loop; END IF; when others => -- 16-bit bank with one 16-bit DDR hexread(l, recdata); recaddr(31 downto 25) := (others => '0'); Bank_Load := recaddr(24 downto 23); Rows_Load := recaddr(22 downto 10); Cols_Load := recaddr(9 downto 1); Init_mem (Bank_Load, To_Integer(Rows_Load)); IF Bank_Load = "00" THEN for i in 0 to 3 loop Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); end loop; ELSIF Bank_Load = "01" THEN for i in 0 to 3 loop Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); end loop; ELSIF Bank_Load = "10" THEN for i in 0 to 3 loop Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); end loop; ELSIF Bank_Load = "11" THEN for i in 0 to 3 loop Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); end loop; END IF; END case; END IF; END LOOP; END IF; END PROCESS; -- -- Dqs Receiver -- dqs_rcvrs : PROCESS VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); BEGIN WAIT ON Dqs; -- Latch data at posedge Dqs IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN Dq_temp := Dq; Dm_temp := Dm; END IF; -- Latch data at negedge Dqs IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN Dq_pair <= (Dq & Dq_temp); Dm_pair <= (Dm & Dm_temp); END IF; END PROCESS; -- -- Setup timing checks -- Setup_check : PROCESS BEGIN WAIT ON Sys_clk; IF Sys_clk'EVENT AND Sys_clk = '1' THEN ASSERT(Cke'LAST_EVENT >= tIS) REPORT "CKE Setup time violation -- tIS" SEVERITY WARNING; ASSERT(Cs_n'LAST_EVENT >= tIS) REPORT "CS# Setup time violation -- tIS" SEVERITY WARNING; ASSERT(Cas_n'LAST_EVENT >= tIS) REPORT "CAS# Setup time violation -- tIS" SEVERITY WARNING; ASSERT(Ras_n'LAST_EVENT >= tIS) REPORT "RAS# Setup time violation -- tIS" SEVERITY WARNING; ASSERT(We_n'LAST_EVENT >= tIS) REPORT "WE# Setup time violation -- tIS" SEVERITY WARNING; ASSERT(Addr'LAST_EVENT >= tIS) REPORT "ADDR Setup time violation -- tIS" SEVERITY WARNING; ASSERT(Ba'LAST_EVENT >= tIS) REPORT "BA Setup time violation -- tIS" SEVERITY WARNING; END IF; END PROCESS; -- -- Hold timing checks -- Hold_check : PROCESS BEGIN WAIT ON Sys_clk'DELAYED (tIH); IF Sys_clk'DELAYED (tIH) = '1' THEN ASSERT(Cke'LAST_EVENT >= tIH) REPORT "CKE Hold time violation -- tIH" SEVERITY WARNING; ASSERT(Cs_n'LAST_EVENT >= tIH) REPORT "CS# Hold time violation -- tIH" SEVERITY WARNING; ASSERT(Cas_n'LAST_EVENT >= tIH) REPORT "CAS# Hold time violation -- tIH" SEVERITY WARNING; ASSERT(Ras_n'LAST_EVENT >= tIH) REPORT "RAS# Hold time violation -- tIH" SEVERITY WARNING; ASSERT(We_n'LAST_EVENT >= tIH) REPORT "WE# Hold time violation -- tIH" SEVERITY WARNING; ASSERT(Addr'LAST_EVENT >= tIH) REPORT "ADDR Hold time violation -- tIH" SEVERITY WARNING; ASSERT(Ba'LAST_EVENT >= tIH) REPORT "BA Hold time violation -- tIH" SEVERITY WARNING; END IF; END PROCESS; END behave;

mit

impedimentToProgress/UCI-BlueChip

VhdlParser/test/memoryPreLoad.vhd

1

9295

package memoryPreLoad is CONSTANT NAHBMST : integer := 16; CONSTANT NAHBSLV : integer := 16; CONSTANT NAPBSLV : integer := 16; CONSTANT NAHBIRQ : integer := 32; CONSTANT NAHBAMR : integer := 4; CONSTANT NAHBIR : integer := 4; CONSTANT NAHBCFG : integer := 4 + 4; CONSTANT NAPBIR : integer := 1; CONSTANT NAPBAMR : integer := 1; CONSTANT NAPBCFG : integer := 1 + 1; CONSTANT NBUS : integer := 4; SUBTYPE amba_config_word IS std_logic_vector ( 31 downto 0 ); TYPE ahb_config_type IS ARRAY ( 0 to 4 + 4 - 1 ) OF amba_config_word; TYPE apb_config_type IS ARRAY ( 0 to 1 + 1 - 1 ) OF amba_config_word; TYPE ahb_mst_in_type IS RECORD hgrant : std_logic_vector ( 0 to 16 - 1 ); hready : std_ulogic; hresp : std_logic_vector ( 1 downto 0 ); hrdata : std_logic_vector ( 31 downto 0 ); hcache : std_ulogic; hirq : std_logic_vector ( 32 - 1 downto 0 ); testen : std_ulogic; testrst : std_ulogic; scanen : std_ulogic; testoen : std_ulogic; END RECORD; TYPE ahb_mst_out_type IS RECORD hbusreq : std_ulogic; hlock : std_ulogic; htrans : std_logic_vector ( 1 downto 0 ); haddr : std_logic_vector ( 31 downto 0 ); hwrite : std_ulogic; hsize : std_logic_vector ( 2 downto 0 ); hburst : std_logic_vector ( 2 downto 0 ); hprot : std_logic_vector ( 3 downto 0 ); hwdata : std_logic_vector ( 31 downto 0 ); hirq : std_logic_vector ( 32 - 1 downto 0 ); hconfig : ahb_config_type; hindex : integer RANGE 0 to 16 - 1; END RECORD; TYPE ahb_slv_in_type IS RECORD hsel : std_logic_vector ( 0 to 16 - 1 ); haddr : std_logic_vector ( 31 downto 0 ); hwrite : std_ulogic; htrans : std_logic_vector ( 1 downto 0 ); hsize : std_logic_vector ( 2 downto 0 ); hburst : std_logic_vector ( 2 downto 0 ); hwdata : std_logic_vector ( 31 downto 0 ); hprot : std_logic_vector ( 3 downto 0 ); hready : std_ulogic; hmaster : std_logic_vector ( 3 downto 0 ); hmastlock : std_ulogic; hmbsel : std_logic_vector ( 0 to 4 - 1 ); hcache : std_ulogic; hirq : std_logic_vector ( 32 - 1 downto 0 ); testen : std_ulogic; testrst : std_ulogic; scanen : std_ulogic; testoen : std_ulogic; END RECORD; TYPE ahb_slv_out_type IS RECORD hready : std_ulogic; hresp : std_logic_vector ( 1 downto 0 ); hrdata : std_logic_vector ( 31 downto 0 ); hsplit : std_logic_vector ( 15 downto 0 ); hcache : std_ulogic; hirq : std_logic_vector ( 32 - 1 downto 0 ); hconfig : ahb_config_type; hindex : integer RANGE 0 to 16 - 1; END RECORD; TYPE ahb_mst_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_mst_out_type; TYPE ahb_slv_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_slv_out_type; SUBTYPE ahb_mst_out_vector IS ahb_mst_out_vector_type ( 16 - 1 downto 0 ); SUBTYPE ahb_slv_out_vector IS ahb_slv_out_vector_type ( 16 - 1 downto 0 ); TYPE ahb_mst_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_mst_out_vector; TYPE ahb_slv_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_slv_out_vector; CONSTANT HTRANS_IDLE : std_logic_vector ( 1 downto 0 ) := "00"; CONSTANT HTRANS_BUSY : std_logic_vector ( 1 downto 0 ) := "01"; CONSTANT HTRANS_NONSEQ : std_logic_vector ( 1 downto 0 ) := "10"; CONSTANT HTRANS_SEQ : std_logic_vector ( 1 downto 0 ) := "11"; CONSTANT HBURST_SINGLE : std_logic_vector ( 2 downto 0 ) := "000"; CONSTANT HBURST_INCR : std_logic_vector ( 2 downto 0 ) := "001"; CONSTANT HBURST_WRAP4 : std_logic_vector ( 2 downto 0 ) := "010"; CONSTANT HBURST_INCR4 : std_logic_vector ( 2 downto 0 ) := "011"; CONSTANT HBURST_WRAP8 : std_logic_vector ( 2 downto 0 ) := "100"; CONSTANT HBURST_INCR8 : std_logic_vector ( 2 downto 0 ) := "101"; CONSTANT HBURST_WRAP16 : std_logic_vector ( 2 downto 0 ) := "110"; CONSTANT HBURST_INCR16 : std_logic_vector ( 2 downto 0 ) := "111"; CONSTANT HSIZE_BYTE : std_logic_vector ( 2 downto 0 ) := "000"; CONSTANT HSIZE_HWORD : std_logic_vector ( 2 downto 0 ) := "001"; CONSTANT HSIZE_WORD : std_logic_vector ( 2 downto 0 ) := "010"; CONSTANT HSIZE_DWORD : std_logic_vector ( 2 downto 0 ) := "011"; CONSTANT HSIZE_4WORD : std_logic_vector ( 2 downto 0 ) := "100"; CONSTANT HSIZE_8WORD : std_logic_vector ( 2 downto 0 ) := "101"; CONSTANT HSIZE_16WORD : std_logic_vector ( 2 downto 0 ) := "110"; CONSTANT HSIZE_32WORD : std_logic_vector ( 2 downto 0 ) := "111"; CONSTANT HRESP_OKAY : std_logic_vector ( 1 downto 0 ) := "00"; CONSTANT HRESP_ERROR : std_logic_vector ( 1 downto 0 ) := "01"; CONSTANT HRESP_RETRY : std_logic_vector ( 1 downto 0 ) := "10"; CONSTANT HRESP_SPLIT : std_logic_vector ( 1 downto 0 ) := "11"; TYPE apb_slv_in_type IS RECORD psel : std_logic_vector ( 0 to 16 - 1 ); penable : std_ulogic; paddr : std_logic_vector ( 31 downto 0 ); pwrite : std_ulogic; pwdata : std_logic_vector ( 31 downto 0 ); pirq : std_logic_vector ( 32 - 1 downto 0 ); testen : std_ulogic; testrst : std_ulogic; scanen : std_ulogic; testoen : std_ulogic; END RECORD; TYPE apb_slv_out_type IS RECORD prdata : std_logic_vector ( 31 downto 0 ); pirq : std_logic_vector ( 32 - 1 downto 0 ); pconfig : apb_config_type; pindex : integer RANGE 0 to 16 - 1; END RECORD; TYPE apb_slv_out_vector IS ARRAY ( 0 to 16 - 1 ) OF apb_slv_out_type; CONSTANT AMBA_CONFIG_VER0 : std_logic_vector ( 1 downto 0 ) := "00"; SUBTYPE amba_vendor_type IS integer RANGE 0 to 16#ff#; SUBTYPE amba_device_type IS integer RANGE 0 to 16#3ff#; SUBTYPE amba_version_type IS integer RANGE 0 to 16#3f#; SUBTYPE amba_cfgver_type IS integer RANGE 0 to 3; SUBTYPE amba_irq_type IS integer RANGE 0 to 32 - 1; SUBTYPE ahb_addr_type IS integer RANGE 0 to 16#fff#; CONSTANT zx : std_logic_vector ( 31 downto 0 ) := ( OTHERS => '0' ); CONSTANT zxirq : std_logic_vector ( 32 - 1 downto 0 ) := ( OTHERS => '0' ); CONSTANT zy : std_logic_vector ( 0 to 31 ) := ( OTHERS => '0' ); TYPE memory_in_type IS RECORD data : std_logic_vector ( 31 downto 0 ); brdyn : std_logic; bexcn : std_logic; writen : std_logic; wrn : std_logic_vector ( 3 downto 0 ); bwidth : std_logic_vector ( 1 downto 0 ); sd : std_logic_vector ( 63 downto 0 ); cb : std_logic_vector ( 7 downto 0 ); scb : std_logic_vector ( 7 downto 0 ); edac : std_logic; END RECORD; TYPE memory_out_type IS RECORD address : std_logic_vector ( 31 downto 0 ); data : std_logic_vector ( 31 downto 0 ); sddata : std_logic_vector ( 63 downto 0 ); ramsn : std_logic_vector ( 7 downto 0 ); ramoen : std_logic_vector ( 7 downto 0 ); ramn : std_ulogic; romn : std_ulogic; mben : std_logic_vector ( 3 downto 0 ); iosn : std_logic; romsn : std_logic_vector ( 7 downto 0 ); oen : std_logic; writen : std_logic; wrn : std_logic_vector ( 3 downto 0 ); bdrive : std_logic_vector ( 3 downto 0 ); vbdrive : std_logic_vector ( 31 downto 0 ); svbdrive : std_logic_vector ( 63 downto 0 ); read : std_logic; sa : std_logic_vector ( 14 downto 0 ); cb : std_logic_vector ( 7 downto 0 ); scb : std_logic_vector ( 7 downto 0 ); vcdrive : std_logic_vector ( 7 downto 0 ); svcdrive : std_logic_vector ( 7 downto 0 ); ce : std_ulogic; END RECORD; TYPE sdctrl_in_type IS RECORD wprot : std_ulogic; data : std_logic_vector ( 127 downto 0 ); cb : std_logic_vector ( 15 downto 0 ); END RECORD; TYPE sdctrl_out_type IS RECORD sdcke : std_logic_vector ( 1 downto 0 ); sdcsn : std_logic_vector ( 1 downto 0 ); sdwen : std_ulogic; rasn : std_ulogic; casn : std_ulogic; dqm : std_logic_vector ( 15 downto 0 ); bdrive : std_ulogic; qdrive : std_ulogic; vbdrive : std_logic_vector ( 31 downto 0 ); address : std_logic_vector ( 16 downto 2 ); data : std_logic_vector ( 127 downto 0 ); cb : std_logic_vector ( 15 downto 0 ); ce : std_ulogic; ba : std_logic_vector ( 1 downto 0 ); cal_en : std_logic_vector ( 7 downto 0 ); cal_inc : std_logic_vector ( 7 downto 0 ); cal_rst : std_logic; odt : std_logic_vector ( 1 downto 0 ); END RECORD; TYPE sdram_out_type IS RECORD sdcke : std_logic_vector ( 1 downto 0 ); sdcsn : std_logic_vector ( 1 downto 0 ); sdwen : std_ulogic; rasn : std_ulogic; casn : std_ulogic; dqm : std_logic_vector ( 7 downto 0 ); END RECORD; end package memoryPreLoad;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/esa/pci/pci_arb.in.vhd

6

202

-- PCI arbiter constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/grspwc_axcelerator.vhd

2

19858

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grspwc_axcelerator -- File: grspwc_axcelerator.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: tech wrapper for axcelerator grspwc netlist ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library axcelerator; use axcelerator.all; entity grspwc_axcelerator is generic( sysfreq : integer := 40000; usegen : integer range 0 to 1 := 1; nsync : integer range 1 to 2 := 1; rmap : integer range 0 to 1 := 0; rmapcrc : integer range 0 to 1 := 0; fifosize1 : integer range 4 to 32 := 16; fifosize2 : integer range 16 to 64 := 16; rxunaligned : integer range 0 to 1 := 0; rmapbufs : integer range 2 to 8 := 4; scantest : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; clk : in std_ulogic; txclk : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --spw in di : in std_logic_vector(1 downto 0); si : in std_logic_vector(1 downto 0); --spw out do : out std_logic_vector(1 downto 0); so : out std_logic_vector(1 downto 0); --time iface tickin : in std_ulogic; tickout : out std_ulogic; --irq irq : out std_logic; --misc clkdiv10 : in std_logic_vector(7 downto 0); dcrstval : in std_logic_vector(9 downto 0); timerrstval : in std_logic_vector(11 downto 0); --rmapen rmapen : in std_ulogic; --clk bufs rxclki : in std_logic_vector(1 downto 0); nrxclki : in std_logic_vector(1 downto 0); rxclko : out std_logic_vector(1 downto 0); --rx ahb fifo rxrenable : out std_ulogic; rxraddress : out std_logic_vector(4 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(4 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; txraddress : out std_logic_vector(4 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(4 downto 0); txrdata : in std_logic_vector(31 downto 0); --nchar fifo ncrenable : out std_ulogic; ncraddress : out std_logic_vector(5 downto 0); ncwrite : out std_ulogic; ncwdata : out std_logic_vector(8 downto 0); ncwaddress : out std_logic_vector(5 downto 0); ncrdata : in std_logic_vector(8 downto 0); --rmap buf rmrenable : out std_ulogic; rmraddress : out std_logic_vector(7 downto 0); rmwrite : out std_ulogic; rmwdata : out std_logic_vector(7 downto 0); rmwaddress : out std_logic_vector(7 downto 0); rmrdata : in std_logic_vector(7 downto 0); linkdis : out std_ulogic; testclk : in std_ulogic := '0'; testrst : in std_ulogic := '0'; testen : in std_ulogic := '0' ); end entity; architecture rtl of grspwc_axcelerator is component grspwc_axcelerator_16_16_rmap0_crc1 is port( rst : in std_logic; clk : in std_logic; txclk : in std_logic; hgrant : in std_logic; hready : in std_logic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); hbusreq : out std_logic; hlock : out std_logic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_logic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); psel : in std_logic; penable : in std_logic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_logic; pwdata : in std_logic_vector(31 downto 0); prdata : out std_logic_vector(31 downto 0); di : in std_logic_vector(1 downto 0); si : in std_logic_vector(1 downto 0); do : out std_logic_vector(1 downto 0); so : out std_logic_vector(1 downto 0); tickin : in std_logic; tickout : out std_logic; irq : out std_logic; clkdiv10 : in std_logic_vector(7 downto 0); dcrstval : in std_logic_vector(9 downto 0); timerrstval : in std_logic_vector(11 downto 0); rmapen : in std_logic; rxclki : in std_logic_vector(1 downto 0); nrxclki : in std_logic_vector(1 downto 0); rxclko : out std_logic_vector(1 downto 0); rxrenable : out std_logic; rxraddress : out std_logic_vector(4 downto 0); rxwrite : out std_logic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(4 downto 0); rxrdata : in std_logic_vector(31 downto 0); txrenable : out std_logic; txraddress : out std_logic_vector(4 downto 0); txwrite : out std_logic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(4 downto 0); txrdata : in std_logic_vector(31 downto 0); ncrenable : out std_logic; ncraddress : out std_logic_vector(5 downto 0); ncwrite : out std_logic; ncwdata : out std_logic_vector(8 downto 0); ncwaddress : out std_logic_vector(5 downto 0); ncrdata : in std_logic_vector(8 downto 0); rmrenable : out std_logic; rmraddress : out std_logic_vector(7 downto 0); rmwrite : out std_logic; rmwdata : out std_logic_vector(7 downto 0); rmwaddress : out std_logic_vector(7 downto 0); rmrdata : in std_logic_vector(7 downto 0); linkdis : out std_logic; testclk : in std_logic; testrst : in std_logic; testen : in std_logic); end component; component grspwc_axcelerator_16_16_rmap8_crc1 is port( rst : in std_logic; clk : in std_logic; txclk : in std_logic; hgrant : in std_logic; hready : in std_logic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); hbusreq : out std_logic; hlock : out std_logic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_logic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); psel : in std_logic; penable : in std_logic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_logic; pwdata : in std_logic_vector(31 downto 0); prdata : out std_logic_vector(31 downto 0); di : in std_logic_vector(1 downto 0); si : in std_logic_vector(1 downto 0); do : out std_logic_vector(1 downto 0); so : out std_logic_vector(1 downto 0); tickin : in std_logic; tickout : out std_logic; irq : out std_logic; clkdiv10 : in std_logic_vector(7 downto 0); dcrstval : in std_logic_vector(9 downto 0); timerrstval : in std_logic_vector(11 downto 0); rmapen : in std_logic; rxclki : in std_logic_vector(1 downto 0); nrxclki : in std_logic_vector(1 downto 0); rxclko : out std_logic_vector(1 downto 0); rxrenable : out std_logic; rxraddress : out std_logic_vector(4 downto 0); rxwrite : out std_logic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(4 downto 0); rxrdata : in std_logic_vector(31 downto 0); txrenable : out std_logic; txraddress : out std_logic_vector(4 downto 0); txwrite : out std_logic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(4 downto 0); txrdata : in std_logic_vector(31 downto 0); ncrenable : out std_logic; ncraddress : out std_logic_vector(5 downto 0); ncwrite : out std_logic; ncwdata : out std_logic_vector(8 downto 0); ncwaddress : out std_logic_vector(5 downto 0); ncrdata : in std_logic_vector(8 downto 0); rmrenable : out std_logic; rmraddress : out std_logic_vector(7 downto 0); rmwrite : out std_logic; rmwdata : out std_logic_vector(7 downto 0); rmwaddress : out std_logic_vector(7 downto 0); rmrdata : in std_logic_vector(7 downto 0); linkdis : out std_logic; testclk : in std_logic; testrst : in std_logic; testen : in std_logic); end component; component grspwc_axcelerator_16_16_rmap0_crc0 is port( rst : in std_logic; clk : in std_logic; txclk : in std_logic; hgrant : in std_logic; hready : in std_logic; hresp : in std_logic_vector (1 downto 0); hrdata : in std_logic_vector (31 downto 0); hbusreq : out std_logic; hlock : out std_logic; htrans : out std_logic_vector (1 downto 0); haddr : out std_logic_vector (31 downto 0); hwrite : out std_logic; hsize : out std_logic_vector (2 downto 0); hburst : out std_logic_vector (2 downto 0); hprot : out std_logic_vector (3 downto 0); hwdata : out std_logic_vector (31 downto 0); psel : in std_logic; penable : in std_logic; paddr : in std_logic_vector (31 downto 0); pwrite : in std_logic; pwdata : in std_logic_vector (31 downto 0); prdata : out std_logic_vector (31 downto 0); di : in std_logic_vector(1 downto 0); si : in std_logic_vector(1 downto 0); do : out std_logic_vector(1 downto 0); so : out std_logic_vector(1 downto 0); tickin : in std_logic; tickout : out std_logic; irq : out std_logic; clkdiv10 : in std_logic_vector (7 downto 0); dcrstval : in std_logic_vector (9 downto 0); timerrstval : in std_logic_vector (11 downto 0); rmapen : in std_logic; rxclki : in std_logic_vector(1 downto 0); nrxclki : in std_logic_vector(1 downto 0); rxclko : out std_logic_vector(1 downto 0); rxrenable : out std_logic; rxraddress : out std_logic_vector (4 downto 0); rxwrite : out std_logic; rxwdata : out std_logic_vector (31 downto 0); rxwaddress : out std_logic_vector (4 downto 0); rxrdata : in std_logic_vector (31 downto 0); txrenable : out std_logic; txraddress : out std_logic_vector (4 downto 0); txwrite : out std_logic; txwdata : out std_logic_vector (31 downto 0); txwaddress : out std_logic_vector (4 downto 0); txrdata : in std_logic_vector (31 downto 0); ncrenable : out std_logic; ncraddress : out std_logic_vector (5 downto 0); ncwrite : out std_logic; ncwdata : out std_logic_vector (8 downto 0); ncwaddress : out std_logic_vector (5 downto 0); ncrdata : in std_logic_vector (8 downto 0); rmrenable : out std_logic; rmraddress : out std_logic_vector (7 downto 0); rmwrite : out std_logic; rmwdata : out std_logic_vector (7 downto 0); rmwaddress : out std_logic_vector (7 downto 0); rmrdata : in std_logic_vector (7 downto 0); linkdis : out std_logic; testclk : in std_logic; testrst : in std_logic; testen : in std_logic); end component; begin hlock <= '0'; f16_16_crc1 : if (rmapcrc = 1) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate grspwc0 : grspwc_axcelerator_16_16_rmap0_crc1 port map( rst => rst, clk => clk, txclk => txclk, --ahb mst in hgrant => hgrant, hready => hready, hresp => hresp, hrdata => hrdata, --ahb mst out hbusreq => hbusreq, hlock => open, --hlock, htrans => htrans, haddr => haddr, hwrite => hwrite, hsize => hsize, hburst => hburst, hprot => hprot, hwdata => hwdata, --apb slv in psel => psel, penable => penable, paddr => paddr, pwrite => pwrite, pwdata => pwdata, --apb slv out prdata => prdata, --spw in di => di, si => si, --spw out do => do, so => so, --time iface tickin => tickin, tickout => tickout, --clk bufs rxclki => rxclki, nrxclki => nrxclki, rxclko => rxclko, --irq irq => irq, --misc clkdiv10 => clkdiv10, dcrstval => dcrstval, timerrstval => timerrstval, --rmapen rmapen => rmapen, --rx ahb fifo rxrenable => rxrenable, rxraddress => rxraddress, rxwrite => rxwrite, rxwdata => rxwdata, rxwaddress => rxwaddress, rxrdata => rxrdata, --tx ahb fifo txrenable => txrenable, txraddress => txraddress, txwrite => txwrite, txwdata => txwdata, txwaddress => txwaddress, txrdata => txrdata, --nchar fifo ncrenable => ncrenable, ncraddress => ncraddress, ncwrite => ncwrite, ncwdata => ncwdata, ncwaddress => ncwaddress, ncrdata => ncrdata, --rmap buf rmrenable => rmrenable, rmraddress => rmraddress, rmwrite => rmwrite, rmwdata => rmwdata, rmwaddress => rmwaddress, rmrdata => rmrdata, linkdis => linkdis, testclk => testclk, testrst => testrst, testen => testen ); end generate; f16_16_rmap8_crc1 : if (rmapcrc = 1) and (rmap = 1) and (rmapbufs = 8) and (fifosize1 = 16) and (fifosize2 = 16) generate grspwc0 : grspwc_axcelerator_16_16_rmap8_crc1 port map( rst => rst, clk => clk, txclk => txclk, --ahb mst in hgrant => hgrant, hready => hready, hresp => hresp, hrdata => hrdata, --ahb mst out hbusreq => hbusreq, hlock => open, --hlock, htrans => htrans, haddr => haddr, hwrite => hwrite, hsize => hsize, hburst => hburst, hprot => hprot, hwdata => hwdata, --apb slv in psel => psel, penable => penable, paddr => paddr, pwrite => pwrite, pwdata => pwdata, --apb slv out prdata => prdata, --spw in di => di, si => si, --spw out do => do, so => so, --time iface tickin => tickin, tickout => tickout, --clk bufs rxclki => rxclki, nrxclki => nrxclki, rxclko => rxclko, --irq irq => irq, --misc clkdiv10 => clkdiv10, dcrstval => dcrstval, timerrstval => timerrstval, --rmapen rmapen => rmapen, --rx ahb fifo rxrenable => rxrenable, rxraddress => rxraddress, rxwrite => rxwrite, rxwdata => rxwdata, rxwaddress => rxwaddress, rxrdata => rxrdata, --tx ahb fifo txrenable => txrenable, txraddress => txraddress, txwrite => txwrite, txwdata => txwdata, txwaddress => txwaddress, txrdata => txrdata, --nchar fifo ncrenable => ncrenable, ncraddress => ncraddress, ncwrite => ncwrite, ncwdata => ncwdata, ncwaddress => ncwaddress, ncrdata => ncrdata, --rmap buf rmrenable => rmrenable, rmraddress => rmraddress, rmwrite => rmwrite, rmwdata => rmwdata, rmwaddress => rmwaddress, rmrdata => rmrdata, linkdis => linkdis, testclk => testclk, testrst => testrst, testen => testen ); end generate; f16_16_crc0 : if (rmapcrc = 0) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate grspwc0 : grspwc_axcelerator_16_16_rmap0_crc0 port map( rst => rst, clk => clk, txclk => txclk, --ahb mst in hgrant => hgrant, hready => hready, hresp => hresp, hrdata => hrdata, --ahb mst out hbusreq => hbusreq, hlock => open, --hlock, htrans => htrans, haddr => haddr, hwrite => hwrite, hsize => hsize, hburst => hburst, hprot => hprot, hwdata => hwdata, --apb slv in psel => psel, penable => penable, paddr => paddr, pwrite => pwrite, pwdata => pwdata, --apb slv out prdata => prdata, --spw in di => di, si => si, --spw out do => do, so => so, --time iface tickin => tickin, tickout => tickout, --clk bufs rxclki => rxclki, nrxclki => nrxclki, rxclko => rxclko, --irq irq => irq, --misc clkdiv10 => clkdiv10, dcrstval => dcrstval, timerrstval => timerrstval, --rmapen rmapen => rmapen, --rx ahb fifo rxrenable => rxrenable, rxraddress => rxraddress, rxwrite => rxwrite, rxwdata => rxwdata, rxwaddress => rxwaddress, rxrdata => rxrdata, --tx ahb fifo txrenable => txrenable, txraddress => txraddress, txwrite => txwrite, txwdata => txwdata, txwaddress => txwaddress, txrdata => txrdata, --nchar fifo ncrenable => ncrenable, ncraddress => ncraddress, ncwrite => ncwrite, ncwdata => ncwdata, ncwaddress => ncwaddress, ncrdata => ncrdata, --rmap buf rmrenable => rmrenable, rmraddress => rmraddress, rmwrite => rmwrite, rmwdata => rmwdata, rmwaddress => rmwaddress, rmrdata => rmrdata, linkdis => linkdis, testclk => testclk, testrst => testrst, testen => testen ); end generate; end architecture;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/tech/axcelerator/components/axcelerator_vtables.vhd

2

4887

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; package VTABLES is CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) -- CLR_ipd, CLK_delayed, Q_zd, D, E_delayed, PRE_ipd, CLK_ipd CONSTANT DFEG_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, H, H, x, x, H, x, H ), ( H, L, H, x, H, x, H, x, H ), ( H, L, x, H, L, x, H, x, H ), ( H, H, x, x, x, H, x, x, S ), ( H, x, x, x, x, L, x, x, H ), ( H, x, x, x, x, H, L, x, S ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, H, H, H, x, L ), ( x, L, x, L, L, H, H, x, L ), ( U, x, L, x, x, H, x, x, L ), ( H, x, H, x, x, U, x, x, H )); -- CLR_ipd, CLK_delayed, T_delayed, Q_zd, CLK_ipd CONSTANT tflipflop_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, L, H, H, x, H ), ( H, L, H, L, H, x, H ), ( H, H, x, x, x, x, S ), ( H, x, x, x, L, x, S ), ( x, L, L, L, H, x, L ), ( x, L, H, H, H, x, L )); -- CLR_ipd, CLK_delayed, PRE_delayed,K_delayed,J_delayed, Q_zd, CLK_ipd CONSTANT jkflipflop_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, L, H, x, H, x, H ), ( H, L, x, L, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, H, L, x, H, x, L ), ( x, L, L, H, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, x, x, L, x, x, L ), ( H, x, U, x, x, H, x, x, H )); CONSTANT JKF2A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, L, H, x, H, x, H ), ( H, L, L, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, H, L, x, H, x, L ), ( x, L, H, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, L, x, x, L )); CONSTANT JKF3A_Q_tab : VitalStateTableType := ( ( L, H, L, x, H, H, x, L ), ( L, H, x, H, H, H, x, L ), ( L, L, H, x, x, H, x, H ), ( L, L, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, H, U, x, x, H )); CONSTANT dlatch_DLE3B_Q_tab : VitalStateTableType := ( ( x, x, x, H, x, H ), --active high preset ( H, x, x, L, x, S ), --latch ( x, H, x, L, x, S ), --latch ( L, L, H, L, x, H ), --transparent ( L, L, L, L, x, L ), --transparent ( U, x, H, L, H, H ), --o/p mux pessimism ( x, U, H, L, H, H ), --o/p mux pessimism ( U, x, L, L, L, L ), --o/p mux pessimism ( x, U, L, L, L, L ), --o/p mux pessimism ( L, L, H, U, x, H ), --PRE==X ( H, x, x, U, H, H ), --PRE==X ( x, H, x, U, H, H ), --PRE==X ( L, U, H, U, H, H ), --PRE==X ( U, L, H, U, H, H ), --PRE==X ( U, U, H, U, H, H )); --PRE==X --G, E, D, P, Qn, Qn+1 CONSTANT dlatch_DLE2B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), --active low clear ( H, H, x, x, x, S ), --latch ( H, x, H, x, x, S ), --latch ( H, L, L, H, x, H ), --transparent ( H, L, L, L, x, L ), --transparent ( H, x, x, L, L, L ), --o/p mux pessimism ( H, x, x, H, H, H ), --o/p mux pessimism ( U, x, x, L, L, L ), --CLR==X, o/p mux pessimism ( U, H, x, x, L, L ), --CLR==X, o/p mux pessimism, latch ( U, x, H, x, L, L ), --CLR==X, o/p mux pessimism, latch ( U, L, L, L, x, L )); --CLR==X, i/p mux pessimism --C, G, E, D, Qn, Qn+1 CONSTANT dlatch_DL2C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), --active low clear ( H, x, x, H, x, H ), --active high preset ( H, H, x, L, x, S ), --latch ( H, L, L, L, x, L ), --transparent ( U, L, L, L, x, L ), --CLR==U ( U, H, x, L, L, L ), --CLR==U ( x, U, L, L, L, L ), --CLR,G==U ( H, U, H, x, H, H ), --PRE==U/x,G==U ( H, L, H, x, x, H ), --PRE==U/x ( H, H, x, U, H, H )); --PRE==U --CLR, G, D, PRE, Qn, Qn+1 end VTABLES; --------------------- END OF VITABLE TABLE SECTION ----------------

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/techmap/axcelerator/memory_axcelerator.vhd

2

11227

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: various -- File: mem_axcelerator_gen.vhd -- Author: Jiri Gaisler Gaisler Research -- Description: Memory generators for Actel AX rams ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -- pragma translate_off library axcelerator; use axcelerator.RAM64K36; -- pragma translate_on entity axcel_ssram is generic (abits : integer := 16; dbits : integer := 36); port ( wa, ra : in std_logic_vector(15 downto 0); wclk, rclk : in std_ulogic; di : in std_logic_vector(dbits -1 downto 0); do : out std_logic_vector(dbits -1 downto 0); width : in std_logic_vector(2 downto 0); ren, wen : in std_ulogic ); end; architecture rtl of axcel_ssram is component RAM64K36 port( WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10, WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6, WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19, WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32, WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK, RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10, RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic; RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic); end component; signal gnd : std_ulogic; signal depth : std_logic_vector(4 downto 0); signal d, q : std_logic_vector(36 downto 0); begin depth <= "00000"; do <= q(dbits-1 downto 0); d(dbits-1 downto 0) <= di; d(36 downto dbits) <= (others => '0'); u0 : RAM64K36 port map ( WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3), WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7), WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11), WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15), WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4), WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9), WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14), WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19), WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24), WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29), WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34), WD35 => d(35), WEN => wen, DEPTH0 => depth(0), DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3), WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk, RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3), RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7), RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11), RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15), REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2), RCLK => rclk, RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4), RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9), RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14), RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19), RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24), RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29), RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34), RD35 => q(35)); end; library ieee; use ieee.std_logic_1164.all; library techmap; entity axcel_syncram_2p is generic ( abits : integer := 10; dbits : integer := 8 ); port ( rclk : in std_ulogic; rena : in std_ulogic; raddr : in std_logic_vector (abits -1 downto 0); dout : out std_logic_vector (dbits -1 downto 0); wclk : in std_ulogic; waddr : in std_logic_vector (abits -1 downto 0); din : in std_logic_vector (dbits -1 downto 0); write : in std_ulogic); end; architecture rtl of axcel_syncram_2p is component axcel_ssram generic (abits : integer := 16; dbits : integer := 36); port ( wa, ra : in std_logic_vector(15 downto 0); wclk, rclk : in std_ulogic; di : in std_logic_vector(dbits -1 downto 0); do : out std_logic_vector(dbits -1 downto 0); width : in std_logic_vector(2 downto 0); ren, wen : in std_ulogic ); end component; type dwtype is array (1 to 24) of integer; constant dwmap : dwtype := (36, 36, 36, 36, 36, 36, 36, 18, 9, 4, 2, others => 1); constant xbits : integer := dwmap(abits); constant dw : integer := dbits + 36; signal wen, gnd : std_ulogic; signal ra, wa : std_logic_vector(31 downto 0); signal d, q : std_logic_vector(dw downto 0); signal ren : std_ulogic; signal width : std_logic_vector(2 downto 0); constant READFAST : std_ulogic := '0'; begin width <= "101" when abits <= 7 else "100" when abits = 8 else "011" when abits = 9 else "010" when abits = 10 else "001" when abits = 11 else "000"; wen <= write; ren <= rena or READFAST; gnd <= '0'; ra(31 downto abits) <= (others =>'0'); wa(31 downto abits) <= (others =>'0'); ra(abits-1 downto 0) <= raddr(abits-1 downto 0); wa(abits-1 downto 0) <= waddr(abits-1 downto 0); d(dw downto dbits) <= (others =>'0'); d(dbits-1 downto 0) <= din(dbits-1 downto 0); dout <= q(dbits-1 downto 0); a7 : if abits <= 7 generate agen : for i in 0 to (dbits-1)/xbits generate u0 : axcel_ssram generic map (abits => 7, dbits => xbits) port map (ra => ra(15 downto 0), wa => wa(15 downto 0), di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width, wclk => wclk, ren => ren, rclk => rclk, do => q(xbits*(i+1)-1 downto xbits*i)); end generate; end generate; a8to12 : if (abits > 7) and (abits <= 12) generate agen : for i in 0 to (dbits-1)/xbits generate u0 : axcel_ssram generic map (abits => abits, dbits => xbits) port map (ra => ra(15 downto 0), wa => wa(15 downto 0), di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width, wclk => wclk, ren => ren, rclk => rclk, do => q(xbits*(i+1)-1 downto xbits*i)); end generate; end generate; -- pragma translate_off a_to_high : if abits > 12 generate x : process begin assert false report "Address depth larger than 12 not supported for AX rams" severity failure; wait; end process; end generate; -- pragma translate_on end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity axcel_syncram is generic ( abits : integer := 10; dbits : integer := 8 ); port ( clk : in std_ulogic; address : in std_logic_vector((abits -1) downto 0); datain : in std_logic_vector((dbits -1) downto 0); dataout : out std_logic_vector((dbits -1) downto 0); enable : in std_ulogic; write : in std_ulogic ); end; architecture rtl of axcel_syncram is component axcel_syncram_2p generic ( abits : integer := 10; dbits : integer := 8 ); port ( rclk : in std_ulogic; rena : in std_ulogic; raddr : in std_logic_vector (abits -1 downto 0); dout : out std_logic_vector (dbits -1 downto 0); wclk : in std_ulogic; waddr : in std_logic_vector (abits -1 downto 0); din : in std_logic_vector (dbits -1 downto 0); write : in std_ulogic); end component; component axcel_ssram generic (abits : integer := 16; dbits : integer := 36); port ( wa, ra : in std_logic_vector(15 downto 0); wclk, rclk : in std_ulogic; di : in std_logic_vector(dbits -1 downto 0); do : out std_logic_vector(dbits -1 downto 0); width : in std_logic_vector(2 downto 0); ren, wen : in std_ulogic ); end component; type d_type is array (0 to 3) of std_logic_vector(35 downto 0); signal wen : std_logic_vector(3 downto 0); signal q : d_type; signal addr : std_logic_vector(15 downto 0); signal addrreg : std_logic_vector(1 downto 0); begin a : if not ((abits = 10 or abits = 11) and dbits = 36) generate u0 : axcel_syncram_2p generic map (abits, dbits) port map (clk, enable, address, dataout, clk, address, datain, write); end generate; -- Special case for 4 or 8 KB cache with FT: 36x1024 or 2048: 2 or 4 banks of 4*9*512 a10to11d36 : if (abits = 10 or abits = 11) and dbits = 36 generate addr_reg : process (clk) begin if rising_edge(clk) then addrreg(abits-10 downto 0) <= address(abits-1 downto 9); end if; end process; addr(15 downto 9) <= (others => '0'); addr(8 downto 0) <= address(8 downto 0); decode : process (address, write) variable vwen : std_logic_vector(3 downto 0); begin vwen := (others => '0'); if write = '1' then vwen( to_integer(unsigned(address(abits-1 downto 9))) ) := '1'; end if; wen <= vwen; end process; loop0 : for b in 0 to 2*(abits-9)-1 generate agen0 : for i in 0 to 3 generate u0 : axcel_ssram generic map (abits => 9, dbits => 9) port map (ra => addr, wa => addr, di => datain(9*(i+1)-1 downto 9*i), wen => wen(b), width => "011", wclk => clk, ren => enable, rclk => clk, do => q(b)(9*(i+1)-1 downto 9*i)); end generate; end generate; dout10: if abits = 10 generate dataout <= q(0) when addrreg(0)='0' else q(1); end generate; dout11: if abits = 11 generate dataout <= q(0) when addrreg(1 downto 0)="00" else q(1) when addrreg(1 downto 0)="01" else q(2) when addrreg(1 downto 0)="10" else q(3); end generate; end generate; end;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/memAttack/lib/gleichmann/dac/dac.vhd

2

1629

library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package dac is type adcdac_in_type is record adc_in : std_ulogic; end record; type adcdac_out_type is record adc_fb : std_ulogic; dac_out : std_ulogic; end record; component adcdac generic ( pindex : integer; paddr : integer; pmask : integer; nbits : integer); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; adcdaci : in adcdac_in_type; adcdaco : out adcdac_out_type); end component; component dac_ahb generic ( length : integer; hindex : integer; haddr : integer; hmask : integer; tech : integer; kbytes : integer); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; dac_out : out std_ulogic); end component; component sigdelt generic ( c_dacin_length : positive); port ( reset : in std_logic; clock : in std_logic; dac_in : in std_logic_vector(c_dacin_length-1 downto 0); dac_out : out std_logic); end component; component adc_sigdelt generic ( c_adcin_length : positive); port ( rstn : in std_ulogic; clk : in std_ulogic; valid : out std_ulogic; adc_fb : out std_ulogic; adc_out : out std_logic_vector(c_adcin_length-1 downto 0); adc_in : in std_ulogic); end component; end dac;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/gaisler/misc/i2c.in.vhd

6

73

-- I2C master constant CFG_I2C_ENABLE : integer := CONFIG_I2C_ENABLE;

mit

impedimentToProgress/UCI-BlueChip

AttackFiles/Attacks/privEsc/lib/tech/unisim/simprims/xilinx_simprims.vhd

2

783945

---------------------------------------------------------------------------- -- Simple simulation models for some Xilinx blocks ---------------------------------------------------------------------------- -- pragma translate_off library ieee; use ieee.std_logic_1164.all; library STD; use STD.TEXTIO.all; package vpkg is signal GSR : std_logic := '0'; signal GTS : std_logic := '0'; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN STRING := ""; Constant Unit : IN STRING := ""; Constant ExpectedValueMsg : IN STRING := ""; Constant ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ); PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN INTEGER; Constant Unit : IN STRING := ""; Constant ExpectedValueMsg : IN STRING := ""; Constant ExpectedGenericValue : IN INTEGER; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ); PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN BOOLEAN; Constant Unit : IN STRING := ""; Constant ExpectedValueMsg : IN STRING := ""; Constant ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ); PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN INTEGER; CONSTANT Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ); PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN REAL; CONSTANT Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ); procedure detect_resolution ( constant model_name : in string); function slv_to_int (slv : in std_logic_vector) return integer; function addr_is_valid (slv : in std_logic_vector) return boolean ; function DECODE_ADDR4 ( ADDRESS : in std_logic_vector(3 downto 0) ) return integer; function DECODE_ADDR5 ( ADDRESS : in std_logic_vector(4 downto 0) ) return integer; function SLV_TO_STR ( SLV : in std_logic_vector ) return string; end; package body vpkg is function SLV_TO_STR ( SLV : in std_logic_vector ) return string is variable j : integer := SLV'length; variable STR : string (SLV'length downto 1); begin for I in SLV'high downto SLV'low loop case SLV(I) is when '0' => STR(J) := '0'; when '1' => STR(J) := '1'; when 'X' => STR(J) := 'X'; when 'U' => STR(J) := 'U'; when others => STR(J) := 'X'; end case; J := J - 1; end loop; return STR; end SLV_TO_STR; function DECODE_ADDR4 ( ADDRESS : in std_logic_vector(3 downto 0) ) return integer is variable I : integer; begin case ADDRESS is when "0000" => I := 0; when "0001" => I := 1; when "0010" => I := 2; when "0011" => I := 3; when "0100" => I := 4; when "0101" => I := 5; when "0110" => I := 6; when "0111" => I := 7; when "1000" => I := 8; when "1001" => I := 9; when "1010" => I := 10; when "1011" => I := 11; when "1100" => I := 12; when "1101" => I := 13; when "1110" => I := 14; when "1111" => I := 15; when others => I := 16; end case; return I; end DECODE_ADDR4; function ADDR_IS_VALID ( SLV : in std_logic_vector ) return boolean is variable IS_VALID : boolean := TRUE; begin for I in SLV'high downto SLV'low loop if (SLV(I) /= '0' AND SLV(I) /= '1') then IS_VALID := FALSE; end if; end loop; return IS_VALID; end ADDR_IS_VALID; function SLV_TO_INT(SLV: in std_logic_vector ) return integer is variable int : integer; begin int := 0; for i in SLV'high downto SLV'low loop int := int * 2; if SLV(i) = '1' then int := int + 1; end if; end loop; return int; end; procedure detect_resolution ( constant model_name : in string ) IS variable test_value : time; variable Message : LINE; BEGIN test_value := 1 ps; if (test_value = 0 ps) then Write (Message, STRING'(" Simulator Resolution Error : ")); Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. ")); Write (Message, STRING'(" In order to simulate the ")); Write (Message, model_name); Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller ")); ASSERT FALSE REPORT Message.ALL SEVERITY ERROR; DEALLOCATE (Message); end if; END detect_resolution; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN STRING := ""; Constant Unit : IN STRING := ""; Constant ExpectedValueMsg : IN STRING := ""; Constant ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ) IS VARIABLE Message : LINE; BEGIN Write ( Message, HeaderMsg ); Write ( Message, STRING'(" The attribute ") ); Write ( Message, GenericName ); Write ( Message, STRING'(" on ") ); Write ( Message, EntityName ); Write ( Message, STRING'(" instance ") ); Write ( Message, InstanceName ); Write ( Message, STRING'(" is set to ") ); Write ( Message, GenericValue ); Write ( Message, Unit ); Write ( Message, '.' & LF ); Write ( Message, ExpectedValueMsg ); Write ( Message, ExpectedGenericValue ); Write ( Message, Unit ); Write ( Message, TailMsg ); ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; DEALLOCATE (Message); END GenericValueCheckMessage; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN INTEGER; CONSTANT Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN INTEGER; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ) IS VARIABLE Message : LINE; BEGIN Write ( Message, HeaderMsg ); Write ( Message, STRING'(" The attribute ") ); Write ( Message, GenericName ); Write ( Message, STRING'(" on ") ); Write ( Message, EntityName ); Write ( Message, STRING'(" instance ") ); Write ( Message, InstanceName ); Write ( Message, STRING'(" is set to ") ); Write ( Message, GenericValue ); Write ( Message, Unit ); Write ( Message, '.' & LF ); Write ( Message, ExpectedValueMsg ); Write ( Message, ExpectedGenericValue ); Write ( Message, Unit ); Write ( Message, TailMsg ); ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; DEALLOCATE (Message); END GenericValueCheckMessage; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN BOOLEAN; Constant Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ) IS VARIABLE Message : LINE; BEGIN Write ( Message, HeaderMsg ); Write ( Message, STRING'(" The attribute ") ); Write ( Message, GenericName ); Write ( Message, STRING'(" on ") ); Write ( Message, EntityName ); Write ( Message, STRING'(" instance ") ); Write ( Message, InstanceName ); Write ( Message, STRING'(" is set to ") ); Write ( Message, GenericValue ); Write ( Message, Unit ); Write ( Message, '.' & LF ); Write ( Message, ExpectedValueMsg ); Write ( Message, ExpectedGenericValue ); Write ( Message, Unit ); Write ( Message, TailMsg ); ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; DEALLOCATE (Message); END GenericValueCheckMessage; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN INTEGER; CONSTANT Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ) IS VARIABLE Message : LINE; BEGIN Write ( Message, HeaderMsg ); Write ( Message, STRING'(" The attribute ") ); Write ( Message, GenericName ); Write ( Message, STRING'(" on ") ); Write ( Message, EntityName ); Write ( Message, STRING'(" instance ") ); Write ( Message, InstanceName ); Write ( Message, STRING'(" is set to ") ); Write ( Message, GenericValue ); Write ( Message, Unit ); Write ( Message, '.' & LF ); Write ( Message, ExpectedValueMsg ); Write ( Message, ExpectedGenericValue ); Write ( Message, Unit ); Write ( Message, TailMsg ); ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; DEALLOCATE (Message); END GenericValueCheckMessage; PROCEDURE GenericValueCheckMessage ( CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; CONSTANT GenericName : IN STRING := ""; CONSTANT EntityName : IN STRING := ""; CONSTANT InstanceName : IN STRING := ""; CONSTANT GenericValue : IN REAL; CONSTANT Unit : IN STRING := ""; CONSTANT ExpectedValueMsg : IN STRING := ""; CONSTANT ExpectedGenericValue : IN STRING := ""; CONSTANT TailMsg : IN STRING; CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING ) IS VARIABLE Message : LINE; BEGIN Write ( Message, HeaderMsg ); Write ( Message, STRING'(" The attribute ") ); Write ( Message, GenericName ); Write ( Message, STRING'(" on ") ); Write ( Message, EntityName ); Write ( Message, STRING'(" instance ") ); Write ( Message, InstanceName ); Write ( Message, STRING'(" is set to ") ); Write ( Message, GenericValue ); Write ( Message, Unit ); Write ( Message, '.' & LF ); Write ( Message, ExpectedValueMsg ); Write ( Message, ExpectedGenericValue ); Write ( Message, Unit ); Write ( Message, TailMsg ); ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; DEALLOCATE (Message); END GenericValueCheckMessage; function DECODE_ADDR5 ( ADDRESS : in std_logic_vector(4 downto 0) ) return integer is variable I : integer; begin case ADDRESS is when "00000" => I := 0; when "00001" => I := 1; when "00010" => I := 2; when "00011" => I := 3; when "00100" => I := 4; when "00101" => I := 5; when "00110" => I := 6; when "00111" => I := 7; when "01000" => I := 8; when "01001" => I := 9; when "01010" => I := 10; when "01011" => I := 11; when "01100" => I := 12; when "01101" => I := 13; when "01110" => I := 14; when "01111" => I := 15; when "10000" => I := 16; when "10001" => I := 17; when "10010" => I := 18; when "10011" => I := 19; when "10100" => I := 20; when "10101" => I := 21; when "10110" => I := 22; when "10111" => I := 23; when "11000" => I := 24; when "11001" => I := 25; when "11010" => I := 26; when "11011" => I := 27; when "11100" => I := 28; when "11101" => I := 29; when "11110" => I := 30; when "11111" => I := 31; when others => I := 32; end case; return I; end DECODE_ADDR5; end; library ieee; use ieee.std_logic_1164.all; package simple_simprim is component ramb4_generic generic ( abits : integer := 10; dbits : integer := 8 ); port (DI : in std_logic_vector (dbits-1 downto 0); EN : in std_ulogic; WE : in std_ulogic; RST : in std_ulogic; CLK : in std_ulogic; ADDR : in std_logic_vector (abits-1 downto 0); DO : out std_logic_vector (dbits-1 downto 0) ); end component; component ramb4_sx_sx generic (abits : integer := 10; dbits : integer := 8 ); port (DIA : in std_logic_vector (dbits-1 downto 0); DIB : in std_logic_vector (dbits-1 downto 0); ENA : in std_ulogic; ENB : in std_ulogic; WEA : in std_ulogic; WEB : in std_ulogic; RSTA : in std_ulogic; RSTB : in std_ulogic; CLKA : in std_ulogic; CLKB : in std_ulogic; ADDRA : in std_logic_vector (abits-1 downto 0); ADDRB : in std_logic_vector (abits-1 downto 0); DOA : out std_logic_vector (dbits-1 downto 0); DOB : out std_logic_vector (dbits-1 downto 0) ); end component; component ramb16_sx generic (abits : integer := 10; dbits : integer := 8 ); port ( DO : out std_logic_vector (dbits-1 downto 0); ADDR : in std_logic_vector (abits-1 downto 0); DI : in std_logic_vector (dbits-1 downto 0); EN : in std_ulogic; CLK : in std_ulogic; WE : in std_ulogic; SSR : in std_ulogic); end component; component ram16_sx_sx generic (abits : integer := 10; dbits : integer := 8 ); port ( DOA : out std_logic_vector (dbits-1 downto 0); DOB : out std_logic_vector (dbits-1 downto 0); ADDRA : in std_logic_vector (abits-1 downto 0); CLKA : in std_ulogic; DIA : in std_logic_vector (dbits-1 downto 0); ENA : in std_ulogic; WEA : in std_ulogic; ADDRB : in std_logic_vector (abits-1 downto 0); CLKB : in std_ulogic; DIB : in std_logic_vector (dbits-1 downto 0); ENB : in std_ulogic; WEB : in std_ulogic); end component; end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ramb4_generic is generic ( abits : integer := 10; dbits : integer := 8 ); port (DI : in std_logic_vector (dbits-1 downto 0); EN : in std_ulogic; WE : in std_ulogic; RST : in std_ulogic; CLK : in std_ulogic; ADDR : in std_logic_vector (abits-1 downto 0); DO : out std_logic_vector (dbits-1 downto 0) ); end; architecture behavioral of ramb4_generic is type mem is array(0 to (2**abits -1)) of std_logic_vector((dbits -1) downto 0); begin main : process(clk) variable memarr : mem; begin if rising_edge(clk)then if (en = '1') and not (is_x(addr)) then do <= memarr(to_integer(unsigned(addr))); end if; if (we and en) = '1' then if not is_x(addr) then memarr(to_integer(unsigned(addr))) := di; end if; end if; end if; end process; end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ramb16_sx is generic ( abits : integer := 10; dbits : integer := 8 ); port ( DO : out std_logic_vector (dbits-1 downto 0); ADDR : in std_logic_vector (abits-1 downto 0); DI : in std_logic_vector (dbits-1 downto 0); EN : in std_ulogic; CLK : in std_ulogic; WE : in std_ulogic; SSR : in std_ulogic ); end; architecture behav of ramb16_sx is begin rp : process(clk) subtype dword is std_logic_vector(dbits-1 downto 0); type dregtype is array (0 to 2**abits -1) of DWord; variable rfd : dregtype := (others => (others => '0')); begin if rising_edge(clk) and not is_x (addr) then if en = '1' then do <= rfd(to_integer(unsigned(addr))); if we = '1' then rfd(to_integer(unsigned(addr))) := di; end if; end if; end if; end process; end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram16_sx_sx is generic ( abits : integer := 10; dbits : integer := 8 ); port ( DOA : out std_logic_vector (dbits-1 downto 0); DOB : out std_logic_vector (dbits-1 downto 0); ADDRA : in std_logic_vector (abits-1 downto 0); CLKA : in std_ulogic; DIA : in std_logic_vector (dbits-1 downto 0); ENA : in std_ulogic; WEA : in std_ulogic; ADDRB : in std_logic_vector (abits-1 downto 0); CLKB : in std_ulogic; DIB : in std_logic_vector (dbits-1 downto 0); ENB : in std_ulogic; WEB : in std_ulogic ); end; architecture behav of ram16_sx_sx is signal async : std_ulogic := '0'; begin ramproc : process(clka, clkb) subtype dword is std_logic_vector(dbits-1 downto 0); type dregtype is array (0 to 2**abits -1) of DWord; variable rfd : dregtype := (others => (others => '0')); begin if rising_edge(clka) and not is_x (addra) then if ena = '1' then if wea = '1' then rfd(to_integer(unsigned(addra))) := dia; end if; doa <= rfd(to_integer(unsigned(addra))); end if; end if; if rising_edge(clkb) and not is_x (addrb) then if enb = '1' then if web = '1' then rfd(to_integer(unsigned(addrb))) := dib; end if; dob <= rfd(to_integer(unsigned(addrb))); end if; end if; end process; end; library ieee; use ieee.std_logic_1164.all; entity BSCAN_VIRTEX is port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TDO1 : in STD_ULOGIC; TDO2 : in STD_ULOGIC); end; architecture behav of BSCAN_VIRTEX is begin CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0'; RESET <= '0'; SEL1 <= '0'; SEL2 <= '0'; SHIFT <= '0'; TDI <= '0'; UPDATE <= '0'; end; library ieee; use ieee.std_logic_1164.all; entity BSCAN_VIRTEX2 is port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TDO1 : in STD_ULOGIC; TDO2 : in STD_ULOGIC); end; architecture behav of BSCAN_VIRTEX2 is begin CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0'; RESET <= '0'; SEL1 <= '0'; SEL2 <= '0'; SHIFT <= '0'; TDI <= '0'; UPDATE <= '0'; end; library ieee; use ieee.std_logic_1164.all; entity BSCAN_VIRTEX4 is generic( JTAG_CHAIN : integer := 1 ); port( CAPTURE : out std_ulogic ; DRCK : out std_ulogic ; RESET : out std_ulogic ; SEL : out std_ulogic ; SHIFT : out std_ulogic ; TDI : out std_ulogic ; UPDATE : out std_ulogic ; TDO : in std_ulogic ); end BSCAN_VIRTEX4; architecture behav of BSCAN_VIRTEX4 is begin CAPTURE <= '0'; DRCK <= '0'; RESET <= '0'; SEL <= '0'; SHIFT <= '0'; TDI <= '0'; UPDATE <= '0'; end; library ieee; use ieee.std_logic_1164.all; entity BSCAN_VIRTEX5 is generic( JTAG_CHAIN : integer := 1 ); port( CAPTURE : out std_ulogic ; DRCK : out std_ulogic ; RESET : out std_ulogic ; SEL : out std_ulogic ; SHIFT : out std_ulogic ; TDI : out std_ulogic ; UPDATE : out std_ulogic ; TDO : in std_ulogic ); end BSCAN_VIRTEX5; architecture behav of BSCAN_VIRTEX5 is begin CAPTURE <= '0'; DRCK <= '0'; RESET <= '0'; SEL <= '0'; SHIFT <= '0'; TDI <= '0'; UPDATE <= '0'; end; library ieee; use ieee.std_logic_1164.all; entity BSCAN_SPARTAN3 is port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TDO1 : in STD_ULOGIC; TDO2 : in STD_ULOGIC); end; architecture behav of BSCAN_SPARTAN3 is begin CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0'; RESET <= '0'; SEL1 <= '0'; SEL2 <= '0'; SHIFT <= '0'; TDI <= '0'; UPDATE <= '0'; end; library ieee; use ieee.std_logic_1164.all; entity BUFGMUX is port (O : out std_logic; I0, I1, S : in std_logic); end; architecture beh of BUFGMUX is begin o <= to_X01(I0) when to_X01(S) = '0' else I1; end; library ieee; use ieee.std_logic_1164.all; entity BUFG is port (O : out std_logic; I : in std_logic); end; architecture beh of BUFG is begin o <= to_X01(i); end; library ieee; use ieee.std_logic_1164.all; entity BUFGP is port (O : out std_logic; I : in std_logic); end; architecture beh of BUFGP is begin o <= to_X01(i); end; library ieee; use ieee.std_logic_1164.all; entity BUFGDLL is port (O : out std_logic; I : in std_logic); end; architecture beh of BUFGDLL is begin o <= to_X01(i); end; library ieee; use ieee.std_logic_1164.all; entity IBUFG is generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; architecture beh of IBUFG is begin o <= to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity IBUF is generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; architecture beh of IBUF is begin o <= to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity OBUF is generic ( CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12; IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW"); port (O : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUF is begin o <= to_X01(i) after 2 ns when slew = "SLOW" else to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity IOBUF is generic ( CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12; IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW"); port ( O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end; architecture beh of IOBUF is begin io <= 'X' after 2 ns when to_X01(t) = 'X' else I after 2 ns when (to_X01(t) = '0') else 'Z' after 2 ns when to_X01(t) = '1'; o <= to_X01(io) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity IOBUFDS is generic ( CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0"; IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO"); port ( O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end; architecture beh of IOBUFDS is begin io <= 'X' after 2 ns when to_X01(t) = 'X' else I after 2 ns when (to_X01(t) = '0') else 'Z' after 2 ns when to_X01(t) = '1'; iob <= 'X' after 2 ns when to_X01(t) = 'X' else not I after 2 ns when (to_X01(t) = '0') else 'Z' after 2 ns when to_X01(t) = '1'; o <= to_X01(io) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity OBUFT is generic ( CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12; IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW"); port ( O : out std_ulogic; I, T : in std_ulogic); end; architecture beh of OBUFT is begin o <= I after 2 ns when to_X01(t) = '0' else 'Z' after 2 ns when to_X01(t) = '1' else 'X' after 2 ns ; end; library ieee; use ieee.std_logic_1164.all; entity IBUFDS is generic ( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0"; IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT"); port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFDS is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity IBUFDS_LVDS_25 is port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFDS_LVDS_25 is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity IBUFDS_LVDS_33 is port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFDS_LVDS_33 is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity IBUFGDS_LVDS_25 is port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFGDS_LVDS_25 is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity IBUFGDS_LVDS_33 is port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFGDS_LVDS_33 is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity IBUFGDS is generic( CAPACITANCE : string := "DONT_CARE"; DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0"; IOSTANDARD : string := "DEFAULT"); port (O : out std_logic; I, IB : in std_logic); end; architecture beh of IBUFGDS is signal old : std_ulogic; begin old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; library ieee; use ieee.std_logic_1164.all; entity OBUFDS is generic(IOSTANDARD : string := "DEFAULT"); port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS is begin o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity OBUFDS_LVDS_25 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_25 is begin o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity OBUFDS_LVDS_33 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_33 is begin o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; end; ----- CELL BUFGCE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.all; entity BUFGCE is port( O : out STD_ULOGIC; CE: in STD_ULOGIC; I : in STD_ULOGIC ); end BUFGCE; architecture BUFGCE_V of BUFGCE is signal NCE : STD_ULOGIC := 'X'; signal GND : STD_ULOGIC := '0'; component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component; begin B1 : BUFGMUX port map ( I0 => I, I1 => GND, O =>O, s =>NCE); -- I1 : INV -- port map ( -- I => CE, -- O => NCE); nCE <= not CE; end BUFGCE_V; ----- CELL CLKDLL ----- ----- x_clkdll_maximum_period_check ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library STD; use STD.TEXTIO.all; entity x_clkdll_maximum_period_check is generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic ); end x_clkdll_maximum_period_check; architecture x_clkdll_maximum_period_check_V of x_clkdll_maximum_period_check is begin MAX_PERIOD_CHECKER : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; variable clock_period : time := 0 ps; variable Message : line; begin clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (clock_edge_previous > 0 ps) then clock_period := clock_edge_current - clock_edge_previous; end if; if (clock_period > maximum_period) then Write ( Message, string'(" Timing Violation Error : Input Clock Period of")); Write ( Message, clock_period/1000.0 ); Write ( Message, string'(" on the ") ); Write ( Message, clock_name ); Write ( Message, string'(" port ") ); Write ( Message, string'(" of CLKDLL instance ") ); Write ( Message, InstancePath ); Write ( Message, string'(" exceeds allotted value of ") ); Write ( Message, maximum_period/1000.0 ); Write ( Message, string'(" at simulation time ") ); Write ( Message, clock_edge_current/1000.0 ); Write ( Message, '.' & LF ); assert false report Message.all severity warning; DEALLOCATE (Message); end if; wait on clock; end process MAX_PERIOD_CHECKER; end x_clkdll_maximum_period_check_V; ----- CLKDLL ----- library IEEE; use IEEE.std_logic_1164.all; library STD; use STD.TEXTIO.all; library IEEE; use Ieee.Vital_Primitives.all; use Ieee.Vital_Timing.all; library unisim; use unisim.vpkg.all; entity CLKDLL is generic ( TimingChecksOn : boolean := true; InstancePath : string := "*"; Xon : boolean := true; MsgOn : boolean := false; tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns); tpd_CLKIN_LOCKED : VitalDelayType01 := (0.000 ns, 0.000 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns; tpw_CLKIN_negedge : VitalDelayType := 0.000 ns; tpw_CLKIN_posedge : VitalDelayType := 0.000 ns; tpw_RST_posedge : VitalDelayType := 0.000 ns; CLKDV_DIVIDE : real := 2.0; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; --non-simulatable MAXPERCLKIN : time := 40000 ps; --simulation parameter SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --simulation parameter SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --simulation parameter STARTUP_WAIT : boolean := false --non-simulatable ); port ( CLK0 : out std_ulogic := '0'; CLK180 : out std_ulogic := '0'; CLK270 : out std_ulogic := '0'; CLK2X : out std_ulogic := '0'; CLK90 : out std_ulogic := '0'; CLKDV : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; CLKFB : in std_ulogic := '0'; CLKIN : in std_ulogic := '0'; RST : in std_ulogic := '0' ); attribute VITAL_LEVEL0 of CLKDLL : entity is true; end CLKDLL; architecture CLKDLL_V of CLKDLL is component x_clkdll_maximum_period_check generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic ); end component; signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic; signal clk0_out : std_ulogic; signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0'; signal clkfb_type : integer; signal divide_type : integer; signal clk1x_type : integer; signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; signal lock_out : std_logic_vector(1 downto 0) := "00"; signal lock_fb : std_ulogic := '0'; signal fb_delay_found : std_ulogic := '0'; signal clkin_ps : std_ulogic; signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic; signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns); signal period : time := 0 ps; signal period_orig : time := 0 ps; signal period_ps : time := 0 ps; signal clkout_delay : time := 0 ps; signal fb_delay : time := 0 ps; signal period_dv_high, period_dv_low : time := 0 ps; signal cycle_jitter, period_jitter : time := 0 ps; signal clkin_window, clkfb_window : std_ulogic := '0'; signal clkin_5050 : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0) := "000"; signal clkin_period_real0_temp : time := 0 ps; signal ps_lock_temp : std_ulogic := '0'; signal clk0_temp : std_ulogic := '0'; signal clk2x_temp : std_ulogic := '0'; signal no_stop : boolean := false; begin INITPROC : process begin detect_resolution (model_name => "CLKDLL" ); if (CLKDV_DIVIDE = 1.5) then divide_type <= 3; elsif (CLKDV_DIVIDE = 2.0) then divide_type <= 4; elsif (CLKDV_DIVIDE = 2.5) then divide_type <= 5; elsif (CLKDV_DIVIDE = 3.0) then divide_type <= 6; elsif (CLKDV_DIVIDE = 4.0) then divide_type <= 8; elsif (CLKDV_DIVIDE = 5.0) then divide_type <= 10; elsif (CLKDV_DIVIDE = 8.0) then divide_type <= 16; elsif (CLKDV_DIVIDE = 16.0) then divide_type <= 32; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKDV_DIVIDE", EntityName => "CLKDLL", InstanceName => InstancePath, GenericValue => CLKDV_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; clkfb_type <= 2; period_jitter <= SIM_CLKIN_PERIOD_JITTER; cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; case DUTY_CYCLE_CORRECTION is when false => clk1x_type <= 0; when true => clk1x_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DUTY_CYCLE_CORRECTION", EntityName => "CLKDLL", InstanceName => InstancePath, GenericValue => DUTY_CYCLE_CORRECTION, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; case STARTUP_WAIT is when false => null; when true => null; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "STARTUP_WAIT", EntityName => "CLKDLL", InstanceName => InstancePath, GenericValue => STARTUP_WAIT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; wait; end process INITPROC; -- -- input wire delays -- WireDelay : block begin VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN); VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB); VitalWireDelay (RST_ipd, RST, tipd_RST); end block; i_max_clkin : x_clkdll_maximum_period_check generic map ( clock_name => "CLKIN", maximum_period => MAXPERCLKIN) port map ( clock => clkin_ipd); assign_clkin_ps : process begin if (rst_ipd = '0') then clkin_ps <= clkin_ipd; elsif (rst_ipd = '1') then clkin_ps <= '0'; wait until (falling_edge(rst_reg(2))); end if; wait on clkin_ipd, rst_ipd; end process assign_clkin_ps; clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4; clkin_fb1 <= transport clkin_fb0 after period_ps/4; clkin_fb2 <= transport clkin_fb1 after period_ps/4; clkin_fb <= transport clkin_fb2 after period_ps/4; determine_period_ps : process variable clkin_ps_edge_previous : time := 0 ps; variable clkin_ps_edge_current : time := 0 ps; begin if (rst_ipd'event) then clkin_ps_edge_previous := 0 ps; clkin_ps_edge_current := 0 ps; period_ps <= 0 ps; else if (rising_edge(clkin_ps)) then clkin_ps_edge_previous := clkin_ps_edge_current; clkin_ps_edge_current := NOW; wait for 0 ps; if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; end if; end if; end if; wait on clkin_ps, rst_ipd; end process determine_period_ps; assign_lock_fb : process begin if (rising_edge(clkin_ps)) then lock_fb <= lock_period; end if; wait on clkin_ps; end process assign_lock_fb; calculate_clkout_delay : process begin if (rst_ipd'event) then clkout_delay <= 0 ps; elsif (period'event or fb_delay'event) then clkout_delay <= period - fb_delay; end if; wait on period, fb_delay, rst_ipd; end process calculate_clkout_delay; -- --generate master reset signal -- gen_master_rst : process begin if (rising_edge(clkin_ipd)) then rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; rst_reg(1) <= rst_reg(0) and rst_ipd; rst_reg(0) <= rst_ipd; end if; wait on clkin_ipd; end process gen_master_rst; check_rst_width : process variable Message : line; begin if (falling_edge(rst_ipd)) then if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then Write ( Message, string'(" Timing Violation Error : RST on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); assert false report Message.all severity error; DEALLOCATE (Message); end if; end if; wait on rst_ipd; end process check_rst_width; -- --determine clock period -- determine_clock_period : process variable clkin_edge_previous : time := 0 ps; variable clkin_edge_current : time := 0 ps; begin if (rst_ipd'event) then clkin_period_real(0) <= 0 ps; clkin_period_real(1) <= 0 ps; clkin_period_real(2) <= 0 ps; elsif (rising_edge(clkin_ps)) then clkin_edge_previous := clkin_edge_current; clkin_edge_current := NOW; clkin_period_real(2) <= clkin_period_real(1); clkin_period_real(1) <= clkin_period_real(0); if (clkin_edge_previous /= 0 ps) then clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; end if; end if; if (no_stop'event) then clkin_period_real(0) <= clkin_period_real0_temp; end if; wait on clkin_ps, no_stop, rst_ipd; end process determine_clock_period; evaluate_clock_period : process variable clock_stopped : std_ulogic := '1'; variable Message : line; begin if (rst_ipd'event) then lock_period <= '0'; clock_stopped := '1'; clkin_period_real0_temp <= 0 ps; else if (falling_edge(clkin_ps)) then if (lock_period = '0') then if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then lock_period <= '1'; period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; period <= clkin_period_real(0); end if; elsif (lock_period = '1') then if (100000000 ps < clkin_period_real(0)/1000) then Write ( Message, string'(" Timing Violation Error : CLKIN stopped toggling on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, string'(" 10000 ")); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, string'(" clkin_period(0) / 10000.0 ")); Write ( Message, string'(" ns ")); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then clkin_period_real0_temp <= clkin_period_real(1); no_stop <= not no_stop; clock_stopped := '1'; elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then Write ( Message, string'(" Timing Violation Error : Input Clock Period Jitter on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, period_jitter / 1000.0 ); Write ( Message, string'(" Locked CLKIN Period = ")); Write ( Message, period_orig / 1000.0 ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) / 1000.0 ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then Write ( Message, string'(" Timing Violation Error : Input Clock Cycle Jitter on on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, cycle_jitter / 1000.0 ); Write ( Message, string'(" Previous CLKIN Period = ")); Write ( Message, clkin_period_real(1) / 1000.0 ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) / 1000.0 ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); else period <= clkin_period_real(0); clock_stopped := '0'; end if; end if; end if; end if; wait on clkin_ps, rst_ipd; end process evaluate_clock_period; -- --determine clock delay -- determine_clock_delay : process variable delay_edge : time := 0 ps; variable temp1 : integer := 0; variable temp2 : integer := 0; variable temp : integer := 0; variable delay_edge_current : time := 0 ps; begin if (rst_ipd'event) then fb_delay <= 0 ps; fb_delay_found <= '0'; else if (rising_edge(lock_period)) then if ((lock_period = '1') and (clkfb_type /= 0)) then if (clkfb_type = 1) then wait until ((rising_edge(clk0_temp)) or (rst_ipd'event)); delay_edge := NOW; elsif (clkfb_type = 2) then wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event)); delay_edge := NOW; end if; wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); temp2 := (period_orig * 1)/ (1 ps); temp := temp1 mod temp2; fb_delay <= temp * 1 ps; end if; end if; fb_delay_found <= '1'; end if; wait on lock_period, rst_ipd; end process determine_clock_delay; -- -- determine feedback lock -- GEN_CLKFB_WINDOW : process begin if (rst_ipd'event) then clkfb_window <= '0'; else if (rising_edge(CLKFB_ipd)) then wait for 0 ps; clkfb_window <= '1'; wait for cycle_jitter; clkfb_window <= '0'; end if; end if; wait on clkfb_ipd, rst_ipd; end process GEN_CLKFB_WINDOW; GEN_CLKIN_WINDOW : process begin if (rst_ipd'event) then clkin_window <= '0'; else if (rising_edge(clkin_fb)) then wait for 0 ps; clkin_window <= '1'; wait for cycle_jitter; clkin_window <= '0'; end if; end if; wait on clkin_fb, rst_ipd; end process GEN_CLKIN_WINDOW; set_reset_lock_clkin : process begin if (rst_ipd'event) then lock_clkin <= '0'; else if (rising_edge(clkin_fb)) then wait for 1 ps; if ((clkfb_window = '1') and (fb_delay_found = '1')) then lock_clkin <= '1'; else lock_clkin <= '0'; end if; end if; end if; wait on clkin_fb, rst_ipd; end process set_reset_lock_clkin; set_reset_lock_clkfb : process begin if (rst_ipd'event) then lock_clkfb <= '0'; else if (rising_edge(clkfb_ipd)) then wait for 1 ps; if ((clkin_window = '1') and (fb_delay_found = '1')) then lock_clkfb <= '1'; else lock_clkfb <= '0'; end if; end if; end if; wait on clkfb_ipd, rst_ipd; end process set_reset_lock_clkfb; assign_lock_delay : process begin if (rst_ipd'event) then lock_delay <= '0'; else if (falling_edge(clkin_fb)) then lock_delay <= lock_clkin or lock_clkfb; end if; end if; wait on clkin_fb, rst_ipd; end process; -- --generate lock signal -- generate_lock : process begin if (rst_ipd'event) then lock_out <= "00"; locked_out <= '0'; else if (rising_edge(clkin_ps)) then if (clkfb_type = 0) then lock_out(0) <= lock_period; else lock_out(0) <= lock_period and lock_delay and lock_fb; end if; lock_out(1) <= lock_out(0); locked_out <= lock_out(1); end if; end if; wait on clkin_ps, rst_ipd; end process generate_lock; -- --generate the clk1x_out -- gen_clk1x : process begin if (rst_ipd'event) then clkin_5050 <= '0'; else if (rising_edge(clkin_ps)) then clkin_5050 <= '1'; wait for (period/2); clkin_5050 <= '0'; end if; end if; wait on clkin_ps, rst_ipd; end process gen_clk1x; clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps; -- --generate the clk2x_out -- gen_clk2x : process begin if (rising_edge(clkin_ps)) then clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; if (lock_out(0) = '1') then wait for (period / 4); clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; else wait for (period / 2); end if; end if; wait on clkin_ps; end process gen_clk2x; -- --generate the clkdv_out -- determine_clkdv_period : process begin if (period'event) then period_dv_high <= (period / 2) * (divide_type / 2); period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2); end if; wait on period; end process determine_clkdv_period; gen_clkdv : process begin if (rising_edge(clkin_ps)) then if (lock_out(0) = '1') then clkdv_out <= '1'; wait for (period_dv_high); clkdv_out <= '0'; wait for (period_dv_low); clkdv_out <= '1'; wait for (period_dv_high); clkdv_out <= '0'; wait for (period_dv_low - period/2); end if; end if; wait on clkin_ps; end process gen_clkdv; -- --generate all output signal -- schedule_outputs : process variable LOCKED_GlitchData : VitalGlitchDataType; begin if (CLK0_out'event) then CLK0 <= transport CLK0_out after clkout_delay; clk0_temp <= transport CLK0_out after clkout_delay; CLK90 <= transport clk0_out after (clkout_delay + period / 4); CLK180 <= transport clk0_out after (clkout_delay + period / 2); CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4); end if; if (clk2x_out'event) then CLK2X <= transport clk2x_out after clkout_delay; clk2x_temp <= transport clk2x_out after clkout_delay; end if; if (clkdv_out'event) then CLKDV <= transport clkdv_out after clkout_delay; end if; VitalPathDelay01 ( OutSignal => LOCKED, GlitchData => LOCKED_GlitchData, OutSignalName => "LOCKED", OutTemp => locked_out, Paths => (0 => (locked_out'last_event, tpd_CLKIN_LOCKED, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); wait on clk0_out, clk2x_out, clkdv_out, locked_out; end process schedule_outputs; VitalTimingCheck : process variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Pviol_CLKIN : std_ulogic := '0'; variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_PSCLK : std_ulogic := '0'; variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_RST : std_ulogic := '0'; variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit; begin if (TimingChecksOn) then VitalPeriodPulseCheck ( Violation => Pviol_CLKIN, PeriodData => PInfo_CLKIN, TestSignal => CLKIN_ipd, TestSignalName => "CLKIN", TestDelay => 0 ns, Period => tperiod_CLKIN_POSEDGE, PulseWidthHigh => tpw_CLKIN_posedge, PulseWidthLow => tpw_CLKIN_negedge, CheckEnabled => TO_X01(not RST_ipd) /= '0', HeaderMsg => InstancePath &"/CLKDLL", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_RST, PeriodData => PInfo_RST, TestSignal => RST_ipd, TestSignalName => "RST", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_RST_posedge, PulseWidthLow => 0 ns, CheckEnabled => true, HeaderMsg => InstancePath &"/CLKDLL", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); end if; wait on CLKIN_ipd, RST_ipd; end process VITALTimingCheck; end CLKDLL_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library STD; use STD.TEXTIO.all; entity clkdllhf_maximum_period_check is generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end clkdllhf_maximum_period_check; architecture clkdllhf_maximum_period_check_V of clkdllhf_maximum_period_check is begin MAX_PERIOD_CHECKER : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; variable clock_period : time := 0 ps; variable Message : line; begin if (rising_edge(clock)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (clock_edge_previous > 0 ps) then clock_period := clock_edge_current - clock_edge_previous; end if; if ((clock_period > maximum_period) and (rst = '0')) then Write ( Message, string'(" Timing Violation Error : Input Clock Period of")); Write ( Message, clock_period/1000.0 ); Write ( Message, string'(" on the ") ); Write ( Message, clock_name ); Write ( Message, string'(" port ") ); Write ( Message, string'(" of CLKDLLHF instance ") ); Write ( Message, InstancePath ); Write ( Message, string'(" exceeds allotted value of ") ); Write ( Message, maximum_period/1000.0 ); Write ( Message, string'(" at simulation time ") ); Write ( Message, clock_edge_current/1000.0 ); Write ( Message, '.' & LF ); assert false report Message.all severity warning; DEALLOCATE (Message); end if; end if; wait on clock; end process MAX_PERIOD_CHECKER; end clkdllhf_maximum_period_check_V; ----- CELL CLKDLLHF ----- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.VPKG.all; library unisim; use unisim.VCOMPONENTS.all; entity CLKDLLHF is generic ( TimingChecksOn : boolean := true; InstancePath : string := "*"; Xon : boolean := true; MsgOn : boolean := false; tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns); tpd_CLKIN_LOCKED : VitalDelayType01 := (0.000 ns, 0.000 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns; tpw_CLKIN_negedge : VitalDelayType := 0.000 ns; tpw_CLKIN_posedge : VitalDelayType := 0.000 ns; tpw_RST_posedge : VitalDelayType := 0.000 ns; CLKDV_DIVIDE : real := 2.0; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"FFF0"; --non-simulatable STARTUP_WAIT : boolean := false --non-simulatable ); port ( CLK0 : out std_ulogic := '0'; CLK180 : out std_ulogic := '0'; CLKDV : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; CLKFB : in std_ulogic := '0'; CLKIN : in std_ulogic := '0'; RST : in std_ulogic := '0' ); attribute VITAL_LEVEL0 of CLKDLLHF : entity is true; end CLKDLLHF; architecture CLKDLLHF_V of CLKDLLHF is component clkdllhf_maximum_period_check generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end component; constant MAXPERCLKIN : time := 40000 ps; constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic; signal clk0_out : std_ulogic; signal clkdv_out, locked_out : std_ulogic := '0'; signal clkfb_type : integer; signal divide_type : integer; signal clk1x_type : integer; signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; signal lock_out : std_logic_vector(1 downto 0) := "00"; signal lock_fb : std_ulogic := '0'; signal fb_delay_found : std_ulogic := '0'; signal clkin_ps : std_ulogic; signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic; signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns); signal period : time := 0 ps; signal period_orig : time := 0 ps; signal period_ps : time := 0 ps; signal clkout_delay : time := 0 ps; signal fb_delay : time := 0 ps; signal period_dv_high, period_dv_low : time := 0 ps; signal cycle_jitter, period_jitter : time := 0 ps; signal clkin_window, clkfb_window : std_ulogic := '0'; signal clkin_5050 : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0) := "000"; signal clkin_period_real0_temp : time := 0 ps; signal ps_lock_temp : std_ulogic := '0'; signal clk0_temp : std_ulogic := '0'; signal clk2X_temp : std_ulogic := '0'; signal no_stop : boolean := false; begin INITPROC : process begin detect_resolution (model_name => "CLKDLLHF" ); if (CLKDV_DIVIDE = 1.5) then divide_type <= 3; elsif (CLKDV_DIVIDE = 2.0) then divide_type <= 4; elsif (CLKDV_DIVIDE = 2.5) then divide_type <= 5; elsif (CLKDV_DIVIDE = 3.0) then divide_type <= 6; elsif (CLKDV_DIVIDE = 4.0) then divide_type <= 8; elsif (CLKDV_DIVIDE = 5.0) then divide_type <= 10; elsif (CLKDV_DIVIDE = 8.0) then divide_type <= 16; elsif (CLKDV_DIVIDE = 16.0) then divide_type <= 32; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKDV_DIVIDE", EntityName => "CLKDLLHF", InstanceName => InstancePath, GenericValue => CLKDV_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; clkfb_type <= 1; period_jitter <= SIM_CLKIN_PERIOD_JITTER; cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; case DUTY_CYCLE_CORRECTION is when false => clk1x_type <= 0; when true => clk1x_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DUTY_CYCLE_CORRECTION", EntityName => "CLKDLLHF", InstanceName => InstancePath, GenericValue => DUTY_CYCLE_CORRECTION, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; case STARTUP_WAIT is when false => null; when true => null; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "STARTUP_WAIT", EntityName => "CLKDLLHF", InstanceName => InstancePath, GenericValue => STARTUP_WAIT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; wait; end process INITPROC; -- -- input wire delays -- WireDelay : block begin VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN); VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB); VitalWireDelay (RST_ipd, RST, tipd_RST); end block; i_max_clkin : clkdllhf_maximum_period_check generic map ( clock_name => "CLKIN", maximum_period => MAXPERCLKIN) port map ( clock => clkin_ipd, rst => rst_ipd); assign_clkin_ps : process begin if (rst_ipd = '0') then clkin_ps <= clkin_ipd; elsif (rst_ipd = '1') then clkin_ps <= '0'; wait until (falling_edge(rst_reg(2))); end if; wait on clkin_ipd, rst_ipd; end process assign_clkin_ps; clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4; clkin_fb1 <= transport clkin_fb0 after period_ps/4; clkin_fb2 <= transport clkin_fb1 after period_ps/4; clkin_fb <= transport clkin_fb2 after period_ps/4; determine_period_ps : process variable clkin_ps_edge_previous : time := 0 ps; variable clkin_ps_edge_current : time := 0 ps; begin if (rst_ipd'event) then clkin_ps_edge_previous := 0 ps; clkin_ps_edge_current := 0 ps; period_ps <= 0 ps; else if (rising_edge(clkin_ps)) then clkin_ps_edge_previous := clkin_ps_edge_current; clkin_ps_edge_current := NOW; wait for 0 ps; if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; end if; end if; end if; wait on clkin_ps, rst_ipd; end process determine_period_ps; assign_lock_fb : process begin if (rising_edge(clkin_ps)) then lock_fb <= lock_period; end if; wait on clkin_ps; end process assign_lock_fb; calculate_clkout_delay : process begin if (rst_ipd'event) then clkout_delay <= 0 ps; elsif (period'event or fb_delay'event) then clkout_delay <= period - fb_delay; end if; wait on period, fb_delay, rst_ipd; end process calculate_clkout_delay; -- --generate master reset signal -- gen_master_rst : process begin if (rising_edge(clkin_ipd)) then rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; rst_reg(1) <= rst_reg(0) and rst_ipd; rst_reg(0) <= rst_ipd; end if; wait on clkin_ipd; end process gen_master_rst; check_rst_width : process variable Message : line; variable rst_tmp1, rst_tmp2 : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then if (rst_ipd = '1') then rst_tmp1 := NOW; elsif (rst_ipd = '1') then rst_tmp2 := NOW - rst_tmp1; end if; if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then Write ( Message, string'(" Timing Violation Error : RST on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" must be asserted atleast for 2 ns. ")); assert false report Message.all severity error; DEALLOCATE (Message); end if; end if; wait on rst_ipd; end process check_rst_width; -- --determine clock period -- determine_clock_period : process variable clkin_edge_previous : time := 0 ps; variable clkin_edge_current : time := 0 ps; begin if (rst_ipd'event) then clkin_period_real(0) <= 0 ps; clkin_period_real(1) <= 0 ps; clkin_period_real(2) <= 0 ps; elsif (rising_edge(clkin_ps)) then clkin_edge_previous := clkin_edge_current; clkin_edge_current := NOW; clkin_period_real(2) <= clkin_period_real(1); clkin_period_real(1) <= clkin_period_real(0); if (clkin_edge_previous /= 0 ps) then clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; end if; end if; if (no_stop'event) then clkin_period_real(0) <= clkin_period_real0_temp; end if; wait on clkin_ps, no_stop, rst_ipd; end process determine_clock_period; evaluate_clock_period : process variable clock_stopped : std_ulogic := '1'; variable Message : line; begin if (rst_ipd'event) then lock_period <= '0'; clock_stopped := '1'; clkin_period_real0_temp <= 0 ps; else if (falling_edge(clkin_ps)) then if (lock_period = '0') then if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then lock_period <= '1'; period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; period <= clkin_period_real(0); end if; elsif (lock_period = '1') then if (100000000 ps < clkin_period_real(0)/1000) then Write ( Message, string'(" Timing Violation Error : CLKIN stopped toggling on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, string'(" 10000 ")); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, string'(" clkin_period(0) / 10000.0 ")); Write ( Message, string'(" ns ")); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then clkin_period_real0_temp <= clkin_period_real(1); no_stop <= not no_stop; clock_stopped := '1'; elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then Write ( Message, string'(" Timing Violation Error : Input Clock Period Jitter on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, period_jitter / 1000.0 ); Write ( Message, string'(" Locked CLKIN Period = ")); Write ( Message, period_orig / 1000.0 ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) / 1000.0 ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then Write ( Message, string'(" Timing Violation Error : Input Clock Cycle Jitter on on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, cycle_jitter / 1000.0 ); Write ( Message, string'(" Previous CLKIN Period = ")); Write ( Message, clkin_period_real(1) / 1000.0 ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) / 1000.0 ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); end if; else period <= clkin_period_real(0); clock_stopped := '0'; end if; end if; end if; wait on clkin_ps, rst_ipd; end process evaluate_clock_period; determine_clock_delay : process variable delay_edge : time := 0 ps; variable temp1 : integer := 0; variable temp2 : integer := 0; variable temp : integer := 0; variable delay_edge_current : time := 0 ps; begin if (rst_ipd'event) then fb_delay <= 0 ps; fb_delay_found <= '0'; else if (rising_edge(lock_period)) then if ((lock_period = '1') and (clkfb_type /= 0)) then if (clkfb_type = 1) then wait until ((rising_edge(clk0_temp)) or (rst_ipd'event)); delay_edge := NOW; elsif (clkfb_type = 2) then wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event)); delay_edge := NOW; end if; wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); temp2 := (period_orig * 1)/ (1 ps); temp := temp1 mod temp2; fb_delay <= temp * 1 ps; end if; end if; fb_delay_found <= '1'; end if; wait on lock_period, rst_ipd; end process determine_clock_delay; -- -- determine feedback lock -- GEN_CLKFB_WINDOW : process begin if (rst_ipd'event) then clkfb_window <= '0'; else if (rising_edge(CLKFB_ipd)) then wait for 0 ps; clkfb_window <= '1'; wait for cycle_jitter; clkfb_window <= '0'; end if; end if; wait on clkfb_ipd, rst_ipd; end process GEN_CLKFB_WINDOW; GEN_CLKIN_WINDOW : process begin if (rst_ipd'event) then clkin_window <= '0'; else if (rising_edge(clkin_fb)) then wait for 0 ps; clkin_window <= '1'; wait for cycle_jitter; clkin_window <= '0'; end if; end if; wait on clkin_fb, rst_ipd; end process GEN_CLKIN_WINDOW; set_reset_lock_clkin : process begin if (rst_ipd'event) then lock_clkin <= '0'; else if (rising_edge(clkin_fb)) then wait for 1 ps; if ((clkfb_window = '1') and (fb_delay_found = '1')) then lock_clkin <= '1'; else lock_clkin <= '0'; end if; end if; end if; wait on clkin_fb, rst_ipd; end process set_reset_lock_clkin; set_reset_lock_clkfb : process begin if (rst_ipd'event) then lock_clkfb <= '0'; else if (rising_edge(clkfb_ipd)) then wait for 1 ps; if ((clkin_window = '1') and (fb_delay_found = '1')) then lock_clkfb <= '1'; else lock_clkfb <= '0'; end if; end if; end if; wait on clkfb_ipd, rst_ipd; end process set_reset_lock_clkfb; assign_lock_delay : process begin if (rst_ipd'event) then lock_delay <= '0'; else if (falling_edge(clkin_fb)) then lock_delay <= lock_clkin or lock_clkfb; end if; end if; wait on clkin_fb, rst_ipd; end process; -- --generate lock signal -- generate_lock : process begin if (rst_ipd'event) then lock_out <= "00"; locked_out <= '0'; else if (rising_edge(clkin_ps)) then if (clkfb_type = 0) then lock_out(0) <= lock_period; else lock_out(0) <= lock_period and lock_delay and lock_fb; end if; lock_out(1) <= lock_out(0); locked_out <= lock_out(1); end if; end if; wait on clkin_ps, rst_ipd; end process generate_lock; -- --generate the clk1x_out -- gen_clk1x : process begin if (rst_ipd'event) then clkin_5050 <= '0'; else if (rising_edge(clkin_ps)) then clkin_5050 <= '1'; wait for (period/2); clkin_5050 <= '0'; end if; end if; wait on clkin_ps, rst_ipd; end process gen_clk1x; clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps; -- --generate the clkdv_out -- determine_clkdv_period : process begin if (period'event) then period_dv_high <= (period / 2) * (divide_type / 2); period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2); end if; wait on period; end process determine_clkdv_period; gen_clkdv : process begin if (rising_edge(clkin_ps)) then if (lock_out(0) = '1') then clkdv_out <= '1'; wait for (period_dv_high); clkdv_out <= '0'; wait for (period_dv_low); clkdv_out <= '1'; wait for (period_dv_high); clkdv_out <= '0'; wait for (period_dv_low - period/2); end if; end if; wait on clkin_ps; end process gen_clkdv; -- --generate all output signal -- schedule_outputs : process variable LOCKED_GlitchData : VitalGlitchDataType; begin if (CLK0_out'event) then CLK0 <= transport CLK0_out after clkout_delay; clk0_temp <= transport CLK0_out after clkout_delay; CLK180 <= transport clk0_out after (clkout_delay + period / 2); end if; if (clkdv_out'event) then CLKDV <= transport clkdv_out after clkout_delay; end if; VitalPathDelay01 ( OutSignal => LOCKED, GlitchData => LOCKED_GlitchData, OutSignalName => "LOCKED", OutTemp => locked_out, Paths => (0 => (locked_out'last_event, tpd_CLKIN_LOCKED, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); wait on clk0_out, clkdv_out, locked_out; end process schedule_outputs; VitalTimingCheck : process variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Pviol_CLKIN : std_ulogic := '0'; variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_PSCLK : std_ulogic := '0'; variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_RST : std_ulogic := '0'; variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit; begin if (TimingChecksOn) then VitalPeriodPulseCheck ( Violation => Pviol_CLKIN, PeriodData => PInfo_CLKIN, TestSignal => CLKIN_ipd, TestSignalName => "CLKIN", TestDelay => 0 ns, Period => tperiod_CLKIN_POSEDGE, PulseWidthHigh => tpw_CLKIN_posedge, PulseWidthLow => tpw_CLKIN_negedge, CheckEnabled => TO_X01(not RST_ipd) /= '0', HeaderMsg => InstancePath &"/CLKDLLHF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_RST, PeriodData => PInfo_RST, TestSignal => RST_ipd, TestSignalName => "RST", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_RST_posedge, PulseWidthLow => 0 ns, CheckEnabled => true, HeaderMsg => InstancePath &"/CLKDLLHF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); end if; wait on CLKIN_ipd, RST_ipd; end process VITALTimingCheck; end CLKDLLHF_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity IDDR is generic( DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; INIT_Q1 : bit := '0'; INIT_Q2 : bit := '0'; SRTYPE : string := "SYNC" ); port( Q1 : out std_ulogic; Q2 : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end IDDR; architecture IDDR_V OF IDDR is constant SYNC_PATH_DELAY : time := 100 ps; signal C_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal D_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal R_ipd : std_ulogic := 'X'; signal S_ipd : std_ulogic := 'X'; signal C_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal D_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal R_dly : std_ulogic := 'X'; signal S_dly : std_ulogic := 'X'; signal Q1_zd : std_ulogic := 'X'; signal Q2_zd : std_ulogic := 'X'; signal Q1_viol : std_ulogic := 'X'; signal Q2_viol : std_ulogic := 'X'; signal Q1_o_reg : std_ulogic := 'X'; signal Q2_o_reg : std_ulogic := 'X'; signal Q3_o_reg : std_ulogic := 'X'; signal Q4_o_reg : std_ulogic := 'X'; signal ddr_clk_edge_type : integer := -999; signal sr_type : integer := -999; begin --------------------- -- INPUT PATH DELAYs -------------------- C_dly <= C after 0 ps; CE_dly <= CE after 0 ps; D_dly <= D after 0 ps; GSR_dly <= GSR after 0 ps; R_dly <= R after 0 ps; S_dly <= S after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then ddr_clk_edge_type <= 1; elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then ddr_clk_edge_type <= 2; elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then ddr_clk_edge_type <= 3; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DDR_CLK_EDGE ", EntityName => "/IDDR", GenericValue => DDR_CLK_EDGE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED.", TailMsg => "", MsgSeverity => ERROR ); end if; if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then sr_type <= 1; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then sr_type <= 2; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " SRTYPE ", EntityName => "/IDDR", GenericValue => SRTYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " ASYNC or SYNC. ", TailMsg => "", MsgSeverity => ERROR ); end if; wait; end process prcs_init; --#################################################################### --##### q1_q2_q3_q4 reg ##### --#################################################################### prcs_q1q2q3q4_reg:process(C_dly, D_dly, GSR_dly, R_dly, S_dly) variable Q1_var : std_ulogic := TO_X01(INIT_Q1); variable Q2_var : std_ulogic := TO_X01(INIT_Q2); variable Q3_var : std_ulogic := TO_X01(INIT_Q1); variable Q4_var : std_ulogic := TO_X01(INIT_Q2); begin if(GSR_dly = '1') then Q1_var := TO_X01(INIT_Q1); Q3_var := TO_X01(INIT_Q1); Q2_var := TO_X01(INIT_Q2); Q4_var := TO_X01(INIT_Q2); elsif(GSR_dly = '0') then case sr_type is when 1 => if(R_dly = '1') then Q1_var := '0'; Q2_var := '0'; Q3_var := '0'; Q4_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q1_var := '1'; Q2_var := '1'; Q3_var := '1'; Q4_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(rising_edge(C_dly)) then Q3_var := Q1_var; Q1_var := D_dly; Q4_var := Q2_var; end if; if(falling_edge(C_dly)) then Q2_var := D_dly; end if; end if; end if; when 2 => if(rising_edge(C_dly)) then if(R_dly = '1') then Q1_var := '0'; Q3_var := '0'; Q4_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q1_var := '1'; Q3_var := '1'; Q4_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then Q3_var := Q1_var; Q1_var := D_dly; Q4_var := Q2_var; end if; end if; end if; if(falling_edge(C_dly)) then if(R_dly = '1') then Q2_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q2_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then Q2_var := D_dly; end if; end if; end if; when others => null; end case; end if; q1_o_reg <= Q1_var; q2_o_reg <= Q2_var; q3_o_reg <= Q3_var; q4_o_reg <= Q4_var; end process prcs_q1q2q3q4_reg; --#################################################################### --##### q1 & q2 mux ##### --#################################################################### prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg) begin case ddr_clk_edge_type is when 1 => Q1_zd <= q1_o_reg; Q2_zd <= q2_o_reg; when 2 => Q1_zd <= q1_o_reg; Q2_zd <= q4_o_reg; when 3 => Q1_zd <= q3_o_reg; Q2_zd <= q4_o_reg; when others => null; end case; end process prcs_q1q2_mux; --#################################################################### --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(Q1_zd, Q2_zd) begin Q1 <= Q1_zd after SYNC_PATH_DELAY; Q2 <= Q2_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end IDDR_V; library IEEE; use IEEE.STD_LOGIC_1164.all; --use unisim.vpkg.all; library unisim; use unisim.vpkg.all; entity ODDR is generic( DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D1 : in std_ulogic; D2 : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end ODDR; architecture ODDR_V OF ODDR is constant SYNC_PATH_DELAY : time := 100 ps; signal C_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal D1_ipd : std_ulogic := 'X'; signal D2_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal R_ipd : std_ulogic := 'X'; signal S_ipd : std_ulogic := 'X'; signal C_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal D1_dly : std_ulogic := 'X'; signal D2_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal R_dly : std_ulogic := 'X'; signal S_dly : std_ulogic := 'X'; signal Q_zd : std_ulogic := 'X'; signal Q_viol : std_ulogic := 'X'; signal ddr_clk_edge_type : integer := -999; signal sr_type : integer := -999; begin --------------------- -- INPUT PATH DELAYs -------------------- C_dly <= C after 0 ps; CE_dly <= CE after 0 ps; D1_dly <= D1 after 0 ps; D2_dly <= D2 after 0 ps; GSR_dly <= GSR after 0 ps; R_dly <= R after 0 ps; S_dly <= S after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then ddr_clk_edge_type <= 1; elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then ddr_clk_edge_type <= 2; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DDR_CLK_EDGE ", EntityName => "/ODDR", GenericValue => DDR_CLK_EDGE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE.", TailMsg => "", MsgSeverity => ERROR ); end if; if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then sr_type <= 1; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then sr_type <= 2; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " SRTYPE ", EntityName => "/ODDR", GenericValue => SRTYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " ASYNC or SYNC. ", TailMsg => "", MsgSeverity => ERROR ); end if; wait; end process prcs_init; --#################################################################### --##### q1_q2_q3 reg ##### --#################################################################### prcs_q1q2q3_reg:process(C_dly, GSR_dly, R_dly, S_dly) variable Q1_var : std_ulogic := TO_X01(INIT); variable Q2_posedge_var : std_ulogic := TO_X01(INIT); begin if(GSR_dly = '1') then Q1_var := TO_X01(INIT); Q2_posedge_var := TO_X01(INIT); elsif(GSR_dly = '0') then case sr_type is when 1 => if(R_dly = '1') then Q1_var := '0'; Q2_posedge_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q1_var := '1'; Q2_posedge_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(rising_edge(C_dly)) then Q1_var := D1_dly; Q2_posedge_var := D2_dly; end if; if(falling_edge(C_dly)) then case ddr_clk_edge_type is when 1 => Q1_var := D2_dly; when 2 => Q1_var := Q2_posedge_var; when others => null; end case; end if; end if; end if; when 2 => if(rising_edge(C_dly)) then if(R_dly = '1') then Q1_var := '0'; Q2_posedge_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q1_var := '1'; Q2_posedge_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then Q1_var := D1_dly; Q2_posedge_var := D2_dly; end if; end if; end if; if(falling_edge(C_dly)) then if(R_dly = '1') then Q1_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then Q1_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then case ddr_clk_edge_type is when 1 => Q1_var := D2_dly; when 2 => Q1_var := Q2_posedge_var; when others => null; end case; end if; end if; end if; when others => null; end case; end if; Q_zd <= Q1_var; end process prcs_q1q2q3_reg; --#################################################################### --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(Q_zd) begin Q <= Q_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end ODDR_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDDRRSE is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end FDDRRSE; architecture FDDRRSE_V of FDDRRSE is begin VITALBehavior : process(C0, C1) variable FIRST_TIME : boolean := true; begin if (FIRST_TIME) then Q <= TO_X01(INIT); FIRST_TIME := false ; end if; if ( rising_edge(C0) = true) then if (R = '1') then Q <= '0' after 100 ps; elsif (S = '1' ) then Q <= '1' after 100 ps; elsif (CE = '1' ) then Q <= D0 after 100 ps; end if; elsif (rising_edge(C1) = true ) then if (R = '1') then Q <= '0' after 100 ps; elsif (S = '1' ) then Q <= '1' after 100 ps; elsif (CE = '1') then Q <= D1 after 100 ps; end if; end if; end process VITALBehavior; end FDDRRSE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity OFDDRRSE is port( Q : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end OFDDRRSE; architecture OFDDRRSE_V of OFDDRRSE is signal Q_out : std_ulogic := 'X'; begin O1 : OBUF port map ( I => Q_out, O => Q ); F0 : FDDRRSE generic map (INIT => '0' ) port map ( C0 => C0, C1 => C1, CE => CE, R => R, D0 => D0, D1 => D1, S => S, Q => Q_out ); end OFDDRRSE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDRSE is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end FDRSE; architecture FDRSE_V of FDRSE is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (R = '1') then Q <= '0' after 100 ps; elsif (S = '1') then Q <= '1' after 100 ps; elsif (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDRSE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity IFDDRRSE is port( Q0 : out std_ulogic; Q1 : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end IFDDRRSE; architecture IFDDRRSE_V of IFDDRRSE is signal D_in : std_ulogic := 'X'; begin I1 : IBUF port map ( I => D, O => D_in ); F0 : FDRSE generic map ( INIT => '0') port map ( C => C0, CE => CE, R => R, D => D_in, S => S, Q => Q0 ); F1 : FDRSE generic map ( INIT => '0') port map ( C => C1, CE => CE, R => R, D => D, S => S, Q => Q1 ); end IFDDRRSE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FD is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic ); end FD; architecture FD_V of FD is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then Q <= D after 100 ps; end if; end process; end FD_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDR is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; R : in std_ulogic ); end FDR; architecture FDR_V of FDR is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (R = '1') then Q <= '0' after 100 ps; else Q <= D after 100 ps; end if; end if; end process; end FDR_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDRE is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; R : in std_ulogic ); end FDRE; architecture FDRE_V of FDRE is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (R = '1') then Q <= '0' after 100 ps; elsif (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDRE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDRS is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end FDRS; architecture FDRS_V of FDRS is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (R = '1') then Q <= '0' after 100 ps; elsif (S = '1') then Q <= '1' after 100 ps; else Q <= D after 100 ps; end if; end if; end process; end FDRS_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity VCC is port( P : out std_ulogic := '1' ); end VCC; architecture VCC_V of VCC is begin P <= '1'; end VCC_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity GND is port( G : out std_ulogic := '0' ); end GND; architecture GND_V of GND is begin G <= '0'; end GND_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXF5 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end MUXF5; architecture MUXF5_V of MUXF5 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; elsif (S = '1') then O <= I1; end if; end process; end MUXF5_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDE is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic ); end FDE; architecture FDE_V of FDE is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity IDELAY is generic( IOBDELAY_TYPE : string := "DEFAULT"; IOBDELAY_VALUE : integer := 0 ); port( O : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; I : in std_ulogic; INC : in std_ulogic; RST : in std_ulogic ); end IDELAY; architecture IDELAY_V OF IDELAY is constant SIM_TAPDELAY_VALUE : integer := 75; --------------------------------------------------------- -- Function str_2_int converts string to integer --------------------------------------------------------- function str_2_int(str: in string ) return integer is variable int : integer; variable val : integer := 0; variable neg_flg : boolean := false; variable is_it_int : boolean := true; begin int := 0; val := 0; is_it_int := true; neg_flg := false; for i in 1 to str'length loop case str(i) is when '-' => if(i = 1) then neg_flg := true; val := -1; end if; when '1' => val := 1; when '2' => val := 2; when '3' => val := 3; when '4' => val := 4; when '5' => val := 5; when '6' => val := 6; when '7' => val := 7; when '8' => val := 8; when '9' => val := 9; when '0' => val := 0; when others => is_it_int := false; end case; if(val /= -1) then int := int *10 + val; end if; val := 0; end loop; if(neg_flg) then int := int * (-1); end if; if(NOT is_it_int) then int := -9999; end if; return int; end; ----------------------------------------------------------- constant SYNC_PATH_DELAY : time := 100 ps; constant MIN_TAP_COUNT : integer := 0; constant MAX_TAP_COUNT : integer := 63; signal C_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal I_ipd : std_ulogic := 'X'; signal INC_ipd : std_ulogic := 'X'; signal RST_ipd : std_ulogic := 'X'; signal C_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal I_dly : std_ulogic := 'X'; signal INC_dly : std_ulogic := 'X'; signal RST_dly : std_ulogic := 'X'; signal O_zd : std_ulogic := 'X'; signal O_viol : std_ulogic := 'X'; signal TapCount : integer := 0; signal IsTapDelay : boolean := true; signal IsTapFixed : boolean := false; signal IsTapDefault : boolean := false; signal Delay : time := 0 ps; begin --------------------- -- INPUT PATH DELAYs -------------------- C_dly <= C after 0 ps; CE_dly <= CE after 0 ps; GSR_dly <= GSR after 0 ps; I_dly <= I after 0 ps; INC_dly <= INC after 0 ps; RST_dly <= RST after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process variable TapCount_var : integer := 0; variable IsTapDelay_var : boolean := true; variable IsTapFixed_var : boolean := false; variable IsTapDefault_var : boolean := false; begin -- if((IOBDELAY_VALUE = "OFF") or (IOBDELAY_VALUE = "off")) then -- IsTapDelay_var := false; -- elsif((IOBDELAY_VALUE = "ON") or (IOBDELAY_VALUE = "on")) then -- IsTapDelay_var := false; -- else -- TapCount_var := str_2_int(IOBDELAY_VALUE); TapCount_var := IOBDELAY_VALUE; If((TapCount_var >= 0) and (TapCount_var <= 63)) then IsTapDelay_var := true; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " IOBDELAY_VALUE ", EntityName => "/IOBDELAY_VALUE", GenericValue => IOBDELAY_VALUE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " OFF, 1, 2, ..., 62, 63 ", TailMsg => "", MsgSeverity => failure ); end if; -- end if; if(IsTapDelay_var) then if((IOBDELAY_TYPE = "FIXED") or (IOBDELAY_TYPE = "fixed")) then IsTapFixed_var := true; elsif((IOBDELAY_TYPE = "VARIABLE") or (IOBDELAY_TYPE = "variable")) then IsTapFixed_var := false; elsif((IOBDELAY_TYPE = "DEFAULT") or (IOBDELAY_TYPE = "default")) then IsTapDefault_var := true; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " IOBDELAY_TYPE ", EntityName => "/IOBDELAY_TYPE", GenericValue => IOBDELAY_TYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " FIXED or VARIABLE ", TailMsg => "", MsgSeverity => failure ); end if; end if; IsTapDelay <= IsTapDelay_var; IsTapFixed <= IsTapFixed_var; IsTapDefault <= IsTapDefault_var; TapCount <= TapCount_var; wait; end process prcs_init; --#################################################################### --##### CALCULATE DELAY ##### --#################################################################### prcs_refclk:process(C_dly, GSR_dly, RST_dly) variable TapCount_var : integer :=0; variable FIRST_TIME : boolean :=true; variable BaseTime_var : time := 1 ps ; variable delay_var : time := 0 ps ; begin if(IsTapDelay) then if((GSR_dly = '1') or (FIRST_TIME))then TapCount_var := TapCount; Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var; FIRST_TIME := false; elsif(GSR_dly = '0') then if(rising_edge(C_dly)) then if(RST_dly = '1') then TapCount_var := TapCount; elsif((RST_dly = '0') and (CE_dly = '1')) then -- CR fix CR 213995 if(INC_dly = '1') then if (TapCount_var < MAX_TAP_COUNT) then TapCount_var := TapCount_var + 1; else TapCount_var := MIN_TAP_COUNT; end if; elsif(INC_dly = '0') then if (TapCount_var > MIN_TAP_COUNT) then TapCount_var := TapCount_var - 1; else TapCount_var := MAX_TAP_COUNT; end if; end if; -- INC_dly end if; -- RST_dly Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var; end if; -- C_dly end if; -- GSR_dly end if; -- IsTapDelay end process prcs_refclk; --#################################################################### --##### DELAY INPUT ##### --#################################################################### prcs_i:process(I_dly) begin if(IsTapFixed) then O_zd <= transport I_dly after (TapCount *SIM_TAPDELAY_VALUE * 1 ps); else O_zd <= transport I_dly after delay; end if; end process prcs_i; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(O_zd) begin O <= O_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end IDELAY_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity IDELAYCTRL is port( RDY : out std_ulogic; REFCLK : in std_ulogic; RST : in std_ulogic ); end IDELAYCTRL; architecture IDELAYCTRL_V OF IDELAYCTRL is constant SYNC_PATH_DELAY : time := 100 ps; signal REFCLK_ipd : std_ulogic := 'X'; signal RST_ipd : std_ulogic := 'X'; signal GSR_dly : std_ulogic := '0'; signal REFCLK_dly : std_ulogic := 'X'; signal RST_dly : std_ulogic := 'X'; signal RDY_zd : std_ulogic := '0'; signal RDY_viol : std_ulogic := 'X'; -- taken from DCM_adv signal period : time := 0 ps; signal lost : std_ulogic := '0'; signal lost_r : std_ulogic := '0'; signal lost_f : std_ulogic := '0'; signal clock_negedge, clock_posedge, clock : std_ulogic; signal temp1 : boolean := false; signal temp2 : boolean := false; signal clock_low, clock_high : std_ulogic := '0'; begin --------------------- -- INPUT PATH DELAYs -------------------- REFCLK_dly <= REFCLK after 0 ps; RST_dly <= RST after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### RDY ##### --#################################################################### prcs_rdy:process(RST_dly, lost) begin if((RST_dly = '1') or (lost = '1')) then RDY_zd <= '0'; elsif((RST_dly = '0') and (lost = '0')) then RDY_zd <= '1'; end if; end process prcs_rdy; --#################################################################### --##### prcs_determine_period ##### --#################################################################### prcs_determine_period : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; begin if (rising_edge(REFCLK_dly)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then period <= NOW - clock_edge_previous; elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then period <= 0 ps; elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps)) then period <= NOW - clock_edge_previous; end if; end if; wait on REFCLK_dly; end process prcs_determine_period; --#################################################################### --##### prcs_clock_lost_checker ##### --#################################################################### prcs_clock_lost_checker : process variable clock_low, clock_high : std_ulogic := '0'; begin if (rising_edge(clock)) then clock_low := '0'; clock_high := '1'; clock_posedge <= '0'; clock_negedge <= '1'; end if; if (falling_edge(clock)) then clock_high := '0'; clock_low := '1'; clock_posedge <= '1'; clock_negedge <= '0'; end if; wait on clock; end process prcs_clock_lost_checker; --#################################################################### --##### prcs_set_reset_lost_r ##### --#################################################################### prcs_set_reset_lost_r : process begin if (rising_edge(clock)) then if (period /= 0 ps) then lost_r <= '0'; end if; wait for (period * 9.1)/10; if ((clock_low /= '1') and (clock_posedge /= '1')) then lost_r <= '1'; end if; end if; wait on clock; end process prcs_set_reset_lost_r; --#################################################################### --##### prcs_assign_lost ##### --#################################################################### prcs_assign_lost : process begin if (lost_r'event) then lost <= lost_r; end if; if (lost_f'event) then lost <= lost_f; end if; wait on lost_r, lost_f; end process prcs_assign_lost; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(RDY_zd) begin RDY <= RDY_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end IDELAYCTRL_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity BUFIO is port( O : out std_ulogic; I : in std_ulogic ); end BUFIO; architecture BUFIO_V of BUFIO is begin O <= I after 0 ps; end BUFIO_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity BUFR is generic( BUFR_DIVIDE : string := "BYPASS"; SIM_DEVICE : string := "VIRTEX4" ); port( O : out std_ulogic; CE : in std_ulogic; CLR : in std_ulogic; I : in std_ulogic ); end BUFR; architecture BUFR_V OF BUFR is -- 06/30/2005 - CR # 211199 -- -- constant SYNC_PATH_DELAY : time := 100 ps; signal CE_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := '0'; signal I_ipd : std_ulogic := 'X'; signal CLR_ipd : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := '0'; signal I_dly : std_ulogic := 'X'; signal CLR_dly : std_ulogic := 'X'; signal O_zd : std_ulogic := 'X'; signal O_viol : std_ulogic := 'X'; signal q4_sig : std_ulogic := 'X'; signal ce_en : std_ulogic; signal divide : boolean := false; signal divide_by : integer := -1; signal FIRST_TOGGLE_COUNT : integer := -1; signal SECOND_TOGGLE_COUNT : integer := -1; begin --------------------- -- INPUT PATH DELAYs -------------------- CE_dly <= CE after 0 ps; CLR_dly <= CLR after 0 ps; GSR_dly <= GSR after 0 ps; I_dly <= I after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process variable FIRST_TOGGLE_COUNT_var : integer := -1; variable SECOND_TOGGLE_COUNT_var : integer := -1; variable ODD : integer := -1; variable divide_var : boolean := false; variable divide_by_var : integer := -1; begin if(BUFR_DIVIDE = "BYPASS") then divide_var := false; elsif(BUFR_DIVIDE = "1") then divide_var := true; divide_by_var := 1; FIRST_TOGGLE_COUNT_var := 1; SECOND_TOGGLE_COUNT_var := 1; elsif(BUFR_DIVIDE = "2") then divide_var := true; divide_by_var := 2; FIRST_TOGGLE_COUNT_var := 2; SECOND_TOGGLE_COUNT_var := 2; elsif(BUFR_DIVIDE = "3") then divide_var := true; divide_by_var := 3; FIRST_TOGGLE_COUNT_var := 2; SECOND_TOGGLE_COUNT_var := 4; elsif(BUFR_DIVIDE = "4") then divide_var := true; divide_by_var := 4; FIRST_TOGGLE_COUNT_var := 4; SECOND_TOGGLE_COUNT_var := 4; elsif(BUFR_DIVIDE = "5") then divide_var := true; divide_by_var := 5; FIRST_TOGGLE_COUNT_var := 4; SECOND_TOGGLE_COUNT_var := 6; elsif(BUFR_DIVIDE = "6") then divide_var := true; divide_by_var := 6; FIRST_TOGGLE_COUNT_var := 6; SECOND_TOGGLE_COUNT_var := 6; elsif(BUFR_DIVIDE = "7") then divide_var := true; divide_by_var := 7; FIRST_TOGGLE_COUNT_var := 6; SECOND_TOGGLE_COUNT_var := 8; elsif(BUFR_DIVIDE = "8") then divide_var := true; divide_by_var := 8; FIRST_TOGGLE_COUNT_var := 8; SECOND_TOGGLE_COUNT_var := 8; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " BUFR_DIVIDE ", EntityName => "/BUFR", GenericValue => BUFR_DIVIDE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8 ", TailMsg => "", MsgSeverity => ERROR ); end if; if (SIM_DEVICE /= "VIRTEX4" and SIM_DEVICE /= "VIRTEX5") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " SIM_DEVICE ", EntityName => "/BUFR", GenericValue => SIM_DEVICE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " VIRTEX4 or VIRTEX5 ", TailMsg => "", MsgSeverity => ERROR ); end if; FIRST_TOGGLE_COUNT <= FIRST_TOGGLE_COUNT_var; SECOND_TOGGLE_COUNT <= SECOND_TOGGLE_COUNT_var; divide <= divide_var; divide_by <= divide_by_var; wait; end process prcs_init; --#################################################################### --##### CLOCK_ENABLE ##### --#################################################################### prcs_ce:process(I_Dly, GSR_dly) variable fall_i_count : integer := 0; variable q4_var : std_ulogic := '0'; variable q3_var : std_ulogic := '0'; variable q2_var : std_ulogic := '0'; variable q1_var : std_ulogic := '0'; begin -- 06/30/2005 - CR # 211199 -- removed CLR_dly dependency if(GSR_dly = '1') then q4_var := '0'; q3_var := '0'; q2_var := '0'; q1_var := '0'; elsif(GSR_dly = '0') then if(falling_edge(I_dly)) then q4_var := q3_var; q3_var := q2_var; q2_var := q1_var; q1_var := CE_dly; end if; q4_sig <= q4_var; end if; end process prcs_ce; ce_en <= CE_dly when (SIM_DEVICE = "VIRTEX5") else q4_sig; --#################################################################### --##### CLK-I ##### --#################################################################### prcs_I:process(I_dly, GSR_dly, CLR_dly, ce_en) variable clk_count : integer := 0; variable toggle_count : integer := 0; variable first : boolean := true; variable FIRST_TIME : boolean := true; begin if(divide) then if((GSR_dly = '1') or (CLR_dly = '1')) then O_zd <= '0'; clk_count := 0; FIRST_TIME := true; elsif((GSR_dly = '0') and (CLR_dly = '0')) then if(ce_en = '1') then if((I_dly='1') and (FIRST_TIME)) then O_zd <= '1'; first := true; toggle_count := FIRST_TOGGLE_COUNT; FIRST_TIME := false; elsif ((I_dly'event) and ( FIRST_TIME = false)) then if(clk_count = toggle_count) then O_zd <= not O_zd; clk_count := 0; first := not first; if(first = true) then toggle_count := FIRST_TOGGLE_COUNT; else toggle_count := SECOND_TOGGLE_COUNT; end if; end if; end if; if (FIRST_TIME = false) then clk_count := clk_count + 1; end if; else clk_count := 0; FIRST_TIME := true; end if; end if; else O_zd <= I_dly; end if; end process prcs_I; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(O_zd) begin -- 06/30/2005 - CR # 211199 -- -- O <= O_zd after SYNC_PATH_DELAY; O <= O_zd; end process prcs_output; --#################################################################### end BUFR_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity ODDR2 is generic( DDR_ALIGNMENT : string := "NONE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port( Q : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end ODDR2; architecture ODDR2_V OF ODDR2 is constant SYNC_PATH_DELAY : time := 100 ps; signal C0_ipd : std_ulogic := 'X'; signal C1_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal D0_ipd : std_ulogic := 'X'; signal D1_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal R_ipd : std_ulogic := 'X'; signal S_ipd : std_ulogic := 'X'; signal C0_dly : std_ulogic := 'X'; signal C1_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal D0_dly : std_ulogic := 'X'; signal D1_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal R_dly : std_ulogic := 'X'; signal S_dly : std_ulogic := 'X'; signal Q_zd : std_ulogic := 'X'; signal Q_viol : std_ulogic := 'X'; signal ddr_alignment_type : integer := -999; signal sr_type : integer := -999; begin --------------------- -- INPUT PATH DELAYs -------------------- C0_dly <= C0 after 0 ps; C1_dly <= C1 after 0 ps; CE_dly <= CE after 0 ps; D0_dly <= D0 after 0 ps; D1_dly <= D1 after 0 ps; GSR_dly <= GSR after 0 ps; R_dly <= R after 0 ps; S_dly <= S after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then ddr_alignment_type <= 1; elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then ddr_alignment_type <= 2; elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then ddr_alignment_type <= 3; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error :", GenericName => " DDR_ALIGNMENT ", EntityName => "/ODDR2", GenericValue => DDR_ALIGNMENT, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " NONE, C0 or C1.", TailMsg => "", MsgSeverity => failure ); end if; if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then sr_type <= 1; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then sr_type <= 2; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error :", GenericName => " SRTYPE ", EntityName => "/ODDR2", GenericValue => SRTYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " ASYNC or SYNC. ", TailMsg => "", MsgSeverity => failure ); end if; wait; end process prcs_init; --#################################################################### --##### functionality ##### --#################################################################### prcs_func_reg:process(C0_dly, C1_dly, GSR_dly, R_dly, S_dly) variable FIRST_TIME : boolean := true; variable q_var : std_ulogic := TO_X01(INIT); variable q_d0_c1_out_var : std_ulogic := TO_X01(INIT); variable q_d1_c0_out_var : std_ulogic := TO_X01(INIT); begin if((GSR_dly = '1') or (FIRST_TIME)) then q_var := TO_X01(INIT); q_d0_c1_out_var := TO_X01(INIT); q_d1_c0_out_var := TO_X01(INIT); FIRST_TIME := false; else case sr_type is when 1 => if(R_dly = '1') then q_var := '0'; q_d0_c1_out_var := '0'; q_d1_c0_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q_var := '1'; q_d0_c1_out_var := '1'; q_d1_c0_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(rising_edge(C0_dly)) then if(ddr_alignment_type = 3) then q_var := q_d0_c1_out_var; else q_var := D0_dly; if(ddr_alignment_type = 2) then q_d1_c0_out_var := D1_dly; end if; end if; end if; if(rising_edge(C1_dly)) then if(ddr_alignment_type = 2) then q_var := q_d1_c0_out_var; else q_var := D1_dly; if(ddr_alignment_type = 3) then q_d0_c1_out_var := D0_dly; end if; end if; end if; end if; end if; when 2 => if(rising_edge(C0_dly)) then if(R_dly = '1') then q_var := '0'; q_d1_c0_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q_var := '1'; q_d1_c0_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(ddr_alignment_type = 3) then q_var := q_d0_c1_out_var; else q_var := D0_dly; if(ddr_alignment_type = 2) then q_d1_c0_out_var := D1_dly; end if; end if; end if; end if; end if; if(rising_edge(C1_dly)) then if(R_dly = '1') then q_var := '0'; q_d0_c1_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q_var := '1'; q_d0_c1_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(ddr_alignment_type = 2) then q_var := q_d1_c0_out_var; else q_var := D1_dly; if(ddr_alignment_type = 3) then q_d0_c1_out_var := D0_dly; end if; end if; end if; end if; end if; when others => null; end case; end if; Q_zd <= q_var; end process prcs_func_reg; --#################################################################### --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(Q_zd) begin Q <= Q_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end ODDR2_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity IDDR2 is generic( DDR_ALIGNMENT : string := "NONE"; INIT_Q0 : bit := '0'; INIT_Q1 : bit := '0'; SRTYPE : string := "SYNC" ); port( Q0 : out std_ulogic; Q1 : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; R : in std_ulogic; S : in std_ulogic ); end IDDR2; architecture IDDR2_V OF IDDR2 is constant SYNC_PATH_DELAY : time := 100 ps; signal C0_ipd : std_ulogic := 'X'; signal C1_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal D_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal R_ipd : std_ulogic := 'X'; signal S_ipd : std_ulogic := 'X'; signal C0_dly : std_ulogic := 'X'; signal C1_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal D_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal R_dly : std_ulogic := 'X'; signal S_dly : std_ulogic := 'X'; signal Q0_zd : std_ulogic := 'X'; signal Q1_zd : std_ulogic := 'X'; signal Q0_viol : std_ulogic := 'X'; signal Q1_viol : std_ulogic := 'X'; signal q0_o_reg : std_ulogic := 'X'; signal q0_c1_o_reg : std_ulogic := 'X'; signal q1_o_reg : std_ulogic := 'X'; signal q1_c0_o_reg : std_ulogic := 'X'; signal ddr_alignment_type : integer := -999; signal sr_type : integer := -999; begin --------------------- -- INPUT PATH DELAYs -------------------- C0_dly <= C0 after 0 ps; C1_dly <= C1 after 0 ps; CE_dly <= CE after 0 ps; D_dly <= D after 0 ps; GSR_dly <= GSR after 0 ps; R_dly <= R after 0 ps; S_dly <= S after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then ddr_alignment_type <= 1; elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then ddr_alignment_type <= 2; elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then ddr_alignment_type <= 3; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error ", GenericName => " DDR_ALIGNMENT ", EntityName => "/IDDR2", GenericValue => DDR_ALIGNMENT, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " NONE or C0 or C1.", TailMsg => "", MsgSeverity => ERROR ); end if; if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then sr_type <= 1; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then sr_type <= 2; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error ", GenericName => " SRTYPE ", EntityName => "/IDDR2", GenericValue => SRTYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " ASYNC or SYNC. ", TailMsg => "", MsgSeverity => ERROR ); end if; wait; end process prcs_init; --#################################################################### --##### functionality ##### --#################################################################### prcs_func_reg:process(C0_dly, C1_dly, D_dly, GSR_dly, R_dly, S_dly) variable FIRST_TIME : boolean := true; variable q0_out_var : std_ulogic := TO_X01(INIT_Q0); variable q1_out_var : std_ulogic := TO_X01(INIT_Q1); variable q0_c1_out_var : std_ulogic := TO_X01(INIT_Q0); variable q1_c0_out_var : std_ulogic := TO_X01(INIT_Q1); begin if((GSR_dly = '1') or (FIRST_TIME)) then q0_out_var := TO_X01(INIT_Q0); q1_out_var := TO_X01(INIT_Q1); q0_c1_out_var := TO_X01(INIT_Q0); q1_c0_out_var := TO_X01(INIT_Q1); FIRST_TIME := false; else case sr_type is when 1 => if(R_dly = '1') then q0_out_var := '0'; q1_out_var := '0'; q1_c0_out_var := '0'; q0_c1_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q0_out_var := '1'; q1_out_var := '1'; q1_c0_out_var := '1'; q0_c1_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then if(rising_edge(C0_dly)) then q0_out_var := D_dly; q1_c0_out_var := q1_out_var; end if; if(rising_edge(C1_dly)) then q1_out_var := D_dly; q0_c1_out_var := q0_out_var; end if; end if; end if; when 2 => if(rising_edge(C0_dly)) then if(R_dly = '1') then q0_out_var := '0'; q1_c0_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q0_out_var := '1'; q1_c0_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then q0_out_var := D_dly; q1_c0_out_var := q1_out_var; end if; end if; end if; if(rising_edge(C1_dly)) then if(R_dly = '1') then q1_out_var := '0'; q0_c1_out_var := '0'; elsif((R_dly = '0') and (S_dly = '1')) then q1_out_var := '1'; q0_c1_out_var := '1'; elsif((R_dly = '0') and (S_dly = '0')) then if(CE_dly = '1') then q1_out_var := D_dly; q0_c1_out_var := q0_out_var; end if; end if; end if; when others => null; end case; end if; q0_o_reg <= q0_out_var; q1_o_reg <= q1_out_var; q0_c1_o_reg <= q0_c1_out_var; q1_c0_o_reg <= q1_c0_out_var; end process prcs_func_reg; --#################################################################### --##### output mux ##### --#################################################################### prcs_output_mux:process(q0_o_reg, q1_o_reg, q0_c1_o_reg, q1_c0_o_reg) begin case ddr_alignment_type is when 1 => Q0_zd <= q0_o_reg; Q1_zd <= q1_o_reg; when 2 => Q0_zd <= q0_o_reg; Q1_zd <= q1_c0_o_reg; when 3 => Q0_zd <= q0_c1_o_reg; Q1_zd <= q1_o_reg; when others => null; end case; end process prcs_output_mux; --#################################################################### --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(Q0_zd, Q1_zd) begin Q0 <= Q0_zd after SYNC_PATH_DELAY; Q1 <= Q1_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end IDDR2_V; ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 9.1i -- \ \ Description : Xilinx Timing Simulation Library Component -- / / Digital Clock Manager -- /___/ /\ Filename : X_DCM.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. -- 05/11/05 - Add clkin alignment check control to remove the glitch when -- clkin stopped. (CR207409). -- 05/25/05 - Seperate clock_second_pos and neg to another process due to -- wait caused unreset. Set fb_delay_found after fb_delay computed. -- Enable clkfb_div after lock_fb high (CR 208771) -- 06/03/05 - Use after instead wait for clk0_out(CR209283). -- Update error message (CR 209076). -- 07/06/05 - Add lock_fb_dly to alignment check. (CR210755). -- Use counter to generate clkdv_out to align with clk0_out. (CR211465). -- 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). -- 08/30/05 - Change reset for CLK270, CLK180 (CR 213641). -- 09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828). -- 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) -- 02/28/06 - Remove 1 ps in clkfx_out block to support fs resolution (CR222390) -- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR418722). -- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). -- 04/06/07 - Enable the clock out in clock low time after reset in model -- clock_divide_by_2 (CR 437471). -- End Revision ----- x_dcm_clock_divide_by_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; entity x_dcm_clock_divide_by_2 is port( clock_out : out std_ulogic := '0'; clock : in std_ulogic; clock_type : in integer; rst : in std_ulogic ); end x_dcm_clock_divide_by_2; architecture x_dcm_clock_divide_by_2_V of x_dcm_clock_divide_by_2 is signal clock_div2 : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0); signal clk_src : std_ulogic; begin CLKIN_DIVIDER : process begin if (rising_edge(clock)) then clock_div2 <= not clock_div2; end if; wait on clock; end process CLKIN_DIVIDER; gen_reset : process begin if (rising_edge(clock)) then rst_reg(0) <= rst; rst_reg(1) <= rst_reg(0) and rst; rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst; end if; wait on clock; end process gen_reset; clk_src <= clock_div2 when (clock_type = 1) else clock; assign_clkout : process begin if (rst = '0') then clock_out <= clk_src; elsif (rst = '1') then clock_out <= '0'; wait until falling_edge(rst_reg(2)); if (clk_src = '1') then wait until falling_edge(clk_src); end if; end if; wait on clk_src, rst, rst_reg; end process assign_clkout; end x_dcm_clock_divide_by_2_V; ----- x_dcm_maximum_period_check ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library STD; use STD.TEXTIO.all; entity x_dcm_maximum_period_check is generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end x_dcm_maximum_period_check; architecture x_dcm_maximum_period_check_V of x_dcm_maximum_period_check is begin MAX_PERIOD_CHECKER : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; variable clock_period : time := 0 ps; variable Message : line; begin if (rising_edge(clock)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (clock_edge_previous > 0 ps) then clock_period := clock_edge_current - clock_edge_previous; end if; if (clock_period > maximum_period and rst = '0') then Write ( Message, string'(" Warning : Input Clock Period of ")); Write ( Message, clock_period ); Write ( Message, string'(" on the ") ); Write ( Message, clock_name ); Write ( Message, string'(" port ") ); Write ( Message, string'(" of X_DCM instance ") ); Write ( Message, string'(" exceeds allowed value of ") ); Write ( Message, maximum_period ); Write ( Message, string'(" at simulation time ") ); Write ( Message, clock_edge_current ); Write ( Message, '.' & LF ); assert false report Message.all severity warning; DEALLOCATE (Message); end if; end if; wait on clock; end process MAX_PERIOD_CHECKER; end x_dcm_maximum_period_check_V; ----- x_dcm_clock_lost ----- library IEEE; use IEEE.STD_LOGIC_1164.all; entity x_dcm_clock_lost is port( lost : out std_ulogic := '0'; clock : in std_ulogic; enable : in boolean := false; rst : in std_ulogic ); end x_dcm_clock_lost; architecture x_dcm_clock_lost_V of x_dcm_clock_lost is signal period : time := 0 ps; signal lost_r : std_ulogic := '0'; signal lost_f : std_ulogic := '0'; signal lost_sig : std_ulogic := '0'; signal clock_negedge, clock_posedge : std_ulogic; signal clock_low, clock_high : std_ulogic := '0'; signal clock_second_pos, clock_second_neg : std_ulogic := '0'; begin determine_period : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; begin if (rst = '1') then period <= 0 ps; elsif (rising_edge(clock)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then period <= NOW - clock_edge_previous; elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then period <= 0 ps; elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then period <= NOW - clock_edge_previous; end if; end if; wait on clock, rst; end process determine_period; CLOCK_LOST_CHECKER : process begin if (rst = '1') then clock_low <= '0'; clock_high <= '0'; clock_posedge <= '0'; clock_negedge <= '0'; else if (rising_edge(clock)) then clock_low <= '0'; clock_high <= '1'; clock_posedge <= '0'; clock_negedge <= '1'; end if; if (falling_edge(clock)) then clock_high <= '0'; clock_low <= '1'; clock_posedge <= '1'; clock_negedge <= '0'; end if; end if; wait on clock, rst; end process CLOCK_LOST_CHECKER; CLOCK_SECOND_P : process begin if (rst = '1') then clock_second_pos <= '0'; clock_second_neg <= '0'; else if (rising_edge(clock)) then clock_second_pos <= '1'; end if; if (falling_edge(clock)) then clock_second_neg <= '1'; end if; end if; wait on clock, rst; end process CLOCK_SECOND_P; SET_RESET_LOST_R : process begin if (rst = '1') then lost_r <= '0'; else if ((enable = true) and (clock_second_pos = '1'))then if (rising_edge(clock)) then wait for 1 ps; if (period /= 0 ps) then lost_r <= '0'; end if; wait for (period * (9.1/10.0)); if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then lost_r <= '1'; end if; end if; end if; end if; wait on clock, rst; end process SET_RESET_LOST_R; SET_RESET_LOST_F : process begin if (rst = '1') then lost_f <= '0'; else if ((enable = true) and (clock_second_neg = '1'))then if (falling_edge(clock)) then if (period /= 0 ps) then lost_f <= '0'; end if; wait for (period * (9.1/10.0)); if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then lost_f <= '1'; end if; end if; end if; end if; wait on clock, rst; end process SET_RESET_LOST_F; assign_lost : process begin if (enable = true) then if (lost_r'event) then lost <= lost_r; end if; if (lost_f'event) then lost <= lost_f; end if; end if; wait on lost_r, lost_f; end process assign_lost; end x_dcm_clock_lost_V; ----- CELL X_DCM ----- library IEEE; use IEEE.std_logic_1164.all; library IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.vpkg.all; entity X_DCM is generic ( TimingChecksOn : boolean := true; InstancePath : string := "*"; Xon : boolean := true; MsgOn : boolean := false; LOC : string := "UNPLACED"; thold_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; ticd_PSCLK : VitalDelayType := 0.000 ns; tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DSSEN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSCLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSEN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSINCDEC : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns); tisd_PSINCDEC_PSCLK : VitalDelayType := 0.000 ns; tisd_PSEN_PSCLK : VitalDelayType := 0.000 ns; tpd_CLKIN_LOCKED : VitalDelayType01 := (0.100 ns, 0.100 ns); tpd_PSCLK_PSDONE : VitalDelayType01 := (0.100 ns, 0.100 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns; tperiod_PSCLK_POSEDGE : VitalDelayType := 0.000 ns; tpw_CLKIN_negedge : VitalDelayType := 0.000 ns; tpw_CLKIN_posedge : VitalDelayType := 0.000 ns; tpw_PSCLK_negedge : VitalDelayType := 0.000 ns; tpw_PSCLK_posedge : VitalDelayType := 0.000 ns; tpw_RST_posedge : VitalDelayType := 0.000 ns; tsetup_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; --non-simulatable CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; --non-simulatable DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; --non-simulatable MAXPERCLKIN : time := 1000000 ps; --non-modifiable simulation parameter MAXPERPSCLK : time := 100000000 ps; --non-modifiable simulation parameter PHASE_SHIFT : integer := 0; SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --non-modifiable simulation parameter SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --non-modifiable simulation parameter STARTUP_WAIT : boolean := false --non-simulatable ); port ( CLK0 : out std_ulogic := '0'; CLK180 : out std_ulogic := '0'; CLK270 : out std_ulogic := '0'; CLK2X : out std_ulogic := '0'; CLK2X180 : out std_ulogic := '0'; CLK90 : out std_ulogic := '0'; CLKDV : out std_ulogic := '0'; CLKFX : out std_ulogic := '0'; CLKFX180 : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; PSDONE : out std_ulogic := '0'; STATUS : out std_logic_vector(7 downto 0) := "00000000"; CLKFB : in std_ulogic := '0'; CLKIN : in std_ulogic := '0'; DSSEN : in std_ulogic := '0'; PSCLK : in std_ulogic := '0'; PSEN : in std_ulogic := '0'; PSINCDEC : in std_ulogic := '0'; RST : in std_ulogic := '0' ); attribute VITAL_LEVEL0 of X_DCM : entity is true; end X_DCM; architecture X_DCM_V of X_DCM is component x_dcm_clock_divide_by_2 port( clock_out : out std_ulogic; clock : in std_ulogic; clock_type : in integer; rst : in std_ulogic ); end component; component x_dcm_maximum_period_check generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end component; component x_dcm_clock_lost port( lost : out std_ulogic; clock : in std_ulogic; enable : in boolean := false; rst : in std_ulogic ); end component; signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic; signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic; signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0'; signal clk0_out : std_ulogic; signal clk2x_out, clkdv_out : std_ulogic := '0'; signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0'; signal locked_out_out : std_ulogic := '0'; signal LOCKED_sig : std_ulogic := '0'; signal clkdv_cnt : integer := 0; signal clkfb_type : integer; signal divide_type : integer; signal clkin_type : integer; signal ps_type : integer; signal deskew_adjust_mode : integer; signal dfs_mode_type : integer; signal dll_mode_type : integer; signal clk1x_type : integer; signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; signal lock_out : std_logic_vector(1 downto 0) := "00"; signal lock_out1_neg : std_ulogic := '0'; signal lock_fb : std_ulogic := '0'; signal lock_fb_dly : std_ulogic := '0'; signal lock_fb_dly_tmp : std_ulogic := '0'; signal fb_delay_found : std_ulogic := '0'; signal clkin_div : std_ulogic; signal clkin_ps : std_ulogic; signal clkin_fb : std_ulogic; signal ps_delay : time := 0 ps; signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns); signal period : time := 0 ps; signal period_div : time := 0 ps; signal period_orig : time := 0 ps; signal period_ps : time := 0 ps; signal clkout_delay : time := 0 ps; signal fb_delay : time := 0 ps; signal period_fx, remain_fx : time := 0 ps; signal period_dv_high, period_dv_low : time := 0 ps; signal cycle_jitter, period_jitter : time := 0 ps; signal clkin_window, clkfb_window : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0) := "000"; signal rst_flag : std_ulogic := '0'; signal numerator, denominator, gcd : integer := 1; signal clkin_lost_out : std_ulogic := '0'; signal clkfx_lost_out : std_ulogic := '0'; signal remain_fx_temp : integer := 0; signal clkin_period_real0_temp : time := 0 ps; signal ps_lock_reg : std_ulogic := '0'; signal clk0_sig : std_ulogic := '0'; signal clk2x_sig : std_ulogic := '0'; signal no_stop : boolean := false; signal clkfx180_en : std_ulogic := '0'; signal status_out : std_logic_vector(7 downto 0) := "00000000"; signal first_time_locked : boolean := false; signal en_status : boolean := false; signal ps_overflow_out_ext : std_ulogic := '0'; signal clkin_lost_out_ext : std_ulogic := '0'; signal clkfx_lost_out_ext : std_ulogic := '0'; signal clkfb_div : std_ulogic := '0'; signal clkfb_div_en : std_ulogic := '0'; signal clkfb_chk : std_ulogic := '0'; signal lock_period_dly : std_ulogic := '0'; signal lock_period_pulse : std_ulogic := '0'; signal clock_stopped : std_ulogic := '1'; signal clkin_chkin, clkfb_chkin : std_ulogic := '0'; signal chk_enable, chk_rst : std_ulogic := '0'; signal lock_ps : std_ulogic := '0'; signal lock_ps_dly : std_ulogic := '0'; begin INITPROC : process begin detect_resolution (model_name => "X_DCM" ); if (CLKDV_DIVIDE = 1.5) then divide_type <= 3; elsif (CLKDV_DIVIDE = 2.0) then divide_type <= 4; elsif (CLKDV_DIVIDE = 2.5) then divide_type <= 5; elsif (CLKDV_DIVIDE = 3.0) then divide_type <= 6; elsif (CLKDV_DIVIDE = 3.5) then divide_type <= 7; elsif (CLKDV_DIVIDE = 4.0) then divide_type <= 8; elsif (CLKDV_DIVIDE = 4.5) then divide_type <= 9; elsif (CLKDV_DIVIDE = 5.0) then divide_type <= 10; elsif (CLKDV_DIVIDE = 5.5) then divide_type <= 11; elsif (CLKDV_DIVIDE = 6.0) then divide_type <= 12; elsif (CLKDV_DIVIDE = 6.5) then divide_type <= 13; elsif (CLKDV_DIVIDE = 7.0) then divide_type <= 14; elsif (CLKDV_DIVIDE = 7.5) then divide_type <= 15; elsif (CLKDV_DIVIDE = 8.0) then divide_type <= 16; elsif (CLKDV_DIVIDE = 9.0) then divide_type <= 18; elsif (CLKDV_DIVIDE = 10.0) then divide_type <= 20; elsif (CLKDV_DIVIDE = 11.0) then divide_type <= 22; elsif (CLKDV_DIVIDE = 12.0) then divide_type <= 24; elsif (CLKDV_DIVIDE = 13.0) then divide_type <= 26; elsif (CLKDV_DIVIDE = 14.0) then divide_type <= 28; elsif (CLKDV_DIVIDE = 15.0) then divide_type <= 30; elsif (CLKDV_DIVIDE = 16.0) then divide_type <= 32; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKDV_DIVIDE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLKDV_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKFX_DIVIDE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLKFX_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1....32", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKFX_MULTIPLY", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLKFX_MULTIPLY, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 2....32", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; case CLKIN_DIVIDE_BY_2 is when false => clkin_type <= 0; when true => clkin_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKIN_DIVIDE_BY_2", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLKIN_DIVIDE_BY_2, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_type <= 0; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_type <= 1; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_type <= 2; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKOUT_PHASE_SHIFT", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLKOUT_PHASE_SHIFT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then clkfb_type <= 0; elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then clkfb_type <= 1; elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then clkfb_type <= 2; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLK_FEEDBACK", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => CLK_FEEDBACK, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then DESKEW_ADJUST_mode <= 8; elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then DESKEW_ADJUST_mode <= 11; elsif ((DESKEW_ADJUST = "0")) then DESKEW_ADJUST_mode <= 0; elsif ((DESKEW_ADJUST = "1")) then DESKEW_ADJUST_mode <= 1; elsif ((DESKEW_ADJUST = "2")) then DESKEW_ADJUST_mode <= 2; elsif ((DESKEW_ADJUST = "3")) then DESKEW_ADJUST_mode <= 3; elsif ((DESKEW_ADJUST = "4")) then DESKEW_ADJUST_mode <= 4; elsif ((DESKEW_ADJUST = "5")) then DESKEW_ADJUST_mode <= 5; elsif ((DESKEW_ADJUST = "6")) then DESKEW_ADJUST_mode <= 6; elsif ((DESKEW_ADJUST = "7")) then DESKEW_ADJUST_mode <= 7; elsif ((DESKEW_ADJUST = "8")) then DESKEW_ADJUST_mode <= 8; elsif ((DESKEW_ADJUST = "9")) then DESKEW_ADJUST_mode <= 9; elsif ((DESKEW_ADJUST = "10")) then DESKEW_ADJUST_mode <= 10; elsif ((DESKEW_ADJUST = "11")) then DESKEW_ADJUST_mode <= 11; elsif ((DESKEW_ADJUST = "12")) then DESKEW_ADJUST_mode <= 12; elsif ((DESKEW_ADJUST = "13")) then DESKEW_ADJUST_mode <= 13; elsif ((DESKEW_ADJUST = "14")) then DESKEW_ADJUST_mode <= 14; elsif ((DESKEW_ADJUST = "15")) then DESKEW_ADJUST_mode <= 15; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DESKEW_ADJUST_MODE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => DESKEW_ADJUST_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then dfs_mode_type <= 1; elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then dfs_mode_type <= 0; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DFS_FREQUENCY_MODE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => DFS_FREQUENCY_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then dll_mode_type <= 1; elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then dll_mode_type <= 0; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DLL_FREQUENCY_MODE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => DLL_FREQUENCY_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DSS_MODE", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => DSS_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; case DUTY_CYCLE_CORRECTION is when false => clk1x_type <= 0; when true => clk1x_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DUTY_CYCLE_CORRECTION", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => DUTY_CYCLE_CORRECTION, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "PHASE_SHIFT", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => PHASE_SHIFT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; period_jitter <= SIM_CLKIN_PERIOD_JITTER; cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; case STARTUP_WAIT is when false => null; when true => null; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "STARTUP_WAIT", EntityName => "X_DCM", InstanceName => InstancePath, GenericValue => STARTUP_WAIT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; -- -- fx parameters -- gcd <= 1; for i in 2 to CLKFX_MULTIPLY loop if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then gcd <= i; end if; end loop; numerator <= CLKFX_MULTIPLY / gcd; denominator <= CLKFX_DIVIDE / gcd; wait; end process INITPROC; -- -- input wire delays -- WireDelay : block begin VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN); VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB); VitalWireDelay (DSSEN_ipd, DSSEN, tipd_DSSEN); VitalWireDelay (PSCLK_ipd, PSCLK, tipd_PSCLK); VitalWireDelay (PSEN_ipd, PSEN, tipd_PSEN); VitalWireDelay (PSINCDEC_ipd, PSINCDEC, tipd_PSINCDEC); VitalWireDelay (RST_ipd, RST, tipd_RST); end block; SignalDelay : block begin VitalSignalDelay (PSCLK_dly, PSCLK_ipd, ticd_PSCLK); VitalSignalDelay (PSEN_dly, PSEN_ipd, tisd_PSEN_PSCLK); VitalSignalDelay (PSINCDEC_dly, PSINCDEC_ipd, tisd_PSINCDEC_PSCLK); end block; i_clock_divide_by_2 : x_dcm_clock_divide_by_2 port map ( clock => clkin_ipd, clock_type => clkin_type, rst => rst_ipd, clock_out => clkin_div); i_max_clkin : x_dcm_maximum_period_check generic map ( clock_name => "CLKIN", maximum_period => MAXPERCLKIN) port map ( clock => clkin_ipd, rst => rst_ipd); i_max_psclk : x_dcm_maximum_period_check generic map ( clock_name => "PSCLK", maximum_period => MAXPERPSCLK) port map ( clock => psclk_dly, rst => rst_ipd); i_clkin_lost : x_dcm_clock_lost port map ( lost => clkin_lost_out, clock => clkin_ipd, enable => first_time_locked, rst => rst_ipd ); i_clkfx_lost : x_dcm_clock_lost port map ( lost => clkfx_lost_out, clock => clkfx_out, enable => first_time_locked, rst => rst_ipd ); clkin_ps <= transport clkin_div after ps_delay; clkin_fb <= transport (clkin_ps and lock_fb); detect_first_time_locked : process begin if (first_time_locked = false) then if (rising_edge(locked_out)) then first_time_locked <= true; end if; end if; wait on locked_out; end process detect_first_time_locked; set_reset_en_status : process begin if (rst_ipd = '1') then en_status <= false; elsif (rising_edge(Locked_sig)) then en_status <= true; end if; wait on rst_ipd, Locked_sig; end process set_reset_en_status; gen_clkfb_div_en: process begin if (rst_ipd = '1') then clkfb_div_en <= '0'; elsif (falling_edge(clkfb_ipd)) then if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then clkfb_div_en <= '1'; end if; end if; wait on clkfb_ipd, rst_ipd; end process gen_clkfb_div_en; gen_clkfb_div: process begin if (rst_ipd = '1') then clkfb_div <= '0'; elsif (rising_edge(clkfb_ipd)) then if (clkfb_div_en='1') then clkfb_div <= not clkfb_div; end if; end if; wait on clkfb_ipd, rst_ipd; end process gen_clkfb_div; determine_clkfb_chk: process begin if (clkfb_type = 2) then clkfb_chk <= clkfb_div; else clkfb_chk <= clkfb_ipd and lock_fb_dly; end if; wait on clkfb_ipd, clkfb_div; end process determine_clkfb_chk; set_reset_clkin_chkin : process begin if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then if (chk_rst = '1') then clkin_chkin <= '0'; else clkin_chkin <= '1'; end if; end if; wait on clkin_fb, chk_rst; end process set_reset_clkin_chkin; set_reset_clkfb_chkin : process begin if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then if (chk_rst = '1') then clkfb_chkin <= '0'; else clkfb_chkin <= '1'; end if; end if; wait on clkfb_chk, chk_rst; end process set_reset_clkfb_chkin; -- assign_chk_rst: process -- begin -- if ((rst_ipd = '1') or (clock_stopped = '1')) then -- chk_rst <= '1'; -- else -- chk_rst <= '0'; -- end if; -- wait on rst_ipd, clock_stopped; -- end process assign_chk_rst; chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0'; -- assign_chk_enable: process -- begin -- if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then -- chk_enable <= '1'; -- else -- chk_enable <= '0'; -- end if; -- wait on clkin_chkin, clkfb_chkin; -- end process assign_chk_enable; chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0'; control_status_bits: process begin if ((rst_ipd = '1') or (en_status = false)) then ps_overflow_out_ext <= '0'; clkin_lost_out_ext <= '0'; clkfx_lost_out_ext <= '0'; else ps_overflow_out_ext <= ps_overflow_out; clkin_lost_out_ext <= clkin_lost_out; clkfx_lost_out_ext <= clkfx_lost_out; end if; wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd; end process control_status_bits; determine_period_div : process variable clkin_div_edge_previous : time := 0 ps; variable clkin_div_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_div_edge_previous := 0 ps; clkin_div_edge_current := 0 ps; period_div <= 0 ps; else if (rising_edge(clkin_div)) then clkin_div_edge_previous := clkin_div_edge_current; clkin_div_edge_current := NOW; if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then period_div <= clkin_div_edge_current - clkin_div_edge_previous; elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then period_div <= clkin_div_edge_current - clkin_div_edge_previous; end if; end if; end if; wait on clkin_div, rst_ipd; end process determine_period_div; determine_period_ps : process variable clkin_ps_edge_previous : time := 0 ps; variable clkin_ps_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_ps_edge_previous := 0 ps; clkin_ps_edge_current := 0 ps; period_ps <= 0 ps; else if (rising_edge(clkin_ps)) then clkin_ps_edge_previous := clkin_ps_edge_current; clkin_ps_edge_current := NOW; wait for 0 ps; if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; end if; end if; end if; wait on clkin_ps, rst_ipd; end process determine_period_ps; assign_lock_ps_fb : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_fb <= '0'; lock_ps <= '0'; lock_ps_dly <= '0'; lock_fb_dly <= '0'; lock_fb_dly_tmp <= '0'; else if (rising_edge(clkin_ps)) then lock_ps <= lock_period; lock_ps_dly <= lock_ps; lock_fb <= lock_ps_dly; lock_fb_dly_tmp <= lock_fb; end if; if (falling_edge(clkin_ps)) then lock_fb_dly <= lock_fb_dly_tmp after (period/4); end if; end if; wait on clkin_ps, rst_ipd; end process assign_lock_ps_fb; calculate_clkout_delay : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkout_delay <= 0 ps; elsif (fb_delay = 0 ps) then clkout_delay <= 0 ps; elsif (period'event or fb_delay'event) then clkout_delay <= period - fb_delay; end if; wait on period, fb_delay, rst_ipd; end process calculate_clkout_delay; -- --generate master reset signal -- gen_master_rst : process begin if (rising_edge(clkin_ipd)) then rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; rst_reg(1) <= rst_reg(0) and rst_ipd; rst_reg(0) <= rst_ipd; end if; wait on clkin_ipd; end process gen_master_rst; check_rst_width : process variable Message : line; begin if (rst_ipd ='1') then rst_flag <= '0'; end if; if (falling_edge(rst_ipd)) then if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then rst_flag <= '1'; Write ( Message, string'(" Input Error : RST on X_DCM ")); Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); assert false report Message.all severity error; DEALLOCATE (Message); end if; end if; wait on rst_ipd; end process check_rst_width; -- --phase shift parameters -- determine_phase_shift : process variable Message : line; variable FINE_SHIFT_RANGE : time; variable first_time : boolean := true; variable ps_in : integer; begin if (first_time = true) then if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_in := 256; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_in := 256 + PHASE_SHIFT; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_in := 256 + PHASE_SHIFT; end if; first_time := false; end if; if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_in := 256; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_in := 256 + PHASE_SHIFT; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_in := 256 + PHASE_SHIFT; else end if; ps_lock <= '0'; ps_overflow_out <= '0'; ps_delay <= 0 ps; else if (rising_edge (lock_period)) then if (ps_type = 1) then FINE_SHIFT_RANGE := 10000 ps; elsif (ps_type = 2) then FINE_SHIFT_RANGE := 5000 ps; end if; if (PHASE_SHIFT > 0) then if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then Write ( Message, string'(" Function Error : Instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" Requested Phase Shift = ")); Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); Write ( Message, PHASE_SHIFT); Write ( Message, string'(" * ")); Write ( Message, period_orig / 256); Write ( Message, string'(" = ")); Write ( Message, (PHASE_SHIFT) * period_orig / 256 ); Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); Write ( Message, FINE_SHIFT_RANGE); assert false report Message.all severity error; DEALLOCATE (Message); end if; elsif (PHASE_SHIFT < 0) then if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then Write ( Message, string'(" Function Error : Instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" Requested Phase Shift = ")); Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); Write ( Message, PHASE_SHIFT); Write ( Message, string'(" * ")); Write ( Message, period_orig / 256); Write ( Message, string'(" = ")); Write ( Message, (-PHASE_SHIFT) * period_orig / 256 ); Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); Write ( Message, FINE_SHIFT_RANGE); assert false report Message.all severity error; DEALLOCATE (Message); end if; end if; end if; if (rising_edge(lock_period_pulse)) then ps_delay <= (ps_in * period_div / 256); end if; if (rising_edge(PSCLK_dly)) then if (ps_type = 2) then if (psen_dly = '1') then if (ps_lock = '1') then Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); assert false report Message.all severity warning; DEALLOCATE (Message); else if (psincdec_dly = '1') then if (ps_in = 511) then ps_overflow_out <= '1'; elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then ps_overflow_out <= '1'; else ps_in := ps_in + 1; ps_delay <= (ps_in * period_div / 256); ps_overflow_out <= '0'; end if; ps_lock <= '1'; elsif (psincdec_dly = '0') then if (ps_in = 1) then ps_overflow_out <= '1'; elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then ps_overflow_out <= '1'; else ps_in := ps_in - 1; ps_delay <= (ps_in * period_div / 256); ps_overflow_out <= '0'; end if; ps_lock <= '1'; end if; end if; end if; end if; end if; end if; if (ps_lock_reg'event) then ps_lock <= ps_lock_reg; end if; wait on lock_period, lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd; end process determine_phase_shift; determine_psdone_out : process begin if (rising_edge(ps_lock)) then ps_lock_reg <= '1'; wait until (rising_edge(clkin_ps)); wait until (rising_edge(psclk_dly)); wait until (rising_edge(psclk_dly)); wait until (rising_edge(psclk_dly)); psdone_out <= '1'; wait until (rising_edge(psclk_dly)); psdone_out <= '0'; ps_lock_reg <= '0'; end if; wait on ps_lock; end process determine_psdone_out; -- --determine clock period -- determine_clock_period : process variable clkin_edge_previous : time := 0 ps; variable clkin_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_period_real(0) <= 0 ps; clkin_period_real(1) <= 0 ps; clkin_period_real(2) <= 0 ps; clkin_edge_previous := 0 ps; clkin_edge_current := 0 ps; elsif (rising_edge(clkin_div)) then clkin_edge_previous := clkin_edge_current; clkin_edge_current := NOW; clkin_period_real(2) <= clkin_period_real(1); clkin_period_real(1) <= clkin_period_real(0); if (clkin_edge_previous /= 0 ps) then clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; end if; end if; if (no_stop'event) then clkin_period_real(0) <= clkin_period_real0_temp; end if; wait on clkin_div, no_stop, rst_ipd; end process determine_clock_period; evaluate_clock_period : process variable Message : line; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_period <= '0'; clock_stopped <= '1'; clkin_period_real0_temp <= 0 ps; else if (falling_edge(clkin_div)) then if (lock_period = '0') then if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then lock_period <= '1'; period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; period <= clkin_period_real(0); end if; elsif (lock_period = '1') then if (100000000 ns < clkin_period_real(0)) then Write ( Message, string'(" Warning : CLKIN stopped toggling on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, string'(" 100 ms ")); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0)); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then clkin_period_real0_temp <= clkin_period_real(1); no_stop <= not no_stop; clock_stopped <= '1'; elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then Write ( Message, string'(" Warning : Input Clock Period Jitter on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, period_jitter ); Write ( Message, string'(" Locked CLKIN Period = ")); Write ( Message, period_orig ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, cycle_jitter ); Write ( Message, string'(" Previous CLKIN Period = ")); Write ( Message, clkin_period_real(1) ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); else period <= clkin_period_real(0); clock_stopped <= '0'; end if; end if; end if; end if; wait on clkin_div, rst_ipd; end process evaluate_clock_period; lock_period_dly <= transport lock_period after period/2; -- determine_lock_period_pulse: process -- begin -- if ((lock_period = '1') and (lock_period_dly = '0')) then -- lock_period_pulse <= '1'; -- else -- lock_period_pulse <= '0'; -- end if; -- wait on lock_period, lock_period_dly; -- end process determine_lock_period_pulse; lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0'; -- --determine clock delay -- determine_clock_delay : process variable delay_edge : time := 0 ps; variable temp1 : integer := 0; variable temp2 : integer := 0; variable temp : integer := 0; variable delay_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then fb_delay <= 0 ps; fb_delay_found <= '0'; else if (rising_edge(lock_ps_dly)) then if ((lock_period = '1') and (clkfb_type /= 0)) then if (clkfb_type = 1) then wait until ((rising_edge(clk0_sig)) or (rst_ipd'event)); delay_edge := NOW; elsif (clkfb_type = 2) then wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event)); delay_edge := NOW; end if; wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); temp2 := (period_orig * 1)/ (1 ps); temp := temp1 mod temp2; fb_delay <= temp * 1 ps; fb_delay_found <= '1'; end if; end if; end if; wait on lock_ps_dly, rst_ipd; end process determine_clock_delay; -- -- determine feedback lock -- GEN_CLKFB_WINDOW : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkfb_window <= '0'; else if (rising_edge(clkfb_chk)) then wait for 0 ps; clkfb_window <= '1'; wait for cycle_jitter; clkfb_window <= '0'; end if; end if; wait on clkfb_chk, rst_ipd; end process GEN_CLKFB_WINDOW; GEN_CLKIN_WINDOW : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_window <= '0'; else if (rising_edge(clkin_fb)) then wait for 0 ps; clkin_window <= '1'; wait for cycle_jitter; clkin_window <= '0'; end if; end if; wait on clkin_fb, rst_ipd; end process GEN_CLKIN_WINDOW; set_reset_lock_clkin : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_clkin <= '0'; else if (rising_edge(clkin_fb)) then wait for 1 ps; if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then lock_clkin <= '1'; else if (chk_enable = '1') then lock_clkin <= '0'; end if; end if; end if; end if; wait on clkin_fb, rst_ipd; end process set_reset_lock_clkin; set_reset_lock_clkfb : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_clkfb <= '0'; else if (rising_edge(clkfb_chk)) then wait for 1 ps; if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then lock_clkfb <= '1'; else if (chk_enable = '1') then lock_clkfb <= '0'; end if; end if; end if; end if; wait on clkfb_chk, rst_ipd; end process set_reset_lock_clkfb; assign_lock_delay : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_delay <= '0'; else if (falling_edge(clkin_fb)) then lock_delay <= lock_clkin or lock_clkfb; end if; end if; wait on clkin_fb, rst_ipd; end process; -- --generate lock signal -- generate_lock : process(clkin_ps, rst_ipd) begin if (rst_ipd='1') then lock_out <= "00"; locked_out <= '0'; lock_out1_neg <= '0'; elsif (rising_edge(clkin_ps)) then if (clkfb_type = 0) then lock_out(0) <= lock_period; else lock_out(0) <= lock_period and lock_delay and lock_fb; end if; lock_out(1) <= lock_out(0); locked_out <= lock_out(1); elsif (falling_edge(clkin_ps)) then lock_out1_neg <= lock_out(1); end if; end process generate_lock; -- --generate the clk1x_out -- gen_clk1x : process( clkin_ps, rst_ipd) begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clk0_out <= '0'; elsif (clkin_ps'event) then if (clkin_ps = '1' ) then if ((clk1x_type = 1) and (lock_out(0) = '1')) then clk0_out <= '1', '0' after period/2; else clk0_out <= '1'; end if; else if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then clk0_out <= '0'; end if; end if; end if; end process gen_clk1x; -- --generate the clk2x_out -- gen_clk2x : process begin if (rising_edge(rst_ipd) or (rst_ipd = '1')) then clk2x_out <= '0'; else if (rising_edge(clkin_ps)) then clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; wait for (period / 4); clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; end if; end if; wait on clkin_ps, rst_ipd; end process gen_clk2x; -- --generate the clkdv_out -- gen_clkdv : process (clkin_ps, rst_ipd) begin if (rst_ipd='1') then clkdv_out <= '0'; clkdv_cnt <= 0; elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then if (lock_out1_neg = '1') then if (clkdv_cnt >= divide_type -1) then clkdv_cnt <= 0; else clkdv_cnt <= clkdv_cnt + 1; end if; if (clkdv_cnt < divide_type /2) then clkdv_out <= '1'; else if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then clkdv_out <= '0' after (period/4); else clkdv_out <= '0'; end if; end if; end if; end if; end process; -- -- generate fx output signal -- calculate_period_fx : process begin if (lock_period = '1') then period_fx <= (period * denominator) / (numerator * 2); remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps; end if; wait on lock_period, period, denominator, numerator; end process calculate_period_fx; generate_clkfx : process variable temp : integer; begin if (rst_ipd = '1') then clkfx_out <= '0'; elsif (clkin_lost_out_ext = '1') then wait until (rising_edge(rst_ipd)); clkfx_out <= '0'; wait until (falling_edge(rst_reg(2))); elsif (rising_edge(clkin_ps)) then if (lock_out(1) = '1') then clkfx_out <= '1'; temp := numerator * 2 - 1 - 1; for p in 0 to temp loop wait for (period_fx); clkfx_out <= not clkfx_out; end loop; if (period_fx > (period / 2)) then wait for (period_fx - (period / 2)); end if; end if; if (clkin_lost_out_ext = '1') then wait until (rising_edge(rst_ipd)); clkfx_out <= '0'; wait until (falling_edge(rst_reg(2))); end if; end if; wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2); end process generate_clkfx; -- --generate all output signal -- schedule_p1_outputs : process begin if (CLK0_out'event) then if (clkfb_type /= 0) then CLK0 <= transport CLK0_out after clkout_delay; clk0_sig <= transport CLK0_out after clkout_delay; end if; if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK90 <= transport clk0_out after (clkout_delay + period / 4); end if; end if; if (CLK0_out'event or rst_ipd'event)then if (rst_ipd = '1') then CLK180 <= '0'; CLK270 <= '0'; elsif (CLK0_out'event) then if (clkfb_type /= 0) then CLK180 <= transport (not clk0_out) after clkout_delay; end if; if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK270 <= transport (not clk0_out) after (clkout_delay + period/4); end if; end if; end if; if (clk2x_out'event) then if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK2X <= transport clk2x_out after clkout_delay; clk2x_sig <= transport clk2x_out after clkout_delay; end if; end if; if (CLK2X_out'event or rst_ipd'event) then if (rst_ipd = '1') then CLK2X180 <= '0'; elsif (CLK2X_out'event) then if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK2X180 <= transport (not CLK2X_out) after clkout_delay; end if; end if; end if; if (clkdv_out'event) then if (clkfb_type /= 0) then CLKDV <= transport clkdv_out after clkout_delay; end if; end if; if (clkfx_out'event or rst_ipd'event) then if (rst_ipd = '1') then CLKFX <= '0'; elsif (clkfx_out'event) then CLKFX <= transport clkfx_out after clkout_delay; end if; end if; if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then if ((rst_ipd = '1') or (not first_time_locked)) then CLKFX180 <= '0'; else CLKFX180 <= transport (not clkfx_out) after clkout_delay; end if; end if; if (status_out(0)'event) then status(0) <= status_out(0); end if; if (status_out(1)'event) then status(1) <= status_out(1); end if; if (status_out(2)'event) then status(2) <= status_out(2); end if; wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out; end process; assign_status_out : process begin if (rst_ipd = '1') then status_out(0) <= '0'; status_out(1) <= '0'; status_out(2) <= '0'; elsif (ps_overflow_out_ext'event) then status_out(0) <= ps_overflow_out_ext; elsif (clkin_lost_out_ext'event) then status_out(1) <= clkin_lost_out_ext; elsif (clkfx_lost_out_ext'event) then status_out(2) <= clkfx_lost_out_ext; end if; wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd; end process assign_status_out; locked_out_out <= 'X' when rst_flag = '1' else locked_out; -- LOCKED <= locked_out_out; -- PSDONE <= psdone_out; -- LOCKED_sig <= locked_out_out; schedule_outputs : process variable PSDONE_GlitchData : VitalGlitchDataType; variable LOCKED_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => PSDONE, GlitchData => PSDONE_GlitchData, OutSignalName => "PSDONE", OutTemp => psdone_out, Paths => (0 => (psdone_out'last_event, tpd_PSCLK_PSDONE, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); LOCKED_sig <= locked_out_out after tpd_CLKIN_LOCKED(tr01); VitalPathDelay01 ( OutSignal => LOCKED, GlitchData => LOCKED_GlitchData, OutSignalName => "LOCKED", OutTemp => locked_out_out, Paths => (0 => (locked_out_out'last_event, tpd_CLKIN_LOCKED, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); wait on locked_out_out, psdone_out; end process schedule_outputs; VitalTimingCheck : process variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Pviol_CLKIN : std_ulogic := '0'; variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_PSCLK : std_ulogic := '0'; variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_RST : std_ulogic := '0'; variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit; begin if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_PSINCDEC_PSCLK_posedge, TimingData => Tmkr_PSINCDEC_PSCLK_posedge, TestSignal => PSINCDEC_dly, TestSignalName => "PSINCDEC", TestDelay => tisd_PSINCDEC_PSCLK, RefSignal => PSCLK_dly, RefSignalName => "PSCLK", RefDelay => ticd_PSCLK, SetupHigh => tsetup_PSINCDEC_PSCLK_posedge_posedge, SetupLow => tsetup_PSINCDEC_PSCLK_negedge_posedge, HoldLow => thold_PSINCDEC_PSCLK_posedge_posedge, HoldHigh => thold_PSINCDEC_PSCLK_negedge_posedge, CheckEnabled => (TO_X01(((NOT RST_ipd)) AND (PSEN_dly)) /= '0'), RefTransition => 'R', HeaderMsg => InstancePath & "/X_DCM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalSetupHoldCheck ( Violation => Tviol_PSEN_PSCLK_posedge, TimingData => Tmkr_PSEN_PSCLK_posedge, TestSignal => PSEN_dly, TestSignalName => "PSEN", TestDelay => tisd_PSEN_PSCLK, RefSignal => PSCLK_dly, RefSignalName => "PSCLK", RefDelay => ticd_PSCLK, SetupHigh => tsetup_PSEN_PSCLK_posedge_posedge, SetupLow => tsetup_PSEN_PSCLK_negedge_posedge, HoldLow => thold_PSEN_PSCLK_posedge_posedge, HoldHigh => thold_PSEN_PSCLK_negedge_posedge, CheckEnabled => TO_X01(NOT RST_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/X_DCM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_PSCLK, PeriodData => PInfo_PSCLK, TestSignal => PSCLK_dly, TestSignalName => "PSCLK", TestDelay => 0 ns, Period => tperiod_PSCLK_POSEDGE, PulseWidthHigh => tpw_PSCLK_posedge, PulseWidthLow => tpw_PSCLK_negedge, CheckEnabled => true, HeaderMsg => InstancePath &"/X_DCM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_CLKIN, PeriodData => PInfo_CLKIN, TestSignal => CLKIN_ipd, TestSignalName => "CLKIN", TestDelay => 0 ns, Period => tperiod_CLKIN_POSEDGE, PulseWidthHigh => tpw_CLKIN_posedge, PulseWidthLow => tpw_CLKIN_negedge, CheckEnabled => TO_X01(NOT RST_ipd) /= '0', HeaderMsg => InstancePath &"/X_DCM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_RST, PeriodData => PInfo_RST, TestSignal => RST_ipd, TestSignalName => "RST", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_RST_posedge, PulseWidthLow => 0 ns, CheckEnabled => true, HeaderMsg => InstancePath &"/X_DCM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); end if; wait on CLKIN_ipd, PSCLK_dly, PSEN_dly, PSINCDEC_dly, RST_ipd; end process VITALTimingCheck; end X_DCM_V; ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 9.1i -- \ \ Description : Xilinx Timing Simulation Library Component -- / / Digital Clock Manager -- /___/ /\ Filename : X_DCM_SP.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/06/06 - Initial version. -- 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). -- 06/14/06 - Add period_int2 and period_int3 for multiple cycle phase shifting (CR 233283). -- 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). -- Give warning not support initial phase shifting for variable phase shifting. -- (CR 235216). -- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). -- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). -- 04/06/07 - Enable the clock out in clock low time after reset in model -- clock_divide_by_2 (CR 437471). -- End Revision ----- x_dcm_sp_clock_divide_by_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; entity x_dcm_sp_clock_divide_by_2 is port( clock_out : out std_ulogic := '0'; clock : in std_ulogic; clock_type : in integer; rst : in std_ulogic ); end x_dcm_sp_clock_divide_by_2; architecture x_dcm_sp_clock_divide_by_2_V of x_dcm_sp_clock_divide_by_2 is signal clock_div2 : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0); signal clk_src : std_ulogic; begin CLKIN_DIVIDER : process begin if (rising_edge(clock)) then clock_div2 <= not clock_div2; end if; wait on clock; end process CLKIN_DIVIDER; gen_reset : process begin if (rising_edge(clock)) then rst_reg(0) <= rst; rst_reg(1) <= rst_reg(0) and rst; rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst; end if; wait on clock; end process gen_reset; clk_src <= clock_div2 when (clock_type = 1) else clock; assign_clkout : process begin if (rst = '0') then clock_out <= clk_src; elsif (rst = '1') then clock_out <= '0'; wait until falling_edge(rst_reg(2)); if (clk_src = '1') then wait until falling_edge(clk_src); end if; end if; wait on clk_src, rst, rst_reg; end process assign_clkout; end x_dcm_sp_clock_divide_by_2_V; ----- x_dcm_sp_maximum_period_check ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library STD; use STD.TEXTIO.all; entity x_dcm_sp_maximum_period_check is generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end x_dcm_sp_maximum_period_check; architecture x_dcm_sp_maximum_period_check_V of x_dcm_sp_maximum_period_check is begin MAX_PERIOD_CHECKER : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; variable clock_period : time := 0 ps; variable Message : line; begin if (rising_edge(clock)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (clock_edge_previous > 0 ps) then clock_period := clock_edge_current - clock_edge_previous; end if; if (clock_period > maximum_period and rst = '0') then Write ( Message, string'(" Warning : Input Clock Period of ")); Write ( Message, clock_period ); Write ( Message, string'(" on the ") ); Write ( Message, clock_name ); Write ( Message, string'(" port ") ); Write ( Message, string'(" of X_DCM_SP instance ") ); Write ( Message, string'(" exceeds allowed value of ") ); Write ( Message, maximum_period ); Write ( Message, string'(" at simulation time ") ); Write ( Message, clock_edge_current ); Write ( Message, '.' & LF ); assert false report Message.all severity warning; DEALLOCATE (Message); end if; end if; wait on clock; end process MAX_PERIOD_CHECKER; end x_dcm_sp_maximum_period_check_V; ----- x_dcm_sp_clock_lost ----- library IEEE; use IEEE.STD_LOGIC_1164.all; entity x_dcm_sp_clock_lost is port( lost : out std_ulogic := '0'; clock : in std_ulogic; enable : in boolean := false; rst : in std_ulogic ); end x_dcm_sp_clock_lost; architecture x_dcm_sp_clock_lost_V of x_dcm_sp_clock_lost is signal period : time := 0 ps; signal lost_r : std_ulogic := '0'; signal lost_f : std_ulogic := '0'; signal lost_sig : std_ulogic := '0'; signal clock_negedge, clock_posedge : std_ulogic; signal clock_low, clock_high : std_ulogic := '0'; signal clock_second_pos, clock_second_neg : std_ulogic := '0'; begin determine_period : process variable clock_edge_previous : time := 0 ps; variable clock_edge_current : time := 0 ps; begin if (rst = '1') then period <= 0 ps; elsif (rising_edge(clock)) then clock_edge_previous := clock_edge_current; clock_edge_current := NOW; if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then period <= NOW - clock_edge_previous; elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then period <= 0 ps; elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then period <= NOW - clock_edge_previous; end if; end if; wait on clock, rst; end process determine_period; CLOCK_LOST_CHECKER : process begin if (rst = '1') then clock_low <= '0'; clock_high <= '0'; clock_posedge <= '0'; clock_negedge <= '0'; else if (rising_edge(clock)) then clock_low <= '0'; clock_high <= '1'; clock_posedge <= '0'; clock_negedge <= '1'; end if; if (falling_edge(clock)) then clock_high <= '0'; clock_low <= '1'; clock_posedge <= '1'; clock_negedge <= '0'; end if; end if; wait on clock, rst; end process CLOCK_LOST_CHECKER; CLOCK_SECOND_P : process begin if (rst = '1') then clock_second_pos <= '0'; clock_second_neg <= '0'; else if (rising_edge(clock)) then clock_second_pos <= '1'; end if; if (falling_edge(clock)) then clock_second_neg <= '1'; end if; end if; wait on clock, rst; end process CLOCK_SECOND_P; SET_RESET_LOST_R : process begin if (rst = '1') then lost_r <= '0'; else if ((enable = true) and (clock_second_pos = '1'))then if (rising_edge(clock)) then wait for 1 ps; if (period /= 0 ps) then lost_r <= '0'; end if; wait for (period * (9.1/10.0)); if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then lost_r <= '1'; end if; end if; end if; end if; wait on clock, rst; end process SET_RESET_LOST_R; SET_RESET_LOST_F : process begin if (rst = '1') then lost_f <= '0'; else if ((enable = true) and (clock_second_neg = '1'))then if (falling_edge(clock)) then if (period /= 0 ps) then lost_f <= '0'; end if; wait for (period * (9.1/10.0)); if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then lost_f <= '1'; end if; end if; end if; end if; wait on clock, rst; end process SET_RESET_LOST_F; assign_lost : process begin if (enable = true) then if (lost_r'event) then lost <= lost_r; end if; if (lost_f'event) then lost <= lost_f; end if; end if; wait on lost_r, lost_f; end process assign_lost; end x_dcm_sp_clock_lost_V; ----- CELL X_DCM_SP ----- library IEEE; use IEEE.std_logic_1164.all; library IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.vpkg.all; entity X_DCM_SP is generic ( TimingChecksOn : boolean := true; InstancePath : string := "*"; Xon : boolean := true; MsgOn : boolean := false; LOC : string := "UNPLACED"; thold_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; ticd_PSCLK : VitalDelayType := 0.000 ns; tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DSSEN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSCLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSEN : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PSINCDEC : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns); tisd_PSINCDEC_PSCLK : VitalDelayType := 0.000 ns; tisd_PSEN_PSCLK : VitalDelayType := 0.000 ns; tpd_CLKIN_LOCKED : VitalDelayType01 := (0.100 ns, 0.100 ns); tpd_PSCLK_PSDONE : VitalDelayType01 := (0.100 ns, 0.100 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns; tperiod_PSCLK_POSEDGE : VitalDelayType := 0.000 ns; tpw_CLKIN_negedge : VitalDelayType := 0.000 ns; tpw_CLKIN_posedge : VitalDelayType := 0.000 ns; tpw_PSCLK_negedge : VitalDelayType := 0.000 ns; tpw_PSCLK_posedge : VitalDelayType := 0.000 ns; tpw_RST_posedge : VitalDelayType := 0.000 ns; tsetup_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns; tsetup_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns; CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; --non-simulatable CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; --non-simulatable DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; --non-simulatable MAXPERCLKIN : time := 1000000 ps; --non-modifiable simulation parameter MAXPERPSCLK : time := 100000000 ps; --non-modifiable simulation parameter PHASE_SHIFT : integer := 0; SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --non-modifiable simulation parameter SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --non-modifiable simulation parameter STARTUP_WAIT : boolean := false --non-simulatable ); port ( CLK0 : out std_ulogic := '0'; CLK180 : out std_ulogic := '0'; CLK270 : out std_ulogic := '0'; CLK2X : out std_ulogic := '0'; CLK2X180 : out std_ulogic := '0'; CLK90 : out std_ulogic := '0'; CLKDV : out std_ulogic := '0'; CLKFX : out std_ulogic := '0'; CLKFX180 : out std_ulogic := '0'; LOCKED : out std_ulogic := '0'; PSDONE : out std_ulogic := '0'; STATUS : out std_logic_vector(7 downto 0) := "00000000"; CLKFB : in std_ulogic := '0'; CLKIN : in std_ulogic := '0'; DSSEN : in std_ulogic := '0'; PSCLK : in std_ulogic := '0'; PSEN : in std_ulogic := '0'; PSINCDEC : in std_ulogic := '0'; RST : in std_ulogic := '0' ); attribute VITAL_LEVEL0 of X_DCM_SP : entity is true; end X_DCM_SP; architecture X_DCM_SP_V of X_DCM_SP is component x_dcm_sp_clock_divide_by_2 port( clock_out : out std_ulogic; clock : in std_ulogic; clock_type : in integer; rst : in std_ulogic ); end component; component x_dcm_sp_maximum_period_check generic ( InstancePath : string := "*"; clock_name : string := ""; maximum_period : time); port( clock : in std_ulogic; rst : in std_ulogic ); end component; component x_dcm_sp_clock_lost port( lost : out std_ulogic; clock : in std_ulogic; enable : in boolean := false; rst : in std_ulogic ); end component; signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic; signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic; signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0'; signal clk0_out : std_ulogic; signal clk2x_out, clkdv_out : std_ulogic := '0'; signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0'; signal locked_out_out : std_ulogic := '0'; signal LOCKED_sig : std_ulogic := '0'; signal clkdv_cnt : integer := 0; signal clkfb_type : integer; signal divide_type : integer; signal clkin_type : integer; signal ps_type : integer; signal deskew_adjust_mode : integer; signal dfs_mode_type : integer; signal dll_mode_type : integer; signal clk1x_type : integer; signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; signal lock_out : std_logic_vector(1 downto 0) := "00"; signal lock_out1_neg : std_ulogic := '0'; signal lock_fb : std_ulogic := '0'; signal lock_fb_dly : std_ulogic := '0'; signal lock_fb_dly_tmp : std_ulogic := '0'; signal fb_delay_found : std_ulogic := '0'; signal clkin_div : std_ulogic; signal clkin_ps : std_ulogic; signal clkin_ps_tmp : std_ulogic; signal clkin_ps_mkup : std_ulogic := '0'; signal clkin_ps_mkup_win : std_ulogic := '0'; signal clkin_fb : std_ulogic; signal ps_delay : time := 0 ps; signal ps_delay_init : time := 0 ps; signal ps_delay_md : time := 0 ps; signal ps_delay_all : time := 0 ps; signal ps_max_range : integer := 0; signal ps_acc : integer := 0; signal period_int : integer := 0; signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns); signal period : time := 0 ps; signal period_div : time := 0 ps; signal period_orig : time := 0 ps; signal period_ps : time := 0 ps; signal clkout_delay : time := 0 ps; signal fb_delay : time := 0 ps; signal period_fx, remain_fx : time := 0 ps; signal period_dv_high, period_dv_low : time := 0 ps; signal cycle_jitter, period_jitter : time := 0 ps; signal clkin_window, clkfb_window : std_ulogic := '0'; signal rst_reg : std_logic_vector(2 downto 0) := "000"; signal rst_flag : std_ulogic := '0'; signal numerator, denominator, gcd : integer := 1; signal clkin_lost_out : std_ulogic := '0'; signal clkfx_lost_out : std_ulogic := '0'; signal remain_fx_temp : integer := 0; signal clkin_period_real0_temp : time := 0 ps; signal ps_lock_reg : std_ulogic := '0'; signal clk0_sig : std_ulogic := '0'; signal clk2x_sig : std_ulogic := '0'; signal no_stop : boolean := false; signal clkfx180_en : std_ulogic := '0'; signal status_out : std_logic_vector(7 downto 0) := "00000000"; signal first_time_locked : boolean := false; signal en_status : boolean := false; signal ps_overflow_out_ext : std_ulogic := '0'; signal clkin_lost_out_ext : std_ulogic := '0'; signal clkfx_lost_out_ext : std_ulogic := '0'; signal clkfb_div : std_ulogic := '0'; signal clkfb_div_en : std_ulogic := '0'; signal clkfb_chk : std_ulogic := '0'; signal lock_period_dly : std_ulogic := '0'; signal lock_period_dly1 : std_ulogic := '0'; signal lock_period_pulse : std_ulogic := '0'; signal clock_stopped : std_ulogic := '1'; signal clkin_chkin, clkfb_chkin : std_ulogic := '0'; signal chk_enable, chk_rst : std_ulogic := '0'; signal lock_ps : std_ulogic := '0'; signal lock_ps_dly : std_ulogic := '0'; constant PS_STEP : time := 25 ps; begin INITPROC : process begin detect_resolution (model_name => "X_DCM_SP" ); if (CLKDV_DIVIDE = 1.5) then divide_type <= 3; elsif (CLKDV_DIVIDE = 2.0) then divide_type <= 4; elsif (CLKDV_DIVIDE = 2.5) then divide_type <= 5; elsif (CLKDV_DIVIDE = 3.0) then divide_type <= 6; elsif (CLKDV_DIVIDE = 3.5) then divide_type <= 7; elsif (CLKDV_DIVIDE = 4.0) then divide_type <= 8; elsif (CLKDV_DIVIDE = 4.5) then divide_type <= 9; elsif (CLKDV_DIVIDE = 5.0) then divide_type <= 10; elsif (CLKDV_DIVIDE = 5.5) then divide_type <= 11; elsif (CLKDV_DIVIDE = 6.0) then divide_type <= 12; elsif (CLKDV_DIVIDE = 6.5) then divide_type <= 13; elsif (CLKDV_DIVIDE = 7.0) then divide_type <= 14; elsif (CLKDV_DIVIDE = 7.5) then divide_type <= 15; elsif (CLKDV_DIVIDE = 8.0) then divide_type <= 16; elsif (CLKDV_DIVIDE = 9.0) then divide_type <= 18; elsif (CLKDV_DIVIDE = 10.0) then divide_type <= 20; elsif (CLKDV_DIVIDE = 11.0) then divide_type <= 22; elsif (CLKDV_DIVIDE = 12.0) then divide_type <= 24; elsif (CLKDV_DIVIDE = 13.0) then divide_type <= 26; elsif (CLKDV_DIVIDE = 14.0) then divide_type <= 28; elsif (CLKDV_DIVIDE = 15.0) then divide_type <= 30; elsif (CLKDV_DIVIDE = 16.0) then divide_type <= 32; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKDV_DIVIDE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLKDV_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKFX_DIVIDE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLKFX_DIVIDE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 1....32", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKFX_MULTIPLY", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLKFX_MULTIPLY, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are 2....32", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; case CLKIN_DIVIDE_BY_2 is when false => clkin_type <= 0; when true => clkin_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKIN_DIVIDE_BY_2", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLKIN_DIVIDE_BY_2, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_type <= 0; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_type <= 1; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_type <= 2; if (PHASE_SHIFT /= 0) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Warning", GenericName => "PHASE_SHIFT", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => PHASE_SHIFT, Unit => "", ExpectedValueMsg => "The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => warning ); end if; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLKOUT_PHASE_SHIFT", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLKOUT_PHASE_SHIFT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then clkfb_type <= 0; elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then clkfb_type <= 1; elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then clkfb_type <= 2; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "CLK_FEEDBACK", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => CLK_FEEDBACK, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then DESKEW_ADJUST_mode <= 8; elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then DESKEW_ADJUST_mode <= 11; elsif ((DESKEW_ADJUST = "0")) then DESKEW_ADJUST_mode <= 0; elsif ((DESKEW_ADJUST = "1")) then DESKEW_ADJUST_mode <= 1; elsif ((DESKEW_ADJUST = "2")) then DESKEW_ADJUST_mode <= 2; elsif ((DESKEW_ADJUST = "3")) then DESKEW_ADJUST_mode <= 3; elsif ((DESKEW_ADJUST = "4")) then DESKEW_ADJUST_mode <= 4; elsif ((DESKEW_ADJUST = "5")) then DESKEW_ADJUST_mode <= 5; elsif ((DESKEW_ADJUST = "6")) then DESKEW_ADJUST_mode <= 6; elsif ((DESKEW_ADJUST = "7")) then DESKEW_ADJUST_mode <= 7; elsif ((DESKEW_ADJUST = "8")) then DESKEW_ADJUST_mode <= 8; elsif ((DESKEW_ADJUST = "9")) then DESKEW_ADJUST_mode <= 9; elsif ((DESKEW_ADJUST = "10")) then DESKEW_ADJUST_mode <= 10; elsif ((DESKEW_ADJUST = "11")) then DESKEW_ADJUST_mode <= 11; elsif ((DESKEW_ADJUST = "12")) then DESKEW_ADJUST_mode <= 12; elsif ((DESKEW_ADJUST = "13")) then DESKEW_ADJUST_mode <= 13; elsif ((DESKEW_ADJUST = "14")) then DESKEW_ADJUST_mode <= 14; elsif ((DESKEW_ADJUST = "15")) then DESKEW_ADJUST_mode <= 15; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DESKEW_ADJUST_MODE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => DESKEW_ADJUST_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then dfs_mode_type <= 1; elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then dfs_mode_type <= 0; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DFS_FREQUENCY_MODE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => DFS_FREQUENCY_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then dll_mode_type <= 1; elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then dll_mode_type <= 0; else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DLL_FREQUENCY_MODE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => DLL_FREQUENCY_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then else GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DSS_MODE", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => DSS_MODE, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are NONE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; case DUTY_CYCLE_CORRECTION is when false => clk1x_type <= 0; when true => clk1x_type <= 1; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "DUTY_CYCLE_CORRECTION", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => DUTY_CYCLE_CORRECTION, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "PHASE_SHIFT", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => PHASE_SHIFT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end if; period_jitter <= SIM_CLKIN_PERIOD_JITTER; cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; case STARTUP_WAIT is when false => null; when true => null; when others => GenericValueCheckMessage (HeaderMsg => "Attribute Syntax Error", GenericName => "STARTUP_WAIT", EntityName => "X_DCM_SP", InstanceName => InstancePath, GenericValue => STARTUP_WAIT, Unit => "", ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", ExpectedGenericValue => "", TailMsg => "", MsgSeverity => error ); end case; -- -- fx parameters -- gcd <= 1; for i in 2 to CLKFX_MULTIPLY loop if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then gcd <= i; end if; end loop; numerator <= CLKFX_MULTIPLY / gcd; denominator <= CLKFX_DIVIDE / gcd; wait; end process INITPROC; -- -- input wire delays -- WireDelay : block begin VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN); VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB); VitalWireDelay (DSSEN_ipd, DSSEN, tipd_DSSEN); VitalWireDelay (PSCLK_ipd, PSCLK, tipd_PSCLK); VitalWireDelay (PSEN_ipd, PSEN, tipd_PSEN); VitalWireDelay (PSINCDEC_ipd, PSINCDEC, tipd_PSINCDEC); VitalWireDelay (RST_ipd, RST, tipd_RST); end block; SignalDelay : block begin VitalSignalDelay (PSCLK_dly, PSCLK_ipd, ticd_PSCLK); VitalSignalDelay (PSEN_dly, PSEN_ipd, tisd_PSEN_PSCLK); VitalSignalDelay (PSINCDEC_dly, PSINCDEC_ipd, tisd_PSINCDEC_PSCLK); end block; i_clock_divide_by_2 : x_dcm_sp_clock_divide_by_2 port map ( clock => clkin_ipd, clock_type => clkin_type, rst => rst_ipd, clock_out => clkin_div); i_max_clkin : x_dcm_sp_maximum_period_check generic map ( clock_name => "CLKIN", maximum_period => MAXPERCLKIN) port map ( clock => clkin_ipd, rst => rst_ipd); i_max_psclk : x_dcm_sp_maximum_period_check generic map ( clock_name => "PSCLK", maximum_period => MAXPERPSCLK) port map ( clock => psclk_dly, rst => rst_ipd); i_clkin_lost : x_dcm_sp_clock_lost port map ( lost => clkin_lost_out, clock => clkin_ipd, enable => first_time_locked, rst => rst_ipd ); i_clkfx_lost : x_dcm_sp_clock_lost port map ( lost => clkfx_lost_out, clock => clkfx_out, enable => first_time_locked, rst => rst_ipd ); clkin_ps_tmp <= transport clkin_div after ps_delay_md; clkin_ps <= clkin_ps_mkup when clkin_ps_mkup_win = '1' else clkin_ps_tmp; clkin_fb <= transport (clkin_ps and lock_fb); clkin_ps_tmp_p: process variable ps_delay_last : integer := 0; variable ps_delay_int : integer; variable period_int2 : integer := 0; variable period_int3 : integer := 0; begin if (ps_type = 2) then ps_delay_int := (ps_delay /1 ps ) * 1; period_int2 := 2 * period_int; period_int3 := 3 * period_int; if (rising_edge(clkin_div)) then if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or (ps_delay_last >= period_int and ps_delay_int < period_int) or (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or (ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then clkin_ps_mkup_win <= '1'; clkin_ps_mkup <= '1'; wait until falling_edge(clkin_div); clkin_ps_mkup_win <= '1'; clkin_ps_mkup <= '0'; else clkin_ps_mkup_win <= '0'; clkin_ps_mkup <= '0'; end if; end if; if (falling_edge(clkin_div)) then if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or (ps_delay_last >= period_int and ps_delay_int < period_int) or (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or (ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then clkin_ps_mkup <= '0'; clkin_ps_mkup_win <= '0'; wait until rising_edge(clkin_div); clkin_ps_mkup <= '1'; clkin_ps_mkup_win <= '1'; wait until falling_edge(clkin_div); clkin_ps_mkup <= '0'; clkin_ps_mkup_win <= '1'; else clkin_ps_mkup <= '0'; clkin_ps_mkup_win <= '0'; end if; end if; ps_delay_last := ps_delay_int; end if; wait on clkin_div; end process; detect_first_time_locked : process begin if (first_time_locked = false) then if (rising_edge(locked_out)) then first_time_locked <= true; end if; end if; wait on locked_out; end process detect_first_time_locked; set_reset_en_status : process begin if (rst_ipd = '1') then en_status <= false; elsif (rising_edge(Locked_sig)) then en_status <= true; end if; wait on rst_ipd, Locked_sig; end process set_reset_en_status; gen_clkfb_div_en: process begin if (rst_ipd = '1') then clkfb_div_en <= '0'; elsif (falling_edge(clkfb_ipd)) then if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then clkfb_div_en <= '1'; end if; end if; wait on clkfb_ipd, rst_ipd; end process gen_clkfb_div_en; gen_clkfb_div: process begin if (rst_ipd = '1') then clkfb_div <= '0'; elsif (rising_edge(clkfb_ipd)) then if (clkfb_div_en = '1') then clkfb_div <= not clkfb_div; end if; end if; wait on clkfb_ipd, rst_ipd; end process gen_clkfb_div; determine_clkfb_chk: process begin if (clkfb_type = 2) then clkfb_chk <= clkfb_div; else clkfb_chk <= clkfb_ipd and lock_fb_dly; end if; wait on clkfb_ipd, clkfb_div; end process determine_clkfb_chk; set_reset_clkin_chkin : process begin if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then if (chk_rst = '1') then clkin_chkin <= '0'; else clkin_chkin <= '1'; end if; end if; wait on clkin_fb, chk_rst; end process set_reset_clkin_chkin; set_reset_clkfb_chkin : process begin if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then if (chk_rst = '1') then clkfb_chkin <= '0'; else clkfb_chkin <= '1'; end if; end if; wait on clkfb_chk, chk_rst; end process set_reset_clkfb_chkin; -- assign_chk_rst: process -- begin -- if ((rst_ipd = '1') or (clock_stopped = '1')) then -- chk_rst <= '1'; -- else -- chk_rst <= '0'; -- end if; -- wait on rst_ipd, clock_stopped; -- end process assign_chk_rst; chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0'; -- assign_chk_enable: process -- begin -- if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then -- chk_enable <= '1'; -- else -- chk_enable <= '0'; -- end if; -- wait on clkin_chkin, clkfb_chkin; -- end process assign_chk_enable; chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0'; control_status_bits: process begin if ((rst_ipd = '1') or (en_status = false)) then ps_overflow_out_ext <= '0'; clkin_lost_out_ext <= '0'; clkfx_lost_out_ext <= '0'; else ps_overflow_out_ext <= ps_overflow_out; clkin_lost_out_ext <= clkin_lost_out; clkfx_lost_out_ext <= clkfx_lost_out; end if; wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd; end process control_status_bits; determine_period_div : process variable clkin_div_edge_previous : time := 0 ps; variable clkin_div_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_div_edge_previous := 0 ps; clkin_div_edge_current := 0 ps; period_div <= 0 ps; else if (rising_edge(clkin_div)) then clkin_div_edge_previous := clkin_div_edge_current; clkin_div_edge_current := NOW; if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then period_div <= clkin_div_edge_current - clkin_div_edge_previous; elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then period_div <= clkin_div_edge_current - clkin_div_edge_previous; end if; end if; end if; wait on clkin_div, rst_ipd; end process determine_period_div; determine_period_ps : process variable clkin_ps_edge_previous : time := 0 ps; variable clkin_ps_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_ps_edge_previous := 0 ps; clkin_ps_edge_current := 0 ps; period_ps <= 0 ps; else if (rising_edge(clkin_ps)) then clkin_ps_edge_previous := clkin_ps_edge_current; clkin_ps_edge_current := NOW; wait for 0 ps; if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; end if; end if; end if; wait on clkin_ps, rst_ipd; end process determine_period_ps; assign_lock_ps_fb : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_fb <= '0'; lock_ps <= '0'; lock_ps_dly <= '0'; lock_fb_dly <= '0'; lock_fb_dly_tmp <= '0'; else if (rising_edge(clkin_ps)) then lock_ps <= lock_period; lock_ps_dly <= lock_ps; lock_fb <= lock_ps_dly; lock_fb_dly_tmp <= lock_fb; end if; if (falling_edge(clkin_ps)) then lock_fb_dly <= lock_fb_dly_tmp after (period/4); end if; end if; wait on clkin_ps, rst_ipd; end process assign_lock_ps_fb; calculate_clkout_delay : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkout_delay <= 0 ps; elsif (fb_delay = 0 ps) then clkout_delay <= 0 ps; elsif (period'event or fb_delay'event) then clkout_delay <= period - fb_delay; end if; wait on period, fb_delay, rst_ipd; end process calculate_clkout_delay; -- --generate master reset signal -- gen_master_rst : process begin if (rising_edge(clkin_ipd)) then rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; rst_reg(1) <= rst_reg(0) and rst_ipd; rst_reg(0) <= rst_ipd; end if; wait on clkin_ipd; end process gen_master_rst; check_rst_width : process variable Message : line; begin if (rst_ipd ='1') then rst_flag <= '0'; end if; if (falling_edge(rst_ipd)) then if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then rst_flag <= '1'; Write ( Message, string'(" Input Error : RST on X_DCM_SP ")); Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); assert false report Message.all severity error; DEALLOCATE (Message); end if; end if; wait on rst_ipd; end process check_rst_width; -- --phase shift parameters -- ps_max_range_p : process (period) variable period_ps_tmp : integer := 0; begin period_int <= (period/ 1 ps ) * 1; if (clkin_type = 1) then period_ps_tmp := 2 * (period/ 1 ns ); else period_ps_tmp := (period/ 1 ns ) * 1; end if; if (period_ps_tmp > 3) then ps_max_range <= 20 * (period_ps_tmp - 3); else ps_max_range <= 0; end if; end process; ps_delay_md_p : process (period, ps_delay, lock_period, rst_ipd) variable tmp_value : integer; variable tmp_value1 : integer; variable tmp_value2 : integer; begin if (rst_ipd = '1') then ps_delay_md <= 0 ps; elsif (lock_period = '1') then tmp_value := (ps_delay / 1 ps ) * 1; tmp_value1 := (period / 1 ps) * 1; tmp_value2 := tmp_value mod tmp_value1; ps_delay_md <= period + tmp_value2 * 1 ps; end if; end process; determine_phase_shift : process variable Message : line; variable first_time : boolean := true; variable ps_in : integer; variable ps_acc : integer := 0; variable ps_step_int : integer := 0; begin if (first_time = true) then if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_in := 256; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_in := 256 + PHASE_SHIFT; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_in := 256 + PHASE_SHIFT; end if; ps_step_int := (PS_STEP / 1 ps ) * 1; first_time := false; end if; if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then ps_in := 256; elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then ps_in := 256 + PHASE_SHIFT; elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then ps_in := 256 + PHASE_SHIFT; else end if; ps_lock <= '0'; ps_overflow_out <= '0'; ps_delay <= 0 ps; ps_acc := 0; elsif (rising_edge(lock_period_pulse)) then ps_delay <= (ps_in * period_div / 256); elsif (rising_edge(PSCLK_dly)) then if (ps_type = 2) then if (psen_dly = '1') then if (ps_lock = '1') then Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); assert false report Message.all severity warning; DEALLOCATE (Message); else if (lock_ps = '1') then if (psincdec_dly = '1') then if (ps_acc > ps_max_range) then ps_overflow_out <= '1'; else ps_delay <= ps_delay + PS_STEP; ps_acc := ps_acc + 1; ps_overflow_out <= '0'; end if; ps_lock <= '1'; elsif (psincdec_dly = '0') then if (ps_acc < -ps_max_range) then ps_overflow_out <= '1'; else ps_delay <= ps_delay - PS_STEP; ps_acc := ps_acc - 1; ps_overflow_out <= '0'; end if; ps_lock <= '1'; end if; end if; end if; end if; end if; end if; if (ps_lock_reg'event) then ps_lock <= ps_lock_reg; end if; wait on lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd; end process determine_phase_shift; determine_psdone_out : process begin if (rising_edge(ps_lock)) then ps_lock_reg <= '1'; wait until (rising_edge(clkin_ps)); wait until (rising_edge(psclk_dly)); wait until (rising_edge(psclk_dly)); wait until (rising_edge(psclk_dly)); psdone_out <= '1'; wait until (rising_edge(psclk_dly)); psdone_out <= '0'; ps_lock_reg <= '0'; end if; wait on ps_lock; end process determine_psdone_out; -- --determine clock period -- determine_clock_period : process variable clkin_edge_previous : time := 0 ps; variable clkin_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_period_real(0) <= 0 ps; clkin_period_real(1) <= 0 ps; clkin_period_real(2) <= 0 ps; clkin_edge_previous := 0 ps; clkin_edge_current := 0 ps; elsif (rising_edge(clkin_div)) then clkin_edge_previous := clkin_edge_current; clkin_edge_current := NOW; clkin_period_real(2) <= clkin_period_real(1); clkin_period_real(1) <= clkin_period_real(0); if (clkin_edge_previous /= 0 ps) then clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; end if; end if; if (no_stop'event) then clkin_period_real(0) <= clkin_period_real0_temp; end if; wait on clkin_div, no_stop, rst_ipd; end process determine_clock_period; evaluate_clock_period : process variable Message : line; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_period <= '0'; clock_stopped <= '1'; clkin_period_real0_temp <= 0 ps; else if (falling_edge(clkin_div)) then if (lock_period = '0') then if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then lock_period <= '1'; period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; period <= clkin_period_real(0); end if; elsif (lock_period = '1') then if (100000000 ns < clkin_period_real(0)) then Write ( Message, string'(" Warning : CLKIN stopped toggling on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, string'(" 100 ms ")); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0)); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then clkin_period_real0_temp <= clkin_period_real(1); no_stop <= not no_stop; clock_stopped <= '1'; elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then Write ( Message, string'(" Warning : Input Clock Period Jitter on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, period_jitter ); Write ( Message, string'(" Locked CLKIN Period = ")); Write ( Message, period_orig ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance ")); Write ( Message, Instancepath ); Write ( Message, string'(" exceeds ")); Write ( Message, cycle_jitter ); Write ( Message, string'(" Previous CLKIN Period = ")); Write ( Message, clkin_period_real(1) ); Write ( Message, string'(" Current CLKIN Period = ")); Write ( Message, clkin_period_real(0) ); assert false report Message.all severity warning; DEALLOCATE (Message); lock_period <= '0'; wait until (falling_edge(rst_reg(2))); else period <= clkin_period_real(0); clock_stopped <= '0'; end if; end if; end if; end if; wait on clkin_div, rst_ipd; end process evaluate_clock_period; lock_period_dly1 <= transport lock_period after 1 ps; lock_period_dly <= transport lock_period_dly1 after period/2; lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0'; -- --determine clock delay -- determine_clock_delay : process variable delay_edge : time := 0 ps; variable temp1 : integer := 0; variable temp2 : integer := 0; variable temp : integer := 0; variable delay_edge_current : time := 0 ps; begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then fb_delay <= 0 ps; fb_delay_found <= '0'; else if (rising_edge(lock_ps_dly)) then if ((lock_period = '1') and (clkfb_type /= 0)) then if (clkfb_type = 1) then wait until ((rising_edge(clk0_sig)) or (rst_ipd'event)); delay_edge := NOW; elsif (clkfb_type = 2) then wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event)); delay_edge := NOW; end if; wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); temp2 := (period_orig * 1)/ (1 ps); temp := temp1 mod temp2; fb_delay <= temp * 1 ps; fb_delay_found <= '1'; end if; end if; end if; wait on lock_ps_dly, rst_ipd; end process determine_clock_delay; -- -- determine feedback lock -- GEN_CLKFB_WINDOW : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkfb_window <= '0'; else if (rising_edge(clkfb_chk)) then wait for 0 ps; clkfb_window <= '1'; wait for cycle_jitter; clkfb_window <= '0'; end if; end if; wait on clkfb_chk, rst_ipd; end process GEN_CLKFB_WINDOW; GEN_CLKIN_WINDOW : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clkin_window <= '0'; else if (rising_edge(clkin_fb)) then wait for 0 ps; clkin_window <= '1'; wait for cycle_jitter; clkin_window <= '0'; end if; end if; wait on clkin_fb, rst_ipd; end process GEN_CLKIN_WINDOW; set_reset_lock_clkin : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_clkin <= '0'; else if (rising_edge(clkin_fb)) then wait for 1 ps; if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then lock_clkin <= '1'; else if (chk_enable = '1') then lock_clkin <= '0'; end if; end if; end if; end if; wait on clkin_fb, rst_ipd; end process set_reset_lock_clkin; set_reset_lock_clkfb : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_clkfb <= '0'; else if (rising_edge(clkfb_chk)) then wait for 1 ps; if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then lock_clkfb <= '1'; else if (chk_enable = '1') then lock_clkfb <= '0'; end if; end if; end if; end if; wait on clkfb_chk, rst_ipd; end process set_reset_lock_clkfb; assign_lock_delay : process begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then lock_delay <= '0'; else if (falling_edge(clkin_fb)) then lock_delay <= lock_clkin or lock_clkfb; end if; end if; wait on clkin_fb, rst_ipd; end process; -- --generate lock signal -- generate_lock : process(clkin_ps, rst_ipd) begin if (rst_ipd='1') then lock_out <= "00"; locked_out <= '0'; lock_out1_neg <= '0'; elsif (rising_edge(clkin_ps)) then if (clkfb_type = 0) then lock_out(0) <= lock_period; else lock_out(0) <= lock_period and lock_delay and lock_fb; end if; lock_out(1) <= lock_out(0); locked_out <= lock_out(1); elsif (falling_edge(clkin_ps)) then lock_out1_neg <= lock_out(1); end if; end process generate_lock; -- --generate the clk1x_out -- gen_clk1x : process( clkin_ps, rst_ipd) begin if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then clk0_out <= '0'; elsif (clkin_ps'event) then if (clkin_ps = '1' ) then if ((clk1x_type = 1) and (lock_out(0) = '1')) then clk0_out <= '1', '0' after period/2; else clk0_out <= '1'; end if; else if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then clk0_out <= '0'; end if; end if; end if; end process gen_clk1x; -- --generate the clk2x_out -- gen_clk2x : process begin if (rising_edge(rst_ipd) or (rst_ipd = '1')) then clk2x_out <= '0'; else if (rising_edge(clkin_ps)) then clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; wait for (period / 4); clk2x_out <= '1'; wait for (period / 4); clk2x_out <= '0'; end if; end if; wait on clkin_ps, rst_ipd; end process gen_clk2x; -- --generate the clkdv_out -- gen_clkdv : process (clkin_ps, rst_ipd) begin if (rst_ipd='1') then clkdv_out <= '0'; clkdv_cnt <= 0; elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then if (lock_out1_neg = '1') then if (clkdv_cnt >= divide_type -1) then clkdv_cnt <= 0; else clkdv_cnt <= clkdv_cnt + 1; end if; if (clkdv_cnt < divide_type /2) then clkdv_out <= '1'; else if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then clkdv_out <= '0' after (period/4); else clkdv_out <= '0'; end if; end if; end if; end if; end process; -- -- generate fx output signal -- calculate_period_fx : process begin if (lock_period = '1') then period_fx <= (period * denominator) / (numerator * 2); remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps; end if; wait on lock_period, period, denominator, numerator; end process calculate_period_fx; generate_clkfx : process variable temp : integer; begin if (rst_ipd = '1') then clkfx_out <= '0'; elsif (clkin_lost_out_ext = '1') then wait until (rising_edge(rst_ipd)); clkfx_out <= '0'; wait until (falling_edge(rst_reg(2))); elsif (rising_edge(clkin_ps)) then if (lock_out(1) = '1') then clkfx_out <= '1'; temp := numerator * 2 - 1 - 1; for p in 0 to temp loop wait for (period_fx); clkfx_out <= not clkfx_out; end loop; if (period_fx > (period / 2)) then wait for (period_fx - (period / 2)); end if; end if; if (clkin_lost_out_ext = '1') then wait until (rising_edge(rst_ipd)); clkfx_out <= '0'; wait until (falling_edge(rst_reg(2))); end if; end if; wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2); end process generate_clkfx; -- --generate all output signal -- schedule_p1_outputs : process begin if (CLK0_out'event) then if (clkfb_type /= 0) then CLK0 <= transport CLK0_out after clkout_delay; clk0_sig <= transport CLK0_out after clkout_delay; end if; if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK90 <= transport clk0_out after (clkout_delay + period / 4); end if; end if; if (CLK0_out'event or rst_ipd'event)then if (rst_ipd = '1') then CLK180 <= '0'; CLK270 <= '0'; elsif (CLK0_out'event) then if (clkfb_type /= 0) then CLK180 <= transport (not clk0_out) after clkout_delay; end if; if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK270 <= transport (not clk0_out) after (clkout_delay + period/4); end if; end if; end if; if (clk2x_out'event) then if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK2X <= transport clk2x_out after clkout_delay; clk2x_sig <= transport clk2x_out after clkout_delay; end if; end if; if (CLK2X_out'event or rst_ipd'event) then if (rst_ipd = '1') then CLK2X180 <= '0'; elsif (CLK2X_out'event) then if ((dll_mode_type = 0) and (clkfb_type /= 0)) then CLK2X180 <= transport (not CLK2X_out) after clkout_delay; end if; end if; end if; if (clkdv_out'event) then if (clkfb_type /= 0) then CLKDV <= transport clkdv_out after clkout_delay; end if; end if; if (clkfx_out'event or rst_ipd'event) then if (rst_ipd = '1') then CLKFX <= '0'; elsif (clkfx_out'event) then CLKFX <= transport clkfx_out after clkout_delay; end if; end if; if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then if ((rst_ipd = '1') or (not first_time_locked)) then CLKFX180 <= '0'; else CLKFX180 <= transport (not clkfx_out) after clkout_delay; end if; end if; if (status_out(0)'event) then status(0) <= status_out(0); end if; if (status_out(1)'event) then status(1) <= status_out(1); end if; if (status_out(2)'event) then status(2) <= status_out(2); end if; wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out; end process; assign_status_out : process begin if (rst_ipd = '1') then status_out(0) <= '0'; status_out(1) <= '0'; status_out(2) <= '0'; elsif (ps_overflow_out_ext'event) then status_out(0) <= ps_overflow_out_ext; elsif (clkin_lost_out_ext'event) then status_out(1) <= clkin_lost_out_ext; elsif (clkfx_lost_out_ext'event) then status_out(2) <= clkfx_lost_out_ext; end if; wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd; end process assign_status_out; locked_out_out <= 'X' when rst_flag = '1' else locked_out; -- LOCKED <= locked_out_out; -- PSDONE <= psdone_out; -- LOCKED_sig <= locked_out_out; schedule_outputs : process variable PSDONE_GlitchData : VitalGlitchDataType; variable LOCKED_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => PSDONE, GlitchData => PSDONE_GlitchData, OutSignalName => "PSDONE", OutTemp => psdone_out, Paths => (0 => (psdone_out'last_event, tpd_PSCLK_PSDONE, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); LOCKED_sig <= locked_out_out after tpd_CLKIN_LOCKED(tr01); VitalPathDelay01 ( OutSignal => LOCKED, GlitchData => LOCKED_GlitchData, OutSignalName => "LOCKED", OutTemp => locked_out_out, Paths => (0 => (locked_out_out'last_event, tpd_CLKIN_LOCKED, true)), Mode => OnEvent, Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning ); wait on locked_out_out, psdone_out; end process schedule_outputs; VitalTimingCheck : process variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0'; variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit; variable Pviol_CLKIN : std_ulogic := '0'; variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_PSCLK : std_ulogic := '0'; variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit; variable Pviol_RST : std_ulogic := '0'; variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit; begin if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_PSINCDEC_PSCLK_posedge, TimingData => Tmkr_PSINCDEC_PSCLK_posedge, TestSignal => PSINCDEC_dly, TestSignalName => "PSINCDEC", TestDelay => tisd_PSINCDEC_PSCLK, RefSignal => PSCLK_dly, RefSignalName => "PSCLK", RefDelay => ticd_PSCLK, SetupHigh => tsetup_PSINCDEC_PSCLK_posedge_posedge, SetupLow => tsetup_PSINCDEC_PSCLK_negedge_posedge, HoldLow => thold_PSINCDEC_PSCLK_posedge_posedge, HoldHigh => thold_PSINCDEC_PSCLK_negedge_posedge, CheckEnabled => (TO_X01(((NOT RST_ipd)) AND (PSEN_dly)) /= '0'), RefTransition => 'R', HeaderMsg => InstancePath & "/X_DCM_SP", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalSetupHoldCheck ( Violation => Tviol_PSEN_PSCLK_posedge, TimingData => Tmkr_PSEN_PSCLK_posedge, TestSignal => PSEN_dly, TestSignalName => "PSEN", TestDelay => tisd_PSEN_PSCLK, RefSignal => PSCLK_dly, RefSignalName => "PSCLK", RefDelay => ticd_PSCLK, SetupHigh => tsetup_PSEN_PSCLK_posedge_posedge, SetupLow => tsetup_PSEN_PSCLK_negedge_posedge, HoldLow => thold_PSEN_PSCLK_posedge_posedge, HoldHigh => thold_PSEN_PSCLK_negedge_posedge, CheckEnabled => TO_X01(NOT RST_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/X_DCM_SP", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_PSCLK, PeriodData => PInfo_PSCLK, TestSignal => PSCLK_dly, TestSignalName => "PSCLK", TestDelay => 0 ns, Period => tperiod_PSCLK_POSEDGE, PulseWidthHigh => tpw_PSCLK_posedge, PulseWidthLow => tpw_PSCLK_negedge, CheckEnabled => true, HeaderMsg => InstancePath &"/X_DCM_SP", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_CLKIN, PeriodData => PInfo_CLKIN, TestSignal => CLKIN_ipd, TestSignalName => "CLKIN", TestDelay => 0 ns, Period => tperiod_CLKIN_POSEDGE, PulseWidthHigh => tpw_CLKIN_posedge, PulseWidthLow => tpw_CLKIN_negedge, CheckEnabled => TO_X01(NOT RST_ipd) /= '0', HeaderMsg => InstancePath &"/X_DCM_SP", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); VitalPeriodPulseCheck ( Violation => Pviol_RST, PeriodData => PInfo_RST, TestSignal => RST_ipd, TestSignalName => "RST", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_RST_posedge, PulseWidthLow => 0 ns, CheckEnabled => true, HeaderMsg => InstancePath &"/X_DCM_SP", Xon => Xon, MsgOn => MsgOn, MsgSeverity => warning); end if; wait on CLKIN_ipd, PSCLK_dly, PSEN_dly, PSINCDEC_dly, RST_ipd; end process VITALTimingCheck; end X_DCM_SP_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; entity DCM is generic ( CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := false ); port ( CLKFB : in std_logic; CLKIN : in std_logic; DSSEN : in std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector (7 downto 0)); end ; architecture sim of DCM is begin x0 : entity unisim.X_DCM generic map ( CLKDV_DIVIDE => CLKDV_DIVIDE, CLKFX_DIVIDE => CLKFX_DIVIDE, CLKFX_MULTIPLY => CLKFX_MULTIPLY, CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2, CLKIN_PERIOD => CLKIN_PERIOD, CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT, CLK_FEEDBACK => CLK_FEEDBACK, DESKEW_ADJUST => DESKEW_ADJUST, DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE, DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE, DSS_MODE => DSS_MODE, DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION, FACTORY_JF => FACTORY_JF, PHASE_SHIFT => PHASE_SHIFT, STARTUP_WAIT => STARTUP_WAIT ) port map ( CLKFB => CLKFB, CLKIN => CLKIN, DSSEN => DSSEN, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, RST => RST, CLK0 => CLK0, CLK90 => CLK90, CLK180 => CLK180, CLK270 => CLK270, CLK2X => CLK2X, CLK2X180 => CLK2X180, CLKDV => CLKDV, CLKFX => CLKFX, CLKFX180 => CLKFX180, LOCKED => LOCKED, PSDONE => PSDONE, STATUS => STATUS); end; library IEEE; use IEEE.STD_LOGIC_1164.all; library grlib; use IEEE.NUMERIC_STD.all; library STD; use STD.TEXTIO.all; library unisim; --use unisim.vpkg.all; use unisim.vpkg.all; entity SYSMON is generic ( INIT_40 : bit_vector := X"0000"; INIT_41 : bit_vector := X"0000"; INIT_42 : bit_vector := X"0800"; INIT_43 : bit_vector := X"0000"; INIT_44 : bit_vector := X"0000"; INIT_45 : bit_vector := X"0000"; INIT_46 : bit_vector := X"0000"; INIT_47 : bit_vector := X"0000"; INIT_48 : bit_vector := X"0000"; INIT_49 : bit_vector := X"0000"; INIT_4A : bit_vector := X"0000"; INIT_4B : bit_vector := X"0000"; INIT_4C : bit_vector := X"0000"; INIT_4D : bit_vector := X"0000"; INIT_4E : bit_vector := X"0000"; INIT_4F : bit_vector := X"0000"; INIT_50 : bit_vector := X"0000"; INIT_51 : bit_vector := X"0000"; INIT_52 : bit_vector := X"0000"; INIT_53 : bit_vector := X"0000"; INIT_54 : bit_vector := X"0000"; INIT_55 : bit_vector := X"0000"; INIT_56 : bit_vector := X"0000"; INIT_57 : bit_vector := X"0000"; SIM_MONITOR_FILE : string := "design.txt" ); port ( ALM : out std_logic_vector(2 downto 0); BUSY : out std_ulogic; CHANNEL : out std_logic_vector(4 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; EOC : out std_ulogic; EOS : out std_ulogic; JTAGBUSY : out std_ulogic; JTAGLOCKED : out std_ulogic; JTAGMODIFIED : out std_ulogic; OT : out std_ulogic; CONVST : in std_ulogic; CONVSTCLK : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; RESET : in std_ulogic; VAUXN : in std_logic_vector(15 downto 0); VAUXP : in std_logic_vector(15 downto 0); VN : in std_ulogic; VP : in std_ulogic ); end SYSMON; architecture SYSMON_V of SYSMON is --------------------------------------------------------------------------- -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER --------------------------------------------------------------------------- function SLV_TO_INT(SLV: in std_logic_vector ) return integer is variable int : integer; begin int := 0; for i in SLV'high downto SLV'low loop int := int * 2; if SLV(i) = '1' then int := int + 1; end if; end loop; return int; end; --------------------------------------------------------------------------- -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE -- is returned if any argument bit is other than a '0' or '1'. --------------------------------------------------------------------------- function ADDR_IS_VALID ( SLV : in std_logic_vector ) return boolean is variable IS_VALID : boolean := TRUE; begin for I in SLV'high downto SLV'low loop if (SLV(I) /= '0' AND SLV(I) /= '1') then IS_VALID := FALSE; end if; end loop; return IS_VALID; end ADDR_IS_VALID; function int2real( int_in : in integer) return real is variable conline1 : line; variable rl_value : real; variable tmpv1 : real; variable tmpv2 : real := 1.0; variable tmpi : integer; begin tmpi := int_in; write (conline1, tmpi); write (conline1, string'(".0 ")); write (conline1, tmpv2); read (conline1, tmpv1); rl_value := tmpv1; return rl_value; DEALLOCATE(conline1); end int2real; function real2int( real_in : in real) return integer is variable int_value : integer; variable tmpt : time; variable tmpt1 : time; variable tmpa : real; variable tmpr : real; variable int_out : integer; begin tmpa := abs(real_in); tmpt := tmpa * 1 ps; int_value := (tmpt / 1 ps ) * 1; tmpt1 := int_value * 1 ps; tmpr := int2real(int_value); if ( real_in < 0.0000) then if (tmpr > tmpa) then int_out := 1 - int_value; else int_out := -int_value; end if; else if (tmpr > tmpa) then int_out := int_value - 1; else int_out := int_value; end if; end if; return int_out; end real2int; FUNCTION To_Upper ( CONSTANT val : IN String ) RETURN STRING IS VARIABLE result : string (1 TO val'LENGTH) := val; VARIABLE ch : character; BEGIN FOR i IN 1 TO val'LENGTH LOOP ch := result(i); EXIT WHEN ((ch = NUL) OR (ch = nul)); IF ( ch >= 'a' and ch <= 'z') THEN result(i) := CHARACTER'VAL( CHARACTER'POS(ch) - CHARACTER'POS('a') + CHARACTER'POS('A') ); END IF; END LOOP; RETURN result; END To_Upper; procedure get_token(buf : inout LINE; token : out string; token_len : out integer) is variable index : integer := buf'low; variable tk_index : integer := 0; variable old_buf : LINE := buf; BEGIN while ((index <= buf' high) and ((buf(index) = ' ') or (buf(index) = HT))) loop index := index + 1; end loop; while((index <= buf'high) and ((buf(index) /= ' ') and (buf(index) /= HT))) loop tk_index := tk_index + 1; token(tk_index) := buf(index); index := index + 1; end loop; token_len := tk_index; buf := new string'(old_buf(index to old_buf'high)); old_buf := NULL; END; procedure skip_blanks(buf : inout LINE) is variable index : integer := buf'low; variable old_buf : LINE := buf; BEGIN while ((index <= buf' high) and ((buf(index) = ' ') or (buf(index) = HT))) loop index := index + 1; end loop; buf := new string'(old_buf(index to old_buf'high)); old_buf := NULL; END; procedure infile_format is variable message_line : line; begin write(message_line, string'("***** SYSMON Simulation Analog Data File Format ******")); writeline(output, message_line); write(message_line, string'("NAME: design.txt or user file name passed with generic sim_monitor_file")); writeline(output, message_line); write(message_line, string'("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VP VN VAUXP[0] VAUXN[0] ....")); writeline(output, message_line); write(message_line, string'("TIME must be in first column.")); writeline(output, message_line); write(message_line, string'("Time value need to be integer in ns scale")); writeline(output, message_line); write(message_line, string'("Analog value need to be real and contain a decimal point '.', zero should be 0.0, 3 should be 3.0")); writeline(output, message_line); write(message_line, string'("Each line including header line can not have extra space after the last character/digit.")); writeline(output, message_line); write(message_line, string'("Each data line must have same number of columns as the header line.")); writeline(output, message_line); write(message_line, string'("Comment line start with -- or //")); writeline(output, message_line); write(message_line, string'("Example:")); writeline(output, message_line); write(message_line, string'("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]")); writeline(output, message_line); write(message_line, string'("000 125.6 1.0 0.7 0.4 0.3 0.6")); writeline(output, message_line); write(message_line, string'("200 25.6 0.8 0.5 0.3 0.8 0.2")); writeline(output, message_line); end infile_format; type REG_FILE is array (integer range <>) of std_logic_vector(15 downto 0); signal dr_sram : REG_FILE(16#40# to 16#57#) := ( 16#40# => TO_STDLOGICVECTOR(INIT_40), 16#41# => TO_STDLOGICVECTOR(INIT_41), 16#42# => TO_STDLOGICVECTOR(INIT_42), 16#43# => TO_STDLOGICVECTOR(INIT_43), 16#44# => TO_STDLOGICVECTOR(INIT_44), 16#45# => TO_STDLOGICVECTOR(INIT_45), 16#46# => TO_STDLOGICVECTOR(INIT_46), 16#47# => TO_STDLOGICVECTOR(INIT_47), 16#48# => TO_STDLOGICVECTOR(INIT_48), 16#49# => TO_STDLOGICVECTOR(INIT_49), 16#4A# => TO_STDLOGICVECTOR(INIT_4A), 16#4B# => TO_STDLOGICVECTOR(INIT_4B), 16#4C# => TO_STDLOGICVECTOR(INIT_4C), 16#4D# => TO_STDLOGICVECTOR(INIT_4D), 16#4E# => TO_STDLOGICVECTOR(INIT_4E), 16#4F# => TO_STDLOGICVECTOR(INIT_4F), 16#50# => TO_STDLOGICVECTOR(INIT_50), 16#51# => TO_STDLOGICVECTOR(INIT_51), 16#52# => TO_STDLOGICVECTOR(INIT_52), 16#53# => TO_STDLOGICVECTOR(INIT_53), 16#54# => TO_STDLOGICVECTOR(INIT_54), 16#55# => TO_STDLOGICVECTOR(INIT_55), 16#56# => TO_STDLOGICVECTOR(INIT_56), 16#57# => TO_STDLOGICVECTOR(INIT_57) ); signal ot_sf_limit_low_reg : unsigned(15 downto 0) := "1010111001000000"; --X"AE40"; type adc_statetype is (INIT_STATE, ACQ_STATE, CONV_STATE, ADC_PRE_END, END_STATE, SINGLE_SEQ_STATE); type ANALOG_DATA is array (0 to 31) of real; type DR_data_reg is array (0 to 63) of std_logic_vector(15 downto 0); type ACC_ARRAY is array (0 to 31) of integer; type int_array is array(0 to 31) of integer; type seq_array is array(32 downto 0 ) of integer; signal ot_limit_reg : UNSIGNED(15 downto 0) := "1100011110000000"; signal adc_state : adc_statetype := CONV_STATE; signal next_state : adc_statetype; signal cfg_reg0 : std_logic_vector(15 downto 0) := "0000000000000000"; signal cfg_reg0_adc : std_logic_vector(15 downto 0) := "0000000000000000"; signal cfg_reg0_seq : std_logic_vector(15 downto 0) := "0000000000000000"; signal cfg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; signal cfg_reg1_init : std_logic_vector(15 downto 0) := "0000000000000000"; signal cfg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq1_0 : std_logic_vector(1 downto 0) := "00"; signal curr_seq1_0 : std_logic_vector(1 downto 0) := "00"; signal curr_seq1_0_lat : std_logic_vector(1 downto 0) := "00"; signal busy_r : std_ulogic := '0'; signal busy_r_rst : std_ulogic := '0'; signal busy_rst : std_ulogic := '0'; signal busy_conv : std_ulogic := '0'; signal busy_out_tmp : std_ulogic := '0'; signal busy_out_dly : std_ulogic := '0'; signal busy_out_sync : std_ulogic := '0'; signal busy_out_low_edge : std_ulogic := '0'; signal shorten_acq : integer := 1; signal busy_seq_rst : std_ulogic := '0'; signal busy_sync1 : std_ulogic := '0'; signal busy_sync2 : std_ulogic := '0'; signal busy_sync_fall : std_ulogic := '0'; signal busy_sync_rise : std_ulogic := '0'; signal cal_chan_update : std_ulogic := '0'; signal first_cal_chan : std_ulogic := '0'; signal seq_reset_flag : std_ulogic := '0'; signal seq_reset_flag_dly : std_ulogic := '0'; signal seq_reset_dly : std_ulogic := '0'; signal seq_reset_busy_out : std_ulogic := '0'; signal rst_in_not_seq : std_ulogic := '0'; signal rst_in_out : std_ulogic := '0'; signal rst_lock_early : std_ulogic := '0'; signal conv_count : integer := 0; signal acq_count : integer := 1; signal do_out_rdtmp : std_logic_vector(15 downto 0); signal rst_in1 : std_ulogic := '0'; signal rst_in2 : std_ulogic := '0'; signal int_rst : std_ulogic := '1'; signal rst_input_t : std_ulogic := '0'; signal rst_in : std_ulogic := '0'; signal ot_en : std_logic := '1'; signal curr_clkdiv_sel : std_logic_vector(7 downto 0) := "00000000"; signal curr_clkdiv_sel_int : integer := 0; signal adcclk : std_ulogic := '0'; signal adcclk_div1 : std_ulogic := '0'; signal sysclk : std_ulogic := '0'; signal curr_adc_resl : std_logic_vector(2 downto 0) := "010"; signal nx_seq : std_logic_vector(15 downto 0) := "0000000000000000"; signal curr_seq : std_logic_vector(15 downto 0) := "0000000000000000"; signal acq_cnt : integer := 0; signal acq_chan : std_logic_vector(4 downto 0) := "00000"; signal acq_chan_index : integer := 0; signal acq_chan_lat : std_logic_vector(4 downto 0) := "00000"; signal curr_chan : std_logic_vector(4 downto 0) := "00000"; signal curr_chan_dly : std_logic_vector(4 downto 0) := "00000"; signal curr_chan_lat : std_logic_vector(4 downto 0) := "00000"; signal curr_avg_set : std_logic_vector(1 downto 0) := "00"; signal acq_avg : std_logic_vector(1 downto 0) := "00"; signal curr_e_c : std_logic:= '0'; signal acq_e_c : std_logic:= '0'; signal acq_b_u : std_logic:= '0'; signal curr_b_u : std_logic:= '0'; signal acq_acqsel : std_logic:= '0'; signal curr_acq : std_logic:= '0'; signal seq_cnt : integer := 0; signal busy_rst_cnt : integer := 0; signal adc_s1_flag : std_ulogic := '0'; signal adc_convst : std_ulogic := '0'; signal conv_start : std_ulogic := '0'; signal conv_end : std_ulogic := '0'; signal eos_en : std_ulogic := '0'; signal eos_tmp_en : std_ulogic := '0'; signal seq_cnt_en : std_ulogic := '0'; signal eoc_en : std_ulogic := '0'; signal eoc_en_delay : std_ulogic := '0'; signal eoc_out_tmp : std_ulogic := '0'; signal eos_out_tmp : std_ulogic := '0'; signal eoc_out_tmp1 : std_ulogic := '0'; signal eos_out_tmp1 : std_ulogic := '0'; signal eoc_up_data : std_ulogic := '0'; signal eoc_up_alarm : std_ulogic := '0'; signal conv_time : integer := 17; signal conv_time_cal_1 : integer := 69; signal conv_time_cal : integer := 69; signal conv_result : std_logic_vector(15 downto 0) := "0000000000000000"; signal conv_result_reg : std_logic_vector(15 downto 0) := "0000000000000000"; signal data_written : std_logic_vector(15 downto 0) := "0000000000000000"; signal conv_result_int : integer := 0; signal conv_result_int_resl : integer := 0; signal analog_in_uni : ANALOG_DATA :=(others=>0.0); signal analog_in_diff : ANALOG_DATA :=(others=>0.0); signal analog_in : ANALOG_DATA :=(others=>0.0); signal analog_in_comm : ANALOG_DATA :=(others=>0.0); signal chan_val_tmp : ANALOG_DATA :=(others=>0.0); signal chan_valn_tmp : ANALOG_DATA :=(others=>0.0); signal data_reg : DR_data_reg :=( 36 to 39 => "1111111111111111", others=>"0000000000000000"); signal tmp_data_reg_out : std_logic_vector(15 downto 0) := "0000000000000000"; signal tmp_dr_sram_out : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_chan_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_chan_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_acq_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_acq_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_avg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_avg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_du_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_du_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; signal seq_count : integer := 1; signal seq_count_en : std_ulogic := '0'; signal conv_acc : ACC_ARRAY :=(others=>0); signal conv_avg_count : ACC_ARRAY :=(others=>0); signal conv_acc_vec : std_logic_vector (20 downto 1); signal conv_acc_result : std_logic_vector(15 downto 0); signal seq_status_avg : integer := 0; signal curr_chan_index : integer := 0; signal curr_chan_index_lat : integer := 0; signal conv_avg_cnt : int_array :=(others=>0); signal analog_mux_in : real := 0.0; signal adc_temp_result : real := 0.0; signal adc_intpwr_result : real := 0.0; signal adc_ext_result : real := 0.0; signal seq_reset : std_ulogic := '0'; signal seq_en : std_ulogic := '0'; signal seq_en_drp : std_ulogic := '0'; signal seq_en_init : std_ulogic := '0'; signal seq_en_dly : std_ulogic := '0'; signal seq_num : integer := 0; signal seq_mem : seq_array :=(others=>0); signal adc_seq_reset : std_ulogic := '0'; signal adc_seq_en : std_ulogic := '0'; signal adc_seq_reset_dly : std_ulogic := '0'; signal adc_seq_en_dly : std_ulogic := '0'; signal adc_seq_reset_hold : std_ulogic := '0'; signal adc_seq_en_hold : std_ulogic := '0'; signal rst_lock : std_ulogic := '1'; signal sim_file_flag : std_ulogic := '0'; signal gsr_in : std_ulogic := '0'; signal convstclk_in : std_ulogic := '0'; signal convst_raw_in : std_ulogic := '0'; signal convst_in : std_ulogic := '0'; signal dclk_in : std_ulogic := '0'; signal den_in : std_ulogic := '0'; signal rst_input : std_ulogic := '0'; signal dwe_in : std_ulogic := '0'; signal di_in : std_logic_vector(15 downto 0) := "0000000000000000"; signal daddr_in : std_logic_vector(6 downto 0) := "0000000"; signal daddr_in_lat : std_logic_vector(6 downto 0) := "0000000"; signal daddr_in_lat_int : integer := 0; signal drdy_out_tmp1 : std_ulogic := '0'; signal drdy_out_tmp2 : std_ulogic := '0'; signal drdy_out_tmp3 : std_ulogic := '0'; signal drp_update : std_ulogic := '0'; signal alarm_en : std_logic_vector(2 downto 0) := "111"; signal alarm_update : std_ulogic := '0'; signal adcclk_tmp : std_ulogic := '0'; signal ot_out_reg : std_ulogic := '0'; signal alarm_out_reg : std_logic_vector(2 downto 0) := "000"; signal conv_end_reg_read : std_logic_vector(3 downto 0) := "0000"; signal busy_reg_read : std_ulogic := '0'; signal single_chan_conv_end : std_ulogic := '0'; signal first_acq : std_ulogic := '1'; signal conv_start_cont : std_ulogic := '0'; signal conv_start_sel : std_ulogic := '0'; signal reset_conv_start : std_ulogic := '0'; signal reset_conv_start_tmp : std_ulogic := '0'; signal busy_r_rst_done : std_ulogic := '0'; signal op_count : integer := 15; -- Input/Output Pin signals signal DI_ipd : std_logic_vector(15 downto 0); signal DADDR_ipd : std_logic_vector(6 downto 0); signal DEN_ipd : std_ulogic; signal DWE_ipd : std_ulogic; signal DCLK_ipd : std_ulogic; signal CONVSTCLK_ipd : std_ulogic; signal RESET_ipd : std_ulogic; signal CONVST_ipd : std_ulogic; signal do_out : std_logic_vector(15 downto 0) := "0000000000000000"; signal drdy_out : std_ulogic := '0'; signal ot_out : std_ulogic := '0'; signal alarm_out : std_logic_vector(2 downto 0) := "000"; signal channel_out : std_logic_vector(4 downto 0) := "00000"; signal eoc_out : std_ulogic := '0'; signal eos_out : std_ulogic := '0'; signal busy_out : std_ulogic := '0'; signal DI_dly : std_logic_vector(15 downto 0); signal DADDR_dly : std_logic_vector(6 downto 0); signal DEN_dly : std_ulogic; signal DWE_dly : std_ulogic; signal DCLK_dly : std_ulogic; signal CONVSTCLK_dly : std_ulogic; signal RESET_dly : std_ulogic; signal CONVST_dly : std_ulogic; begin BUSY <= busy_out after 100 ps; DRDY <= drdy_out after 100 ps; EOC <= eoc_out after 100 ps; EOS <= eos_out after 100 ps; OT <= ot_out after 100 ps; DO <= do_out after 100 ps; CHANNEL <= channel_out after 100 ps; ALM <= alarm_out after 100 ps; convst_raw_in <= CONVST; convstclk_in <= CONVSTCLK; dclk_in <= DCLK; den_in <= DEN; rst_input <= RESET; dwe_in <= DWE; di_in <= Di; daddr_in <= DADDR; gsr_in <= GSR; convst_in <= '1' when (convst_raw_in = '1' or convstclk_in = '1') else '0'; JTAGLOCKED <= '0'; JTAGMODIFIED <= '0'; JTAGBUSY <= '0'; DEFAULT_CHECK : process variable init40h_tmp : std_logic_vector(15 downto 0); variable init41h_tmp : std_logic_vector(15 downto 0); variable init42h_tmp : std_logic_vector(15 downto 0); variable init4eh_tmp : std_logic_vector(15 downto 0); variable init40h_tmp_chan : integer; variable init42h_tmp_clk : integer; variable tmp_value : std_logic_vector(7 downto 0); begin init40h_tmp := TO_STDLOGICVECTOR(INIT_40); init40h_tmp_chan := SLV_TO_INT(SLV=>init40h_tmp(4 downto 0)); init41h_tmp := TO_STDLOGICVECTOR(INIT_41); init42h_tmp := TO_STDLOGICVECTOR(INIT_42); tmp_value := init42h_tmp(15 downto 8); init42h_tmp_clk := SLV_TO_INT(SLV=>tmp_value); init4eh_tmp := TO_STDLOGICVECTOR(INIT_4E); if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(8)='1') and (init40h_tmp_chan /= 3 ) and (init40h_tmp_chan < 16)) then assert false report " Attribute Syntax warning : The attribute INIT_40 bit[8] must be set to 0 on SYSMON. Long acquistion mode is only allowed for external channels." severity warning; end if; if ((init41h_tmp(13 downto 12) /="11") and (init4eh_tmp(10 downto 0) /= "00000000000") and (init4eh_tmp(15 downto 12) /= "0000")) then assert false report " Attribute Syntax warning : The attribute INIT_4E Bit[15:12] and bit[10:0] must be set to 0. Long acquistion mode is only allowed for external channels." severity warning; end if; if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(9) = '1') and (init40h_tmp(4 downto 0) /= "00011") and (init40h_tmp_chan < 16)) then assert false report " Attribute Syntax warning : The attribute INIT_40 bit[9] must be set to 0 on SYSMON. Event mode timing can only be used with external channels, and only in single channel mode." severity warning; end if; if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(13 downto 12) /= "00") and (INIT_48 /=X"0000") and (INIT_49 /= X"0000")) then assert false report " Attribute Syntax warning : The attribute INIT_48 and INIT_49 must be set to 0000h in single channel mode and averaging enabled." severity warning; end if; if (init42h_tmp(1 downto 0) /= "00") then assert false report " Attribute Syntax Error : The attribute INIT_42 Bit[1:0] must be set to 00." severity Error; end if; if (init42h_tmp_clk < 8) then assert false report " Attribute Syntax Error : The attribute INIT_42 Bit[15:8] is the ADC Clock divider and must be equal or greater than 8." severity failure; end if; if (INIT_43 /= "0000000000000000") then assert false report " Warning : The attribute INIT_43 must be set to 0000." severity warning; end if; if (INIT_44 /= "0000000000000000") then assert false report " Warning : The attribute INIT_44 must be set to 0000." severity warning; end if; if (INIT_45 /= "0000000000000000") then assert false report " Warning : The attribute INIT_45 must be set to 0000." severity warning; end if; if (INIT_46 /= "0000000000000000") then assert false report " Warning : The attribute INIT_46 must be set to 0000." severity warning; end if; if (INIT_47 /= "0000000000000000") then assert false report " Warning : The attribute INIT_47 must be set to 0000." severity warning; end if; wait; end process; curr_chan_index <= SLV_TO_INT(curr_chan); curr_chan_index_lat <= SLV_TO_INT(curr_chan_lat); CHEK_COMM_P : process( busy_r ) variable Message : line; begin if (busy_r'event and busy_r = '1' ) then if (rst_in = '0' and acq_b_u = '0' and ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then if ( chan_valn_tmp(acq_chan_index) > chan_val_tmp(acq_chan_index)) then Write ( Message, string'("Input File Warning: The N input for external channel ")); Write ( Message, acq_chan_index); Write ( Message, string'(" must be smaller than P input when in unipolar mode (P=")); Write ( Message, chan_val_tmp(acq_chan_index)); Write ( Message, string'(" N=")); Write ( Message, chan_valn_tmp(acq_chan_index)); Write ( Message, string'(") for SYSMON.")); assert false report Message.all severity warning; DEALLOCATE (Message); end if; if (( chan_valn_tmp(acq_chan_index) > 0.5) or (chan_valn_tmp(acq_chan_index) < 0.0)) then Write ( Message, string'("Input File Warning: The N input for external channel ")); Write ( Message, acq_chan_index); Write ( Message, string'(" should be between 0V to 0.5V when in unipolar mode (N=")); Write ( Message, chan_valn_tmp(acq_chan_index)); Write ( Message, string'(") for SYSMON.")); assert false report Message.all severity warning; DEALLOCATE (Message); end if; end if; end if; end process; busy_mkup_p : process( dclk_in, rst_in_out) begin if (rst_in_out = '1') then busy_rst <= '1'; rst_lock <= '1'; rst_lock_early <= '1'; busy_rst_cnt <= 0; elsif (rising_edge(dclk_in)) then if (rst_lock = '1') then if (busy_rst_cnt < 29) then busy_rst_cnt <= busy_rst_cnt + 1; if ( busy_rst_cnt = 26) then rst_lock_early <= '0'; end if; else busy_rst <= '0'; rst_lock <= '0'; end if; end if; end if; end process; busy_out_p : process (busy_rst, busy_conv, rst_lock) begin if (rst_lock = '1') then busy_out <= busy_rst; else busy_out <= busy_conv; end if; end process; busy_conv_p : process (dclk_in, rst_in) begin if (rst_in = '1') then busy_conv <= '0'; cal_chan_update <= '0'; elsif (rising_edge(dclk_in)) then if (seq_reset_flag = '1' and curr_clkdiv_sel_int <= 3) then busy_conv <= busy_seq_rst; elsif (busy_sync_fall = '1') then busy_conv <= '0'; elsif (busy_sync_rise = '1') then busy_conv <= '1'; end if; if (conv_count = 21 and curr_chan = "01000" ) then cal_chan_update <= '1'; else cal_chan_update <= '0'; end if; end if; end process; busy_sync_p : process (dclk_in, rst_lock) begin if (rst_lock = '1') then busy_sync1 <= '0'; busy_sync2 <= '0'; elsif (rising_edge (dclk_in)) then busy_sync1 <= busy_r; busy_sync2 <= busy_sync1; end if; end process; busy_sync_fall <= '1' when (busy_r = '0' and busy_sync1 = '1') else '0'; busy_sync_rise <= '1' when (busy_sync1 = '1' and busy_sync2 = '0') else '0'; busy_seq_rst_p : process variable tmp_uns_div : unsigned(7 downto 0); begin if (falling_edge(busy_out) or rising_edge(busy_r)) then if (seq_reset_flag = '1' and seq1_0 = "00" and curr_clkdiv_sel_int <= 3) then wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); busy_seq_rst <= '1'; elsif (seq_reset_flag = '1' and seq1_0 /= "00" and curr_clkdiv_sel_int <= 3) then wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); busy_seq_rst <= '1'; else busy_seq_rst <= '0'; end if; end if; wait on busy_out, busy_r; end process; chan_out_p : process(busy_out, rst_in_out, cal_chan_update) begin if (rst_in_out = '1') then channel_out <= "00000"; elsif (rising_edge(busy_out) or rising_edge(cal_chan_update)) then if ( busy_out = '1' and cal_chan_update = '1') then channel_out <= "01000"; end if; elsif (falling_edge(busy_out)) then channel_out <= curr_chan; curr_chan_lat <= curr_chan; end if; end process; INT_RST_GEN_P : process begin int_rst <= '1'; wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); int_rst <= '0'; wait; end process; rst_input_t <= rst_input or int_rst; RST_DE_SYNC_P: process(dclk_in, rst_input_t) begin if (rst_input_t = '1') then rst_in2 <= '1'; rst_in1 <= '1'; elsif (dclk_in'event and dclk_in='1') then rst_in2 <= rst_in1; rst_in1 <= rst_input_t; end if; end process; rst_in_not_seq <= rst_in2; rst_in <= rst_in2 or seq_reset_dly; rst_in_out <= rst_in2 or seq_reset_busy_out; seq_reset_dly_p : process begin if (rising_edge(seq_reset)) then wait until rising_edge(dclk_in); wait until rising_edge(dclk_in); seq_reset_dly <= '1'; wait until rising_edge(dclk_in); wait until falling_edge(dclk_in); seq_reset_busy_out <= '1'; wait until rising_edge(dclk_in); wait until rising_edge(dclk_in); wait until rising_edge(dclk_in); seq_reset_dly <= '0'; seq_reset_busy_out <= '0'; end if; wait on seq_reset, dclk_in; end process; seq_reset_flag_p : process (seq_reset_dly, busy_r) begin if (rising_edge(seq_reset_dly)) then seq_reset_flag <= '1'; elsif (rising_edge(busy_r)) then seq_reset_flag <= '0'; end if; end process; seq_reset_flag_dly_p : process (seq_reset_flag, busy_out) begin if (rising_edge(seq_reset_flag)) then seq_reset_flag_dly <= '1'; elsif (rising_edge(busy_out)) then seq_reset_flag_dly <= '0'; end if; end process; first_cal_chan_p : process ( busy_out) begin if (rising_edge(busy_out )) then if (seq_reset_flag_dly = '1' and acq_chan = "01000" and seq1_0 = "00") then first_cal_chan <= '1'; else first_cal_chan <= '0'; end if; end if; end process; ADC_SM: process (adcclk, rst_in, sim_file_flag) begin if (sim_file_flag = '1') then adc_state <= INIT_STATE; elsif (rst_in = '1' or rst_lock_early = '1') then adc_state <= INIT_STATE; elsif (adcclk'event and adcclk = '1') then adc_state <= next_state; end if; end process; next_state_p : process (adc_state, eos_en, conv_start , conv_end, curr_seq1_0_lat) begin case (adc_state) is when INIT_STATE => next_state <= ACQ_STATE; when ACQ_STATE => if (conv_start = '1') then next_state <= CONV_STATE; else next_state <= ACQ_STATE; end if; when CONV_STATE => if (conv_end = '1') then next_state <= END_STATE; else next_state <= CONV_STATE; end if; when END_STATE => if (curr_seq1_0_lat = "01") then if (eos_en = '1') then next_state <= SINGLE_SEQ_STATE; else next_state <= ACQ_STATE; end if; else next_state <= ACQ_STATE; end if; when SINGLE_SEQ_STATE => next_state <= INIT_STATE; when others => next_state <= INIT_STATE; end case; end process; seq_en_init_p : process begin seq_en_init <= '0'; if (cfg_reg1_init(13 downto 12) /= "11" ) then wait for 20 ps; seq_en_init <= '1'; wait for 150 ps; seq_en_init <= '0'; end if; wait; end process; seq_en <= seq_en_init or seq_en_drp; DRPORT_DO_OUT_P : process(dclk_in, gsr_in) variable message : line; variable di_str : string (16 downto 1); variable daddr_str : string (7 downto 1); variable di_40 : std_logic_vector(4 downto 0); variable valid_daddr : boolean := false; variable address : integer; variable tmp_value : integer := 0; variable tmp_value1 : std_logic_vector (7 downto 0); begin if (gsr_in = '1') then drdy_out <= '0'; daddr_in_lat <= "0000000"; do_out <= "0000000000000000"; elsif (rising_edge(dclk_in)) then if (den_in = '1') then valid_daddr := addr_is_valid(daddr_in); if (valid_daddr) then address := slv_to_int(daddr_in); if ( (address > 88 or (address >= 13 and address <= 15) or (address >= 39 and address <= 63))) then Write ( Message, string'(" Invalid Input Warning : The DADDR ")); Write ( Message, string'(SLV_TO_STR(daddr_in))); Write ( Message, string'(" is not defined. The data in this location is invalid.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; end if; if (drdy_out_tmp1 = '1' or drdy_out_tmp2 = '1' or drdy_out_tmp3 = '1') then drdy_out_tmp1 <= '0'; else drdy_out_tmp1 <= '1'; end if; daddr_in_lat <= daddr_in; else drdy_out_tmp1 <= '0'; end if; drdy_out_tmp2 <= drdy_out_tmp1; drdy_out_tmp3 <= drdy_out_tmp2; drdy_out <= drdy_out_tmp3; if (drdy_out_tmp3 = '1') then do_out <= do_out_rdtmp; end if; -- write all available daddr addresses if (dwe_in = '1' and den_in = '1') then if (valid_daddr) then dr_sram(address) <= di_in; end if; if ( address = 42 and di_in( 1 downto 0) /= "00") then Write ( Message, string'(" Invalid Input Error : The DI bit[1:0] ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in(1 downto 0)))); Write ( Message, string'(" at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(" of SYSMON is invalid. These must be set to 00.")); assert false report Message.all severity error; end if; tmp_value1 := di_in(15 downto 8) ; tmp_value := SLV_TO_INT(SLV=>tmp_value1); if ( address = 42 and tmp_value < 8) then Write ( Message, string'(" Invalid Input Error : The DI bit[15:8] ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in(15 downto 8)))); Write ( Message, string'(" at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(" of SYSMON is invalid. Bit[15:8] of Control Register 42h is the ADC Clock divider and must be equal or greater than 8.")); assert false report Message.all severity failure; end if; if ( (address >= 43 and address <= 47) and di_in(15 downto 0) /= "0000000000000000") then Write ( Message, string'(" Invalid Input Error : The DI value ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); Write ( Message, string'(" at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(" of SYSMON is invalid. These must be set to 0000.")); assert false report Message.all severity error; DEALLOCATE(Message); end if; tmp_value := SLV_TO_INT(SLV=>di_in(4 downto 0)); if (address = 40) then if (((tmp_value = 6) or ( tmp_value = 7) or ((tmp_value >= 10) and (tmp_value <= 15)))) then Write ( Message, string'(" Invalid Input Warning : The DI bit[4:0] at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(" is ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in(4 downto 0)))); Write ( Message, string'(", which is invalid analog channel.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((cfg_reg1(13 downto 12)="11") and (di_in(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then Write ( Message, string'(" Invalid Input Warning : The DI value is ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); Write ( Message, string'(" at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(". Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((cfg_reg1(13 downto 12)="11") and (di_in(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then Write ( Message, string'(" Invalid Input Warning : The DI value is ")); Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); Write ( Message, string'(" at DADDR ")); Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); Write ( Message, string'(". Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((cfg_reg1(13 downto 12)="11") and (di_in(13 downto 12)/="00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are ")); Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1))); Write ( Message, string'(" and ")); Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2))); Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; end if; tmp_value := SLV_TO_INT(SLV=>cfg_reg0(4 downto 0)); if (address = 41) then if ((di_in(13 downto 12)="11") and (cfg_reg0(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is ")); Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0))); Write ( Message, string'(". Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((di_in(13 downto 12)="11") and (cfg_reg0(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is ")); Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0))); Write ( Message, string'(". Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((di_in(13 downto 12) /= "11") and (seq_acq_reg1(10 downto 0) /= "00000000000") and (seq_acq_reg1(15 downto 12) /= "0000")) then Write ( Message, string'(" Invalid Input Warning : The Control Regiter 4Eh is ")); Write ( Message, bit_vector'(TO_BITVECTOR(seq_acq_reg1))); Write ( Message, string'(". Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; if ((di_in(13 downto 12) = "11") and (cfg_reg0(13 downto 12) /= "00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are ")); Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1))); Write ( Message, string'(" and ")); Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2))); Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled.")); assert false report Message.all severity warning; DEALLOCATE(Message); end if; end if; end if; if (daddr_in = "1000001" ) then if (dwe_in = '1' and den_in = '1') then if (di_in(13 downto 12) /= cfg_reg1(13 downto 12)) then seq_reset <= '1'; else seq_reset <= '0'; end if; if (di_in(13 downto 12) /= "11" ) then seq_en_drp <= '1'; else seq_en_drp <= '0'; end if; else seq_reset <= '0'; seq_en_drp <= '0'; end if; else seq_reset <= '0'; seq_en_drp <= '0'; end if; end if; end process; tmp_dr_sram_out <= dr_sram(daddr_in_lat_int) when (daddr_in_lat_int >= 64 and daddr_in_lat_int <= 87) else "0000000000000000"; tmp_data_reg_out <= data_reg(daddr_in_lat_int) when (daddr_in_lat_int >= 0 and daddr_in_lat_int <= 38) else "0000000000000000"; do_out_rdtmp_p : process( daddr_in_lat, tmp_data_reg_out, tmp_dr_sram_out ) variable Message : line; variable valid_daddr : boolean := false; begin valid_daddr := addr_is_valid(daddr_in_lat); daddr_in_lat_int <= slv_to_int(daddr_in_lat); if (valid_daddr) then if ((daddr_in_lat_int > 88) or (daddr_in_lat_int >= 13 and daddr_in_lat_int <= 15) or (daddr_in_lat_int >= 39 and daddr_in_lat_int <= 63)) then do_out_rdtmp <= "XXXXXXXXXXXXXXXX"; end if; if ((daddr_in_lat_int >= 0 and daddr_in_lat_int <= 12) or (daddr_in_lat_int >= 16 and daddr_in_lat_int <= 38)) then do_out_rdtmp <= tmp_data_reg_out; elsif (daddr_in_lat_int >= 64 and daddr_in_lat_int <= 87) then do_out_rdtmp <= tmp_dr_sram_out; end if; end if; end process; -- end DRP RAM cfg_reg0 <= dr_sram(16#40#); cfg_reg1 <= dr_sram(16#41#); cfg_reg2 <= dr_sram(16#42#); seq_chan_reg1 <= dr_sram(16#48#); seq_chan_reg2 <= dr_sram(16#49#); seq_avg_reg1 <= dr_sram(16#4A#); seq_avg_reg2 <= dr_sram(16#4B#); seq_du_reg1 <= dr_sram(16#4C#); seq_du_reg2 <= dr_sram(16#4D#); seq_acq_reg1 <= dr_sram(16#4E#); seq_acq_reg2 <= dr_sram(16#4F#); seq1_0 <= cfg_reg1(13 downto 12); drp_update_p : process variable seq_bits : std_logic_vector( 1 downto 0); begin if (rst_in = '1') then wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); seq_bits := seq1_0; elsif (rising_edge(drp_update)) then seq_bits := curr_seq1_0; end if; if (rising_edge(drp_update) or (rst_in = '1')) then if (seq_bits = "00") then alarm_en <= "000"; ot_en <= '1'; else ot_en <= not cfg_reg1(0); alarm_en <= not cfg_reg1(3 downto 1); end if; end if; wait on drp_update, rst_in; end process; -- Clock divider, generate and adcclk sysclk_p : process(dclk_in) begin if (rising_edge(dclk_in)) then sysclk <= not sysclk; end if; end process; curr_clkdiv_sel_int_p : process (curr_clkdiv_sel) begin curr_clkdiv_sel_int <= SLV_TO_INT(curr_clkdiv_sel); end process; clk_count_p : process(dclk_in) variable clk_count : integer := -1; begin if (rising_edge(dclk_in)) then if (curr_clkdiv_sel_int > 2 ) then if (clk_count >= curr_clkdiv_sel_int - 1) then clk_count := 0; else clk_count := clk_count + 1; end if; if (clk_count > (curr_clkdiv_sel_int/2) - 1) then adcclk_tmp <= '1'; else adcclk_tmp <= '0'; end if; else adcclk_tmp <= not adcclk_tmp; end if; end if; end process; curr_clkdiv_sel <= cfg_reg2(15 downto 8); adcclk_div1 <= '0' when (curr_clkdiv_sel_int > 1) else '1'; adcclk <= not sysclk when adcclk_div1 = '1' else adcclk_tmp; -- end clock divider -- latch configuration registers acq_latch_p : process ( seq1_0, adc_s1_flag, curr_seq, cfg_reg0_adc, rst_in) begin if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10") then acq_acqsel <= curr_seq(8); elsif (seq1_0 = "11") then acq_acqsel <= cfg_reg0_adc(8); else acq_acqsel <= '0'; end if; if (rst_in = '0') then if (seq1_0 /= "11" and adc_s1_flag = '0') then acq_avg <= curr_seq(13 downto 12); acq_chan <= curr_seq(4 downto 0); acq_b_u <= curr_seq(10); else acq_avg <= cfg_reg0_adc(13 downto 12); acq_chan <= cfg_reg0_adc(4 downto 0); acq_b_u <= cfg_reg0_adc(10); end if; end if; end process; acq_chan_index <= SLV_TO_INT(acq_chan); conv_end_reg_read_P : process ( adcclk, rst_in) begin if (rst_in = '1') then conv_end_reg_read <= "0000"; elsif (rising_edge(adcclk)) then conv_end_reg_read(3 downto 1) <= conv_end_reg_read(2 downto 0); conv_end_reg_read(0) <= single_chan_conv_end or conv_end; end if; end process; -- synch to DCLK busy_reg_read_P : process ( dclk_in, rst_in) begin if (rst_in = '1') then busy_reg_read <= '1'; elsif (rising_edge(dclk_in)) then busy_reg_read <= not conv_end_reg_read(2); end if; end process; cfg_reg0_adc_P : process variable first_after_reset : std_ulogic := '1'; begin if (rst_in='1') then cfg_reg0_seq <= X"0000"; cfg_reg0_adc <= X"0000"; acq_e_c <= '0'; first_after_reset := '1'; elsif (falling_edge(busy_reg_read) or falling_edge(rst_in)) then wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); wait until (rising_edge(dclk_in)); if (first_after_reset = '1') then first_after_reset := '0'; cfg_reg0_adc <= cfg_reg0; cfg_reg0_seq <= cfg_reg0; else cfg_reg0_adc <= cfg_reg0_seq; cfg_reg0_seq <= cfg_reg0; end if; acq_e_c <= cfg_reg0(9); end if; wait on busy_reg_read, rst_in; end process; busy_r_p : process(conv_start, busy_r_rst, rst_in) begin if (rst_in = '1') then busy_r <= '0'; elsif (rising_edge(conv_start) and rst_lock = '0') then busy_r <= '1'; elsif (rising_edge(busy_r_rst)) then busy_r <= '0'; end if; end process; curr_seq1_0_p : process( busy_out) begin if (falling_edge( busy_out)) then if (adc_s1_flag = '1') then curr_seq1_0 <= "00"; else curr_seq1_0 <= seq1_0; end if; end if; end process; start_conv_p : process ( conv_start, rst_in) variable Message : line; begin if (rst_in = '1') then analog_mux_in <= 0.0; curr_chan <= "00000"; elsif (rising_edge(conv_start)) then if ( ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then analog_mux_in <= analog_in_diff(acq_chan_index); else analog_mux_in <= analog_in_uni(acq_chan_index); end if; curr_chan <= acq_chan; curr_seq1_0_lat <= curr_seq1_0; if (acq_chan_index = 6 or acq_chan_index = 7 or (acq_chan_index >= 10 and acq_chan_index <= 15)) then Write ( Message, string'(" Invalid Input Warning : The analog channel ")); Write ( Message, acq_chan_index); Write ( Message, string'(" to SYSMON is invalid.")); assert false report Message.all severity warning; end if; if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10" or seq1_0 = "00") then curr_avg_set <= curr_seq(13 downto 12); curr_b_u <= curr_seq(10); curr_e_c <= '0'; curr_acq <= curr_seq(8); else curr_avg_set <= acq_avg; curr_b_u <= acq_b_u; curr_e_c <= cfg_reg0(9); curr_acq <= cfg_reg0(8); end if; end if; end process; -- end latch configuration registers -- sequence control seq_en_dly <= seq_en after 1 ps; seq_num_p : process(seq_en_dly) variable seq_num_tmp : integer := 0; variable si_tmp : integer := 0; variable si : integer := 0; begin if (rising_edge(seq_en_dly)) then if (seq1_0 = "01" or seq1_0 = "10") then seq_num_tmp := 0; for I in 0 to 15 loop si := I; if (seq_chan_reg1(si) = '1') then seq_num_tmp := seq_num_tmp + 1; seq_mem(seq_num_tmp) <= si; end if; end loop; for I in 16 to 31 loop si := I; si_tmp := si-16; if (seq_chan_reg2(si_tmp) = '1') then seq_num_tmp := seq_num_tmp + 1; seq_mem(seq_num_tmp) <= si; end if; end loop; seq_num <= seq_num_tmp; elsif (seq1_0 = "00") then seq_num <= 4; seq_mem(1) <= 0; seq_mem(2) <= 8; seq_mem(3) <= 9; seq_mem(4) <= 10; end if; end if; end process; curr_seq_p : process(seq_count, seq_en_dly) variable seq_curr_i : std_logic_vector(4 downto 0); variable seq_curr_index : integer; variable tmp_value : integer; variable curr_seq_tmp : std_logic_vector(15 downto 0); begin if (seq_count'event or falling_edge(seq_en_dly)) then seq_curr_index := seq_mem(seq_count); seq_curr_i := STD_LOGIC_VECTOR(TO_UNSIGNED(seq_curr_index, 5)); curr_seq_tmp := "0000000000000000"; if (seq_curr_index >= 0 and seq_curr_index <= 15) then curr_seq_tmp(2 downto 0) := seq_curr_i(2 downto 0); curr_seq_tmp(4 downto 3) := "01"; curr_seq_tmp(8) := seq_acq_reg1(seq_curr_index); curr_seq_tmp(10) := seq_du_reg1(seq_curr_index); if (seq1_0 = "00") then curr_seq_tmp(13 downto 12) := "01"; elsif (seq_avg_reg1(seq_curr_index) = '1') then curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12); else curr_seq_tmp(13 downto 12) := "00"; end if; if (seq_curr_index >= 0 and seq_curr_index <= 7) then curr_seq_tmp(4 downto 3) := "01"; else curr_seq_tmp(4 downto 3) := "00"; end if; elsif (seq_curr_index >= 16 and seq_curr_index <= 31) then tmp_value := seq_curr_index -16; curr_seq_tmp(4 downto 0) := seq_curr_i; curr_seq_tmp(8) := seq_acq_reg2(tmp_value); curr_seq_tmp(10) := seq_du_reg2(tmp_value); if (seq_avg_reg2(tmp_value) = '1') then curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12); else curr_seq_tmp(13 downto 12) := "00"; end if; end if; curr_seq <= curr_seq_tmp; end if; end process; eos_en_p : process (adcclk, rst_in) begin if (rst_in = '1') then seq_count <= 1; eos_en <= '0'; elsif (rising_edge(adcclk)) then if ((seq_count = seq_num ) and (adc_state = CONV_STATE and next_state = END_STATE) and (curr_seq1_0_lat /= "11") and rst_lock = '0') then eos_tmp_en <= '1'; else eos_tmp_en <= '0'; end if; if ((eos_tmp_en = '1') and (seq_status_avg = 0)) then eos_en <= '1'; else eos_en <= '0'; end if; if (eos_tmp_en = '1' or curr_seq1_0_lat = "11") then seq_count <= 1; elsif (seq_count_en = '1' ) then if (seq_count >= 32) then seq_count <= 1; else seq_count <= seq_count +1; end if; end if; end if; end process; -- end sequence control -- Acquisition busy_out_dly <= busy_out after 10 ps; short_acq_p : process(adc_state, rst_in, first_acq) begin if (rst_in = '1') then shorten_acq <= 0; elsif (adc_state'event or first_acq'event) then if ((busy_out_dly = '0') and (adc_state=ACQ_STATE) and (first_acq='1')) then shorten_acq <= 1; else shorten_acq <= 0; end if; end if; end process; acq_count_p : process (adcclk, rst_in) begin if (rst_in = '1') then acq_count <= 1; first_acq <= '1'; elsif (rising_edge(adcclk)) then if (adc_state = ACQ_STATE and rst_lock = '0' and acq_e_c = '0') then first_acq <= '0'; if (acq_acqsel = '1') then if (acq_count <= 11) then acq_count <= acq_count + 1 + shorten_acq; end if; else if (acq_count <= 4) then acq_count <= acq_count + 1 + shorten_acq; end if; end if; if (next_state = CONV_STATE) then if ((acq_acqsel = '1' and acq_count < 10) or (acq_acqsel = '0' and acq_count < 4)) then assert false report "Warning: Acquisition time not enough for SYSMON." severity warning; end if; end if; else if (first_acq = '1') then acq_count <= 1; else acq_count <= 0; end if; end if; end if; end process; conv_start_con_p: process(adc_state, acq_acqsel, acq_count) begin if (adc_state = ACQ_STATE) then if (rst_lock = '0') then if ((seq_reset_flag = '0' or (seq_reset_flag = '1' and curr_clkdiv_sel_int > 3)) and ((acq_acqsel = '1' and acq_count > 10) or (acq_acqsel = '0' and acq_count > 4))) then conv_start_cont <= '1'; else conv_start_cont <= '0'; end if; end if; else conv_start_cont <= '0'; end if; end process; conv_start_sel <= convst_in when (acq_e_c = '1') else conv_start_cont; reset_conv_start_tmp <= '1' when (conv_count=2) else '0'; reset_conv_start <= rst_in or reset_conv_start_tmp; conv_start_p : process(conv_start_sel, reset_conv_start) begin if (reset_conv_start ='1') then conv_start <= '0'; elsif (rising_edge(conv_start_sel)) then conv_start <= '1'; end if; end process; -- end acquisition -- Conversion conv_result_p : process (adc_state, next_state, curr_chan, curr_chan_index, analog_mux_in, curr_b_u) variable conv_result_int_i : integer := 0; variable conv_result_int_tmp : integer := 0; variable conv_result_int_tmp_rl : real := 0.0; variable adc_analog_tmp : real := 0.0; begin if ((adc_state = CONV_STATE and next_state = END_STATE) or adc_state = END_STATE) then if (curr_chan = "00000") then -- temperature conversion adc_analog_tmp := (analog_mux_in + 273.0) * 130.0382; adc_temp_result <= adc_analog_tmp; if (adc_analog_tmp >= 65535.0) then conv_result_int_i := 65535; elsif (adc_analog_tmp < 0.0) then conv_result_int_i := 0; else conv_result_int_tmp := real2int(adc_analog_tmp); conv_result_int_tmp_rl := int2real(conv_result_int_tmp); if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then conv_result_int_i := conv_result_int_tmp + 1; else conv_result_int_i := conv_result_int_tmp; end if; end if; conv_result_int <= conv_result_int_i; conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); elsif (curr_chan = "00001" or curr_chan = "00010") then -- internal power conversion adc_analog_tmp := analog_mux_in * 65536.0 / 3.0; adc_intpwr_result <= adc_analog_tmp; if (adc_analog_tmp >= 65535.0) then conv_result_int_i := 65535; elsif (adc_analog_tmp < 0.0) then conv_result_int_i := 0; else conv_result_int_tmp := real2int(adc_analog_tmp); conv_result_int_tmp_rl := int2real(conv_result_int_tmp); if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then conv_result_int_i := conv_result_int_tmp + 1; else conv_result_int_i := conv_result_int_tmp; end if; end if; conv_result_int <= conv_result_int_i; conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); elsif ((curr_chan = "00011") or ((curr_chan_index >= 16) and (curr_chan_index <= 31))) then adc_analog_tmp := (analog_mux_in) * 65536.0; adc_ext_result <= adc_analog_tmp; if (curr_b_u = '1') then if (adc_analog_tmp > 32767.0) then conv_result_int_i := 32767; elsif (adc_analog_tmp < -32768.0) then conv_result_int_i := -32768; else conv_result_int_tmp := real2int(adc_analog_tmp); conv_result_int_tmp_rl := int2real(conv_result_int_tmp); if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then conv_result_int_i := conv_result_int_tmp + 1; else conv_result_int_i := conv_result_int_tmp; end if; end if; conv_result_int <= conv_result_int_i; conv_result <= STD_LOGIC_VECTOR(TO_SIGNED(conv_result_int_i, 16)); else if (adc_analog_tmp > 65535.0) then conv_result_int_i := 65535; elsif (adc_analog_tmp < 0.0) then conv_result_int_i := 0; else conv_result_int_tmp := real2int(adc_analog_tmp); conv_result_int_tmp_rl := int2real(conv_result_int_tmp); if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then conv_result_int_i := conv_result_int_tmp + 1; else conv_result_int_i := conv_result_int_tmp; end if; end if; conv_result_int <= conv_result_int_i; conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); end if; else conv_result_int <= 0; conv_result <= "0000000000000000"; end if; end if; end process; conv_count_p : process (adcclk, rst_in) begin if (rst_in = '1') then conv_count <= 6; conv_end <= '0'; seq_status_avg <= 0; busy_r_rst <= '0'; busy_r_rst_done <= '0'; for i in 0 to 31 loop conv_avg_count(i) <= 0; -- array of integer end loop; single_chan_conv_end <= '0'; elsif (rising_edge(adcclk)) then if (adc_state = ACQ_STATE) then if (busy_r_rst_done = '0') then busy_r_rst <= '1'; else busy_r_rst <= '0'; end if; busy_r_rst_done <= '1'; end if; if (adc_state = ACQ_STATE and conv_start = '1') then conv_count <= 0; conv_end <= '0'; elsif (adc_state = CONV_STATE ) then busy_r_rst_done <= '0'; conv_count <= conv_count + 1; if (((curr_chan /= "01000" ) and (conv_count = conv_time )) or ((curr_chan = "01000") and (conv_count = conv_time_cal_1) and (first_cal_chan = '1')) or ((curr_chan = "01000") and (conv_count = conv_time_cal) and (first_cal_chan = '0'))) then conv_end <= '1'; else conv_end <= '0'; end if; else conv_end <= '0'; conv_count <= 0; end if; single_chan_conv_end <= '0'; if ( (conv_count = conv_time) or (conv_count = 44)) then single_chan_conv_end <= '1'; end if; if (adc_state = CONV_STATE and next_state = END_STATE and rst_lock = '0') then case curr_avg_set is when "00" => eoc_en <= '1'; conv_avg_count(curr_chan_index) <= 0; when "01" => if (conv_avg_count(curr_chan_index) = 15) then eoc_en <= '1'; conv_avg_count(curr_chan_index) <= 0; seq_status_avg <= seq_status_avg - 1; else eoc_en <= '0'; if (conv_avg_count(curr_chan_index) = 0) then seq_status_avg <= seq_status_avg + 1; end if; conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; end if; when "10" => if (conv_avg_count(curr_chan_index) = 63) then eoc_en <= '1'; conv_avg_count(curr_chan_index) <= 0; seq_status_avg <= seq_status_avg - 1; else eoc_en <= '0'; if (conv_avg_count(curr_chan_index) = 0) then seq_status_avg <= seq_status_avg + 1; end if; conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; end if; when "11" => if (conv_avg_count(curr_chan_index) = 255) then eoc_en <= '1'; conv_avg_count(curr_chan_index) <= 0; seq_status_avg <= seq_status_avg - 1; else eoc_en <= '0'; if (conv_avg_count(curr_chan_index) = 0) then seq_status_avg <= seq_status_avg + 1; end if; conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; end if; when others => eoc_en <= '0'; end case; else eoc_en <= '0'; end if; if (adc_state = END_STATE) then conv_result_reg <= conv_result; end if; end if; end process; -- end conversion -- average conv_acc_result_p : process(adcclk, rst_in) variable conv_acc_vec : std_logic_vector(23 downto 0); variable conv_acc_vec_int : integer; begin if (rst_in = '1') then for j in 0 to 31 loop conv_acc(j) <= 0; end loop; conv_acc_result <= "0000000000000000"; elsif (rising_edge(adcclk)) then if (adc_state = CONV_STATE and next_state = END_STATE) then if (curr_avg_set /= "00" and rst_lock /= '1') then conv_acc(curr_chan_index) <= conv_acc(curr_chan_index) + conv_result_int; else conv_acc(curr_chan_index) <= 0; end if; elsif (eoc_en = '1') then conv_acc_vec_int := conv_acc(curr_chan_index); if ((curr_b_u = '1') and (((curr_chan_index >= 16) and (curr_chan_index <= 31)) or (curr_chan_index = 3))) then conv_acc_vec := STD_LOGIC_VECTOR(TO_SIGNED(conv_acc_vec_int, 24)); else conv_acc_vec := STD_LOGIC_VECTOR(TO_UNSIGNED(conv_acc_vec_int, 24)); end if; case curr_avg_set(1 downto 0) is when "00" => conv_acc_result <= "0000000000000000"; when "01" => conv_acc_result <= conv_acc_vec(19 downto 4); when "10" => conv_acc_result <= conv_acc_vec(21 downto 6); when "11" => conv_acc_result <= conv_acc_vec(23 downto 8); when others => conv_acc_result <= "0000000000000000"; end case; conv_acc(curr_chan_index) <= 0; end if; end if; end process; -- end average -- single sequence adc_s1_flag_p : process(adcclk, rst_in) begin if (rst_in = '1') then adc_s1_flag <= '0'; elsif (rising_edge(adcclk)) then if (adc_state = SINGLE_SEQ_STATE) then adc_s1_flag <= '1'; end if; end if; end process; -- end state eos_eoc_p: process(adcclk, rst_in) begin if (rst_in = '1') then seq_count_en <= '0'; eos_out_tmp <= '0'; eoc_out_tmp <= '0'; elsif (rising_edge(adcclk)) then if ((adc_state = CONV_STATE and next_state = END_STATE) and (curr_seq1_0_lat /= "11") and (rst_lock = '0')) then seq_count_en <= '1'; else seq_count_en <= '0'; end if; if (rst_lock = '0') then eos_out_tmp <= eos_en; eoc_en_delay <= eoc_en; eoc_out_tmp <= eoc_en_delay; else eos_out_tmp <= '0'; eoc_en_delay <= '0'; eoc_out_tmp <= '0'; end if; end if; end process; data_reg_p : process(eoc_out, rst_in_not_seq) variable tmp_uns1 : unsigned(15 downto 0); variable tmp_uns2 : unsigned(15 downto 0); variable tmp_uns3 : unsigned(15 downto 0); begin if (rst_in_not_seq = '1') then for k in 32 to 39 loop if (k >= 36) then data_reg(k) <= "1111111111111111"; else data_reg(k) <= "0000000000000000"; end if; end loop; elsif (rising_edge(eoc_out)) then if ( rst_lock = '0') then if ((curr_chan_index >= 0 and curr_chan_index <= 3) or (curr_chan_index >= 16 and curr_chan_index <= 31)) then if (curr_avg_set = "00") then data_reg(curr_chan_index) <= conv_result_reg; else data_reg(curr_chan_index) <= conv_acc_result; end if; end if; if (curr_chan_index = 4) then data_reg(curr_chan_index) <= X"D555"; end if; if (curr_chan_index = 5) then data_reg(curr_chan_index) <= X"0000"; end if; if (curr_chan_index = 0 or curr_chan_index = 1 or curr_chan_index = 2) then tmp_uns2 := UNSIGNED(data_reg(32 + curr_chan_index)); tmp_uns3 := UNSIGNED(data_reg(36 + curr_chan_index)); if (curr_avg_set = "00") then tmp_uns1 := UNSIGNED(conv_result_reg); if (tmp_uns1 > tmp_uns2) then data_reg(32 + curr_chan_index) <= conv_result_reg; end if; if (tmp_uns1 < tmp_uns3) then data_reg(36 + curr_chan_index) <= conv_result_reg; end if; else tmp_uns1 := UNSIGNED(conv_acc_result); if (tmp_uns1 > tmp_uns2) then data_reg(32 + curr_chan_index) <= conv_acc_result; end if; if (tmp_uns1 < tmp_uns3) then data_reg(36 + curr_chan_index) <= conv_acc_result; end if; end if; end if; end if; end if; end process; data_written_p : process(busy_r, rst_in_not_seq) begin if (rst_in_not_seq = '1') then data_written <= X"0000"; elsif (falling_edge(busy_r)) then if (curr_avg_set = "00") then data_written <= conv_result_reg; else data_written <= conv_acc_result; end if; end if; end process; -- eos and eoc eoc_out_tmp1_p : process (eoc_out_tmp, eoc_out, rst_in) begin if (rst_in = '1') then eoc_out_tmp1 <= '0'; elsif (rising_edge(eoc_out)) then eoc_out_tmp1 <= '0'; elsif (rising_edge(eoc_out_tmp)) then if (curr_chan /= "01000") then eoc_out_tmp1 <= '1'; else eoc_out_tmp1 <= '0'; end if; end if; end process; eos_out_tmp1_p : process (eos_out_tmp, eos_out, rst_in) begin if (rst_in = '1') then eos_out_tmp1 <= '0'; elsif (rising_edge(eos_out)) then eos_out_tmp1 <= '0'; elsif (rising_edge(eos_out_tmp)) then eos_out_tmp1 <= '1'; end if; end process; busy_out_low_edge <= '1' when (busy_out='0' and busy_out_sync='1') else '0'; eoc_eos_out_p : process (dclk_in, rst_in) begin if (rst_in = '1') then op_count <= 15; busy_out_sync <= '0'; drp_update <= '0'; alarm_update <= '0'; eoc_out <= '0'; eos_out <= '0'; elsif ( rising_edge(dclk_in)) then busy_out_sync <= busy_out; if (op_count = 3) then drp_update <= '1'; else drp_update <= '0'; end if; if (op_count = 5 and eoc_out_tmp1 = '1') then alarm_update <= '1'; else alarm_update <= '0'; end if; if (op_count = 9 ) then eoc_out <= eoc_out_tmp1; else eoc_out <= '0'; end if; if (op_count = 9) then eos_out <= eos_out_tmp1; else eos_out <= '0'; end if; if (busy_out_low_edge = '1') then op_count <= 0; elsif (op_count < 15) then op_count <= op_count +1; end if; end if; end process; -- end eos and eoc -- alarm alm_reg_p : process(alarm_update, rst_in_not_seq ) variable tmp_unsig1 : unsigned(15 downto 0); variable tmp_unsig2 : unsigned(15 downto 0); variable tmp_unsig3 : unsigned(15 downto 0); begin if (rst_in_not_seq = '1') then ot_out_reg <= '0'; alarm_out_reg <= "000"; elsif (rising_edge(alarm_update)) then if (rst_lock = '0') then if (curr_chan_lat = "00000") then tmp_unsig1 := UNSIGNED(data_written); tmp_unsig2 := UNSIGNED(dr_sram(16#57#)); if (tmp_unsig1 >= ot_limit_reg) then ot_out_reg <= '1'; elsif (((tmp_unsig1 < tmp_unsig2) and (curr_seq1_0_lat /= "00")) or ((curr_seq1_0_lat = "00") and (tmp_unsig1 < ot_sf_limit_low_reg))) then ot_out_reg <= '0'; end if; tmp_unsig2 := UNSIGNED(dr_sram(16#50#)); tmp_unsig3 := UNSIGNED(dr_sram(16#54#)); if ( tmp_unsig1 > tmp_unsig2) then alarm_out_reg(0) <= '1'; elsif (tmp_unsig1 <= tmp_unsig3) then alarm_out_reg(0) <= '0'; end if; end if; tmp_unsig1 := UNSIGNED(data_written); tmp_unsig2 := UNSIGNED(dr_sram(16#51#)); tmp_unsig3 := UNSIGNED(dr_sram(16#55#)); if (curr_chan_lat = "00001") then if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then alarm_out_reg(1) <= '1'; else alarm_out_reg(1) <= '0'; end if; end if; tmp_unsig1 := UNSIGNED(data_written); tmp_unsig2 := UNSIGNED(dr_sram(16#52#)); tmp_unsig3 := UNSIGNED(dr_sram(16#56#)); if (curr_chan_lat = "00010") then if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then alarm_out_reg(2) <= '1'; else alarm_out_reg(2) <= '0'; end if; end if; end if; end if; end process; alm_p : process(ot_out_reg, ot_en, alarm_out_reg, alarm_en) begin ot_out <= ot_out_reg and ot_en; alarm_out(0) <= alarm_out_reg(0) and alarm_en(0); alarm_out(1) <= alarm_out_reg(1) and alarm_en(1); alarm_out(2) <= alarm_out_reg(2) and alarm_en(2); end process; -- end alarm READFILE_P : process file in_file : text; variable open_status : file_open_status; variable in_buf : line; variable str_token : string(1 to 12); variable str_token_in : string(1 to 12); variable str_token_tmp : string(1 to 12); variable next_time : time := 0 ps; variable pre_time : time := 0 ps; variable time_val : integer := 0; variable a1 : real; variable commentline : boolean := false; variable HeaderFound : boolean := false; variable read_ok : boolean := false; variable token_len : integer; variable HeaderCount : integer := 0; variable vals : ANALOG_DATA := (others => 0.0); variable valsn : ANALOG_DATA := (others => 0.0); variable inchannel : integer := 0 ; type int_a is array (0 to 41) of integer; variable index_to_channel : int_a := (others => -1); variable low : integer := -1; variable low2 : integer := -1; variable sim_file_flag1 : std_ulogic := '0'; variable file_line : integer := 0; type channm_array is array (0 to 31 ) of string(1 to 12); constant chanlist_p : channm_array := ( 0 => "TEMP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 1 => "VCCINT" & NUL & NUL & NUL & NUL & NUL & NUL, 2 => "VCCAUX" & NUL & NUL & NUL & NUL & NUL & NUL, 3 => "VP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 6 => "xxxxxxxxxxxx", 7 => "xxxxxxxxxxxx", 8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 10 => "xxxxxxxxxxxx", 11 => "xxxxxxxxxxxx", 12 => "xxxxxxxxxxxx", 13 => "xxxxxxxxxxxx", 14 => "xxxxxxxxxxxx", 15 => "xxxxxxxxxxxx", 16 => "VAUXP[0]" & NUL & NUL & NUL & NUL, 17 => "VAUXP[1]" & NUL & NUL & NUL & NUL, 18 => "VAUXP[2]" & NUL & NUL & NUL & NUL, 19 => "VAUXP[3]" & NUL & NUL & NUL & NUL, 20 => "VAUXP[4]" & NUL & NUL & NUL & NUL, 21 => "VAUXP[5]" & NUL & NUL & NUL & NUL, 22 => "VAUXP[6]" & NUL & NUL & NUL & NUL, 23 => "VAUXP[7]" & NUL & NUL & NUL & NUL, 24 => "VAUXP[8]" & NUL & NUL & NUL & NUL, 25 => "VAUXP[9]" & NUL & NUL & NUL & NUL, 26 => "VAUXP[10]" & NUL & NUL & NUL, 27 => "VAUXP[11]" & NUL & NUL & NUL, 28 => "VAUXP[12]" & NUL & NUL & NUL, 29 => "VAUXP[13]" & NUL & NUL & NUL, 30 => "VAUXP[14]" & NUL & NUL & NUL, 31 => "VAUXP[15]" & NUL & NUL & NUL ); constant chanlist_n : channm_array := ( 0 => "xxxxxxxxxxxx", 1 => "xxxxxxxxxxxx", 2 => "xxxxxxxxxxxx", 3 => "VN" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 6 => "xxxxxxxxxxxx", 7 => "xxxxxxxxxxxx", 8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, 10 => "xxxxxxxxxxxx", 11 => "xxxxxxxxxxxx", 12 => "xxxxxxxxxxxx", 13 => "xxxxxxxxxxxx", 14 => "xxxxxxxxxxxx", 15 => "xxxxxxxxxxxx", 16 => "VAUXN[0]" & NUL & NUL & NUL & NUL, 17 => "VAUXN[1]" & NUL & NUL & NUL & NUL, 18 => "VAUXN[2]" & NUL & NUL & NUL & NUL, 19 => "VAUXN[3]" & NUL & NUL & NUL & NUL, 20 => "VAUXN[4]" & NUL & NUL & NUL & NUL, 21 => "VAUXN[5]" & NUL & NUL & NUL & NUL, 22 => "VAUXN[6]" & NUL & NUL & NUL & NUL, 23 => "VAUXN[7]" & NUL & NUL & NUL & NUL, 24 => "VAUXN[8]" & NUL & NUL & NUL & NUL, 25 => "VAUXN[9]" & NUL & NUL & NUL & NUL, 26 => "VAUXN[10]" & NUL & NUL & NUL, 27 => "VAUXN[11]" & NUL & NUL & NUL, 28 => "VAUXN[12]" & NUL & NUL & NUL, 29 => "VAUXN[13]" & NUL & NUL & NUL, 30 => "VAUXN[14]" & NUL & NUL & NUL, 31 => "VAUXN[15]" & NUL & NUL & NUL ); begin file_open(open_status, in_file, SIM_MONITOR_FILE, read_mode); if (open_status /= open_ok) then assert false report "*** Warning: The analog data file for SYSMON was not found. Use the SIM_MONITOR_FILE generic to specify the input analog data file name or use default name: design.txt. " severity warning; sim_file_flag1 := '1'; sim_file_flag <= '1'; end if; if ( sim_file_flag1 = '0') then while (not endfile(in_file) and (not HeaderFound)) loop commentline := false; readline(in_file, in_buf); file_line := file_line + 1; if (in_buf'LENGTH > 0 ) then skip_blanks(in_buf); low := in_buf'low; low2 := in_buf'low+2; if ( low2 <= in_buf'high) then if ((in_buf(in_buf'low to in_buf'low+1) = "//" ) or (in_buf(in_buf'low to in_buf'low+1) = "--" )) then commentline := true; end if; while((in_buf'LENGTH > 0 ) and (not commentline)) loop HeaderFound := true; get_token(in_buf, str_token_in, token_len); str_token_tmp := To_Upper(str_token_in); if (str_token_tmp(1 to 4) = "TEMP") then str_token := "TEMP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL; else str_token := str_token_tmp; end if; if(token_len > 0) then HeaderCount := HeaderCount + 1; end if; if (HeaderCount=1) then if (str_token(1 to token_len) /= "TIME") then infile_format; assert false report " Analog Data File Error : No TIME label is found in the input file for SYSMON." severity failure; end if; elsif (HeaderCount > 1) then inchannel := -1; for i in 0 to 31 loop if (chanlist_p(i) = str_token) then inchannel := i; index_to_channel(headercount) := i; end if; end loop; if (inchannel = -1) then for i in 0 to 31 loop if ( chanlist_n(i) = str_token) then inchannel := i; index_to_channel(headercount) := i+32; end if; end loop; end if; if (inchannel = -1 and token_len >0) then infile_format; assert false report "Analog Data File Error : No valid channel name in the input file for SYSMON. Valid names: TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ....." severity failure; end if; else infile_format; assert false report "Analog Data File Error : NOT found header in the input file for SYSMON. The header is: TIME TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ..." severity failure; end if; str_token_in := NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL; end loop; end if; end if; end loop; ----- Read Values while (not endfile(in_file)) loop commentline := false; readline(in_file, in_buf); file_line := file_line + 1; if (in_buf'length > 0) then skip_blanks(in_buf); if (in_buf'low < in_buf'high) then if((in_buf(in_buf'low to in_buf'low+1) = "//" ) or (in_buf(in_buf'low to in_buf'low+1) = "--" )) then commentline := true; end if; if(not commentline and in_buf'length > 0) then for i IN 1 to HeaderCount Loop if ( i=1) then read(in_buf, time_val, read_ok); if (not read_ok) then infile_format; assert false report " Analog Data File Error : The time value should be integer in ns scale and the last time value needs bigger than simulation time." severity failure; end if; next_time := time_val * 1 ns; else read(in_buf, a1, read_ok); if (not read_ok) then assert false report "*** Analog Data File Error: The data type should be REAL, e.g. 3.0 0.0 -0.5 " severity failure; end if; inchannel:= index_to_channel(i); if (inchannel >= 32) then valsn(inchannel-32):=a1; else vals(inchannel):=a1; end if; end if; end loop; -- i loop if ( now < next_time) then wait for ( next_time - now ); end if; for i in 0 to 31 loop chan_val_tmp(i) <= vals(i); chan_valn_tmp(i) <= valsn(i); analog_in_diff(i) <= vals(i)-valsn(i); analog_in_uni(i) <= vals(i); end loop; end if; end if; end if; end loop; -- while loop file_close(in_file); end if; wait; end process READFILE_P; end SYSMON_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity INV is port( O : out std_ulogic; I : in std_ulogic ); end INV; architecture INV_V of INV is begin O <= (not TO_X01(I)); end INV_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; use unisim.VCOMPONENTS.all; entity LUT2_L is generic( INIT : bit_vector := X"0" ); port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic ); end LUT2_L; architecture LUT2_L_V of LUT2_L is begin VITALBehavior : process (I0, I1) variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); variable address : std_logic_vector(1 downto 0); variable address_int : integer := 0; begin address := I1 & I0; address_int := SLV_TO_INT(address(1 downto 0)); if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then LO <= INIT_reg(address_int); else if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and (INIT_reg(0) = INIT_reg(2))) then LO <= INIT_reg(0); elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then LO <= INIT_reg(0); elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then LO <= INIT_reg(2); elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then LO <= INIT_reg(0); elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then LO <= INIT_reg(1); else LO <= 'X'; end if; end if; end process; end LUT2_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT4 is generic( INIT : bit_vector := X"0000" ); port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic ); end LUT4; architecture LUT4_V of LUT4 is function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' and (d(0) xor d(2)) = '0') then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3) -- variable INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); variable I_reg : std_logic_vector(3 downto 0); begin I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0); if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then O <= INIT_reg(SLV_TO_INT(I_reg)); else O <= lut4_mux4 ( (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2)); end if; end process; end LUT4_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT3 is generic( INIT : bit_vector := X"00" ); port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic ); end LUT3; architecture LUT3_V of LUT3 is function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0)) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' and (d(0) xor d(2)) = '0') then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT); begin VITALBehavior : process (I0, I1, I2) variable I_reg : std_logic_vector(2 downto 0); begin I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0); if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then O <= INIT_reg(SLV_TO_INT(I_reg)); else O <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) & lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2))); end if; end process; end LUT3_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT2 is generic( INIT : bit_vector := X"0" ); port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic ); end LUT2; architecture LUT2_V of LUT2 is begin VITALBehavior : process (I0, I1) variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); variable address : std_logic_vector(1 downto 0); variable address_int : integer := 0; begin address := I1 & I0; address_int := SLV_TO_INT(address(1 downto 0)); if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then O <= INIT_reg(address_int); else if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and (INIT_reg(0) = INIT_reg(2))) then O <= INIT_reg(0); elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then O <= INIT_reg(0); O <= INIT_reg(0); elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then O <= INIT_reg(2); elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then O <= INIT_reg(0); elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then O <= INIT_reg(1); else O <= 'X'; end if; end if; end process; end LUT2_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDC is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CLR : in std_ulogic; D : in std_ulogic ); end FDC; architecture FDC_V of FDC is begin VITALBehavior : process(CLR, C) variable FIRST_TIME : boolean := true; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (CLR = '1') then Q <= '0'; elsif (rising_edge(C)) then Q <= D after 100 ps; end if; end process; end FDC_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT3_L is generic( INIT : bit_vector := X"00" ); port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic ); end LUT3_L; architecture LUT3_L_V of LUT3_L is function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0)) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' and (d(0) xor d(2)) = '0') then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT); begin VITALBehavior : process (I0, I1, I2) variable I_reg : std_logic_vector(2 downto 0); begin I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0); if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then LO <= INIT_reg(SLV_TO_INT(I_reg)); else LO <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) & lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2))); end if; end process; end LUT3_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity LUT1 is generic( INIT : bit_vector := X"0" ); port( O : out std_ulogic; I0 : in std_ulogic ); end LUT1; architecture LUT1_V of LUT1 is begin VITALBehavior : process (I0) variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); begin if (INIT_reg(0) = INIT_reg(1)) then O <= INIT_reg(0); elsif (I0 = '0') then O <= INIT_reg(0); elsif (I0 = '1') then O <= INIT_reg(1); else O <= 'X'; end if; end process; end LUT1_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT4_L is generic( INIT : bit_vector := X"0000" ); port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic ); end LUT4_L; architecture LUT4_L_V of LUT4_L is function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) = d(1)) and (d(2) = d(3)) and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3) variable I_reg : std_logic_vector(3 downto 0); begin I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0); if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then LO <= INIT_reg(SLV_TO_INT(I_reg)); else LO <= lut4_mux4 ( (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) & lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2)); end if; end process; end LUT4_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDCE is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; CLR : in std_ulogic; D : in std_ulogic ); end FDCE; architecture FDCE_V of FDCE is begin VITALBehavior : process(C, CLR) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (CLR = '1') then Q <= '0'; elsif (rising_edge(C)) then if (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDCE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDC_1 is generic( INIT : bit := '0' ); port( Q : out std_ulogic; C : in std_ulogic; CLR : in std_ulogic; D : in std_ulogic ); end FDC_1; architecture FDC_1_V of FDC_1 is begin VITALBehavior : process(C, CLR) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (CLR = '1') then Q <= '0'; elsif (falling_edge(C)) then Q <= D after 100 ps; end if; end process; end FDC_1_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDS is generic( INIT : bit := '1' ); port( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end FDS; architecture FDS_V of FDS is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (S = '1') then Q <= '1' after 100 ps; else Q <= D after 100 ps; end if; end if; end process; end FDS_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXCY is port( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end MUXCY; architecture MUXCY_V of MUXCY is begin VITALBehavior : process (CI, DI, S) begin if (S = '0') then O <= DI; elsif (S = '1') then O <= CI; end if; end process; end MUXCY_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity LUT1_L is generic( INIT : bit_vector := X"0" ); port( LO : out std_ulogic; I0 : in std_ulogic ); end LUT1_L; architecture LUT1_L_V of LUT1_L is begin VITALBehavior : process (I0) variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); begin if (I0 = '0') then LO <= INIT_reg(0); elsif (I0 = '1') then LO <= INIT_reg(1); elsif (INIT_reg(0) = INIT_reg(1)) then LO <= INIT_reg(0); else LO <= 'X'; end if; end process; end LUT1_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXF6 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end MUXF6; architecture MUXF6_V of MUXF6 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; elsif (S = '1') then O <= I1; end if; end process; end MUXF6_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXF5_D is port( LO : out std_ulogic; O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end MUXF5_D; architecture MUXF5_D_V of MUXF5_D is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; LO <= I0; elsif (S = '1') then O <= I1; LO <= I1; end if; end process; end MUXF5_D_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity XORCY is port( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end XORCY; architecture XORCY_V of XORCY is begin O <= (CI xor LI); end XORCY_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXCY_L is port( LO : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end MUXCY_L; architecture MUXCY_L_V of MUXCY_L is begin VITALBehavior : process (CI, DI, S) begin if (S = '0') then LO <= DI; elsif (S = '1') then LO <= CI; end if; end process; end MUXCY_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDSE is generic( INIT : bit := '1' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end FDSE; architecture FDSE_V of FDSE is begin VITALBehavior : process(C) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (rising_edge(C)) then if (S = '1') then Q <= '1' after 100 ps; elsif (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDSE_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MULT_AND is port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic ); end MULT_AND; architecture MULT_AND_V of MULT_AND is begin VITALBehavior : process (I1, I0) begin LO <= (I0 and I1) after 0 ps; end process; end MULT_AND_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDP is generic( INIT : bit := '1' ); port( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; PRE : in std_ulogic ); end FDP; architecture FDP_V of FDP is begin VITALBehavior : process(C, PRE) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then Q <= D after 100 ps; end if; end process; end FDP_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity SRL16E is generic ( INIT : bit_vector := X"0000" ); port ( Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC ); end SRL16E; architecture SRL16E_V of SRL16E is signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); begin VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) variable VALID_ADDR : boolean := FALSE; variable LENGTH : integer; variable ADDR : std_logic_vector(3 downto 0); begin ADDR := (A3, A2, A1, A0); VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); if (VALID_ADDR) then LENGTH := SLV_TO_INT(SLV => ADDR); else LENGTH := 16; end if; Q <= SHIFT_REG(LENGTH); end process VITALReadBehavior; VITALWriteBehavior : process variable FIRST_TIME : boolean := TRUE; begin if (FIRST_TIME) then wait until ((CE = '1' or CE = '0') and (CLK'last_value = '0' or CLK'last_value = '1') and (CLK = '0' or CLK = '1')); FIRST_TIME := FALSE; end if; if (CLK'event AND CLK'last_value = '0') then if (CLK = '1') then if (CE = '1') then for I in 15 downto 1 loop SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; end loop; SHIFT_REG(0) <= D after 100 ps; elsif (CE = 'X') then SHIFT_REG <= (others => 'X') after 100 ps; end if; elsif (CLK = 'X') then if (CE /= '0') then SHIFT_REG <= (others => 'X') after 100 ps; end if; end if; elsif (CLK'event AND CLK'last_value = 'X') then if (CLK = '1') then if (CE /= '0') then SHIFT_REG <= (others => 'X') after 100 ps; end if; end if; end if; wait on CLK; end process VITALWriteBehavior; end SRL16E_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity ROM256X1 is generic ( INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic; A6 : in std_ulogic; A7 : in std_ulogic ); end ROM256X1; architecture ROM256X1_V of ROM256X1 is begin VITALBehavior : process (A7, A6, A5, A4, A3, A2, A1, A0) variable INIT_BITS : std_logic_vector(255 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; variable MEM : std_logic_vector( 256 downto 0 ); variable Index : integer := 256; variable Raddress : std_logic_vector (7 downto 0); variable FIRST_TIME : boolean := true; begin if (FIRST_TIME = true) then INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT ); MEM := ('X' & INIT_BITS(255 downto 0)); FIRST_TIME := false; end if; Raddress := (A7, A6, A5, A4, A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Raddress ); O <= MEM(Index); end process VITALBehavior; end ROM256X1_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity FDPE is generic( INIT : bit := '1' ); port( Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D : in std_ulogic; PRE : in std_ulogic ); end FDPE; architecture FDPE_V of FDPE is begin VITALBehavior : process(C, PRE) variable FIRST_TIME : boolean := true ; begin if (FIRST_TIME = true) then Q <= TO_X01(INIT); FIRST_TIME := false; end if; if (PRE = '1') then Q <= '1'; elsif (rising_edge(C)) then if (CE = '1') then Q <= D after 100 ps; end if; end if; end process; end FDPE_V; library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.Vpkg.all; entity MULT18X18 is port ( P : out std_logic_vector (35 downto 0); A : in std_logic_vector (17 downto 0); B : in std_logic_vector (17 downto 0) ); end MULT18X18; architecture MULT18X18_V of MULT18X18 is function INT_TO_SLV(ARG: integer; SIZE: integer) return std_logic_vector is variable result : std_logic_vector (SIZE-1 downto 0); variable temp : integer := ARG; begin temp := ARG; for i in 0 to SIZE-1 loop if (temp mod 2) = 1 then result(i) := '1'; else result(i) := '0'; end if; if temp > 0 then temp := temp /2 ; elsif (temp > integer'low) then temp := (temp-1) / 2; else temp := temp / 2; end if; end loop; return result; end; function COMPLEMENT(ARG: std_logic_vector ) return std_logic_vector is variable RESULT : std_logic_vector (ARG'left downto 0); variable found1 : std_ulogic := '0'; begin for i in 0 to ARG'left loop if (found1 = '0') then RESULT(i) := ARG(i); if (ARG(i) = '1' ) then found1 := '1'; end if; else RESULT(i) := not ARG(i); end if; end loop; return result; end; function VECPLUS(A, B: std_logic_vector ) return std_logic_vector is variable carry: std_ulogic; variable BV, sum: std_logic_vector(A'left downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then sum := (others => 'X'); return(sum); end if; carry := '0'; BV := B; for i in 0 to A'left loop sum(i) := A(i) xor BV(i) xor carry; carry := (A(i) and BV(i)) or (A(i) and carry) or (carry and BV(i)); end loop; return sum; end; begin VITALBehaviour : process (A, B) variable O_zd,O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0); variable IA, IB1,IB2 : integer ; variable sign : std_ulogic := '0'; variable A_i : std_logic_vector(A'left downto 0); variable B_i : std_logic_vector(B'left downto 0); begin if (Is_X(A) or Is_X(B) ) then O_zd := (others => 'X'); else if (A(A'left) = '1' ) then A_i := complement(A); else A_i := A; end if; if (B(B'left) = '1') then B_i := complement(B); else B_i := B; end if; IA := SLV_TO_INT(A_i); IB1 := SLV_TO_INT(B_i (17 downto 9)); IB2 := SLV_TO_INT(B_i (8 downto 0)); O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length); -- shift I1_zd 9 to the left for j in 0 to 8 loop O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0'; end loop; O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length); O_zd := VECPLUS(O1_zd, O2_zd); sign := A(A'left) xor B(B'left); if (sign = '1' ) then O_zd := complement(O_zd); end if; end if; P <= O_zd; end process VITALBehaviour; end MULT18X18_V ; library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.Vpkg.all; entity MULT18X18S is port ( P : out std_logic_vector (35 downto 0); A : in std_logic_vector (17 downto 0); B : in std_logic_vector (17 downto 0); C : in std_ulogic; CE : in std_ulogic; R : in std_ulogic ); end MULT18X18S; architecture MULT18X18S_V of MULT18X18S is function INT_TO_SLV(ARG : integer; SIZE : integer) return std_logic_vector is variable result : std_logic_vector (SIZE-1 downto 0); variable temp : integer := ARG; begin temp := ARG; for i in 0 to SIZE-1 loop if (temp mod 2) = 1 then result(i) := '1'; else result(i) := '0'; end if; if temp > 0 then temp := temp /2; elsif (temp > integer'low) then temp := (temp-1) / 2; else temp := temp / 2; end if; end loop; return result; end; function COMPLEMENT(ARG : std_logic_vector ) return std_logic_vector is variable RESULT : std_logic_vector (ARG'left downto 0); variable found1 : std_ulogic := '0'; begin for i in 0 to ARG'left loop if (found1 = '0') then RESULT(i) := ARG(i); if (ARG(i) = '1' ) then found1 := '1'; end if; else RESULT(i) := not ARG(i); end if; end loop; return result; end; function VECPLUS(A, B : std_logic_vector ) return std_logic_vector is variable carry : std_ulogic; variable BV, sum : std_logic_vector(A'left downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then sum := (others => 'X'); return(sum); end if; carry := '0'; BV := B; for i in 0 to A'left loop sum(i) := A(i) xor BV(i) xor carry; carry := (A(i) and BV(i)) or (A(i) and carry) or (carry and BV(i)); end loop; return sum; end; begin VITALBehaviour : process (C) variable O_zd, O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0); variable B1_zd, B2_zd : bit_vector(A'length+B'length-1 downto 0); variable IA, IB1, Ib2 : integer; variable sign : std_ulogic := '0'; variable A_i : std_logic_vector(A'left downto 0); variable B_i : std_logic_vector(B'left downto 0); begin if (rising_edge(C)) then if (R = '1' ) then O_zd := (others => '0'); elsif (CE = '1' ) then if (Is_X(A) or Is_X(B) ) then O_zd := (others => 'X'); else if (A(A'left) = '1' ) then A_i := complement(A); else A_i := A; end if; if (B(B'left) = '1') then B_i := complement(B); else B_i := B; end if; IA := SLV_TO_INT(A_i); IB1 := SLV_TO_INT(B_i (17 downto 9)); IB2 := SLV_TO_INT(B_i (8 downto 0)); O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length); for j in 0 to 8 loop O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0'; end loop; O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length); O_zd := VECPLUS(O1_zd, O2_zd); sign := A(A'left) xor B(B'left); if (sign = '1' ) then O_zd := complement(O_zd); end if; end if; end if; end if; P <= O_zd after 100 ps; end process VITALBehaviour; end MULT18X18S_V; library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.Vpkg.all; entity ROM128X1 is generic ( INIT : bit_vector := X"00000000000000000000000000000000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic; A6 : in std_ulogic ); end ROM128X1; architecture ROM128X1_V of ROM128X1 is begin VITALBehavior : process (A6, A5, A4, A3, A2, A1, A0) variable INIT_BITS : std_logic_vector(127 downto 0) := To_StdLogicVector(INIT); variable MEM : std_logic_vector( 128 downto 0 ); variable Index : integer := 128; variable Raddress : std_logic_vector (6 downto 0); variable FIRST_TIME : boolean := true; begin if (FIRST_TIME = true) then MEM := ('X' & INIT_BITS(127 downto 0)); FIRST_TIME := false; end if; Raddress := (A6, A5, A4, A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Raddress); O <= MEM(Index); end process VITALBehavior; end ROM128X1_V; library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.Vpkg.all; entity ROM16X1 is generic ( INIT : bit_vector := X"0000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic ); end ROM16X1; architecture ROM16X1_V of ROM16X1 is begin VITALBehavior : process (A3, A2, A1, A0) variable INIT_BITS : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); variable MEM : std_logic_vector( 16 downto 0 ) ; variable Index : integer := 16; variable FIRST_TIME : boolean := TRUE; begin if (FIRST_TIME = TRUE) then MEM := ('X' & INIT_BITS(15 downto 0)); FIRST_TIME := FALSE; end if; Index := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); O <= MEM(Index); end process VITALBehavior; end ROM16X1_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXF7 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end MUXF7; architecture MUXF7_V of MUXF7 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; elsif (S = '1') then O <= I1; end if; end process; end MUXF7_V; ----- CELL IODELAY ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.vpkg.all; entity IODELAY is generic( DELAY_SRC : string := "I"; HIGH_PERFORMANCE_MODE : boolean := true; IDELAY_TYPE : string := "DEFAULT"; IDELAY_VALUE : integer := 0; ODELAY_VALUE : integer := 0; REFCLK_FREQUENCY : real := 200.0; SIGNAL_PATTERN : string := "DATA" ); port( DATAOUT : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; DATAIN : in std_ulogic; IDATAIN : in std_ulogic; INC : in std_ulogic; ODATAIN : in std_ulogic; RST : in std_ulogic; T : in std_ulogic ); end IODELAY; architecture IODELAY_V OF IODELAY is constant ILEAK_ADJUST : real := 1.0; constant D_IOBDELAY_OFFSET : real := 0.0; ----------------------------------------------------------- constant MAX_IDELAY_COUNT : integer := 63; constant MIN_IDELAY_COUNT : integer := 0; constant MAX_ODELAY_COUNT : integer := 63; constant MIN_ODELAY_COUNT : integer := 0; constant MAX_REFCLK_FREQUENCY : real := 225.0; constant MIN_REFCLK_FREQUENCY : real := 175.0; signal C_ipd : std_ulogic := 'X'; signal CE_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal DATAIN_ipd : std_ulogic := 'X'; signal IDATAIN_ipd : std_ulogic := 'X'; signal INC_ipd : std_ulogic := 'X'; signal ODATAIN_ipd : std_ulogic := 'X'; signal RST_ipd : std_ulogic := 'X'; signal T_ipd : std_ulogic := 'X'; signal C_dly : std_ulogic := 'X'; signal CE_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := '0'; signal DATAIN_dly : std_ulogic := 'X'; signal IDATAIN_dly : std_ulogic := 'X'; signal INC_dly : std_ulogic := 'X'; signal ODATAIN_dly : std_ulogic := 'X'; signal RST_dly : std_ulogic := 'X'; signal T_dly : std_ulogic := 'X'; signal IDATAOUT_delayed : std_ulogic := 'X'; -- signal IDATAOUT_zd : std_ulogic := 'X'; -- signal IDATAOUT_viol : std_ulogic := 'X'; signal ODATAOUT_delayed : std_ulogic := 'X'; -- signal ODATAOUT_zd : std_ulogic := 'X'; -- signal ODATAOUT_viol : std_ulogic := 'X'; signal DATAOUT_zd : std_ulogic := 'X'; -- signal DATAOUT_viol : std_ulogic := 'X'; signal iDelay : time := 0.0 ps; signal oDelay : time := 0.0 ps; signal idata_mux : std_ulogic := 'X'; signal Violation : std_ulogic := '0'; begin --------------------- -- INPUT PATH DELAYs -------------------- C_dly <= C after 0 ps; CE_dly <= CE after 0 ps; DATAIN_dly <= DATAIN after 0 ps; IDATAIN_dly <= IDATAIN after 0 ps; INC_dly <= INC after 0 ps; ODATAIN_dly <= ODATAIN after 0 ps; RST_dly <= RST after 0 ps; T_dly <= T after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process variable TapCount_var : integer := 0; variable IsTapDelay_var : boolean := true; variable idelaytypefixed_var : boolean := false; variable idelaytypedefault_var : boolean := false; begin -------- SIGNAL_PATTERN check if((SIGNAL_PATTERN /= "CLOCK") and (SIGNAL_PATTERN /= "DATA"))then assert false report "Attribute Syntax Error: Legal values for SIGNAL_PATTERN are DATA or CLOCK" severity Failure; end if; -------- HIGH_PERFORMANCE_MODE check case HIGH_PERFORMANCE_MODE is when true | false => null; when others => assert false report "Attribute Syntax Error: The attribute HIGH_PERFORMANCE_MODE on IODELAY must be set to either true or false." severity Failure; end case; -------- IDELAY_TYPE check if(IDELAY_TYPE = "FIXED") then idelaytypefixed_var := true; elsif(IDELAY_TYPE = "VARIABLE") then idelaytypefixed_var := false; elsif(IDELAY_TYPE = "DEFAULT") then idelaytypedefault_var := true; idelaytypefixed_var := false; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " IDELAY_TYPE ", EntityName => "/IODELAY", GenericValue => IDELAY_TYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " DEFAULT, FIXED or VARIABLE ", TailMsg => "", MsgSeverity => failure ); end if; -------- IDELAY_VALUE check if((IDELAY_VALUE < MIN_IDELAY_COUNT) or (ODELAY_VALUE > MAX_IDELAY_COUNT)) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " IDELAY_VALUE ", EntityName => "/IODELAY", GenericValue => IDELAY_VALUE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ", TailMsg => "", MsgSeverity => failure ); end if; -------- ODELAY_VALUE check if((ODELAY_VALUE < MIN_ODELAY_COUNT) or (ODELAY_VALUE > MAX_ODELAY_COUNT)) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " ODELAY_VALUE ", EntityName => "/IODELAY", GenericValue => ODELAY_VALUE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ", TailMsg => "", MsgSeverity => failure ); end if; -------- REFCLK_FREQUENCY check if((REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCY) or (REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCY)) then assert false report "Attribute Syntax Error: Legal values for REFCLK_FREQUENCY are 175.0 to 225.0" severity Failure; end if; wait; end process prcs_init; --#################################################################### --##### CALCULATE iDelay ##### --#################################################################### prcs_calc_idelay:process(C_dly, GSR_dly, RST_dly) variable idelay_count_var : integer :=0; variable FIRST_TIME : boolean :=true; variable BaseTime_var : time := 1 ps ; variable CALC_TAPDELAY : real := 0.0; begin if(IDELAY_TYPE = "VARIABLE") then if((GSR_dly = '1') or (FIRST_TIME))then idelay_count_var := IDELAY_VALUE; CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ; iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var; FIRST_TIME := false; elsif(GSR_dly = '0') then if(rising_edge(C_dly)) then if(RST_dly = '1') then idelay_count_var := IDELAY_VALUE; elsif((RST_dly = '0') and (CE_dly = '1')) then if(INC_dly = '1') then if (idelay_count_var < MAX_IDELAY_COUNT) then idelay_count_var := idelay_count_var + 1; else idelay_count_var := MIN_IDELAY_COUNT; end if; elsif(INC_dly = '0') then if (idelay_count_var > MIN_IDELAY_COUNT) then idelay_count_var := idelay_count_var - 1; else idelay_count_var := MAX_IDELAY_COUNT; end if; end if; -- INC_dly end if; -- RST_dly iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var; end if; -- C_dly end if; -- GSR_dly end if; -- IDELAY_TYPE end process prcs_calc_idelay; --#################################################################### --##### CALCULATE oDelay ##### --#################################################################### prcs_calc_odelay:process(C_dly, GSR_dly, RST_dly) variable odelay_count_var : integer :=0; variable FIRST_TIME : boolean :=true; variable BaseTime_var : time := 1 ps ; variable CALC_TAPDELAY : real := 0.0; begin if((GSR_dly = '1') or (FIRST_TIME))then odelay_count_var := ODELAY_VALUE; CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ; oDelay <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var; FIRST_TIME := false; end if; -- elsif(GSR_dly = '0') then -- if(rising_edge(C_dly)) then -- if(RST_dly = '1') then -- odelay_count_var := ODELAY_VALUE; -- elsif((RST_dly = '0') and (CE_dly = '1')) then -- if(INC_dly = '1') then -- if (odelay_count_var < MAX_ODELAY_COUNT) then -- odelay_count_var := odelay_count_var + 1; -- else -- odelay_count_var := MIN_ODELAY_COUNT; -- end if; -- elsif(INC_dly = '0') then -- if (odelay_count_var > MIN_ODELAY_COUNT) then -- odelay_count_var := odelay_count_var - 1; -- else -- odelay_count_var := MAX_ODELAY_COUNT; -- end if; -- -- end if; -- INC_dly -- end if; -- RST_dly -- oDelay <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var; -- end if; -- C_dly -- end if; -- GSR_dly end process prcs_calc_odelay; --#################################################################### --##### SELECT IDATA_MUX ##### --#################################################################### prcs_idata_mux:process(DATAIN_dly, IDATAIN_dly, ODATAIN_dly, T_dly) begin if(DELAY_SRC = "I") then idata_mux <= IDATAIN_dly; elsif(DELAY_SRC = "O") then idata_mux <= ODATAIN_dly; elsif(DELAY_SRC = "IO") then idata_mux <= (IDATAIN_dly and T_dly) or (ODATAIN_dly and (not T_dly)); elsif(DELAY_SRC = "DATAIN") then idata_mux <= DATAIN_dly; else assert false report "Attribute Syntax Error : Legal values for DELAY_SRC on IODELAY instance are I, O, IO or DATAIN." severity Failure; end if; end process prcs_idata_mux; --#################################################################### --##### SELECT I/O ##### --#################################################################### prcs_selectio:process(IDATAOUT_Delayed, ODATAOUT_Delayed, T_dly) begin if(DELAY_SRC = "IO") then if(T_dly = '1') then DATAOUT_zd <= IDATAOUT_delayed; elsif(T_dly = '0') then DATAOUT_zd <= ODATAOUT_delayed; end if; elsif(DELAY_SRC = "O") then DATAOUT_zd <= ODATAOUT_delayed; else DATAOUT_zd <= IDATAOUT_delayed; end if; end process prcs_selectio; --#################################################################### --##### DELAY IDATA ##### --#################################################################### prcs_idata:process(idata_mux) -- variable CALC_TAPDELAY : real := ((1.0/REFCLK_FREQUENCY) * K ) + OFFSET; variable CALC_TAPDELAY : real := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ; begin if(IDELAY_TYPE = "FIXED") then IDATAOUT_delayed <= transport idata_mux after ((real(IDELAY_VALUE) * CALC_TAPDELAY) * 1.0 ps); else IDATAOUT_delayed <= transport idata_mux after iDelay; end if; end process prcs_idata; --#################################################################### --##### DELAY ODATA ##### --#################################################################### prcs_odata:process(idata_mux) begin ODATAOUT_delayed <= transport idata_mux after oDelay; end process prcs_odata; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(DATAOUT_zd) begin DATAOUT <= DATAOUT_zd ; end process prcs_output; --#################################################################### end IODELAY_V; ----- CELL ISERDES ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library unisim; use unisim.vpkg.all; use unisim.vcomponents.all; --//////////////////////////////////////////////////////////// --////////////////////////// BSCNTRL ///////////////////////// --//////////////////////////////////////////////////////////// entity bscntrl is generic( SRTYPE : string; INIT_BITSLIPCNT : bit_vector(3 downto 0) ); port( CLKDIV_INT : out std_ulogic; MUXC : out std_ulogic; BITSLIP : in std_ulogic; C23 : in std_ulogic; C45 : in std_ulogic; C67 : in std_ulogic; CLK : in std_ulogic; CLKDIV : in std_ulogic; DATA_RATE : in std_ulogic; GSR : in std_ulogic; R : in std_ulogic; SEL : in std_logic_vector (1 downto 0) ); end bscntrl; architecture bscntrl_V of bscntrl is -- constant DELAY_FFBSC : time := 300 ns; -- constant DELAY_MXBSC : time := 60 ns; constant DELAY_FFBSC : time := 300 ps; constant DELAY_MXBSC : time := 60 ps; signal AttrSRtype : integer := 0; signal q1 : std_ulogic := 'X'; signal q2 : std_ulogic := 'X'; signal q3 : std_ulogic := 'X'; signal mux : std_ulogic := 'X'; signal qhc1 : std_ulogic := 'X'; signal qhc2 : std_ulogic := 'X'; signal qlc1 : std_ulogic := 'X'; signal qlc2 : std_ulogic := 'X'; signal qr1 : std_ulogic := 'X'; signal qr2 : std_ulogic := 'X'; signal mux1 : std_ulogic := 'X'; signal clkdiv_zd : std_ulogic := 'X'; begin --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then AttrSrtype <= 0; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then AttrSrtype <= 1; end if; wait; end process prcs_init; --#################################################################### --##### Divide by 2 - 8 counter ##### --#################################################################### prcs_div_2_8_cntr:process(qr2, CLK, GSR) variable clkdiv_int_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(0)); variable q1_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(1)); variable q2_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(2)); variable q3_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(3)); begin if(GSR = '1') then clkdiv_int_var := TO_X01(INIT_BITSLIPCNT(0)); q1_var := TO_X01(INIT_BITSLIPCNT(1)); q2_var := TO_X01(INIT_BITSLIPCNT(2)); q3_var := TO_X01(INIT_BITSLIPCNT(3)); elsif(GSR = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if(qr2 = '1') then clkdiv_int_var := '0'; q1_var := '0'; q2_var := '0'; q3_var := '0'; elsif (qhc1 = '1') then clkdiv_int_var := clkdiv_int_var; q1_var := q1_var; q2_var := q2_var; q3_var := q3_var; else if(rising_edge(CLK)) then q3_var := q2_var; q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); q1_var := clkdiv_int_var; clkdiv_int_var := mux; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLK)) then if(qr2 = '1') then clkdiv_int_var := '0'; q1_var := '0'; q2_var := '0'; q3_var := '0'; elsif (qhc1 = '1') then clkdiv_int_var := clkdiv_int_var; q1_var := q1_var; q2_var := q2_var; q3_var := q3_var; else q3_var := q2_var; q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); q1_var := clkdiv_int_var; clkdiv_int_var := mux; end if; end if; when others => null; end case; end if; q1 <= q1_var after DELAY_FFBSC; q2 <= q2_var after DELAY_FFBSC; q3 <= q3_var after DELAY_FFBSC; clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC; end process prcs_div_2_8_cntr; --#################################################################### --##### Divider selections and 4:1 selector mux ##### --#################################################################### prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3) begin case sel is when "00" => mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; when "01" => mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC; when "10" => mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC; when "11" => mux <= NOT (q3) after DELAY_MXBSC; when others => mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; end case; end process prcs_mux_sel; --#################################################################### --##### Bitslip control logic ##### --#################################################################### prcs_logictrl:process(qr1, clkdiv) begin case AttrSRtype is when 0 => --------------- // async SET/RESET if(qr1 = '1') then qlc1 <= '0' after DELAY_FFBSC; qlc2 <= '0' after DELAY_FFBSC; elsif(bitslip = '0') then qlc1 <= qlc1 after DELAY_FFBSC; qlc2 <= '0' after DELAY_FFBSC; else if(rising_edge(clkdiv)) then qlc1 <= NOT qlc1 after DELAY_FFBSC; qlc2 <= (bitslip and mux1) after DELAY_FFBSC; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(clkdiv)) then if(qr1 = '1') then qlc1 <= '0' after DELAY_FFBSC; qlc2 <= '0' after DELAY_FFBSC; elsif(bitslip = '0') then qlc1 <= qlc1 after DELAY_FFBSC; qlc2 <= '0' after DELAY_FFBSC; else qlc1 <= NOT qlc1 after DELAY_FFBSC; qlc2 <= (bitslip and mux1) after DELAY_FFBSC; end if; end if; when others => null; end case; end process prcs_logictrl; --#################################################################### --##### Mux to select between sdr "0" and ddr "1" ##### --#################################################################### prcs_sdr_ddr_mux:process(qlc1, DATA_RATE) begin case DATA_RATE is when '0' => mux1 <= qlc1 after DELAY_MXBSC; when '1' => mux1 <= '1' after DELAY_MXBSC; when others => null; end case; end process prcs_sdr_ddr_mux; --#################################################################### --##### qhc1 and qhc2 ##### --#################################################################### prcs_qhc1_qhc2:process(qr2, CLK) begin -- FP TMP -- should CLK and q2 have to be rising_edge case AttrSRtype is when 0 => --------------- // async SET/RESET if(qr2 = '1') then qhc1 <= '0' after DELAY_FFBSC; qhc2 <= '0' after DELAY_FFBSC; elsif(rising_edge(CLK)) then qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; qhc2 <= qlc2 after DELAY_FFBSC; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLK)) then if(qr2 = '1') then qhc1 <= '0' after DELAY_FFBSC; qhc2 <= '0' after DELAY_FFBSC; else qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; qhc2 <= qlc2 after DELAY_FFBSC; end if; end if; when others => null; end case; end process prcs_qhc1_qhc2; --#################################################################### --##### Mux drives ctrl lines of mux in front of 2nd rnk FFs #### --#################################################################### prcs_muxc:process(mux1, DATA_RATE) begin case DATA_RATE is when '0' => muxc <= mux1 after DELAY_MXBSC; when '1' => muxc <= '0' after DELAY_MXBSC; when others => null; end case; end process prcs_muxc; --#################################################################### --##### Asynchronous set flops ##### --#################################################################### prcs_qr1:process(R, CLKDIV) begin -- FP TMP -- should CLKDIV and R have to be rising_edge case AttrSRtype is when 0 => --------------- // async SET/RESET if(R = '1') then qr1 <= '1' after DELAY_FFBSC; elsif(rising_edge(CLKDIV)) then qr1 <= '0' after DELAY_FFBSC; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLKDIV)) then if(R = '1') then qr1 <= '1' after DELAY_FFBSC; else qr1 <= '0' after DELAY_FFBSC; end if; end if; when others => null; end case; end process prcs_qr1; ---------------------------------------------------------------------- prcs_qr2:process(R, CLK) begin -- FP TMP -- should CLK and R have to be rising_edge case AttrSRtype is when 0 => --------------- // async SET/RESET if(R = '1') then qr2 <= '1' after DELAY_FFBSC; elsif(rising_edge(CLK)) then qr2 <= qr1 after DELAY_FFBSC; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLK)) then if(R = '1') then qr2 <= '1' after DELAY_FFBSC; else qr2 <= qr1 after DELAY_FFBSC; end if; end if; when others => null; end case; end process prcs_qr2; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(clkdiv_zd) begin CLKDIV_INT <= clkdiv_zd; end process prcs_output; --#################################################################### end bscntrl_V; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library unisim; use unisim.vpkg.all; use unisim.vcomponents.all; --//////////////////////////////////////////////////////////// --//////////////////////// ICE MODULE //////////////////////// --//////////////////////////////////////////////////////////// entity ice_module is generic( SRTYPE : string; INIT_CE : bit_vector(1 downto 0) ); port( ICE : out std_ulogic; CE1 : in std_ulogic; CE2 : in std_ulogic; GSR : in std_ulogic; NUM_CE : in std_ulogic; CLKDIV : in std_ulogic; R : in std_ulogic ); end ice_module; architecture ice_V of ice_module is -- constant DELAY_FFICE : time := 300 ns; -- constant DELAY_MXICE : time := 60 ns; constant DELAY_FFICE : time := 300 ps; constant DELAY_MXICE : time := 60 ps; signal AttrSRtype : integer := 0; signal ce1r : std_ulogic := 'X'; signal ce2r : std_ulogic := 'X'; signal cesel : std_logic_vector(1 downto 0) := (others => 'X'); signal ice_zd : std_ulogic := 'X'; begin --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process begin if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then AttrSrtype <= 0; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then AttrSrtype <= 1; end if; wait; end process prcs_init; --################################################################### --##### update cesel ##### --################################################################### cesel <= NUM_CE & CLKDIV; --#################################################################### --##### registers ##### --#################################################################### prcs_reg:process(CLKDIV, GSR) variable ce1r_var : std_ulogic := TO_X01(INIT_CE(1)); variable ce2r_var : std_ulogic := TO_X01(INIT_CE(0)); begin if(GSR = '1') then ce1r_var := TO_X01(INIT_CE(1)); ce2r_var := TO_X01(INIT_CE(0)); elsif(GSR = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if(R = '1') then ce1r_var := '0'; ce2r_var := '0'; elsif(rising_edge(CLKDIV)) then ce1r_var := ce1; ce2r_var := ce2; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLKDIV)) then if(R = '1') then ce1r_var := '0'; ce2r_var := '0'; else ce1r_var := ce1; ce2r_var := ce2; end if; end if; when others => null; end case; end if; ce1r <= ce1r_var after DELAY_FFICE; ce2r <= ce2r_var after DELAY_FFICE; end process prcs_reg; --#################################################################### --##### Output mux ##### --#################################################################### prcs_mux:process(cesel, ce1, ce1r, ce2r) begin case cesel is when "00" => ice_zd <= ce1; when "01" => ice_zd <= ce1; -- 426606 when "10" => ice_zd <= ce2r; when "11" => ice_zd <= ce1r; when others => null; end case; end process prcs_mux; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(ice_zd) begin ICE <= ice_zd; end process prcs_output; end ice_V; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; library unisim; use unisim.vpkg.all; use unisim.vcomponents.all; use unisim.vcomponents.all; ----- CELL ISERDES ----- --//////////////////////////////////////////////////////////// --////////////////////////// ISERDES ///////////////////////// --//////////////////////////////////////////////////////////// entity ISERDES is generic( DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED"; INIT_BITSLIPCNT : bit_vector(3 downto 0) := "0000"; INIT_CE : bit_vector(1 downto 0) := "00"; INIT_RANK1_PARTIAL: bit_vector(4 downto 0) := "00000"; INIT_RANK2 : bit_vector(5 downto 0) := "000000"; INIT_RANK3 : bit_vector(5 downto 0) := "000000"; SERDES : boolean := TRUE; SRTYPE : string := "ASYNC"; BITSLIP_ENABLE : boolean := false; DATA_RATE : string := "DDR"; DATA_WIDTH : integer := 4; INIT_Q1 : bit := '0'; INIT_Q2 : bit := '0'; INIT_Q3 : bit := '0'; INIT_Q4 : bit := '0'; INTERFACE_TYPE : string := "MEMORY"; IOBDELAY : string := "NONE"; IOBDELAY_TYPE : string := "DEFAULT"; IOBDELAY_VALUE : integer := 0; NUM_CE : integer := 2; SERDES_MODE : string := "MASTER"; SRVAL_Q1 : bit := '0'; SRVAL_Q2 : bit := '0'; SRVAL_Q3 : bit := '0'; SRVAL_Q4 : bit := '0' ); port( O : out std_ulogic; Q1 : out std_ulogic; Q2 : out std_ulogic; Q3 : out std_ulogic; Q4 : out std_ulogic; Q5 : out std_ulogic; Q6 : out std_ulogic; SHIFTOUT1 : out std_ulogic; SHIFTOUT2 : out std_ulogic; BITSLIP : in std_ulogic; CE1 : in std_ulogic; CE2 : in std_ulogic; CLK : in std_ulogic; CLKDIV : in std_ulogic; D : in std_ulogic; DLYCE : in std_ulogic; DLYINC : in std_ulogic; DLYRST : in std_ulogic; OCLK : in std_ulogic; REV : in std_ulogic; SHIFTIN1 : in std_ulogic; SHIFTIN2 : in std_ulogic; SR : in std_ulogic ); end ISERDES; architecture ISERDES_V OF ISERDES is component bscntrl generic ( SRTYPE : string; INIT_BITSLIPCNT : bit_vector(3 downto 0) ); port( CLKDIV_INT : out std_ulogic; MUXC : out std_ulogic; BITSLIP : in std_ulogic; C23 : in std_ulogic; C45 : in std_ulogic; C67 : in std_ulogic; CLK : in std_ulogic; CLKDIV : in std_ulogic; DATA_RATE : in std_ulogic; GSR : in std_ulogic; R : in std_ulogic; SEL : in std_logic_vector (1 downto 0) ); end component; component ice_module generic( SRTYPE : string; INIT_CE : bit_vector(1 downto 0) ); port( ICE : out std_ulogic; CE1 : in std_ulogic; CE2 : in std_ulogic; GSR : in std_ulogic; NUM_CE : in std_ulogic; CLKDIV : in std_ulogic; R : in std_ulogic ); end component; component IDELAY generic( IOBDELAY_VALUE : integer := 0; IOBDELAY_TYPE : string := "DEFAULT" ); port( O : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; I : in std_ulogic; INC : in std_ulogic; RST : in std_ulogic ); end component; -- constant DELAY_FFINP : time := 300 ns; -- constant DELAY_MXINP1 : time := 60 ns; -- constant DELAY_MXINP2 : time := 120 ns; -- constant DELAY_OCLKDLY : time := 750 ns; constant SYNC_PATH_DELAY : time := 100 ps; constant DELAY_FFINP : time := 300 ps; constant DELAY_MXINP1 : time := 60 ps; constant DELAY_MXINP2 : time := 120 ps; constant DELAY_OCLKDLY : time := 750 ps; constant MAX_DATAWIDTH : integer := 4; signal BITSLIP_ipd : std_ulogic := 'X'; signal CE1_ipd : std_ulogic := 'X'; signal CE2_ipd : std_ulogic := 'X'; signal CLK_ipd : std_ulogic := 'X'; signal CLKDIV_ipd : std_ulogic := 'X'; signal D_ipd : std_ulogic := 'X'; signal DLYCE_ipd : std_ulogic := 'X'; signal DLYINC_ipd : std_ulogic := 'X'; signal DLYRST_ipd : std_ulogic := 'X'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := 'X'; signal OCLK_ipd : std_ulogic := 'X'; signal REV_ipd : std_ulogic := 'X'; signal SR_ipd : std_ulogic := 'X'; signal SHIFTIN1_ipd : std_ulogic := 'X'; signal SHIFTIN2_ipd : std_ulogic := 'X'; signal BITSLIP_dly : std_ulogic := 'X'; signal CE1_dly : std_ulogic := 'X'; signal CE2_dly : std_ulogic := 'X'; signal CLK_dly : std_ulogic := 'X'; signal CLKDIV_dly : std_ulogic := 'X'; signal D_dly : std_ulogic := 'X'; signal DLYCE_dly : std_ulogic := 'X'; signal DLYINC_dly : std_ulogic := 'X'; signal DLYRST_dly : std_ulogic := 'X'; signal GSR_dly : std_ulogic := 'X'; signal OCLK_dly : std_ulogic := 'X'; signal REV_dly : std_ulogic := 'X'; signal SR_dly : std_ulogic := 'X'; signal SHIFTIN1_dly : std_ulogic := 'X'; signal SHIFTIN2_dly : std_ulogic := 'X'; signal O_zd : std_ulogic := 'X'; signal Q1_zd : std_ulogic := 'X'; signal Q2_zd : std_ulogic := 'X'; signal Q3_zd : std_ulogic := 'X'; signal Q4_zd : std_ulogic := 'X'; signal Q5_zd : std_ulogic := 'X'; signal Q6_zd : std_ulogic := 'X'; signal SHIFTOUT1_zd : std_ulogic := 'X'; signal SHIFTOUT2_zd : std_ulogic := 'X'; signal O_viol : std_ulogic := 'X'; signal Q1_viol : std_ulogic := 'X'; signal Q2_viol : std_ulogic := 'X'; signal Q3_viol : std_ulogic := 'X'; signal Q4_viol : std_ulogic := 'X'; signal Q5_viol : std_ulogic := 'X'; signal Q6_viol : std_ulogic := 'X'; signal SHIFTOUT1_viol : std_ulogic := 'X'; signal SHIFTOUT2_viol : std_ulogic := 'X'; signal AttrSerdes : std_ulogic := 'X'; signal AttrMode : std_ulogic := 'X'; signal AttrDataRate : std_ulogic := 'X'; signal AttrDataWidth : std_logic_vector(3 downto 0) := (others => 'X'); signal AttrInterfaceType : std_ulogic := 'X'; signal AttrBitslipEnable : std_ulogic := 'X'; signal AttrNumCe : std_ulogic := 'X'; signal AttrDdrClkEdge : std_logic_vector(1 downto 0) := (others => 'X'); signal AttrSRtype : integer := 0; signal AttrIobDelay : integer := 0; signal sel1 : std_logic_vector(1 downto 0) := (others => 'X'); signal selrnk3 : std_logic_vector(3 downto 0) := (others => 'X'); signal bsmux : std_logic_vector(2 downto 0) := (others => 'X'); signal cntr : std_logic_vector(4 downto 0) := (others => 'X'); signal q1rnk1 : std_ulogic := 'X'; signal q2nrnk1 : std_ulogic := 'X'; signal q5rnk1 : std_ulogic := 'X'; signal q6rnk1 : std_ulogic := 'X'; signal q6prnk1 : std_ulogic := 'X'; signal q1prnk1 : std_ulogic := 'X'; signal q2prnk1 : std_ulogic := 'X'; signal q3rnk1 : std_ulogic := 'X'; signal q4rnk1 : std_ulogic := 'X'; signal dataq5rnk1 : std_ulogic := 'X'; signal dataq6rnk1 : std_ulogic := 'X'; signal dataq3rnk1 : std_ulogic := 'X'; signal dataq4rnk1 : std_ulogic := 'X'; signal oclkmux : std_ulogic := '0'; signal memmux : std_ulogic := '0'; signal q2pmux : std_ulogic := '0'; signal clkdiv_int : std_ulogic := '0'; signal clkdivmux : std_ulogic := '0'; signal q1rnk2 : std_ulogic := 'X'; signal q2rnk2 : std_ulogic := 'X'; signal q3rnk2 : std_ulogic := 'X'; signal q4rnk2 : std_ulogic := 'X'; signal q5rnk2 : std_ulogic := 'X'; signal q6rnk2 : std_ulogic := 'X'; signal dataq1rnk2 : std_ulogic := 'X'; signal dataq2rnk2 : std_ulogic := 'X'; signal dataq3rnk2 : std_ulogic := 'X'; signal dataq4rnk2 : std_ulogic := 'X'; signal dataq5rnk2 : std_ulogic := 'X'; signal dataq6rnk2 : std_ulogic := 'X'; signal muxc : std_ulogic := 'X'; signal q1rnk3 : std_ulogic := 'X'; signal q2rnk3 : std_ulogic := 'X'; signal q3rnk3 : std_ulogic := 'X'; signal q4rnk3 : std_ulogic := 'X'; signal q5rnk3 : std_ulogic := 'X'; signal q6rnk3 : std_ulogic := 'X'; signal c23 : std_ulogic := 'X'; signal c45 : std_ulogic := 'X'; signal c67 : std_ulogic := 'X'; signal sel : std_logic_vector(1 downto 0) := (others => 'X'); signal ice : std_ulogic := 'X'; signal datain : std_ulogic := 'X'; signal idelay_out : std_ulogic := 'X'; signal CLKN_dly : std_ulogic := '0'; begin --------------------- -- INPUT PATH DELAYs -------------------- BITSLIP_dly <= BITSLIP after 0 ps; CE1_dly <= CE1 after 0 ps; CE2_dly <= CE2 after 0 ps; CLK_dly <= CLK after 0 ps; CLKDIV_dly <= CLKDIV after 0 ps; D_dly <= D after 0 ps; DLYCE_dly <= DLYCE after 0 ps; DLYINC_dly <= DLYINC after 0 ps; DLYRST_dly <= DLYRST after 0 ps; GSR_dly <= GSR after 0 ps; OCLK_dly <= OCLK after 0 ps; REV_dly <= REV after 0 ps; SHIFTIN1_dly <= SHIFTIN1 after 0 ps; SHIFTIN2_dly <= SHIFTIN2 after 0 ps; SR_dly <= SR after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialize ##### --#################################################################### prcs_init:process variable AttrSerdes_var : std_ulogic := 'X'; variable AttrMode_var : std_ulogic := 'X'; variable AttrDataRate_var : std_ulogic := 'X'; variable AttrDataWidth_var : std_logic_vector(3 downto 0) := (others => 'X'); variable AttrInterfaceType_var : std_ulogic := 'X'; variable AttrBitslipEnable_var : std_ulogic := 'X'; variable AttrDdrClkEdge_var : std_logic_vector(1 downto 0) := (others => 'X'); variable AttrIobDelay_var : integer := 0; begin -------------------- SERDES validity check -------------------- if(SERDES = true) then AttrSerdes_var := '1'; else AttrSerdes_var := '0'; end if; ------------- SERDES_MODE validity check -------------------- if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then AttrMode_var := '0'; elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then AttrMode_var := '1'; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => "SERDES_MODE ", EntityName => "/ISERDES", GenericValue => SERDES_MODE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " MASTER or SLAVE.", TailMsg => "", MsgSeverity => FAILURE ); end if; ------------------ DATA_RATE validity check ------------------ if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then AttrDataRate_var := '0'; elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then AttrDataRate_var := '1'; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DATA_RATE ", EntityName => "/ISERDES", GenericValue => DATA_RATE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " DDR or SDR. ", TailMsg => "", MsgSeverity => Failure ); end if; ------------------ DATA_WIDTH validity check ------------------ if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or (DATA_WIDTH = 4) or (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or (DATA_WIDTH = 7) or (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DATA_WIDTH ", EntityName => "/ISERDES", GenericValue => DATA_WIDTH, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ", TailMsg => "", MsgSeverity => Failure ); end if; ------------ DATA_WIDTH /DATA_RATE combination check ------------ if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then case (DATA_WIDTH) is when 4|6|8|10 => null; when others => GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DATA_WIDTH ", EntityName => "/ISERDES", GenericValue => DATA_WIDTH, Unit => "", ExpectedValueMsg => " The Legal values for DDR mode are ", ExpectedGenericValue => " 4, 6, 8, or 10 ", TailMsg => "", MsgSeverity => Failure ); end case; end if; if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then case (DATA_WIDTH) is when 2|3|4|5|6|7|8 => null; when others => GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DATA_WIDTH ", EntityName => "/ISERDES", GenericValue => DATA_WIDTH, Unit => "", ExpectedValueMsg => " The Legal values for SDR mode are ", ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8", TailMsg => "", MsgSeverity => Failure ); end case; end if; ---------------- INTERFACE_TYPE validity check --------------- if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "MEMORY")) then AttrInterfaceType_var := '0'; elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then AttrInterfaceType_var := '1'; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => "INTERFACE_TYPE ", EntityName => "/ISERDES", GenericValue => INTERFACE_TYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " MEMORY or NETWORKING.", TailMsg => "", MsgSeverity => FAILURE ); end if; ---------------- BITSLIP_ENABLE validity check ------------------- if(BITSLIP_ENABLE = false) then AttrBitslipEnable_var := '0'; elsif(BITSLIP_ENABLE = true) then AttrBitslipEnable_var := '1'; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " BITSLIP_ENABLE ", EntityName => "/ISERDES", GenericValue => BITSLIP_ENABLE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " TRUE or FALSE ", TailMsg => "", MsgSeverity => Failure ); end if; ---------------- NUM_CE validity check ------------------- case NUM_CE is when 1 => AttrNumCe <= '0'; when 2 => AttrNumCe <= '1'; when others => GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " NUM_CE ", EntityName => "/ISERDES", GenericValue => NUM_CE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 1 or 2 ", TailMsg => "", MsgSeverity => Failure ); end case; ---------------- IOBDELAY validity check ------------------- if((IOBDELAY = "NONE") or (IOBDELAY = "none")) then AttrIobDelay_var := 0; elsif((IOBDELAY = "IBUF") or (IOBDELAY = "ibuf")) then AttrIobDelay_var := 1; elsif((IOBDELAY = "IFD") or (IOBDELAY = "ifd")) then AttrIobDelay_var := 2; elsif((IOBDELAY = "BOTH") or (IOBDELAY = "both")) then AttrIobDelay_var := 3; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " IOBDELAY ", EntityName => "/ISERDES", GenericValue => IOBDELAY, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " NONE or IBUF or IFD or BOTH ", TailMsg => "", MsgSeverity => Failure ); end if; ------------ IOBDELAY_VALUE validity check ----------------- ------------ IOBDELAY_TYPE validity check ----------------- -- -- -- ------------------ DDR_CLK_EDGE validity check ------------------ if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then AttrDdrClkEdge_var := "00"; elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then AttrDdrClkEdge_var := "01"; elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then AttrDdrClkEdge_var := "10"; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " DDR_CLK_EDGE ", EntityName => "/ISERDES", GenericValue => DDR_CLK_EDGE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ", TailMsg => "", MsgSeverity => Failure ); end if; ------------------ DATA_RATE validity check ------------------ if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then AttrSrtype <= 0; elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then AttrSrtype <= 1; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Warning ", GenericName => " SRTYPE ", EntityName => "/ISERDES", GenericValue => SRTYPE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " ASYNC or SYNC. ", TailMsg => "", MsgSeverity => ERROR ); end if; --------------------------------------------------------------------- AttrSerdes <= AttrSerdes_var; AttrMode <= AttrMode_var; AttrDataRate <= AttrDataRate_var; AttrDataWidth <= AttrDataWidth_var; AttrInterfaceType <= AttrInterfaceType_var; AttrBitslipEnable <= AttrBitslipEnable_var; AttrDdrClkEdge <= AttrDdrClkEdge_var; AttrIobDelay <= AttrIobDelay_var; sel1 <= AttrMode_var & AttrDataRate_var; selrnk3 <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var; cntr <= AttrDataRate_var & AttrDataWidth_var; wait; end process prcs_init; --################################################################### --##### SHIFTOUT1 and SHIFTOUT2 ##### --################################################################### SHIFTOUT2_zd <= q5rnk1; SHIFTOUT1_zd <= q6rnk1; --################################################################### --##### q1rnk1 reg ##### --################################################################### prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly) variable q1rnk1_var : std_ulogic := TO_X01(INIT_Q1); begin if(GSR_dly = '1') then q1rnk1_var := TO_X01(INIT_Q1); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then q1rnk1_var := TO_X01(SRVAL_Q1); elsif(REV_dly = '1') then q1rnk1_var := not TO_X01(SRVAL_Q1); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then if(rising_edge(CLK_dly)) then q1rnk1_var := datain; end if; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLK_dly)) then if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then q1rnk1_var := TO_X01(SRVAL_Q1); Elsif(REV_dly = '1') then q1rnk1_var := not TO_X01(SRVAL_Q1); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then q1rnk1_var := datain; end if; end if; end if; when others => null; end case; end if; q1rnk1 <= q1rnk1_var after DELAY_FFINP; end process prcs_Q1_rnk1; --################################################################### --##### q5rnk1, q6rnk1 and q6prnk1 reg ##### --################################################################### prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly) variable q5rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2)); variable q6rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1)); variable q6prnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0)); begin if(GSR_dly = '1') then q5rnk1_var := TO_X01(INIT_RANK1_PARTIAL(2)); q6rnk1_var := TO_X01(INIT_RANK1_PARTIAL(1)); q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0)); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------- // async SET/RESET -- Not full featured FFs if(SR_dly = '1') then q5rnk1_var := '0'; q6rnk1_var := '0'; q6prnk1_var := '0'; elsif(SR_dly = '0') then if(rising_edge(CLK_dly)) then q5rnk1_var := dataq5rnk1; q6rnk1_var := dataq6rnk1; q6prnk1_var := q6rnk1; end if; end if; when 1 => --------- // sync SET/RESET -- Not full featured FFs if(rising_edge(CLK_dly)) then if(SR_dly = '1') then q5rnk1_var := '0'; q6rnk1_var := '0'; q6prnk1_var := '0'; elsif(SR_dly = '0') then q5rnk1_var := dataq5rnk1; q6rnk1_var := dataq6rnk1; q6prnk1_var := q6rnk1; end if; end if; when others => null; end case; end if; q5rnk1 <= q5rnk1_var after DELAY_FFINP; q6rnk1 <= q6rnk1_var after DELAY_FFINP; q6prnk1 <= q6prnk1_var after DELAY_FFINP; end process prcs_Q5Q6Q6p_rnk1; --################################################################### --##### q2nrnk1 reg ##### --################################################################### prcs_Q2_rnk1:process(CLK_dly, GSR_dly, SR_dly, REV_dly) variable q2nrnk1_var : std_ulogic := TO_X01(INIT_Q2); begin if(GSR_dly = '1') then q2nrnk1_var := TO_X01(INIT_Q2); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then q2nrnk1_var := TO_X01(SRVAL_Q2); elsif(REV_dly = '1') then q2nrnk1_var := not TO_X01(SRVAL_Q2); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then if(falling_edge(CLK_dly)) then q2nrnk1_var := datain; end if; end if; end if; when 1 => --------------- // sync SET/RESET if(falling_edge(CLK_dly)) then if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then q2nrnk1_var := TO_X01(SRVAL_Q2); elsif(REV_dly = '1') then q2nrnk1_var := not TO_X01(SRVAL_Q2); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then q2nrnk1_var := datain; end if; end if; end if; when others => null; end case; end if; q2nrnk1 <= q2nrnk1_var after DELAY_FFINP; end process prcs_Q2_rnk1; --################################################################### --##### q2prnk1 reg ##### --################################################################### prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly) variable q2prnk1_var : std_ulogic := TO_X01(INIT_Q4); begin if(GSR_dly = '1') then q2prnk1_var := TO_X01(INIT_Q4); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then q2prnk1_var := TO_X01(SRVAL_Q4); elsif(REV_dly = '1') then q2prnk1_var := not TO_X01(SRVAL_Q4); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then if(rising_edge(q2pmux)) then q2prnk1_var := q2nrnk1; end if; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(q2pmux)) then if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then q2prnk1_var := TO_X01(SRVAL_Q4); elsif(REV_dly = '1') then q2prnk1_var := not TO_X01(SRVAL_Q4); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then q2prnk1_var := q2nrnk1; end if; end if; end if; when others => null; end case; end if; q2prnk1 <= q2prnk1_var after DELAY_FFINP; end process prcs_Q2p_rnk1; --################################################################### --##### q1prnk1 reg ##### --################################################################### prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly) variable q1prnk1_var : std_ulogic := TO_X01(INIT_Q3); begin if(GSR_dly = '1') then q1prnk1_var := TO_X01(INIT_Q3); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then q1prnk1_var := TO_X01(SRVAL_Q3); elsif(REV_dly = '1') then q1prnk1_var := not TO_X01(SRVAL_Q3); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then if(rising_edge(memmux)) then q1prnk1_var := q1rnk1; end if; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(memmux)) then if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then q1prnk1_var := TO_X01(SRVAL_Q3); elsif(REV_dly = '1') then q1prnk1_var := not TO_X01(SRVAL_Q3); elsif((SR_dly = '0') and (REV_dly = '0')) then if(ice = '1') then q1prnk1_var := q1rnk1; end if; end if; end if; when others => null; end case; end if; q1prnk1 <= q1prnk1_var after DELAY_FFINP; end process prcs_Q1p_rnk1; --################################################################### --##### q3rnk1 and q4rnk1 reg ##### --################################################################### prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly) variable q3rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4)); variable q4rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3)); begin if(GSR_dly = '1') then q3rnk1_var := TO_X01(INIT_RANK1_PARTIAL(4)); q4rnk1_var := TO_X01(INIT_RANK1_PARTIAL(3)); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => -------- // async SET/RESET -- not fully featured FFs if(SR_dly = '1') then q3rnk1_var := '0'; q4rnk1_var := '0'; elsif(SR_dly = '0') then if(rising_edge(memmux)) then q3rnk1_var := dataq3rnk1; q4rnk1_var := dataq4rnk1; end if; end if; when 1 => -------- // sync SET/RESET -- not fully featured FFs if(rising_edge(memmux)) then if(SR_dly = '1') then q3rnk1_var := '0'; q4rnk1_var := '0'; elsif(SR_dly = '0') then q3rnk1_var := dataq3rnk1; q4rnk1_var := dataq4rnk1; end if; end if; when others => null; end case; end if; q3rnk1 <= q3rnk1_var after DELAY_FFINP; q4rnk1 <= q4rnk1_var after DELAY_FFINP; end process prcs_Q3Q4_rnk1; --################################################################### --##### clock mux -- oclkmux with delay element ##### --################################################################### -- prcs_oclkmux:process(OCLK_dly) -- begin -- case AttrOclkDelay is -- when '0' => -- oclkmux <= OCLK_dly after DELAY_MXINP1; -- when '1' => -- oclkmux <= OCLK_dly after DELAY_OCLKDLY; -- when others => -- oclkmux <= OCLK_dly after DELAY_MXINP1; -- end case; -- end process prcs_oclkmux; -- -- -- --/////////////////////////////////////////////////////////////////// --// Mux elements for the 1st Rank --/////////////////////////////////////////////////////////////////// --################################################################### --##### memmux -- 4 clock muxes in first rank ##### --################################################################### prcs_memmux:process(CLK_dly, OCLK_dly) begin case AttrInterfaceType is when '0' => memmux <= OCLK_dly after DELAY_MXINP1; when '1' => memmux <= CLK_dly after DELAY_MXINP1; when others => memmux <= OCLK_dly after DELAY_MXINP1; end case; end process prcs_memmux; --################################################################### --##### q2pmux -- Optional inverter for q2p (4th flop in rank1) --################################################################### prcs_q2pmux:process(memmux) begin case AttrInterfaceType is when '0' => q2pmux <= not memmux after DELAY_MXINP1; when '1' => q2pmux <= memmux after DELAY_MXINP1; when others => q2pmux <= memmux after DELAY_MXINP1; end case; end process prcs_q2pmux; --################################################################### --##### data input muxes for q3q4 and q5q6 ##### --################################################################### prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly) begin case sel1 is when "00" => dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; when "01" => dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; when "10" => dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1; dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; when "11" => dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; when others => dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; end case; end process prcs_Q3Q4_mux; ---------------------------------------------------------------------- prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1) begin case AttrDataRate is when '0' => dataq5rnk1 <= q3rnk1 after DELAY_MXINP1; dataq6rnk1 <= q4rnk1 after DELAY_MXINP1; when '1' => dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; when others => dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; end case; end process prcs_Q5Q6_mux; ---//////////////////////////////////////////////////////////////////// --- 2nd rank of registors ---//////////////////////////////////////////////////////////////////// --################################################################### --##### clkdivmux to choose between clkdiv_int or CLKDIV ##### --################################################################### prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly) begin case AttrBitslipEnable is when '0' => clkdivmux <= CLKDIV_dly after DELAY_MXINP1; when '1' => clkdivmux <= clkdiv_int after DELAY_MXINP1; when others => clkdivmux <= CLKDIV_dly after DELAY_MXINP1; end case; end process prcs_clkdivmux; --################################################################### --##### q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg ##### --################################################################### prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly) variable q1rnk2_var : std_ulogic := TO_X01(INIT_RANK2(0)); variable q2rnk2_var : std_ulogic := TO_X01(INIT_RANK2(1)); variable q3rnk2_var : std_ulogic := TO_X01(INIT_RANK2(2)); variable q4rnk2_var : std_ulogic := TO_X01(INIT_RANK2(3)); variable q5rnk2_var : std_ulogic := TO_X01(INIT_RANK2(4)); variable q6rnk2_var : std_ulogic := TO_X01(INIT_RANK2(5)); begin if(GSR_dly = '1') then q1rnk2_var := TO_X01(INIT_RANK2(0)); q2rnk2_var := TO_X01(INIT_RANK2(1)); q3rnk2_var := TO_X01(INIT_RANK2(2)); q4rnk2_var := TO_X01(INIT_RANK2(3)); q5rnk2_var := TO_X01(INIT_RANK2(4)); q6rnk2_var := TO_X01(INIT_RANK2(5)); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if(SR_dly = '1') then q1rnk2_var := '0'; q2rnk2_var := '0'; q3rnk2_var := '0'; q4rnk2_var := '0'; q5rnk2_var := '0'; q6rnk2_var := '0'; elsif(SR_dly = '0') then if(rising_edge(clkdivmux)) then q1rnk2_var := dataq1rnk2; q2rnk2_var := dataq2rnk2; q3rnk2_var := dataq3rnk2; q4rnk2_var := dataq4rnk2; q5rnk2_var := dataq5rnk2; q6rnk2_var := dataq6rnk2; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(clkdivmux)) then if(SR_dly = '1') then q1rnk2_var := '0'; q2rnk2_var := '0'; q3rnk2_var := '0'; q4rnk2_var := '0'; q5rnk2_var := '0'; q6rnk2_var := '0'; elsif(SR_dly = '0') then q1rnk2_var := dataq1rnk2; q2rnk2_var := dataq2rnk2; q3rnk2_var := dataq3rnk2; q4rnk2_var := dataq4rnk2; q5rnk2_var := dataq5rnk2; q6rnk2_var := dataq6rnk2; end if; end if; when others => null; end case; end if; q1rnk2 <= q1rnk2_var after DELAY_FFINP; q2rnk2 <= q2rnk2_var after DELAY_FFINP; q3rnk2 <= q3rnk2_var after DELAY_FFINP; q4rnk2 <= q4rnk2_var after DELAY_FFINP; q5rnk2 <= q5rnk2_var after DELAY_FFINP; q6rnk2 <= q6rnk2_var after DELAY_FFINP; end process prcs_Q1Q2Q3Q4Q5Q6_rnk2; --################################################################### --##### update bitslip mux ##### --################################################################### bsmux <= AttrBitslipEnable & AttrDataRate & muxc; --################################################################### --##### Data mux for 2nd rank of registers ###### --################################################################### prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1, q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1) begin case bsmux is when "000" | "001" => dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; when "100" => dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; when "101" => dataq1rnk2 <= q1prnk1 after DELAY_MXINP2; dataq2rnk2 <= q4rnk1 after DELAY_MXINP2; dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; dataq4rnk2 <= q6rnk1 after DELAY_MXINP2; dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; dataq6rnk2 <= q6prnk1 after DELAY_MXINP2; when "010" | "011" | "110" | "111" => dataq1rnk2 <= q1rnk1 after DELAY_MXINP2; dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; dataq4rnk2 <= q4rnk1 after DELAY_MXINP2; dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; dataq6rnk2 <= q6rnk1 after DELAY_MXINP2; when others => dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; end case; end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux; ---//////////////////////////////////////////////////////////////////// --- 3rd rank of registors ---//////////////////////////////////////////////////////////////////// --################################################################### --##### q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg ##### --################################################################### prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly) variable q1rnk3_var : std_ulogic := TO_X01(INIT_RANK3(0)); variable q2rnk3_var : std_ulogic := TO_X01(INIT_RANK3(1)); variable q3rnk3_var : std_ulogic := TO_X01(INIT_RANK3(2)); variable q4rnk3_var : std_ulogic := TO_X01(INIT_RANK3(3)); variable q5rnk3_var : std_ulogic := TO_X01(INIT_RANK3(4)); variable q6rnk3_var : std_ulogic := TO_X01(INIT_RANK3(5)); begin if(GSR_dly = '1') then q1rnk3_var := TO_X01(INIT_RANK3(0)); q2rnk3_var := TO_X01(INIT_RANK3(1)); q3rnk3_var := TO_X01(INIT_RANK3(2)); q4rnk3_var := TO_X01(INIT_RANK3(3)); q5rnk3_var := TO_X01(INIT_RANK3(4)); q6rnk3_var := TO_X01(INIT_RANK3(5)); elsif(GSR_dly = '0') then case AttrSRtype is when 0 => --------------- // async SET/RESET if(SR_dly = '1') then q1rnk3_var := '0'; q2rnk3_var := '0'; q3rnk3_var := '0'; q4rnk3_var := '0'; q5rnk3_var := '0'; q6rnk3_var := '0'; elsif(SR_dly = '0') then if(rising_edge(CLKDIV_dly)) then q1rnk3_var := q1rnk2; q2rnk3_var := q2rnk2; q3rnk3_var := q3rnk2; q4rnk3_var := q4rnk2; q5rnk3_var := q5rnk2; q6rnk3_var := q6rnk2; end if; end if; when 1 => --------------- // sync SET/RESET if(rising_edge(CLKDIV_dly)) then if(SR_dly = '1') then q1rnk3_var := '0'; q2rnk3_var := '0'; q3rnk3_var := '0'; q4rnk3_var := '0'; q5rnk3_var := '0'; q6rnk3_var := '0'; elsif(SR_dly = '0') then q1rnk3_var := q1rnk2; q2rnk3_var := q2rnk2; q3rnk3_var := q3rnk2; q4rnk3_var := q4rnk2; q5rnk3_var := q5rnk2; q6rnk3_var := q6rnk2; end if; end if; when others => null; end case; end if; q1rnk3 <= q1rnk3_var after DELAY_FFINP; q2rnk3 <= q2rnk3_var after DELAY_FFINP; q3rnk3 <= q3rnk3_var after DELAY_FFINP; q4rnk3 <= q4rnk3_var after DELAY_FFINP; q5rnk3 <= q5rnk3_var after DELAY_FFINP; q6rnk3 <= q6rnk3_var after DELAY_FFINP; end process prcs_Q1Q2Q3Q4Q5Q6_rnk3; ---//////////////////////////////////////////////////////////////////// --- Outputs ---//////////////////////////////////////////////////////////////////// prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3, q2nrnk1, q2prnk1, q2rnk2, q2rnk3) begin case selrnk3 is when "0000" | "0100" | "0X00" => Q1_zd <= q1prnk1 after DELAY_MXINP1; Q2_zd <= q2prnk1 after DELAY_MXINP1; when "0001" | "0101" | "0X01" => Q1_zd <= q1rnk1 after DELAY_MXINP1; Q2_zd <= q2prnk1 after DELAY_MXINP1; when "0010" | "0110" | "0X10" => Q1_zd <= q1rnk1 after DELAY_MXINP1; Q2_zd <= q2nrnk1 after DELAY_MXINP1; when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" | "100X" | "101X" | "10XX" => Q1_zd <= q1rnk2 after DELAY_MXINP1; Q2_zd <= q2rnk2 after DELAY_MXINP1; when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" | "110X" | "111X" | "11XX" => Q1_zd <= q1rnk3 after DELAY_MXINP1; Q2_zd <= q2rnk3 after DELAY_MXINP1; when others => Q1_zd <= q1rnk2 after DELAY_MXINP1; Q2_zd <= q2rnk2 after DELAY_MXINP1; end case; end process prcs_Q1Q2_rnk3_mux; -------------------------------------------------------------------- prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3, q5rnk2, q5rnk3, q6rnk2, q6rnk3) begin case AttrBitslipEnable is when '0' => Q3_zd <= q3rnk2 after DELAY_MXINP1; Q4_zd <= q4rnk2 after DELAY_MXINP1; Q5_zd <= q5rnk2 after DELAY_MXINP1; Q6_zd <= q6rnk2 after DELAY_MXINP1; when '1' => Q3_zd <= q3rnk3 after DELAY_MXINP1; Q4_zd <= q4rnk3 after DELAY_MXINP1; Q5_zd <= q5rnk3 after DELAY_MXINP1; Q6_zd <= q6rnk3 after DELAY_MXINP1; when others => Q3_zd <= q3rnk2 after DELAY_MXINP1; Q4_zd <= q4rnk2 after DELAY_MXINP1; Q5_zd <= q5rnk2 after DELAY_MXINP1; Q6_zd <= q6rnk2 after DELAY_MXINP1; end case; end process prcs_Q3Q4Q5Q6_rnk3_mux; ---------------------------------------------------------------------- ----------- Inverted CLK ----------------------------------------- ---------------------------------------------------------------------- CLKN_dly <= not CLK_dly; ---------------------------------------------------------------------- ----------- Instant BSCNTRL -------------------------------------- ---------------------------------------------------------------------- INST_BSCNTRL : BSCNTRL generic map ( SRTYPE => SRTYPE, INIT_BITSLIPCNT => INIT_BITSLIPCNT ) port map ( CLKDIV_INT => clkdiv_int, MUXC => muxc, BITSLIP => BITSLIP_dly, C23 => c23, C45 => c45, C67 => c67, CLK => CLKN_dly, CLKDIV => CLKDIV_dly, DATA_RATE => AttrDataRate, GSR => GSR_dly, R => SR_dly, SEL => sel ); --################################################################### --##### Set value of the counter in BSCNTRL ##### --################################################################### prcs_bscntrl_cntr:process begin wait for 10 ps; case cntr is when "00100" => c23<='0'; c45<='0'; c67<='0'; sel<="00"; when "00110" => c23<='1'; c45<='0'; c67<='0'; sel<="00"; when "01000" => c23<='0'; c45<='0'; c67<='0'; sel<="01"; when "01010" => c23<='0'; c45<='1'; c67<='0'; sel<="01"; when "10010" => c23<='0'; c45<='0'; c67<='0'; sel<="00"; when "10011" => c23<='1'; c45<='0'; c67<='0'; sel<="00"; when "10100" => c23<='0'; c45<='0'; c67<='0'; sel<="01"; when "10101" => c23<='0'; c45<='1'; c67<='0'; sel<="01"; when "10110" => c23<='0'; c45<='0'; c67<='0'; sel<="10"; when "10111" => c23<='0'; c45<='0'; c67<='1'; sel<="10"; when "11000" => c23<='0'; c45<='0'; c67<='0'; sel<="11"; when others => assert FALSE report "Error : DATA_WIDTH or DATA_RATE has illegal values." severity failure; end case; wait on cntr, c23, c45, c67, sel; end process prcs_bscntrl_cntr; ---------------------------------------------------------------------- ----------- Instant Clock Enable Circuit ------------------------- ---------------------------------------------------------------------- INST_ICE : ICE_MODULE generic map ( SRTYPE => SRTYPE, INIT_CE => INIT_CE ) port map ( ICE => ice, CE1 => CE1_dly, CE2 => CE2_dly, GSR => GSR_dly, NUM_CE => AttrNumCe, CLKDIV => CLKDIV_dly, R => SR_dly ); ---------------------------------------------------------------------- ----------- Instant IDELAY --------------------------------------- ---------------------------------------------------------------------- INST_IDELAY : IDELAY generic map ( IOBDELAY_VALUE => IOBDELAY_VALUE, IOBDELAY_TYPE => IOBDELAY_TYPE ) port map ( O => idelay_out, C => CLKDIV_dly, CE => DLYCE_dly, I => D_dly, INC => DLYINC_dly, RST => DLYRST_dly ); --################################################################### --##### IOBDELAY -- Delay input Data ##### --################################################################### prcs_d_delay:process(D_dly, idelay_out) begin case AttrIobDelay is when 0 => O_zd <= D_dly; datain <= D_dly; when 1 => O_zd <= idelay_out; datain <= D_dly; when 2 => O_zd <= D_dly; datain <= idelay_out; when 3 => O_zd <= idelay_out; datain <= idelay_out; when others => null; end case; end process prcs_d_delay; --#################################################################### --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(O_zd, Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd, SHIFTOUT1_zd, SHIFTOUT2_zd) begin O <= O_zd; Q1 <= Q1_zd after SYNC_PATH_DELAY; Q2 <= Q2_zd after SYNC_PATH_DELAY; Q3 <= Q3_zd after SYNC_PATH_DELAY; Q4 <= Q4_zd after SYNC_PATH_DELAY; Q5 <= Q5_zd after SYNC_PATH_DELAY; Q6 <= Q6_zd after SYNC_PATH_DELAY; SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY; SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY; end process prcs_output; --#################################################################### end ISERDES_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity RAM16X1S is generic ( INIT : bit_vector(15 downto 0) := X"0000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic ); end RAM16X1S; architecture RAM16X1S_V of RAM16X1S is signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT)); begin VITALReadBehavior : process(A0, A1, A2, A3, MEM) variable Index : integer := 16; variable Address : std_logic_vector(3 downto 0); begin Address := (A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Address); O <= MEM(Index); end process VITALReadBehavior; VITALWriteBehavior : process(WCLK) variable Index : integer := 16; variable Address : std_logic_vector (3 downto 0); begin if (rising_edge(WCLK)) then if (WE = '1') then Address := (A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Address); MEM(Index) <= D after 100 ps; end if; end if; end process VITALWriteBehavior; end RAM16X1S_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity RAM16X1D is generic ( INIT : bit_vector(15 downto 0) := X"0000" ); port ( DPO : out std_ulogic; SPO : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; DPRA0 : in std_ulogic; DPRA1 : in std_ulogic; DPRA2 : in std_ulogic; DPRA3 : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic ); end RAM16X1D; architecture RAM16X1D_V of RAM16X1D is signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); begin VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM) Variable Index_SP : integer := 16 ; Variable Index_DP : integer := 16 ; begin Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0)); SPO <= MEM(Index_SP); DPO <= MEM(Index_DP); end process VITALReadBehavior; VITALWriteBehavior : process(WCLK) variable Index_SP : integer := 16; variable Index_DP : integer := 16; begin Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then MEM(Index_SP) <= D after 100 ps; end if; end process VITALWriteBehavior; end RAM16X1D_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity ROM32X1 is generic ( INIT : bit_vector := X"00000000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic ); end ROM32X1; architecture ROM32X1_V of ROM32X1 is begin VITALBehavior : process (A4, A3, A2, A1, A0) variable INIT_BITS : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); variable MEM : std_logic_vector( 32 downto 0 ); variable Index : integer := 32; variable FIRST_TIME : boolean := true; begin if (FIRST_TIME = true) then MEM := ('X' & INIT_BITS(31 downto 0)); FIRST_TIME := false; end if; Index := DECODE_ADDR5(ADDRESS => (A4, A3, A2, A1, A0)); O <= MEM(Index); end process VITALBehavior; end ROM32X1_V; library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.Vpkg.all; entity ROM64X1 is generic ( INIT : bit_vector := X"0000000000000000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic ); end ROM64X1; architecture ROM64X1_V of ROM64X1 is begin VITALBehavior : process (A5, A4, A3, A2, A1, A0) variable INIT_BITS : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); variable MEM : std_logic_vector( 64 downto 0 ); variable Index : integer := 64; variable Raddress : std_logic_vector (5 downto 0); variable FIRST_TIME : boolean := true; begin if (FIRST_TIME = true) then MEM := ('X' & INIT_BITS(63 downto 0)); FIRST_TIME := false; end if; Raddress := (A5, A4, A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Raddress); O <= MEM(Index); end process VITALBehavior; end ROM64X1_V; library IEEE; use IEEE.STD_LOGIC_1164.all; --use IEEE.STD_LOGIC_SIGNED.all; --use IEEE.STD_LOGIC_ARITH.all; library grlib; use grlib.stdlib.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.vpkg.all; entity DSP48 is generic( AREG : integer := 1; B_INPUT : string := "DIRECT"; BREG : integer := 1; CARRYINREG : integer := 1; CARRYINSELREG : integer := 1; CREG : integer := 1; LEGACY_MODE : string := "MULT18X18S"; MREG : integer := 1; OPMODEREG : integer := 1; PREG : integer := 1; SUBTRACTREG : integer := 1 ); port( BCOUT : out std_logic_vector(17 downto 0); P : out std_logic_vector(47 downto 0); PCOUT : out std_logic_vector(47 downto 0); A : in std_logic_vector(17 downto 0); B : in std_logic_vector(17 downto 0); BCIN : in std_logic_vector(17 downto 0); C : in std_logic_vector(47 downto 0); CARRYIN : in std_ulogic; CARRYINSEL : in std_logic_vector(1 downto 0); CEA : in std_ulogic; CEB : in std_ulogic; CEC : in std_ulogic; CECARRYIN : in std_ulogic; CECINSUB : in std_ulogic; CECTRL : in std_ulogic; CEM : in std_ulogic; CEP : in std_ulogic; CLK : in std_ulogic; OPMODE : in std_logic_vector(6 downto 0); PCIN : in std_logic_vector(47 downto 0); RSTA : in std_ulogic; RSTB : in std_ulogic; RSTC : in std_ulogic; RSTCARRYIN : in std_ulogic; RSTCTRL : in std_ulogic; RSTM : in std_ulogic; RSTP : in std_ulogic; SUBTRACT : in std_ulogic ); end DSP48; -- architecture body -- architecture DSP48_V of DSP48 is procedure invalid_opmode_preg_msg( OPMODE : IN string ; CARRYINSEL : IN string ) is variable Message : line; begin Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); Write ( Message, OPMODE); Write ( Message, string'(" with CARRYINSEL ")); Write ( Message, CARRYINSEL); Write ( Message, string'(" to DSP48 instance ")); Write ( Message, string'("requires attribute PREG set to 1.")); assert false report Message.all severity Warning; DEALLOCATE (Message); end invalid_opmode_preg_msg; procedure invalid_opmode_mreg_msg( OPMODE : IN string ; CARRYINSEL : IN string ) is variable Message : line; begin Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); Write ( Message, OPMODE); Write ( Message, string'(" with CARRYINSEL ")); Write ( Message, CARRYINSEL); Write ( Message, string'(" to DSP48 instance ")); Write ( Message, string'("requires attribute MREG set to 1.")); assert false report Message.all severity Warning; DEALLOCATE (Message); end invalid_opmode_mreg_msg; procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; CARRYINSEL : IN string ) is variable Message : line; begin Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); Write ( Message, OPMODE); Write ( Message, string'(" with CARRYINSEL ")); Write ( Message, CARRYINSEL); Write ( Message, string'(" to DSP48 instance ")); Write ( Message, string'("requires attribute MREG set to 0.")); assert false report Message.all severity Warning; DEALLOCATE (Message); end invalid_opmode_no_mreg_msg; constant SYNC_PATH_DELAY : time := 100 ps; constant MAX_P : integer := 48; constant MAX_PCIN : integer := 48; constant MAX_OPMODE : integer := 7; constant MAX_BCIN : integer := 18; constant MAX_B : integer := 18; constant MAX_A : integer := 18; constant MAX_C : integer := 48; constant MSB_PCIN : integer := 47; constant MSB_OPMODE : integer := 6; constant MSB_BCIN : integer := 17; constant MSB_B : integer := 17; constant MSB_A : integer := 17; constant MSB_C : integer := 47; constant MSB_CARRYINSEL : integer := 1; constant MSB_P : integer := 47; constant MSB_PCOUT : integer := 47; constant MSB_BCOUT : integer := 17; constant SHIFT_MUXZ : integer := 17; signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0'); signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0'); signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0'); signal CARRYIN_ipd : std_ulogic := '0'; signal CARRYINSEL_ipd : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); signal CEA_ipd : std_ulogic := '0'; signal CEB_ipd : std_ulogic := '0'; signal CEC_ipd : std_ulogic := '0'; signal CECARRYIN_ipd : std_ulogic := '0'; signal CECINSUB_ipd : std_ulogic := '0'; signal CECTRL_ipd : std_ulogic := '0'; signal CEM_ipd : std_ulogic := '0'; signal CEP_ipd : std_ulogic := '0'; signal CLK_ipd : std_ulogic := '0'; signal GSR : std_ulogic := '0'; signal GSR_ipd : std_ulogic := '0'; signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); signal RSTA_ipd : std_ulogic := '0'; signal RSTB_ipd : std_ulogic := '0'; signal RSTC_ipd : std_ulogic := '0'; signal RSTCARRYIN_ipd : std_ulogic := '0'; signal RSTCTRL_ipd : std_ulogic := '0'; signal RSTM_ipd : std_ulogic := '0'; signal RSTP_ipd : std_ulogic := '0'; signal SUBTRACT_ipd : std_ulogic := '0'; signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0'); signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0'); signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0'); signal CARRYIN_dly : std_ulogic := '0'; signal CARRYINSEL_dly : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); signal CEA_dly : std_ulogic := '0'; signal CEB_dly : std_ulogic := '0'; signal CEC_dly : std_ulogic := '0'; signal CECARRYIN_dly : std_ulogic := '0'; signal CECINSUB_dly : std_ulogic := '0'; signal CECTRL_dly : std_ulogic := '0'; signal CEM_dly : std_ulogic := '0'; signal CEP_dly : std_ulogic := '0'; signal CLK_dly : std_ulogic := '0'; signal GSR_dly : std_ulogic := '0'; signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); signal RSTA_dly : std_ulogic := '0'; signal RSTB_dly : std_ulogic := '0'; signal RSTC_dly : std_ulogic := '0'; signal RSTCARRYIN_dly : std_ulogic := '0'; signal RSTCTRL_dly : std_ulogic := '0'; signal RSTM_dly : std_ulogic := '0'; signal RSTP_dly : std_ulogic := '0'; signal SUBTRACT_dly : std_ulogic := '0'; signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0'); --- Internal Signal Declarations signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0'); signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0'); signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0'); signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0'); signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); signal mult_o_reg : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); signal mult_o_mux : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); signal subtract_o_reg : std_ulogic := '0'; signal subtract_o_mux : std_ulogic := '0'; signal carryinsel_o_reg : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); signal carryinsel_o_mux : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); signal qcarryin_o_reg1 : std_ulogic := '0'; signal carryin0_o_mux : std_ulogic := '0'; signal carryin1_o_mux : std_ulogic := '0'; signal carryin2_o_mux : std_ulogic := '0'; signal qcarryin_o_reg2 : std_ulogic := '0'; signal carryin_o_mux : std_ulogic := '0'; signal accum_o : std_logic_vector(MSB_P downto 0) := (others => '0'); signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); signal add_i_int : std_logic_vector(47 downto 0) := (others => '0'); signal add_o_int : std_logic_vector(47 downto 0) := (others => '0'); signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0'); signal p_o_int : std_logic_vector(47 downto 0) := (others => '0'); signal subtract1_o_int : std_ulogic := '0'; signal carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0'); signal carry1_o_int : std_ulogic := '0'; signal carry2_o_int : std_ulogic := '0'; signal output_x_sig : std_ulogic := '0'; signal RST_META : std_ulogic := '0'; signal DefDelay : time := 10 ps; begin --------------------- -- INPUT PATH DELAYs --------------------- A_dly <= A after 0 ps; B_dly <= B after 0 ps; BCIN_dly <= BCIN after 0 ps; C_dly <= C after 0 ps; CARRYIN_dly <= CARRYIN after 0 ps; CARRYINSEL_dly <= CARRYINSEL after 0 ps; CEA_dly <= CEA after 0 ps; CEB_dly <= CEB after 0 ps; CEC_dly <= CEC after 0 ps; CECARRYIN_dly <= CECARRYIN after 0 ps; CECINSUB_dly <= CECINSUB after 0 ps; CECTRL_dly <= CECTRL after 0 ps; CEM_dly <= CEM after 0 ps; CEP_dly <= CEP after 0 ps; CLK_dly <= CLK after 0 ps; GSR_dly <= GSR after 0 ps; OPMODE_dly <= OPMODE after 0 ps; PCIN_dly <= PCIN after 0 ps; RSTA_dly <= RSTA after 0 ps; RSTB_dly <= RSTB after 0 ps; RSTC_dly <= RSTC after 0 ps; RSTCARRYIN_dly <= RSTCARRYIN after 0 ps; RSTCTRL_dly <= RSTCTRL after 0 ps; RSTM_dly <= RSTM after 0 ps; RSTP_dly <= RSTP after 0 ps; SUBTRACT_dly <= SUBTRACT after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- --#################################################################### --##### Initialization ### --#################################################################### prcs_init:process begin if((LEGACY_MODE /="NONE") and (LEGACY_MODE /="MULT18X18") and (LEGACY_MODE /="MULT18X18S")) then assert false report "Attribute Syntax Error: The allowed values for LEGACY_MODE are NONE, MULT18X18 or MULT18X18S." severity Failure; elsif((LEGACY_MODE ="MULT18X18") and (MREG /= 0)) then assert false report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18. This requires attribute MREG to be set to 0." severity Failure; elsif((LEGACY_MODE ="MULT18X18S") and (MREG /= 1)) then assert false report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18S. This requires attribute MREG to be set to 1." severity Failure; end if; wait; end process prcs_init; --#################################################################### --##### Input Register A with two levels of registers and a mux ### --#################################################################### prcs_qa_2lvl:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qa_o_reg1 <= ( others => '0'); qa_o_reg2 <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then --FP if((RSTA_dly = '1') and (CEA_dly = '1')) then if(RSTA_dly = '1') then qa_o_reg1 <= ( others => '0'); qa_o_reg2 <= ( others => '0'); elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then qa_o_reg2 <= qa_o_reg1; qa_o_reg1 <= A_dly; end if; end if; end if; end process prcs_qa_2lvl; ------------------------------------------------------------------ prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2) begin case AREG is when 0 => qa_o_mux <= A_dly; when 1 => qa_o_mux <= qa_o_reg1; when 2 => qa_o_mux <= qa_o_reg2; when others => assert false report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" severity Failure; end case; end process prcs_qa_o_mux; --#################################################################### --##### Input Register B with two levels of registers and a mux ### --#################################################################### prcs_b_in:process(B_dly, BCIN_dly) begin if(B_INPUT ="DIRECT") then b_o_mux <= B_dly; elsif(B_INPUT ="CASCADE") then b_o_mux <= BCIN_dly; else assert false report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE." severity Failure; end if; end process prcs_b_in; ------------------------------------------------------------------ prcs_qb_2lvl:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qb_o_reg1 <= ( others => '0'); qb_o_reg2 <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then -- FP if((RSTB_dly = '1') and (CEB_dly = '1')) then if(RSTB_dly = '1') then qb_o_reg1 <= ( others => '0'); qb_o_reg2 <= ( others => '0'); elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then qb_o_reg2 <= qb_o_reg1; qb_o_reg1 <= b_o_mux; end if; end if; end if; end process prcs_qb_2lvl; ------------------------------------------------------------------ prcs_qb_o_mux:process(b_o_mux, qb_o_reg1, qb_o_reg2) begin case BREG is when 0 => qb_o_mux <= b_o_mux; when 1 => qb_o_mux <= qb_o_reg1; when 2 => qb_o_mux <= qb_o_reg2; when others => assert false report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 " severity Failure; end case; end process prcs_qb_o_mux; --#################################################################### --##### Input Register C with 0, 1, level of registers ##### --#################################################################### prcs_qc_1lvl:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qc_o_reg <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then -- FP if((RSTC_dly = '1') and (CEC_dly = '1'))then if(RSTC_dly = '1') then qc_o_reg <= ( others => '0'); elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then qc_o_reg <= C_dly; end if; end if; end if; end process prcs_qc_1lvl; ------------------------------------------------------------------ prcs_qc_o_mux:process(C_dly, qc_o_reg) begin case CREG is when 0 => qc_o_mux <= C_dly; when 1 => qc_o_mux <= qc_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for CREG are 0 or 1" severity Failure; end case; end process prcs_qc_o_mux; --#################################################################### --##### Mulitplier ##### --#################################################################### prcs_mult:process(qa_o_mux, qb_o_mux) begin -- mult_o_int <= qa_o_mux * qb_o_mux; mult_o_int <= signed_mul(qa_o_mux, qb_o_mux); end process prcs_mult; ------------------------------------------------------------------ prcs_mult_reg:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then mult_o_reg <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then --FP if((RSTM_dly = '1') and (CEM_dly = '1'))then if(RSTM_dly = '1') then mult_o_reg <= ( others => '0'); elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then mult_o_reg <= mult_o_int; end if; end if; end if; end process prcs_mult_reg; ------------------------------------------------------------------ prcs_mult_mux:process(mult_o_reg, mult_o_int) begin case MREG is when 0 => mult_o_mux <= mult_o_int; when 1 => mult_o_mux <= mult_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for MREG are 0 or 1" severity Failure; end case; end process prcs_mult_mux; --#################################################################### --##### OpMode ##### --#################################################################### prcs_opmode_reg:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then opmode_o_reg <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then --FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then if(RSTCTRL_dly = '1') then opmode_o_reg <= ( others => '0'); elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then opmode_o_reg <= OPMODE_dly; end if; end if; end if; end process prcs_opmode_reg; ------------------------------------------------------------------ prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) begin case OPMODEREG is when 0 => opmode_o_mux <= OPMODE_dly; when 1 => opmode_o_mux <= opmode_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1" severity Failure; end case; end process prcs_opmode_mux; --#################################################################### --##### MUX_XYZ ##### --#################################################################### -- prcs_mux_xyz:process(opmode_o_mux,,,, FP) -- FP ?? more (Z) should be added to sensitivity list prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, qc_o_mux, PCIN_dly, output_x_sig) begin if(output_x_sig = '1') then muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); elsif(output_x_sig = '0') then --MUX_X ----- case opmode_o_mux(1 downto 0) is when "00" => muxx_o_mux <= ( others => '0'); -- FP ?? better way to concat ? and sign extend ? when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux; if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1'); elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0'); end if; when "10" => muxx_o_mux <= qp_o_mux; when "11" => if(qa_o_mux(MSB_A) = '0') then muxx_o_mux(MSB_P downto 0) <= ("000000000000" & qa_o_mux & qb_o_mux); elsif(qa_o_mux(MSB_A) = '1') then muxx_o_mux(MSB_P downto 0) <= ("111111111111" & qa_o_mux & qb_o_mux); end if; -- when "11" => muxx_o_mux(MSB_B downto 0) <= qb_o_mux; -- muxx_o_mux((MAX_A + MAX_B - 1) downto MAX_B) <= qa_o_mux; -- -- if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then -- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1'); -- elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then -- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0'); -- end if; when others => null; -- assert false -- report "Error: input signal OPMODE(1 downto 0) has unknown values" -- severity Failure; end case; --MUX_Y ----- case opmode_o_mux(3 downto 2) is when "00" => muxy_o_mux <= ( others => '0'); when "01" => muxy_o_mux <= ( others => '0'); when "10" => null; when "11" => muxy_o_mux <= qc_o_mux; when others => null; -- assert false -- report "Error: input signal OPMODE(3 downto 2) has unknown values" -- severity Failure; end case; --MUX_Z ----- case opmode_o_mux(6 downto 4) is when "000" => muxz_o_mux <= ( others => '0'); when "001" => muxz_o_mux <= PCIN_dly; when "010" => muxz_o_mux <= qp_o_mux; when "011" => muxz_o_mux <= qc_o_mux; when "100" => null; -- FP ?? better shift possible ? when "101" => if(PCIN_dly(MSB_PCIN) = '0') then muxz_o_mux <= ( others => '0'); elsif(PCIN_dly(MSB_PCIN) = '1') then muxz_o_mux <= ( others => '1'); end if; muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); when "110" => if(qp_o_mux(MSB_P) = '0') then muxz_o_mux <= ( others => '0'); elsif(qp_o_mux(MSB_P) = '1') then muxz_o_mux <= ( others => '1'); end if; -- muxz_o_mux ((MAX_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto (SHIFT_MUXZ - 1)); muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); when "111" => null; when others => null; -- assert false -- report "Error: input signal OPMODE(6 downto 4) has unknown values" -- severity Failure; end case; end if; end process prcs_mux_xyz; --#################################################################### --##### Subtract ##### --#################################################################### prcs_subtract_reg:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then subtract_o_reg <= '0'; elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then if(RSTCTRL_dly = '1') then subtract_o_reg <= '0'; elsif ((RSTCTRL_dly = '0') and (CECINSUB_dly = '1'))then subtract_o_reg <= SUBTRACT_dly; end if; end if; end if; end process prcs_subtract_reg; ------------------------------------------------------------------ prcs_subtract_mux:process(subtract_o_reg, SUBTRACT_dly) begin case SUBTRACTREG is when 0 => subtract_o_mux <= SUBTRACT_dly; when 1 => subtract_o_mux <= subtract_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for SUBTRACTREG are 0 or 1" severity Failure; end case; end process prcs_subtract_mux; --#################################################################### --##### CarryInSel ##### --#################################################################### prcs_carryinsel_reg:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then carryinsel_o_reg <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then --FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then if(RSTCTRL_dly = '1') then carryinsel_o_reg <= ( others => '0'); elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then carryinsel_o_reg <= CARRYINSEL_dly; end if; end if; end if; end process prcs_carryinsel_reg; ------------------------------------------------------------------ prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly) begin case CARRYINSELREG is when 0 => carryinsel_o_mux <= CARRYINSEL_dly; when 1 => carryinsel_o_mux <= carryinsel_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1" severity Failure; end case; end process prcs_carryinsel_mux; --#################################################################### --##### CarryIn ##### --#################################################################### prcs_carryin_reg1:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qcarryin_o_reg1 <= '0'; elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then if(RSTCARRYIN_dly = '1') then qcarryin_o_reg1 <= '0'; elsif((RSTCARRYIN_dly = '0') and (CECINSUB_dly = '1')) then qcarryin_o_reg1 <= CARRYIN_dly; end if; end if; end if; end process prcs_carryin_reg1; ------------------------------------------------------------------ prcs_carryin0_mux:process(qcarryin_o_reg1, CARRYIN_dly) begin case CARRYINREG is when 0 => carryin0_o_mux <= CARRYIN_dly; when 1 => carryin0_o_mux <= qcarryin_o_reg1; when others => assert false report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1" severity Failure; end case; end process prcs_carryin0_mux; ------------------------------------------------------------------ prcs_carryin1_mux:process(opmode_o_mux(0), opmode_o_mux(1), qa_o_mux(17), qb_o_mux(17)) begin case (opmode_o_mux(0) and opmode_o_mux(1)) is when '0' => carryin1_o_mux <= NOT(qa_o_mux(17) xor qb_o_mux(17)); when '1' => carryin1_o_mux <= NOT qa_o_mux(17); when others => null; -- assert false -- report "Error: UNKOWN Value at PORT OPMODE(1) " -- severity Failure; end case; end process prcs_carryin1_mux; ------------------------------------------------------------------ prcs_carryin2_mux:process(opmode_o_mux(0), opmode_o_mux(1), qp_o_mux(47), PCIN_dly(47)) begin if(((opmode_o_mux(1) = '1') and (opmode_o_mux(0) = '0')) or (opmode_o_mux(5) = '1') or (NOT ((opmode_o_mux(6) = '1') or (opmode_o_mux(4) = '1')))) then carryin2_o_mux <= NOT qp_o_mux(47); else carryin2_o_mux <= NOT PCIN_dly(47); end if; end process prcs_carryin2_mux; ------------------------------------------------------------------ prcs_carryin_reg2:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qcarryin_o_reg2 <= '0'; elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then if(RSTCARRYIN_dly = '1') then qcarryin_o_reg2 <= '0'; elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then qcarryin_o_reg2 <= carryin1_o_mux; end if; end if; end if; end process prcs_carryin_reg2; ------------------------------------------------------------------ prcs_carryin_mux:process(carryinsel_o_mux, carryin0_o_mux, carryin1_o_mux, carryin2_o_mux, qcarryin_o_reg2) begin case carryinsel_o_mux is when "00" => carryin_o_mux <= carryin0_o_mux; when "01" => carryin_o_mux <= carryin2_o_mux; when "10" => carryin_o_mux <= carryin1_o_mux; when "11" => carryin_o_mux <= qcarryin_o_reg2; when others => null; -- assert false -- report "Error: UNKOWN Value at carryinsel_o_mux" -- severity Failure; end case; end process prcs_carryin_mux; --#################################################################### --##### ACCUM ##### --#################################################################### -- -- NOTE : moved it to the drc process -- -- prcs_accum_xyz:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, subtract_o_mux, carryin_o_mux ) -- variable carry_var : integer; -- begin -- if(carryin_o_mux = '1') then -- carry_var := 1; -- elsif (carryin_o_mux = '0') then -- carry_var := 0; ---- else ---- assert false ---- report "Error : CarryIn has Unknown value." ---- severity Failure; -- end if; -- if(subtract_o_mux = '0') then -- accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux); -- elsif(subtract_o_mux = '1') then -- accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux); ---- else ---- assert false ---- report "Error : Subtract has Unknown value." ---- severity Failure; -- end if; -- end process prcs_accum_xyz; --#################################################################### --##### PCOUT ##### --#################################################################### prcs_qp_reg:process(CLK_dly, GSR_dly) begin if(GSR_dly = '1') then qp_o_reg <= ( others => '0'); elsif (GSR_dly = '0') then if(rising_edge(CLK_dly)) then if(RSTP_dly = '1') then qp_o_reg <= ( others => '0'); elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then qp_o_reg <= accum_o; end if; end if; end if; end process prcs_qp_reg; ------------------------------------------------------------------ prcs_qp_mux:process(accum_o, qp_o_reg) begin case PREG is when 0 => qp_o_mux <= accum_o; when 1 => qp_o_mux <= qp_o_reg; when others => assert false report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" severity Failure; end case; end process prcs_qp_mux; --#################################################################### --##### ZERO_DELAY_OUTPUTS ##### --#################################################################### prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux) begin BCOUT_zd <= qb_o_mux; P_zd <= qp_o_mux; PCOUT_zd <= qp_o_mux; end process prcs_zero_delay_outputs; --#################################################################### --##### PMODE DRC ##### --#################################################################### prcs_opmode_drc:process(opmode_o_mux, carryinsel_o_mux, subtract_o_mux, muxx_o_mux, muxy_o_mux, muxz_o_mux, carryin_o_mux) variable Message : line; variable invalid_opmode_flg : boolean := true; variable add_flg : boolean := true; variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0'); begin -- if now > 100 ns then -- The above line was cusing the intial values of A, B or C not trigger opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux; case opmode_carryinsel_var is when "000000000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "000001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "000001100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "000010100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "000110000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "000111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "000111001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "000111100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "000111110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001000000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "001001001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "001001100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001001101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001001110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001010100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001010101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001010110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001010111" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001110000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001110001" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "001111001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "001111100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001111101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "001111110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "010000000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010001100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010001101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010010100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010010101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010110000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010110001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010111001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010111100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010111101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "010111110" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011000000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011001001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011001100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011001110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011010100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011010110" => if (MREG /= 0) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_no_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011010111" => if (MREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011110000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "011111100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "011111101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101000000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "101001100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101001101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101001110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101010100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101010101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101010110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101010111" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101110000" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101110001" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "101111001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "101111100" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101111101" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "101111110" => invalid_opmode_flg := true ; add_flg := true ; output_x_sig <= '0'; when "110000000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110001000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110001100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110001101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110010100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110010101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110110000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110110001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110111000" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110111001" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110111100" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110111101" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when "110111110" => if (PREG /= 1) then accum_o <= (others => 'X'); add_flg := false; if(invalid_opmode_flg) then invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); end if; invalid_opmode_flg := false; else invalid_opmode_flg := true; add_flg := true; output_x_sig <= '0'; end if; when others => if(invalid_opmode_flg = true) then invalid_opmode_flg := false; add_flg := false; output_x_sig <= '1'; accum_o <= (others => 'X'); Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); Write ( Message, slv_to_str(opmode_o_mux)); Write ( Message, string'(" with CARRYINSEL ")); Write ( Message, slv_to_str(carryinsel_o_mux)); Write ( Message, string'(" to DSP48 instance")); Write ( Message, string'(" is invalid.")); assert false report Message.all severity Warning; DEALLOCATE (Message); end if; end case; if(add_flg) then if(subtract_o_mux = '0') then accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux); elsif(subtract_o_mux = '1') then accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux); end if; end if; -- end if; end process prcs_opmode_drc; --#################################################################### --##### OUTPUT ##### --#################################################################### prcs_output:process(BCOUT_zd, PCOUT_zd, P_zd) begin BCOUT <= BCOUT_zd after SYNC_PATH_DELAY; P <= P_zd after SYNC_PATH_DELAY; PCOUT <= PCOUT_zd after SYNC_PATH_DELAY; end process prcs_output; end DSP48_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library grlib; use grlib.stdlib.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.vcomponents.all; use unisim.vpkg.all; entity ARAMB36_INTERNAL is generic ( BRAM_MODE : string := "TRUE_DUAL_PORT"; BRAM_SIZE : integer := 36; DOA_REG : integer := 0; DOB_REG : integer := 0; EN_ECC_READ : boolean := FALSE; EN_ECC_SCRUB : boolean := FALSE; EN_ECC_WRITE : boolean := FALSE; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"000000000000000000"; INIT_B : bit_vector := X"000000000000000000"; RAM_EXTENSION_A : string := "NONE"; RAM_EXTENSION_B : string := "NONE"; READ_WIDTH_A : integer := 0; READ_WIDTH_B : integer := 0; SETUP_ALL : time := 1000 ps; SETUP_READ_FIRST : time := 3000 ps; SIM_COLLISION_CHECK : string := "ALL"; SRVAL_A : bit_vector := X"000000000000000000"; SRVAL_B : bit_vector := X"000000000000000000"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; WRITE_WIDTH_A : integer := 0; WRITE_WIDTH_B : integer := 0 ); port ( CASCADEOUTLATA : out std_ulogic; CASCADEOUTLATB : out std_ulogic; CASCADEOUTREGA : out std_ulogic; CASCADEOUTREGB : out std_ulogic; DBITERR : out std_ulogic; DOA : out std_logic_vector(63 downto 0); DOB : out std_logic_vector(63 downto 0); DOPA : out std_logic_vector(7 downto 0); DOPB : out std_logic_vector(7 downto 0); ECCPARITY : out std_logic_vector(7 downto 0); SBITERR : out std_ulogic; ADDRA : in std_logic_vector(15 downto 0); ADDRB : in std_logic_vector(15 downto 0); CASCADEINLATA : in std_ulogic; CASCADEINLATB : in std_ulogic; CASCADEINREGA : in std_ulogic; CASCADEINREGB : in std_ulogic; CLKA : in std_ulogic; CLKB : in std_ulogic; DIA : in std_logic_vector(63 downto 0); DIB : in std_logic_vector(63 downto 0); DIPA : in std_logic_vector(7 downto 0); DIPB : in std_logic_vector(7 downto 0); ENA : in std_ulogic; ENB : in std_ulogic; REGCEA : in std_ulogic; REGCEB : in std_ulogic; REGCLKA : in std_ulogic; REGCLKB : in std_ulogic; SSRA : in std_ulogic; SSRB : in std_ulogic; WEA : in std_logic_vector(7 downto 0); WEB : in std_logic_vector(7 downto 0) ); end ARAMB36_INTERNAL; -- Architecture body -- architecture ARAMB36_INTERNAL_V of ARAMB36_INTERNAL is signal ADDRA_dly : std_logic_vector(15 downto 0) := (others => 'X'); signal CLKA_dly : std_ulogic := 'X'; signal DIA_dly : std_logic_vector(63 downto 0) := (others => 'X'); signal DIPA_dly : std_logic_vector(7 downto 0) := (others => 'X'); signal ENA_dly : std_ulogic := 'X'; signal REGCEA_dly : std_ulogic := 'X'; signal SSRA_dly : std_ulogic := 'X'; signal WEA_dly : std_logic_vector(7 downto 0) := (others => 'X'); signal CASCADEINLATA_dly : std_ulogic := 'X'; signal CASCADEINREGA_dly : std_ulogic := 'X'; signal ADDRB_dly : std_logic_vector(15 downto 0) := (others => 'X'); signal CLKB_dly : std_ulogic := 'X'; signal DIB_dly : std_logic_vector(63 downto 0) := (others => 'X'); signal DIPB_dly : std_logic_vector(7 downto 0) := (others => 'X'); signal ENB_dly : std_ulogic := 'X'; signal REGCEB_dly : std_ulogic := 'X'; signal REGCLKA_dly : std_ulogic := 'X'; signal REGCLKB_dly : std_ulogic := 'X'; signal SSRB_dly : std_ulogic := 'X'; signal WEB_dly : std_logic_vector(7 downto 0) := (others => 'X'); signal CASCADEINLATB_dly : std_ulogic := 'X'; signal CASCADEINREGB_dly : std_ulogic := 'X'; signal sbiterr_out : std_ulogic := '0'; signal dbiterr_out : std_ulogic := '0'; signal sbiterr_outreg : std_ulogic := '0'; signal dbiterr_outreg : std_ulogic := '0'; signal sbiterr_out_out : std_ulogic := '0'; signal dbiterr_out_out : std_ulogic := '0'; signal doa_out : std_logic_vector(63 downto 0) := (others => '0'); signal dopa_out : std_logic_vector(7 downto 0) := (others => '0'); signal doa_outreg : std_logic_vector(63 downto 0) := (others => '0'); signal dopa_outreg : std_logic_vector(7 downto 0) := (others => '0'); signal dob_outreg : std_logic_vector(63 downto 0) := (others => '0'); signal dopb_outreg : std_logic_vector(7 downto 0) := (others => '0'); signal dob_out : std_logic_vector(63 downto 0) := (others => '0'); signal dopb_out : std_logic_vector(7 downto 0) := (others => '0'); signal doa_out_mux : std_logic_vector(63 downto 0) := (others => '0'); signal dopa_out_mux : std_logic_vector(7 downto 0) := (others => '0'); signal doa_outreg_mux : std_logic_vector(63 downto 0) := (others => '0'); signal dopa_outreg_mux : std_logic_vector(7 downto 0) := (others => '0'); signal dob_outreg_mux : std_logic_vector(63 downto 0) := (others => '0'); signal dopb_outreg_mux : std_logic_vector(7 downto 0) := (others => '0'); signal dob_out_mux : std_logic_vector(63 downto 0) := (others => '0'); signal dopb_out_mux : std_logic_vector(7 downto 0) := (others => '0'); signal doa_out_out : std_logic_vector(63 downto 0) := (others => '0'); signal dopa_out_out : std_logic_vector(7 downto 0) := (others => '0'); signal dob_out_out : std_logic_vector(63 downto 0) := (others => '0'); signal dopb_out_out : std_logic_vector(7 downto 0) := (others => '0'); signal addra_dly_15_reg : std_logic := '0'; signal addrb_dly_15_reg : std_logic := '0'; signal addra_dly_15_reg1 : std_logic := '0'; signal addrb_dly_15_reg1 : std_logic := '0'; signal cascade_a : std_logic_vector(1 downto 0) := (others => '0'); signal cascade_b : std_logic_vector(1 downto 0) := (others => '0'); signal GSR_dly : std_ulogic := 'X'; signal eccparity_out : std_logic_vector(7 downto 0) := (others => 'X'); signal SRVAL_A_STD : std_logic_vector(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); signal SRVAL_B_STD : std_logic_vector(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); signal INIT_A_STD : std_logic_vector(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); signal INIT_B_STD : std_logic_vector(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); signal di_x : std_logic_vector(63 downto 0) := (others => 'X'); function GetWidestWidth ( wr_width_a : in integer; rd_width_a : in integer; wr_width_b : in integer; rd_width_b : in integer ) return integer is variable func_widest_width : integer; begin if ((wr_width_a >= wr_width_b) and (wr_width_a >= rd_width_a) and (wr_width_a >= rd_width_b)) then func_widest_width := wr_width_a; elsif ((wr_width_b >= wr_width_a) and (wr_width_b >= rd_width_a) and (wr_width_b >= rd_width_b)) then func_widest_width := wr_width_b; elsif ((rd_width_a >= wr_width_a) and (rd_width_a >= wr_width_b) and (rd_width_a >= rd_width_b)) then func_widest_width := rd_width_a; elsif ((rd_width_b >= wr_width_a) and (rd_width_b >= wr_width_b) and (rd_width_b >= rd_width_a)) then func_widest_width := rd_width_b; end if; return func_widest_width; end; function GetWidth ( rdwr_width : in integer ) return integer is variable func_width : integer; begin case rdwr_width is when 1 => func_width := 1; when 2 => func_width := 2; when 4 => func_width := 4; when 9 => func_width := 8; when 18 => func_width := 16; when 36 => func_width := 32; when 72 => func_width := 64; when others => func_width := 1; end case; return func_width; end; function GetWidthp ( rdwr_widthp : in integer ) return integer is variable func_widthp : integer; begin case rdwr_widthp is when 9 => func_widthp := 1; when 18 => func_widthp := 2; when 36 => func_widthp := 4; when 72 => func_widthp := 8; when others => func_widthp := 1; end case; return func_widthp; end; function GetMemoryDepth ( rdwr_width : in integer; func_bram_size : in integer ) return integer is variable func_mem_depth : integer; begin case rdwr_width is when 1 => if (func_bram_size = 18) then func_mem_depth := 16384; else func_mem_depth := 32768; end if; when 2 => if (func_bram_size = 18) then func_mem_depth := 8192; else func_mem_depth := 16384; end if; when 4 => if (func_bram_size = 18) then func_mem_depth := 4096; else func_mem_depth := 8192; end if; when 9 => if (func_bram_size = 18) then func_mem_depth := 2048; else func_mem_depth := 4096; end if; when 18 => if (func_bram_size = 18) then func_mem_depth := 1024; else func_mem_depth := 2048; end if; when 36 => if (func_bram_size = 18) then func_mem_depth := 512; else func_mem_depth := 1024; end if; when 72 => if (func_bram_size = 18) then func_mem_depth := 0; else func_mem_depth := 512; end if; when others => func_mem_depth := 32768; end case; return func_mem_depth; end; function GetMemoryDepthP ( rdwr_width : in integer; func_bram_size : in integer ) return integer is variable func_memp_depth : integer; begin case rdwr_width is when 9 => if (func_bram_size = 18) then func_memp_depth := 2048; else func_memp_depth := 4096; end if; when 18 => if (func_bram_size = 18) then func_memp_depth := 1024; else func_memp_depth := 2048; end if; when 36 => if (func_bram_size = 18) then func_memp_depth := 512; else func_memp_depth := 1024; end if; when 72 => if (func_bram_size = 18) then func_memp_depth := 0; else func_memp_depth := 512; end if; when others => func_memp_depth := 4096; end case; return func_memp_depth; end; function GetAddrBitLSB ( rdwr_width : in integer ) return integer is variable func_lsb : integer; begin case rdwr_width is when 1 => func_lsb := 0; when 2 => func_lsb := 1; when 4 => func_lsb := 2; when 9 => func_lsb := 3; when 18 => func_lsb := 4; when 36 => func_lsb := 5; when 72 => func_lsb := 6; when others => func_lsb := 10; end case; return func_lsb; end; function GetAddrBit124 ( rdwr_width : in integer; w_width : in integer ) return integer is variable func_widest_width : integer; begin case rdwr_width is when 1 => case w_width is when 2 => func_widest_width := 0; when 4 => func_widest_width := 1; when 9 => func_widest_width := 2; when 18 => func_widest_width := 3; when 36 => func_widest_width := 4; when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when 2 => case w_width is when 4 => func_widest_width := 1; when 9 => func_widest_width := 2; when 18 => func_widest_width := 3; when 36 => func_widest_width := 4; when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when 4 => case w_width is when 9 => func_widest_width := 2; when 18 => func_widest_width := 3; when 36 => func_widest_width := 4; when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when others => func_widest_width := 10; end case; return func_widest_width; end; function GetAddrBit8 ( rdwr_width : in integer; w_width : in integer ) return integer is variable func_widest_width : integer; begin case rdwr_width is when 9 => case w_width is when 18 => func_widest_width := 3; when 36 => func_widest_width := 4; when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when others => func_widest_width := 10; end case; return func_widest_width; end; function GetAddrBit16 ( rdwr_width : in integer; w_width : in integer ) return integer is variable func_widest_width : integer; begin case rdwr_width is when 18 => case w_width is when 36 => func_widest_width := 4; when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when others => func_widest_width := 10; end case; return func_widest_width; end; function GetAddrBit32 ( rdwr_width : in integer; w_width : in integer ) return integer is variable func_widest_width : integer; begin case rdwr_width is when 36 => case w_width is when 72 => func_widest_width := 5; when others => func_widest_width := 10; end case; when others => func_widest_width := 10; end case; return func_widest_width; end; --------------------------------------------------------------------------- -- Function SLV_X_TO_HEX returns a hex string version of the std_logic_vector -- argument. --------------------------------------------------------------------------- function SLV_X_TO_HEX ( SLV : in std_logic_vector; string_length : in integer ) return string is variable i : integer := 1; variable j : integer := 1; variable STR : string(string_length downto 1); variable nibble : std_logic_vector(3 downto 0) := "0000"; variable full_nibble_count : integer := 0; variable remaining_bits : integer := 0; begin full_nibble_count := SLV'length/4; remaining_bits := SLV'length mod 4; for i in 1 to full_nibble_count loop nibble := SLV(((4*i) - 1) downto ((4*i) - 4)); if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then STR(j) := 'x'; elsif (nibble = "0000") then STR(j) := '0'; elsif (nibble = "0001") then STR(j) := '1'; elsif (nibble = "0010") then STR(j) := '2'; elsif (nibble = "0011") then STR(j) := '3'; elsif (nibble = "0100") then STR(j) := '4'; elsif (nibble = "0101") then STR(j) := '5'; elsif (nibble = "0110") then STR(j) := '6'; elsif (nibble = "0111") then STR(j) := '7'; elsif (nibble = "1000") then STR(j) := '8'; elsif (nibble = "1001") then STR(j) := '9'; elsif (nibble = "1010") then STR(j) := 'a'; elsif (nibble = "1011") then STR(j) := 'b'; elsif (nibble = "1100") then STR(j) := 'c'; elsif (nibble = "1101") then STR(j) := 'd'; elsif (nibble = "1110") then STR(j) := 'e'; elsif (nibble = "1111") then STR(j) := 'f'; end if; j := j + 1; end loop; if (remaining_bits /= 0) then nibble := "0000"; nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits)); if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then STR(j) := 'x'; elsif (nibble = "0000") then STR(j) := '0'; elsif (nibble = "0001") then STR(j) := '1'; elsif (nibble = "0010") then STR(j) := '2'; elsif (nibble = "0011") then STR(j) := '3'; elsif (nibble = "0100") then STR(j) := '4'; elsif (nibble = "0101") then STR(j) := '5'; elsif (nibble = "0110") then STR(j) := '6'; elsif (nibble = "0111") then STR(j) := '7'; elsif (nibble = "1000") then STR(j) := '8'; elsif (nibble = "1001") then STR(j) := '9'; elsif (nibble = "1010") then STR(j) := 'a'; elsif (nibble = "1011") then STR(j) := 'b'; elsif (nibble = "1100") then STR(j) := 'c'; elsif (nibble = "1101") then STR(j) := 'd'; elsif (nibble = "1110") then STR(j) := 'e'; elsif (nibble = "1111") then STR(j) := 'f'; end if; end if; return STR; end SLV_X_TO_HEX; constant widest_width : integer := GetWidestWidth(WRITE_WIDTH_A, READ_WIDTH_A, WRITE_WIDTH_B, READ_WIDTH_B); constant mem_depth : integer := GetMemoryDepth(widest_width, BRAM_SIZE); constant memp_depth : integer := GetMemoryDepthP(widest_width, BRAM_SIZE); constant width : integer := GetWidth(widest_width); constant widthp : integer := GetWidthp(widest_width); constant wa_width : integer := GetWidth(WRITE_WIDTH_A); constant wb_width : integer := GetWidth(WRITE_WIDTH_B); constant ra_width : integer := GetWidth(READ_WIDTH_A); constant rb_width : integer := GetWidth(READ_WIDTH_B); constant wa_widthp : integer := GetWidthp(WRITE_WIDTH_A); constant wb_widthp : integer := GetWidthp(WRITE_WIDTH_B); constant ra_widthp : integer := GetWidthp(READ_WIDTH_A); constant rb_widthp : integer := GetWidthp(READ_WIDTH_B); constant r_addra_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_A); constant r_addrb_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_B); constant w_addra_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_A); constant w_addrb_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_B); constant w_addra_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_A, widest_width); constant r_addra_bit_124 : integer := GetAddrBit124(READ_WIDTH_A, widest_width); constant w_addrb_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_B, widest_width); constant r_addrb_bit_124 : integer := GetAddrBit124(READ_WIDTH_B, widest_width); constant w_addra_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_A, widest_width); constant r_addra_bit_8 : integer := GetAddrBit8(READ_WIDTH_A, widest_width); constant w_addrb_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_B, widest_width); constant r_addrb_bit_8 : integer := GetAddrBit8(READ_WIDTH_B, widest_width); constant w_addra_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_A, widest_width); constant r_addra_bit_16 : integer := GetAddrBit16(READ_WIDTH_A, widest_width); constant w_addrb_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_B, widest_width); constant r_addrb_bit_16 : integer := GetAddrBit16(READ_WIDTH_B, widest_width); constant w_addra_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_A, widest_width); constant r_addra_bit_32 : integer := GetAddrBit32(READ_WIDTH_A, widest_width); constant w_addrb_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_B, widest_width); constant r_addrb_bit_32 : integer := GetAddrBit32(READ_WIDTH_B, widest_width); constant col_addr_lsb : integer := GetAddrBitLSB(widest_width); type Two_D_array_type is array ((mem_depth - 1) downto 0) of std_logic_vector((width - 1) downto 0); type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp -1) downto 0); function slv_to_two_D_array( slv_length : integer; slv_width : integer; SLV : in std_logic_vector ) return two_D_array_type is variable two_D_array : two_D_array_type; variable intermediate : std_logic_vector((slv_width - 1) downto 0); begin for i in 0 to (slv_length - 1) loop intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); two_D_array(i) := intermediate; end loop; return two_D_array; end; function slv_to_two_D_parity_array( slv_length : integer; slv_width : integer; SLV : in std_logic_vector ) return two_D_parity_array_type is variable two_D_parity_array : two_D_parity_array_type; variable intermediate : std_logic_vector((slv_width - 1) downto 0); begin for i in 0 to (slv_length - 1)loop intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); two_D_parity_array(i) := intermediate; end loop; return two_D_parity_array; end; function fn_dip_ecc ( encode : in std_logic; di_in : in std_logic_vector (63 downto 0); dip_in : in std_logic_vector (7 downto 0) ) return std_logic_vector is variable fn_dip_ecc : std_logic_vector (7 downto 0); begin fn_dip_ecc(0) := di_in(0) xor di_in(1) xor di_in(3) xor di_in(4) xor di_in(6) xor di_in(8) xor di_in(10) xor di_in(11) xor di_in(13) xor di_in(15) xor di_in(17) xor di_in(19) xor di_in(21) xor di_in(23) xor di_in(25) xor di_in(26) xor di_in(28) xor di_in(30) xor di_in(32) xor di_in(34) xor di_in(36) xor di_in(38) xor di_in(40) xor di_in(42) xor di_in(44) xor di_in(46) xor di_in(48) xor di_in(50) xor di_in(52) xor di_in(54) xor di_in(56) xor di_in(57) xor di_in(59) xor di_in(61) xor di_in(63); fn_dip_ecc(1) := di_in(0) xor di_in(2) xor di_in(3) xor di_in(5) xor di_in(6) xor di_in(9) xor di_in(10) xor di_in(12) xor di_in(13) xor di_in(16) xor di_in(17) xor di_in(20) xor di_in(21) xor di_in(24) xor di_in(25) xor di_in(27) xor di_in(28) xor di_in(31) xor di_in(32) xor di_in(35) xor di_in(36) xor di_in(39) xor di_in(40) xor di_in(43) xor di_in(44) xor di_in(47) xor di_in(48) xor di_in(51) xor di_in(52) xor di_in(55) xor di_in(56) xor di_in(58) xor di_in(59) xor di_in(62) xor di_in(63); fn_dip_ecc(2) := di_in(1) xor di_in(2) xor di_in(3) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56) xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); fn_dip_ecc(3) := di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56); fn_dip_ecc(4) := di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56); fn_dip_ecc(5) := di_in(26) xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56); fn_dip_ecc(6) := di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); if (encode = '1') then fn_dip_ecc(7) := fn_dip_ecc(0) xor fn_dip_ecc(1) xor fn_dip_ecc(2) xor fn_dip_ecc(3) xor fn_dip_ecc(4) xor fn_dip_ecc(5) xor fn_dip_ecc(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26) xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); else fn_dip_ecc(7) := dip_in(0) xor dip_in(1) xor dip_in(2) xor dip_in(3) xor dip_in(4) xor dip_in(5) xor dip_in(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26) xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); end if; return fn_dip_ecc; end fn_dip_ecc; procedure prcd_chk_for_col_msg ( constant wea_tmp : in std_ulogic; constant web_tmp : in std_ulogic; constant addra_tmp : in std_logic_vector (15 downto 0); constant addrb_tmp : in std_logic_vector (15 downto 0); variable col_wr_wr_msg : inout std_ulogic; variable col_wra_rdb_msg : inout std_ulogic; variable col_wrb_rda_msg : inout std_ulogic ) is variable string_length_1 : integer; variable string_length_2 : integer; variable message : LINE; constant MsgSeverity : severity_level := Error; begin if ((SIM_COLLISION_CHECK = "ALL" or SIM_COLLISION_CHECK = "WARNING_ONLY") and (not(((WRITE_MODE_B = "READ_FIRST" and web_tmp = '1' and wea_tmp = '0') and (not(rising_edge(clka_dly) and (not(rising_edge(clkb_dly)))))) or ((WRITE_MODE_A = "READ_FIRST" and wea_tmp = '1' and web_tmp = '0') and (not(rising_edge(clkb_dly) and (not(rising_edge(clka_dly))))))))) then if ((addra_tmp'length mod 4) = 0) then string_length_1 := addra_tmp'length/4; elsif ((addra_tmp'length mod 4) > 0) then string_length_1 := addra_tmp'length/4 + 1; end if; if ((addrb_tmp'length mod 4) = 0) then string_length_2 := addrb_tmp'length/4; elsif ((addrb_tmp'length mod 4) > 0) then string_length_2 := addrb_tmp'length/4 + 1; end if; if (wea_tmp = '1' and web_tmp = '1' and col_wr_wr_msg = '1') then Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( message, STRING'(" at simulation time ")); Write ( message, now); Write ( message, STRING'(".")); Write ( message, LF ); Write ( message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM.")); Write ( message, STRING'(" The contents written to the RAM at address location ")); Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1)); Write ( message, STRING'(" (hex) ")); Write ( message, STRING'("of Port A and address location ")); Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2)); Write ( message, STRING'(" (hex) ")); Write ( message, STRING'("of Port B are unknown. ")); ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; DEALLOCATE (message); col_wr_wr_msg := '0'; elsif (wea_tmp = '1' and web_tmp = '0' and col_wra_rdb_msg = '1') then Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( message, STRING'(" at simulation time ")); Write ( message, now); Write ( message, STRING'(".")); Write ( message, LF ); Write ( message, STRING'(" A read was performed on address ")); Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2)); Write ( message, STRING'(" (hex) ")); Write ( message, STRING'("of port B while a write was requested to the same address on Port A. ")); Write ( message, STRING'(" The write will be successful however the read value on port B is unknown until the next CLKB cycle. ")); ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; DEALLOCATE (message); col_wra_rdb_msg := '0'; elsif (wea_tmp = '0' and web_tmp = '1' and col_wrb_rda_msg = '1') then Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( message, STRING'(" at simulation time ")); Write ( message, now); Write ( message, STRING'(".")); Write ( message, LF ); Write ( message, STRING'(" A read was performed on address ")); Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1)); Write ( message, STRING'(" (hex) ")); Write ( message, STRING'("of port A while a write was requested to the same address on Port B. ")); Write ( message, STRING'(" The write will be successful however the read value on port A is unknown until the next CLKA cycle. ")); ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; DEALLOCATE (message); col_wrb_rda_msg := '0'; end if; end if; end prcd_chk_for_col_msg; procedure prcd_write_ram ( constant we : in std_logic; constant di : in std_logic_vector; constant dip : in std_logic; variable mem_proc : inout std_logic_vector; variable memp_proc : inout std_logic ) is alias di_tmp : std_logic_vector (di'length-1 downto 0) is di; alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc; begin if (we = '1') then mem_proc_tmp := di_tmp; if (width >= 8) then memp_proc := dip; end if; end if; end prcd_write_ram; procedure prcd_write_ram_col ( constant we_o : in std_logic; constant we : in std_logic; constant di : in std_logic_vector; constant dip : in std_logic; variable mem_proc : inout std_logic_vector; variable memp_proc : inout std_logic ) is alias di_tmp : std_logic_vector (di'length-1 downto 0) is di; alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc; variable i : integer := 0; begin if (we = '1') then for i in 0 to di'length-1 loop if ((mem_proc_tmp(i) /= 'X') or (not(we = we_o and we = '1'))) then mem_proc_tmp(i) := di_tmp(i); end if; end loop; if (width >= 8 and ((memp_proc /= 'X') or (not(we = we_o and we = '1')))) then memp_proc := dip; end if; end if; end prcd_write_ram_col; procedure prcd_x_buf ( constant wr_rd_mode : in std_logic_vector (1 downto 0); constant do_uindex : in integer; constant do_lindex : in integer; constant dop_index : in integer; constant do_ltmp : in std_logic_vector (63 downto 0); variable do_tmp : inout std_logic_vector (63 downto 0); constant dop_ltmp : in std_logic_vector (7 downto 0); variable dop_tmp : inout std_logic_vector (7 downto 0) ) is variable i : integer; begin if (wr_rd_mode = "01") then for i in do_lindex to do_uindex loop if (do_ltmp(i) = 'X') then do_tmp(i) := 'X'; end if; end loop; if (dop_ltmp(dop_index) = 'X') then dop_tmp(dop_index) := 'X'; end if; else do_tmp(do_lindex + 7 downto do_lindex) := do_ltmp(do_lindex + 7 downto do_lindex); dop_tmp(dop_index) := dop_ltmp(dop_index); end if; end prcd_x_buf; procedure prcd_rd_ram_a ( constant addra_tmp : in std_logic_vector (15 downto 0); variable doa_tmp : inout std_logic_vector (63 downto 0); variable dopa_tmp : inout std_logic_vector (7 downto 0); constant mem : in Two_D_array_type; constant memp : in Two_D_parity_array_type ) is variable prcd_tmp_addra_dly_depth : integer; variable prcd_tmp_addra_dly_width : integer; begin case ra_width is when 1 | 2 | 4 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124)); doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124)); doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1 downto prcd_tmp_addra_dly_width * ra_width); end if; when 8 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth); dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3)); doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto prcd_tmp_addra_dly_width * 8); dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width downto prcd_tmp_addra_dly_width); end if; when 16 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth); dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto prcd_tmp_addra_dly_width * 16); dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1 downto prcd_tmp_addra_dly_width * 2); end if; when 32 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); doa_tmp(31 downto 0) := mem(prcd_tmp_addra_dly_depth); dopa_tmp(3 downto 0) := memp(prcd_tmp_addra_dly_depth); end if; when 64 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); doa_tmp(63 downto 0) := mem(prcd_tmp_addra_dly_depth); dopa_tmp(7 downto 0) := memp(prcd_tmp_addra_dly_depth); end if; when others => null; end case; end prcd_rd_ram_a; procedure prcd_rd_ram_b ( constant addrb_tmp : in std_logic_vector (15 downto 0); variable dob_tmp : inout std_logic_vector (63 downto 0); variable dopb_tmp : inout std_logic_vector (7 downto 0); constant mem : in Two_D_array_type; constant memp : in Two_D_parity_array_type ) is variable prcd_tmp_addrb_dly_depth : integer; variable prcd_tmp_addrb_dly_width : integer; begin case rb_width is when 1 | 2 | 4 => if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124)); dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124)); dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1 downto prcd_tmp_addrb_dly_width * rb_width); end if; when 8 => if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth); dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3)); dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto prcd_tmp_addrb_dly_width * 8); dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width downto prcd_tmp_addrb_dly_width); end if; when 16 => if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth); dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto prcd_tmp_addrb_dly_width * 16); dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1 downto prcd_tmp_addrb_dly_width * 2); end if; when 32 => if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); dob_tmp(31 downto 0) := mem(prcd_tmp_addrb_dly_depth); dopb_tmp(3 downto 0) := memp(prcd_tmp_addrb_dly_depth); end if; when others => null; end case; end prcd_rd_ram_b; procedure prcd_col_wr_ram_a ( constant seq : in std_logic_vector (1 downto 0); constant web_tmp : in std_logic_vector (7 downto 0); constant wea_tmp : in std_logic_vector (7 downto 0); constant dia_tmp : in std_logic_vector (63 downto 0); constant dipa_tmp : in std_logic_vector (7 downto 0); constant addrb_tmp : in std_logic_vector (15 downto 0); constant addra_tmp : in std_logic_vector (15 downto 0); variable mem : inout Two_D_array_type; variable memp : inout Two_D_parity_array_type; variable col_wr_wr_msg : inout std_ulogic; variable col_wra_rdb_msg : inout std_ulogic; variable col_wrb_rda_msg : inout std_ulogic ) is variable prcd_tmp_addra_dly_depth : integer; variable prcd_tmp_addra_dly_width : integer; variable junk : std_ulogic; begin case wa_width is when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0)); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width))); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2))); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1)); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (web_tmp(2), wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (web_tmp(3), wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 64 => null; -- prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); -- prcd_write_ram_col ('0', '1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp); -- -- prcd_write_ram_col ('0', '1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7)); ---- if (seq = "00") ---- prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp); -- when others => null; end case; end prcd_col_wr_ram_a; procedure prcd_col_wr_ram_b ( constant seq : in std_logic_vector (1 downto 0); constant wea_tmp : in std_logic_vector (7 downto 0); constant web_tmp : in std_logic_vector (7 downto 0); constant dib_tmp : in std_logic_vector (63 downto 0); constant dipb_tmp : in std_logic_vector (7 downto 0); constant addra_tmp : in std_logic_vector (15 downto 0); constant addrb_tmp : in std_logic_vector (15 downto 0); variable mem : inout Two_D_array_type; variable memp : inout Two_D_parity_array_type; variable col_wr_wr_msg : inout std_ulogic; variable col_wra_rdb_msg : inout std_ulogic; variable col_wrb_rda_msg : inout std_ulogic ) is variable prcd_tmp_addrb_dly_depth : integer; variable prcd_tmp_addrb_dly_width : integer; variable junk : std_ulogic; begin case wb_width is when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0)); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width))); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2))); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1)); end if; if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; end if; when 64 => prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(4), web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(5), web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(6), web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; prcd_write_ram_col (wea_tmp(7), web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7)); if (seq = "00") then prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; when others => null; end case; end prcd_col_wr_ram_b; procedure prcd_col_rd_ram_a ( constant viol_type_tmp : in std_logic_vector (1 downto 0); constant seq : in std_logic_vector (1 downto 0); constant web_tmp : in std_logic_vector (7 downto 0); constant wea_tmp : in std_logic_vector (7 downto 0); constant addra_tmp : in std_logic_vector (15 downto 0); variable doa_tmp : inout std_logic_vector (63 downto 0); variable dopa_tmp : inout std_logic_vector (7 downto 0); constant mem : in Two_D_array_type; constant memp : in Two_D_parity_array_type; constant wr_mode_a_tmp : in std_logic_vector (1 downto 0) ) is variable prcd_tmp_addra_dly_depth : integer; variable prcd_tmp_addra_dly_width : integer; variable junk : std_ulogic; variable doa_ltmp : std_logic_vector (63 downto 0); variable dopa_ltmp : std_logic_vector (7 downto 0); begin doa_ltmp := (others => '0'); dopa_ltmp := (others => '0'); case ra_width is when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124)); doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124)); doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1) downto (prcd_tmp_addra_dly_width * ra_width)); end if; prcd_x_buf (wr_mode_a_tmp, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3)); doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 8) + 7) downto (prcd_tmp_addra_dly_width * 8)); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width); end if; prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 7) downto (prcd_tmp_addra_dly_width * 16)); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width * 2); end if; prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 15) downto ((prcd_tmp_addra_dly_width * 16) + 8)); dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1); end if; prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; when 32 => if (ra_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16); dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2); prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24); dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3); prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; end if; when 64 => prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16); dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2); prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24); dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3); prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and web_tmp(4) = '1' and wea_tmp(4) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(4) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(4) /= '1')) then doa_ltmp(39 downto 32) := mem(prcd_tmp_addra_dly_depth)(39 downto 32); dopa_ltmp(4) := memp(prcd_tmp_addra_dly_depth)(4); prcd_x_buf (wr_mode_a_tmp, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and web_tmp(5) = '1' and wea_tmp(5) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(5) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(5) /= '1')) then doa_ltmp(47 downto 40) := mem(prcd_tmp_addra_dly_depth)(47 downto 40); dopa_ltmp(5) := memp(prcd_tmp_addra_dly_depth)(5); prcd_x_buf (wr_mode_a_tmp, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and web_tmp(6) = '1' and wea_tmp(6) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(6) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(6) /= '1')) then doa_ltmp(55 downto 48) := mem(prcd_tmp_addra_dly_depth)(55 downto 48); dopa_ltmp(6) := memp(prcd_tmp_addra_dly_depth)(6); prcd_x_buf (wr_mode_a_tmp, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and web_tmp(7) = '1' and wea_tmp(7) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(7) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(7) /= '1')) then doa_ltmp(63 downto 56) := mem(prcd_tmp_addra_dly_depth)(63 downto 56); dopa_ltmp(7) := memp(prcd_tmp_addra_dly_depth)(7); prcd_x_buf (wr_mode_a_tmp, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); end if; when others => null; end case; end prcd_col_rd_ram_a; procedure prcd_col_rd_ram_b ( constant viol_type_tmp : in std_logic_vector (1 downto 0); constant seq : in std_logic_vector (1 downto 0); constant wea_tmp : in std_logic_vector (7 downto 0); constant web_tmp : in std_logic_vector (7 downto 0); constant addrb_tmp : in std_logic_vector (15 downto 0); variable dob_tmp : inout std_logic_vector (63 downto 0); variable dopb_tmp : inout std_logic_vector (7 downto 0); constant mem : in Two_D_array_type; constant memp : in Two_D_parity_array_type; constant wr_mode_b_tmp : in std_logic_vector (1 downto 0) ) is variable prcd_tmp_addrb_dly_depth : integer; variable prcd_tmp_addrb_dly_width : integer; variable junk : std_ulogic; variable dob_ltmp : std_logic_vector (63 downto 0); variable dopb_ltmp : std_logic_vector (7 downto 0); begin dob_ltmp := (others => '0'); dopb_ltmp := (others => '0'); case rb_width is when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124)); dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124)); dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1) downto (prcd_tmp_addrb_dly_width * rb_width)); end if; prcd_x_buf (wr_mode_b_tmp, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3)); dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 8) + 7) downto (prcd_tmp_addrb_dly_width * 8)); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width); end if; prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 7) downto (prcd_tmp_addrb_dly_width * 16)); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width * 2); end if; prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 15) downto ((prcd_tmp_addrb_dly_width * 16) + 8)); dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1); end if; prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; when 32 => if (rb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16); dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2); prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24); dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3); prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; end if; when 64 => prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16); dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2); prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24); dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3); prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and wea_tmp(4) = '1' and web_tmp(4) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(4) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(4) /= '1')) then dob_ltmp(39 downto 32) := mem(prcd_tmp_addrb_dly_depth)(39 downto 32); dopb_ltmp(4) := memp(prcd_tmp_addrb_dly_depth)(4); prcd_x_buf (wr_mode_b_tmp, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and wea_tmp(5) = '1' and web_tmp(5) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(5) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(5) /= '1')) then dob_ltmp(47 downto 40) := mem(prcd_tmp_addrb_dly_depth)(47 downto 40); dopb_ltmp(5) := memp(prcd_tmp_addrb_dly_depth)(5); prcd_x_buf (wr_mode_b_tmp, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and wea_tmp(6) = '1' and web_tmp(6) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(6) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(6) /= '1')) then dob_ltmp(55 downto 48) := mem(prcd_tmp_addrb_dly_depth)(55 downto 48); dopb_ltmp(6) := memp(prcd_tmp_addrb_dly_depth)(6); prcd_x_buf (wr_mode_b_tmp, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and wea_tmp(7) = '1' and web_tmp(7) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(7) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(7) /= '1')) then dob_ltmp(63 downto 56) := mem(prcd_tmp_addrb_dly_depth)(63 downto 56); dopb_ltmp(7) := memp(prcd_tmp_addrb_dly_depth)(7); prcd_x_buf (wr_mode_b_tmp, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); end if; when others => null; end case; end prcd_col_rd_ram_b; procedure prcd_wr_ram_a ( constant wea_tmp : in std_logic_vector (7 downto 0); constant dia_tmp : in std_logic_vector (63 downto 0); constant dipa_tmp : in std_logic_vector (7 downto 0); constant addra_tmp : in std_logic_vector (15 downto 0); variable mem : inout Two_D_array_type; variable memp : inout Two_D_parity_array_type; constant syndrome_tmp : in std_logic_vector (7 downto 0) ) is variable prcd_tmp_addra_dly_depth : integer; variable prcd_tmp_addra_dly_width : integer; variable junk : std_ulogic; begin case wa_width is when 1 | 2 | 4 => if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124)); prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124)); prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk); end if; when 8 => if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0)); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3)); prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width))); end if; when 16 => if (wa_width >= width) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); else prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2))); prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1)); end if; when 32 => prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); prcd_write_ram (wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); prcd_write_ram (wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); when 64 => if (syndrome_tmp /= "00000000" and syndrome_tmp(7) = '1' and EN_ECC_SCRUB = TRUE) then prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); prcd_write_ram ('1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); prcd_write_ram ('1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); prcd_write_ram ('1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); prcd_write_ram ('1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); prcd_write_ram ('1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4)); prcd_write_ram ('1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5)); prcd_write_ram ('1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6)); prcd_write_ram ('1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7)); end if; when others => null; end case; end prcd_wr_ram_a; procedure prcd_wr_ram_b ( constant web_tmp : in std_logic_vector (7 downto 0); constant dib_tmp : in std_logic_vector (63 downto 0); constant dipb_tmp : in std_logic_vector (7 downto 0); constant addrb_tmp : in std_logic_vector (15 downto 0); variable mem : inout Two_D_array_type; variable memp : inout Two_D_parity_array_type ) is variable prcd_tmp_addrb_dly_depth : integer; variable prcd_tmp_addrb_dly_width : integer; variable junk : std_ulogic; begin case wb_width is when 1 | 2 | 4 => if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124)); prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124)); prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk); end if; when 8 => if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0)); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width))); end if; when 16 => if (wb_width >= width) then prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); else prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2))); prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1)); end if; when 32 => prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); when 64 => prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); prcd_write_ram (web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4)); prcd_write_ram (web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5)); prcd_write_ram (web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6)); prcd_write_ram (web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7)); when others => null; end case; end prcd_wr_ram_b; procedure prcd_col_ecc_read ( variable do_tmp : inout std_logic_vector (63 downto 0); variable dop_tmp : inout std_logic_vector (7 downto 0); constant addr_tmp : in std_logic_vector (15 downto 0); variable dbiterr_tmp : inout std_logic; variable sbiterr_tmp : inout std_logic; variable mem : inout Two_D_array_type; variable memp : inout Two_D_parity_array_type; variable prcd_syndrome : inout std_logic_vector (7 downto 0) ) is variable prcd_ecc_bit_position : std_logic_vector (71 downto 0); variable prcd_dopr_ecc : std_logic_vector (7 downto 0); variable prcd_di_dly_ecc_corrected : std_logic_vector (63 downto 0); variable prcd_dip_dly_ecc_corrected : std_logic_vector (7 downto 0); variable prcd_tmp_syndrome_int : integer := 0; begin prcd_dopr_ecc := fn_dip_ecc('0', do_tmp, dop_tmp); prcd_syndrome := prcd_dopr_ecc xor dop_tmp; if (prcd_syndrome /= "00000000") then if (prcd_syndrome(7) = '1') then -- dectect single bit error prcd_ecc_bit_position := do_tmp(63 downto 57) & dop_tmp(6) & do_tmp(56 downto 26) & dop_tmp(5) & do_tmp(25 downto 11) & dop_tmp(4) & do_tmp(10 downto 4) & dop_tmp(3) & do_tmp(3 downto 1) & dop_tmp(2) & do_tmp(0) & dop_tmp(1 downto 0) & dop_tmp(7); prcd_tmp_syndrome_int := SLV_TO_INT(prcd_syndrome(6 downto 0)); prcd_ecc_bit_position(prcd_tmp_syndrome_int) := not prcd_ecc_bit_position(prcd_tmp_syndrome_int); -- correct single bit error in the output prcd_di_dly_ecc_corrected := prcd_ecc_bit_position(71 downto 65) & prcd_ecc_bit_position(63 downto 33) & prcd_ecc_bit_position(31 downto 17) & prcd_ecc_bit_position(15 downto 9) & prcd_ecc_bit_position(7 downto 5) & prcd_ecc_bit_position(3); -- correct single bit error in the memory do_tmp := prcd_di_dly_ecc_corrected; prcd_dip_dly_ecc_corrected := prcd_ecc_bit_position(0) & prcd_ecc_bit_position(64) & prcd_ecc_bit_position(32) & prcd_ecc_bit_position(16) & prcd_ecc_bit_position(8) & prcd_ecc_bit_position(4) & prcd_ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory dop_tmp := prcd_dip_dly_ecc_corrected; dbiterr_tmp := '0'; sbiterr_tmp := '1'; elsif (prcd_syndrome(7) = '0') then -- double bit error sbiterr_tmp := '0'; dbiterr_tmp := '1'; end if; else dbiterr_tmp := '0'; sbiterr_tmp := '0'; end if; if (ssra_dly = '1') then -- ssra reset dbiterr_tmp := '0'; sbiterr_tmp := '0'; end if; if (prcd_syndrome /= "00000000" and prcd_syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then prcd_wr_ram_a ("11111111", prcd_di_dly_ecc_corrected, prcd_dip_dly_ecc_corrected, addr_tmp, mem, memp, prcd_syndrome); end if; end prcd_col_ecc_read; begin --------------------- -- INPUT PATH DELAYs -------------------- addra_dly <= ADDRA after 0 ps; addrb_dly <= ADDRB after 0 ps; cascadeinlata_dly <= CASCADEINLATA after 0 ps; cascadeinlatb_dly <= CASCADEINLATB after 0 ps; cascadeinrega_dly <= CASCADEINREGA after 0 ps; cascadeinregb_dly <= CASCADEINREGB after 0 ps; clka_dly <= CLKA after 0 ps; clkb_dly <= CLKB after 0 ps; dia_dly <= DIA after 0 ps; dib_dly <= DIB after 0 ps; dipa_dly <= DIPA after 0 ps; dipb_dly <= DIPB after 0 ps; ena_dly <= ENA after 0 ps; enb_dly <= ENB after 0 ps; regcea_dly <= REGCEA after 0 ps; regceb_dly <= REGCEB after 0 ps; ssra_dly <= SSRA after 0 ps; ssrb_dly <= SSRB after 0 ps; wea_dly <= WEA after 0 ps; web_dly <= WEB after 0 ps; gsr_dly <= GSR after 0 ps; regclka_dly <= REGCLKA after 0 ps; regclkb_dly <= REGCLKB after 0 ps; -------------------- -- BEHAVIOR SECTION -------------------- prcs_clk: process (clka_dly, clkb_dly, gsr_dly) variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) & To_StdLogicVector(INIT_7E) & To_StdLogicVector(INIT_7D) & To_StdLogicVector(INIT_7C) & To_StdLogicVector(INIT_7B) & To_StdLogicVector(INIT_7A) & To_StdLogicVector(INIT_79) & To_StdLogicVector(INIT_78) & To_StdLogicVector(INIT_77) & To_StdLogicVector(INIT_76) & To_StdLogicVector(INIT_75) & To_StdLogicVector(INIT_74) & To_StdLogicVector(INIT_73) & To_StdLogicVector(INIT_72) & To_StdLogicVector(INIT_71) & To_StdLogicVector(INIT_70) & To_StdLogicVector(INIT_6F) & To_StdLogicVector(INIT_6E) & To_StdLogicVector(INIT_6D) & To_StdLogicVector(INIT_6C) & To_StdLogicVector(INIT_6B) & To_StdLogicVector(INIT_6A) & To_StdLogicVector(INIT_69) & To_StdLogicVector(INIT_68) & To_StdLogicVector(INIT_67) & To_StdLogicVector(INIT_66) & To_StdLogicVector(INIT_65) & To_StdLogicVector(INIT_64) & To_StdLogicVector(INIT_63) & To_StdLogicVector(INIT_62) & To_StdLogicVector(INIT_61) & To_StdLogicVector(INIT_60) & To_StdLogicVector(INIT_5F) & To_StdLogicVector(INIT_5E) & To_StdLogicVector(INIT_5D) & To_StdLogicVector(INIT_5C) & To_StdLogicVector(INIT_5B) & To_StdLogicVector(INIT_5A) & To_StdLogicVector(INIT_59) & To_StdLogicVector(INIT_58) & To_StdLogicVector(INIT_57) & To_StdLogicVector(INIT_56) & To_StdLogicVector(INIT_55) & To_StdLogicVector(INIT_54) & To_StdLogicVector(INIT_53) & To_StdLogicVector(INIT_52) & To_StdLogicVector(INIT_51) & To_StdLogicVector(INIT_50) & To_StdLogicVector(INIT_4F) & To_StdLogicVector(INIT_4E) & To_StdLogicVector(INIT_4D) & To_StdLogicVector(INIT_4C) & To_StdLogicVector(INIT_4B) & To_StdLogicVector(INIT_4A) & To_StdLogicVector(INIT_49) & To_StdLogicVector(INIT_48) & To_StdLogicVector(INIT_47) & To_StdLogicVector(INIT_46) & To_StdLogicVector(INIT_45) & To_StdLogicVector(INIT_44) & To_StdLogicVector(INIT_43) & To_StdLogicVector(INIT_42) & To_StdLogicVector(INIT_41) & To_StdLogicVector(INIT_40) & To_StdLogicVector(INIT_3F) & To_StdLogicVector(INIT_3E) & To_StdLogicVector(INIT_3D) & To_StdLogicVector(INIT_3C) & To_StdLogicVector(INIT_3B) & To_StdLogicVector(INIT_3A) & To_StdLogicVector(INIT_39) & To_StdLogicVector(INIT_38) & To_StdLogicVector(INIT_37) & To_StdLogicVector(INIT_36) & To_StdLogicVector(INIT_35) & To_StdLogicVector(INIT_34) & To_StdLogicVector(INIT_33) & To_StdLogicVector(INIT_32) & To_StdLogicVector(INIT_31) & To_StdLogicVector(INIT_30) & To_StdLogicVector(INIT_2F) & To_StdLogicVector(INIT_2E) & To_StdLogicVector(INIT_2D) & To_StdLogicVector(INIT_2C) & To_StdLogicVector(INIT_2B) & To_StdLogicVector(INIT_2A) & To_StdLogicVector(INIT_29) & To_StdLogicVector(INIT_28) & To_StdLogicVector(INIT_27) & To_StdLogicVector(INIT_26) & To_StdLogicVector(INIT_25) & To_StdLogicVector(INIT_24) & To_StdLogicVector(INIT_23) & To_StdLogicVector(INIT_22) & To_StdLogicVector(INIT_21) & To_StdLogicVector(INIT_20) & To_StdLogicVector(INIT_1F) & To_StdLogicVector(INIT_1E) & To_StdLogicVector(INIT_1D) & To_StdLogicVector(INIT_1C) & To_StdLogicVector(INIT_1B) & To_StdLogicVector(INIT_1A) & To_StdLogicVector(INIT_19) & To_StdLogicVector(INIT_18) & To_StdLogicVector(INIT_17) & To_StdLogicVector(INIT_16) & To_StdLogicVector(INIT_15) & To_StdLogicVector(INIT_14) & To_StdLogicVector(INIT_13) & To_StdLogicVector(INIT_12) & To_StdLogicVector(INIT_11) & To_StdLogicVector(INIT_10) & To_StdLogicVector(INIT_0F) & To_StdLogicVector(INIT_0E) & To_StdLogicVector(INIT_0D) & To_StdLogicVector(INIT_0C) & To_StdLogicVector(INIT_0B) & To_StdLogicVector(INIT_0A) & To_StdLogicVector(INIT_09) & To_StdLogicVector(INIT_08) & To_StdLogicVector(INIT_07) & To_StdLogicVector(INIT_06) & To_StdLogicVector(INIT_05) & To_StdLogicVector(INIT_04) & To_StdLogicVector(INIT_03) & To_StdLogicVector(INIT_02) & To_StdLogicVector(INIT_01) & To_StdLogicVector(INIT_00); variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) & To_StdLogicVector(INITP_0E) & To_StdLogicVector(INITP_0D) & To_StdLogicVector(INITP_0C) & To_StdLogicVector(INITP_0B) & To_StdLogicVector(INITP_0A) & To_StdLogicVector(INITP_09) & To_StdLogicVector(INITP_08) & To_StdLogicVector(INITP_07) & To_StdLogicVector(INITP_06) & To_StdLogicVector(INITP_05) & To_StdLogicVector(INITP_04) & To_StdLogicVector(INITP_03) & To_StdLogicVector(INITP_02) & To_StdLogicVector(INITP_01) & To_StdLogicVector(INITP_00); variable mem : Two_D_array_type := slv_to_two_D_array(mem_depth, width, mem_slv); variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(memp_depth, widthp, memp_slv); variable tmp_addra_dly_depth : integer; variable tmp_addra_dly_width : integer; variable tmp_addrb_dly_depth : integer; variable tmp_addrb_dly_width : integer; variable junk1 : std_logic; variable wr_mode_a : std_logic_vector(1 downto 0) := "00"; variable wr_mode_b : std_logic_vector(1 downto 0) := "00"; variable tmp_syndrome_int : integer; variable doa_buf : std_logic_vector(63 downto 0) := (others => '0'); variable dob_buf : std_logic_vector(63 downto 0) := (others => '0'); variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0'); variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0'); variable syndrome : std_logic_vector(7 downto 0) := (others => '0'); variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0'); variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0'); variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0'); variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0'); variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0'); variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0'); variable addra_dly_15_reg_var : std_logic := '0'; variable addrb_dly_15_reg_var : std_logic := '0'; variable addra_dly_15_reg_bram_var : std_logic := '0'; variable addrb_dly_15_reg_bram_var : std_logic := '0'; variable FIRST_TIME : boolean := true; variable curr_time : time := 0 ps; variable prev_time : time := 0 ps; variable viol_time : integer := 0; variable viol_type : std_logic_vector(1 downto 0) := (others => '0'); variable message : line; variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0'); variable dbiterr_out_var : std_ulogic := '0'; variable sbiterr_out_var : std_ulogic := '0'; variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); variable col_wr_wr_msg : std_ulogic := '1'; variable col_wra_rdb_msg : std_ulogic := '1'; variable col_wrb_rda_msg : std_ulogic := '1'; begin -- process prcs_clka if (FIRST_TIME) then case READ_WIDTH_A is when 0 | 1 | 2 | 4 | 9 | 18 => null; when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); end if; when 72 => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; when others => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; end case; case READ_WIDTH_B is when 0 | 1 | 2 | 4 | 9 | 18 => null; when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); end if; when 72 => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; when others => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " READ_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => READ_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; end case; case WRITE_WIDTH_A is when 0 | 1 | 2 | 4 | 9 | 18 => null; when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); end if; when 72 => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; when others => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; end case; case WRITE_WIDTH_B is when 0 | 1 | 2 | 4 | 9 | 18 => null; when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); end if; when 72 => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; when others => if (BRAM_SIZE = 18) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", TailMsg => "", MsgSeverity => failure ); elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_WIDTH_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_WIDTH_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", TailMsg => "", MsgSeverity => failure ); end if; end case; if (not(EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " EN_ECC_READ ", EntityName => "/ARAMB36_INTERNAL", GenericValue => EN_ECC_READ, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " TRUE or FALSE ", TailMsg => "", MsgSeverity => failure ); end if; if (not(EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " EN_ECC_WRITE ", EntityName => "/ARAMB36_INTERNAL", GenericValue => EN_ECC_WRITE, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " TRUE or FALSE ", TailMsg => "", MsgSeverity => failure ); end if; if (EN_ECC_SCRUB = TRUE) then assert false report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is not supported on ARAMB36_INTERNAL instance." severity failure; end if; if (not(EN_ECC_SCRUB = TRUE or EN_ECC_SCRUB = FALSE)) then GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " EN_ECC_SCRUB ", EntityName => "/ARAMB36_INTERNAL", GenericValue => EN_ECC_SCRUB, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " TRUE or FALSE ", TailMsg => "", MsgSeverity => failure ); end if; if (EN_ECC_READ = FALSE and EN_ECC_SCRUB = TRUE) then assert false report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is vaild only if the attribute EN_ECC_READ set to TRUE on ARAMB36_INTERNAL instance." severity failure; end if; if (READ_WIDTH_A = 0 and READ_WIDTH_B = 0) then assert false report "Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on ARAMB36_INTERNAL instance, both can not be 0." severity failure; end if; if (WRITE_MODE_A = "WRITE_FIRST") then wr_mode_a := "00"; elsif (WRITE_MODE_A = "READ_FIRST") then wr_mode_a := "01"; elsif (WRITE_MODE_A = "NO_CHANGE") then wr_mode_a := "10"; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_MODE_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_MODE_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", TailMsg => "", MsgSeverity => failure ); end if; if (WRITE_MODE_B = "WRITE_FIRST") then wr_mode_b := "00"; elsif (WRITE_MODE_B = "READ_FIRST") then wr_mode_b := "01"; elsif (WRITE_MODE_B = "NO_CHANGE") then wr_mode_b := "10"; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " WRITE_MODE_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => WRITE_MODE_B, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", TailMsg => "", MsgSeverity => failure ); end if; if (RAM_EXTENSION_A = "UPPER") then cascade_a <= "11"; elsif (RAM_EXTENSION_A = "LOWER") then cascade_a <= "01"; elsif (RAM_EXTENSION_A= "NONE") then cascade_a <= "00"; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " RAM_EXTENSION_A ", EntityName => "/ARAMB36_INTERNAL", GenericValue => RAM_EXTENSION_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " NONE, LOWER or UPPER ", TailMsg => "", MsgSeverity => failure ); end if; if (RAM_EXTENSION_B = "UPPER") then cascade_b <= "11"; elsif (RAM_EXTENSION_B = "LOWER") then cascade_b <= "01"; elsif (RAM_EXTENSION_B= "NONE") then cascade_b <= "00"; else GenericValueCheckMessage ( HeaderMsg => " Attribute Syntax Error : ", GenericName => " RAM_EXTENSION_B ", EntityName => "/ARAMB36_INTERNAL", GenericValue => RAM_EXTENSION_A, Unit => "", ExpectedValueMsg => " The Legal values for this attribute are ", ExpectedGenericValue => " NONE, LOWER or UPPER ", TailMsg => "", MsgSeverity => failure ); end if; if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (READ_WIDTH_A /= 1)) then assert false report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1." severity Failure; end if; if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (WRITE_WIDTH_A /= 1)) then assert false report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1." severity Failure; end if; if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (READ_WIDTH_B /= 1)) then assert false report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1." severity Failure; end if; if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (WRITE_WIDTH_B /= 1)) then assert false report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1." severity Failure; end if; end if; if (rising_edge(clka_dly)) then if (ena_dly = '1') then prev_time := curr_time; curr_time := now; addra_reg_dly := addra_dly; wea_reg_dly := wea_dly; dia_reg_dly := dia_dly; dipa_reg_dly := dipa_dly; end if; end if; if (rising_edge(clkb_dly)) then if (enb_dly = '1') then prev_time := curr_time; curr_time := now; addrb_reg_dly := addrb_dly; web_reg_dly := web_dly; dib_reg_dly := dib_dly; dipb_reg_dly := dipb_dly; end if; end if; if (gsr_dly = '1' or FIRST_TIME) then doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); if (ra_width >= 8) then dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); end if; dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); if (rb_width >= 8) then dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); end if; dbiterr_out <= '0'; sbiterr_out <= '0'; FIRST_TIME := false; elsif (gsr_dly = '0') then if (rising_edge(clka_dly)) then if (cascade_a(1) = '1') then addra_dly_15_reg_bram_var := not addra_dly(15); else addra_dly_15_reg_bram_var := addra_dly(15); end if; end if; if (rising_edge(clkb_dly)) then if (cascade_b(1) = '1') then addrb_dly_15_reg_bram_var := not addrb_dly(15); else addrb_dly_15_reg_bram_var := addrb_dly(15); end if; end if; if (rising_edge(clka_dly) or rising_edge(clkb_dly)) then if ((cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00")) or (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then ------------------------------------------------------------------------------- -- Collision starts ------------------------------------------------------------------------------- if (SIM_COLLISION_CHECK /= "NONE") then if (curr_time - prev_time = 0 ps) then viol_time := 1; elsif (curr_time - prev_time <= SETUP_READ_FIRST) then viol_time := 2; end if; if (ena_dly = '0' or enb_dly = '0') then viol_time := 0; end if; if ((WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000")) then if ((WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000")) then viol_time := 0; end if; end if; if (viol_time /= 0) then if (rising_edge(clka_dly) and rising_edge(clkb_dly)) then if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then viol_type := "01"; prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); prcd_col_wr_ram_a ("00", web_dly, wea_dly, di_x, di_x(7 downto 0), addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_wr_ram_b ("00", wea_dly, web_dly, di_x, di_x(7 downto 0), addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); prcd_col_wr_ram_a ("10", web_dly, wea_dly, dia_dly, dipa_dly, addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly); eccparity_out <= dip_ecc_col; prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dip_ecc_col, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); else prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dipb_dly, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; if (wr_mode_a /= "01") then prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); end if; if (wr_mode_b /= "01") then prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); end if; if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); end if; else viol_time := 0; end if; elsif (rising_edge(clka_dly) and (not(rising_edge(clkb_dly)))) then if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then viol_type := "10"; prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); prcd_col_wr_ram_a ("00", web_reg_dly, wea_dly, di_x, di_x(7 downto 0), addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_wr_ram_b ("00", wea_dly, web_reg_dly, di_x, di_x(7 downto 0), addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_rd_ram_a (viol_type, "01", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); prcd_col_wr_ram_a ("10", web_reg_dly, wea_dly, dia_dly, dipa_dly, addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then dip_ecc_col := fn_dip_ecc('1', dib_reg_dly, dipb_reg_dly); eccparity_out <= dip_ecc_col; prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dip_ecc_col, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); else prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dipb_reg_dly, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; if (wr_mode_a /= "01") then prcd_col_rd_ram_a (viol_type, "11", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); end if; if (wr_mode_b /= "01") then prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); end if; if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); end if; else viol_time := 0; end if; elsif ((not(rising_edge(clka_dly))) and rising_edge(clkb_dly)) then if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then viol_type := "11"; prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); prcd_col_wr_ram_a ("00", web_dly, wea_reg_dly, di_x, di_x(7 downto 0), addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_wr_ram_b ("00", wea_reg_dly, web_dly, di_x, di_x(7 downto 0), addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); prcd_col_rd_ram_b (viol_type, "01", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); prcd_col_wr_ram_a ("10", web_dly, wea_reg_dly, dia_reg_dly, dipa_reg_dly, addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly); eccparity_out <= dip_ecc_col; prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dip_ecc_col, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); else prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dipb_dly, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); end if; if (wr_mode_a /= "01") then prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); end if; if (wr_mode_b /= "01") then prcd_col_rd_ram_b (viol_type, "11", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); end if; if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then prcd_col_ecc_read (doa_buf, dopa_buf, addra_reg_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); end if; else viol_time := 0; end if; end if; if (SIM_COLLISION_CHECK = "WARNING_ONLY") then viol_time := 0; end if; end if; end if; ------------------------------------------------------------------------------- -- end collision ------------------------------------------------------------------------------- end if; ------------------------------------------------------------------------------- -- Port A ------------------------------------------------------------------------------- if (rising_edge(clka_dly)) then if (ssra_dly = '1' and BRAM_MODE = "ECC") then assert false report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode." severity Warning; end if; -- registering addra_dly(15) the second time if (regcea_dly = '1') then addra_dly_15_reg1 <= addra_dly_15_reg_var; end if; -- registering addra[15) if (ena_dly = '1' and (wr_mode_a /= "10" or wea_dly(0) = '0')) then if (cascade_a(1) = '1') then addra_dly_15_reg_var := not addra_dly(15); else addra_dly_15_reg_var := addra_dly(15); end if; end if; addra_dly_15_reg <= addra_dly_15_reg_var; if (gsr_dly = '0' and ena_dly = '1' and (cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00"))) then if (ssra_dly = '1' and DOA_REG = 0) then doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0); doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); if (ra_width >= 8) then dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); end if; end if; if (viol_time = 0) then -- read for rf if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1)) or (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE)) then prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); -- ECC decode -- only port A if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then dopr_ecc := fn_dip_ecc('0', doa_buf, dopa_buf); syndrome := dopr_ecc xor dopa_buf; if (syndrome /= "00000000") then if (syndrome(7) = '1') then -- dectect single bit error ecc_bit_position := doa_buf(63 downto 57) & dopa_buf(6) & doa_buf(56 downto 26) & dopa_buf(5) & doa_buf(25 downto 11) & dopa_buf(4) & doa_buf(10 downto 4) & dopa_buf(3) & doa_buf(3 downto 1) & dopa_buf(2) & doa_buf(0) & dopa_buf(1 downto 0) & dopa_buf(7); tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0)); ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output dia_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory doa_buf := dia_dly_ecc_corrected; dipa_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory dopa_buf := dipa_dly_ecc_corrected; dbiterr_out_var := '0'; sbiterr_out_var := '1'; elsif (syndrome(7) = '0') then -- double bit error sbiterr_out_var := '0'; dbiterr_out_var := '1'; end if; else dbiterr_out_var := '0'; sbiterr_out_var := '0'; end if; if (ssra_dly = '1') then -- ssra reset dbiterr_out_var := '0'; sbiterr_out_var := '0'; end if; end if; end if; if (syndrome /= "00000000" and syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then prcd_wr_ram_a ("11111111", dia_dly_ecc_corrected, dipa_dly_ecc_corrected, addra_dly, mem, memp, syndrome); else prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome); end if; if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1)) and (not(BRAM_MODE = "ECC" and EN_ECC_READ = TRUE))) then prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); end if; end if; end if; end if; ------------------------------------------------------------------------------- -- Port B ------------------------------------------------------------------------------- if (rising_edge(clkb_dly)) then -- DRC if (ssrb_dly = '1' and BRAM_MODE = "ECC") then assert false report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode." severity Warning; end if; -- registering addrb_dly(15) the second time if (regceb_dly = '1') then addrb_dly_15_reg1 <= addrb_dly_15_reg_var; end if; -- registering addrb(15) if (enb_dly = '1' and (wr_mode_b /= "10" or web_dly(0) = '0' or ssrb_dly = '1')) then if (cascade_b(1) = '1') then addrb_dly_15_reg_var := not addrb_dly(15); else addrb_dly_15_reg_var := addrb_dly(15); end if; end if; addrb_dly_15_reg <= addrb_dly_15_reg_var; if (gsr_dly = '0' and enb_dly = '1' and (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then if (ssrb_dly = '1' and DOB_REG = 0) then dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0); dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); if (rb_width >= 8) then dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); end if; end if; dip_ecc := fn_dip_ecc('1', dib_dly, dipb_dly); eccparity_out <= dip_ecc; if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then dipb_dly_ecc := dip_ecc; else dipb_dly_ecc := dipb_dly; end if; if (viol_time = 0) then if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); end if; if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then prcd_wr_ram_b (web_dly, dib_dly, dipb_dly_ecc, addrb_dly, mem, memp); else prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp); end if; if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); end if; end if; end if; end if; if (ena_dly = '1' and (rising_edge(clka_dly) or viol_time /= 0)) then if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then -- Virtex4 feature if (wr_mode_a = "00" and BRAM_SIZE = 16) then if ((WRITE_WIDTH_A = 18 and not(wea_dly(1 downto 0) = "00" or wea_dly(1 downto 0) = "11")) or (WRITE_WIDTH_A = 36 and not(wea_dly(3 downto 0) = "0000" or wea_dly(3 downto 0) = "1111"))) then if (WRITE_WIDTH_A /= READ_WIDTH_A) then doa_buf(ra_width-1 downto 0) := di_x(ra_width-1 downto 0); if (READ_WIDTH_A >= 9) then dopa_buf(ra_widthp-1 downto 0) := di_x(ra_widthp-1 downto 0); end if; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port A is in WRITE_FIRST mode with parameter WRITE_WIDTH_A = ")); Write ( Message, INTEGER'(WRITE_WIDTH_A)); Write ( Message, STRING'(", which is different from READ_WIDTH_A = ")); Write ( Message, INTEGER'(READ_WIDTH_A)); Write ( Message, STRING'(". The write will be successful however the read value of all bits on port A")); Write ( Message, STRING'(" is unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); elsif (WRITE_WIDTH_A = 18) then for i in 0 to 1 loop if (wea_dly(i) = '0') then doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); dopa_buf(i downto i) := di_x(i downto i); end if; end loop; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,")); Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s).")); Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and")); Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); elsif (WRITE_WIDTH_A = 36) then for i in 0 to 3 loop if (wea_dly(i) = '0') then doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); dopa_buf(i downto i) := di_x(i downto i); end if; end loop; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,")); Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s).")); Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and")); Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); end if; end if; end if; doa_out <= doa_buf; dopa_out <= dopa_buf; end if; end if; if (enb_dly = '1' and (rising_edge(clkb_dly) or viol_time /= 0)) then if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then -- Virtex4 feature if (wr_mode_b = "00" and BRAM_SIZE = 16) then if ((WRITE_WIDTH_B = 18 and not(web_dly(1 downto 0) = "00" or web_dly(1 downto 0) = "11")) or (WRITE_WIDTH_B = 36 and not(web_dly(3 downto 0) = "0000" or web_dly(3 downto 0) = "1111"))) then if (WRITE_WIDTH_B /= READ_WIDTH_B) then dob_buf(rb_width-1 downto 0) := di_x(rb_width-1 downto 0); if (READ_WIDTH_B >= 9) then dopb_buf(rb_widthp-1 downto 0) := di_x(rb_widthp-1 downto 0); end if; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port B is in WRITE_FIRST mode with parameter WRITE_WIDTH_B = ")); Write ( Message, INTEGER'(WRITE_WIDTH_B)); Write ( Message, STRING'(", which is different from READ_WIDTH_B = ")); Write ( Message, INTEGER'(READ_WIDTH_B)); Write ( Message, STRING'(". The write will be successful however the read value of all bits on port B")); Write ( Message, STRING'(" is unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); elsif (WRITE_WIDTH_B = 18) then for i in 0 to 1 loop if (web_dly(i) = '0') then dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); dopb_buf(i downto i) := di_x(i downto i); end if; end loop; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,")); Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s).")); Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and")); Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); elsif (WRITE_WIDTH_B = 36) then for i in 0 to 3 loop if (web_dly(i) = '0') then dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); dopb_buf(i downto i) := di_x(i downto i); end if; end loop; Write ( Message, STRING'(" Functional warning at simulation time ")); Write ( Message, STRING'("( ")); Write ( Message, now); Write ( Message, STRING'(") : ")); Write ( Message, STRING'("ARAMB36_INTERNAL ")); Write ( Message, STRING'("( ")); Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); Write ( Message, STRING'(") ")); Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,")); Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s).")); Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and")); Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. ")); Write ( Message, LF ); ASSERT FALSE REPORT Message.ALL SEVERITY warning; DEALLOCATE (Message); end if; end if; end if; dob_out <= dob_buf; dopb_out <= dopb_buf; end if; end if; viol_time := 0; viol_type := "00"; col_wr_wr_msg := '1'; col_wra_rdb_msg := '1'; col_wrb_rda_msg := '1'; dbiterr_out <= dbiterr_out_var; sbiterr_out <= sbiterr_out_var; end if; end if; end process prcs_clk; outreg_clka: process (regclka_dly, gsr_dly) variable FIRST_TIME : boolean := true; begin -- process outreg_clka if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then if (DOA_REG = 1) then if (gsr_dly = '1' or FIRST_TIME) then dbiterr_outreg <= '0'; sbiterr_outreg <= '0'; doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); if (ra_width >= 8) then dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); end if; FIRST_TIME := false; elsif (gsr_dly = '0') then dbiterr_outreg <= dbiterr_out; sbiterr_outreg <= sbiterr_out; if (regcea_dly = '1') then if (ssra_dly = '1') then doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); if (ra_width >= 8) then dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); end if; elsif (ssra_dly = '0') then doa_outreg <= doa_out; dopa_outreg <= dopa_out; end if; end if; end if; end if; end if; end process outreg_clka; cascade_a_mux: process (clka_dly, cascadeinlata_dly, addra_dly_15_reg, doa_out, dopa_out) begin -- process cascade_a_mux if (rising_edge(clka_dly) or cascadeinlata_dly'event or addra_dly_15_reg'event or doa_out'event or dopa_out'event) then if (cascade_a(1) = '1' and addra_dly_15_reg = '1') then doa_out_mux(0) <= cascadeinlata_dly; else doa_out_mux <= doa_out; dopa_out_mux <= dopa_out; end if; end if; end process cascade_a_mux; cascade_a_muxreg: process (regclka_dly, cascadeinrega_dly, addra_dly_15_reg1, doa_outreg, dopa_outreg) begin -- process cascade_a_muxreg if (rising_edge(regclka_dly) or cascadeinrega_dly'event or addra_dly_15_reg1'event or doa_outreg'event or dopa_outreg'event) then if (cascade_a(1) = '1' and addra_dly_15_reg1 = '1') then doa_outreg_mux(0) <= cascadeinrega_dly; else doa_outreg_mux <= doa_outreg; dopa_outreg_mux <= dopa_outreg; end if; end if; end process cascade_a_muxreg; outmux_clka: process (doa_out_mux, dopa_out_mux, doa_outreg_mux, dopa_outreg_mux, dbiterr_out, dbiterr_outreg, sbiterr_out, sbiterr_outreg) begin -- process outmux_clka case DOA_REG is when 0 => dbiterr_out_out <= dbiterr_out; sbiterr_out_out <= sbiterr_out; doa_out_out <= doa_out_mux; dopa_out_out <= dopa_out_mux; when 1 => dbiterr_out_out <= dbiterr_outreg; sbiterr_out_out <= sbiterr_outreg; doa_out_out <= doa_outreg_mux; dopa_out_out <= dopa_outreg_mux; when others => assert false report "Attribute Syntax Error: The allowed integer values for DOA_REG are 0 or 1." severity Failure; end case; end process outmux_clka; outreg_clkb: process (regclkb_dly, gsr_dly) variable FIRST_TIME : boolean := true; begin -- process outreg_clkb if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then if (DOB_REG = 1) then if (gsr_dly = '1' or FIRST_TIME) then dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); if (rb_width >= 8) then dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); end if; FIRST_TIME := false; elsif (gsr_dly = '0') then if (regceb_dly = '1') then if (ssrb_dly = '1') then dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); if (rb_width >= 8) then dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); end if; elsif (ssrb_dly = '0') then dob_outreg <= dob_out; dopb_outreg <= dopb_out; end if; end if; end if; end if; end if; end process outreg_clkb; cascade_b_mux: process (clkb_dly, cascadeinlatb_dly, addrb_dly_15_reg, dob_out, dopb_out) begin -- process cascade_b_mux if (rising_edge(clkb_dly) or cascadeinlatb_dly'event or addrb_dly_15_reg'event or dob_out'event or dopb_out'event) then if (cascade_b(1) = '1' and addrb_dly_15_reg = '1') then dob_out_mux(0) <= cascadeinlatb_dly; else dob_out_mux <= dob_out; dopb_out_mux <= dopb_out; end if; end if; end process cascade_b_mux; cascade_b_muxreg: process (regclkb_dly, cascadeinregb_dly, addrb_dly_15_reg1, dob_outreg, dopb_outreg) begin -- process cascade_b_muxreg if (rising_edge(regclkb_dly) or cascadeinregb_dly'event or addrb_dly_15_reg1'event or dob_outreg'event or dopb_outreg'event) then if (cascade_b(1) = '1' and addrb_dly_15_reg1 = '1') then dob_outreg_mux(0) <= cascadeinregb_dly; else dob_outreg_mux <= dob_outreg; dopb_outreg_mux <= dopb_outreg; end if; end if; end process cascade_b_muxreg; outmux_clkb: process (dob_out_mux, dopb_out_mux, dob_outreg_mux, dopb_outreg_mux) begin -- process outmux_clkb case DOB_REG is when 0 => dob_out_out <= dob_out_mux; dopb_out_out <= dopb_out_mux; when 1 => dob_out_out <= dob_outreg_mux; dopb_out_out <= dopb_outreg_mux; when others => assert false report "Attribute Syntax Error: The allowed integer values for DOB_REG are 0 or 1." severity Failure; end case; end process outmux_clkb; prcs_output: process (doa_out_out, dopa_out_out, dob_out_out, dopb_out_out, eccparity_out, dbiterr_out_out, sbiterr_out_out, doa_out_mux(0), dob_out_mux(0), doa_outreg_mux(0), dob_outreg_mux(0)) begin -- process prcs_output DOA <= doa_out_out; DOPA <= dopa_out_out; DOB <= dob_out_out; DOPB <= dopb_out_out; ECCPARITY <= eccparity_out; DBITERR <= dbiterr_out_out; SBITERR <= sbiterr_out_out; CASCADEOUTLATA <= doa_out_mux(0); CASCADEOUTLATB <= dob_out_mux(0); CASCADEOUTREGA <= doa_outreg_mux(0); CASCADEOUTREGB <= dob_outreg_mux(0); end process prcs_output; end ARAMB36_INTERNAL_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library STD; use STD.TEXTIO.all; library unisim; use unisim.vpkg.all; entity RAMB16 is generic ( DOA_REG : integer := 0 ; DOB_REG : integer := 0 ; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"000000000"; INIT_B : bit_vector := X"000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INVERT_CLK_DOA_REG : boolean := false; INVERT_CLK_DOB_REG : boolean := false; RAM_EXTENSION_A : string := "NONE"; RAM_EXTENSION_B : string := "NONE"; READ_WIDTH_A : integer := 0; READ_WIDTH_B : integer := 0; SIM_COLLISION_CHECK : string := "ALL"; SRVAL_A : bit_vector := X"000000000"; SRVAL_B : bit_vector := X"000000000"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; WRITE_WIDTH_A : integer := 0; WRITE_WIDTH_B : integer := 0 ); port( CASCADEOUTA : out std_ulogic; CASCADEOUTB : out std_ulogic; DOA : out std_logic_vector (31 downto 0); DOB : out std_logic_vector (31 downto 0); DOPA : out std_logic_vector (3 downto 0); DOPB : out std_logic_vector (3 downto 0); ADDRA : in std_logic_vector (14 downto 0); ADDRB : in std_logic_vector (14 downto 0); CASCADEINA : in std_ulogic; CASCADEINB : in std_ulogic; CLKA : in std_ulogic; CLKB : in std_ulogic; DIA : in std_logic_vector (31 downto 0); DIB : in std_logic_vector (31 downto 0); DIPA : in std_logic_vector (3 downto 0); DIPB : in std_logic_vector (3 downto 0); ENA : in std_ulogic; ENB : in std_ulogic; REGCEA : in std_ulogic; REGCEB : in std_ulogic; SSRA : in std_ulogic; SSRB : in std_ulogic; WEA : in std_logic_vector (3 downto 0); WEB : in std_logic_vector (3 downto 0) ); end RAMB16; architecture RAMB16_V of RAMB16 is component ARAMB36_INTERNAL generic ( BRAM_MODE : string := "TRUE_DUAL_PORT"; BRAM_SIZE : integer := 36; DOA_REG : integer := 0; DOB_REG : integer := 0; INIT_A : bit_vector := X"000000000000000000"; INIT_B : bit_vector := X"000000000000000000"; RAM_EXTENSION_A : string := "NONE"; RAM_EXTENSION_B : string := "NONE"; READ_WIDTH_A : integer := 0; READ_WIDTH_B : integer := 0; SIM_COLLISION_CHECK : string := "ALL"; SRVAL_A : bit_vector := X"000000000000000000"; SRVAL_B : bit_vector := X"000000000000000000"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; WRITE_WIDTH_A : integer := 0; WRITE_WIDTH_B : integer := 0; EN_ECC_READ : boolean := FALSE; EN_ECC_SCRUB : boolean := FALSE; EN_ECC_WRITE : boolean := FALSE; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port ( CASCADEOUTLATA : out std_ulogic; CASCADEOUTLATB : out std_ulogic; CASCADEOUTREGA : out std_ulogic; CASCADEOUTREGB : out std_ulogic; DBITERR : out std_ulogic; DOA : out std_logic_vector(63 downto 0); DOB : out std_logic_vector(63 downto 0); DOPA : out std_logic_vector(7 downto 0); DOPB : out std_logic_vector(7 downto 0); ECCPARITY : out std_logic_vector(7 downto 0); SBITERR : out std_ulogic; ADDRA : in std_logic_vector(15 downto 0); ADDRB : in std_logic_vector(15 downto 0); CASCADEINLATA : in std_ulogic; CASCADEINLATB : in std_ulogic; CASCADEINREGA : in std_ulogic; CASCADEINREGB : in std_ulogic; CLKA : in std_ulogic; CLKB : in std_ulogic; DIA : in std_logic_vector(63 downto 0); DIB : in std_logic_vector(63 downto 0); DIPA : in std_logic_vector(7 downto 0); DIPB : in std_logic_vector(7 downto 0); ENA : in std_ulogic; ENB : in std_ulogic; REGCEA : in std_ulogic; REGCEB : in std_ulogic; REGCLKA : in std_ulogic; REGCLKB : in std_ulogic; SSRA : in std_ulogic; SSRB : in std_ulogic; WEA : in std_logic_vector(7 downto 0); WEB : in std_logic_vector(7 downto 0) ); end component; constant SYNC_PATH_DELAY : time := 100 ps; signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); signal OPEN_4 : std_logic_vector(3 downto 0); signal OPEN_32 : std_logic_vector(31 downto 0); signal doa_dly : std_logic_vector(31 downto 0) := (others => '0'); signal dob_dly : std_logic_vector(31 downto 0) := (others => '0'); signal dopa_dly : std_logic_vector(3 downto 0) := (others => '0'); signal dopb_dly : std_logic_vector(3 downto 0) := (others => '0'); signal cascadeouta_dly : std_ulogic := '0'; signal cascadeoutb_dly : std_ulogic := '0'; signal addra_int : std_logic_vector(15 downto 0) := (others => '0'); signal addrb_int : std_logic_vector(15 downto 0) := (others => '0'); signal wea_int : std_logic_vector(7 downto 0) := (others => '0'); signal web_int : std_logic_vector(7 downto 0) := (others => '0'); signal clka_wire : std_ulogic := '0'; signal clkb_wire : std_ulogic := '0'; signal clka_tmp : std_ulogic := '0'; signal clkb_tmp : std_ulogic := '0'; begin prcs_clk: process (CLKA, CLKB) variable FIRST_TIME : boolean := true; begin if (FIRST_TIME) then if((INVERT_CLK_DOA_REG = true) and (DOA_REG /= 1 )) then assert false report "Attribute Syntax Error: When INVERT_CLK_DOA_REG is set to TRUE, then DOA_REG has to be set to 1." severity Failure; end if; if((INVERT_CLK_DOB_REG = true) and (DOB_REG /= 1 )) then assert false report "Attribute Syntax Error: When INVERT_CLK_DOB_REG is set to TRUE, then DOB_REG has to be set to 1." severity Failure; end if; if((INVERT_CLK_DOA_REG /= TRUE) and (INVERT_CLK_DOA_REG /= FALSE)) then assert false report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOA_REG are TRUE or FALSE" severity Failure; end if; if((INVERT_CLK_DOB_REG /= TRUE) and (INVERT_CLK_DOB_REG /= FALSE)) then assert false report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOB_REG are TRUE or FALSE" severity Failure; end if; FIRST_TIME := false; end if; if (CLKA'event) then if (DOA_REG = 1 and INVERT_CLK_DOA_REG = TRUE) then clka_wire <= not CLKA; else clka_wire <= CLKA; end if; clka_tmp <= CLKA; end if; if (CLKB'event) then if (DOB_REG = 1 and INVERT_CLK_DOB_REG = TRUE) then clkb_wire <= not CLKB; else clkb_wire <= CLKB; end if; clkb_tmp <= CLKB; end if; end process prcs_clk; addra_int <= ADDRA(14) & '0' & ADDRA(13 downto 0); addrb_int <= ADDRB(14) & '0' & ADDRB(13 downto 0); wea_int <= WEA & WEA; web_int <= WEB & WEB; RAMB16_inst : ARAMB36_INTERNAL generic map ( DOA_REG => DOA_REG, DOB_REG => DOB_REG, INIT_A => INIT_A, INIT_B => INIT_B, INIT_00 => INIT_00, INIT_01 => INIT_01, INIT_02 => INIT_02, INIT_03 => INIT_03, INIT_04 => INIT_04, INIT_05 => INIT_05, INIT_06 => INIT_06, INIT_07 => INIT_07, INIT_08 => INIT_08, INIT_09 => INIT_09, INIT_0A => INIT_0A, INIT_0B => INIT_0B, INIT_0C => INIT_0C, INIT_0D => INIT_0D, INIT_0E => INIT_0E, INIT_0F => INIT_0F, INIT_10 => INIT_10, INIT_11 => INIT_11, INIT_12 => INIT_12, INIT_13 => INIT_13, INIT_14 => INIT_14, INIT_15 => INIT_15, INIT_16 => INIT_16, INIT_17 => INIT_17, INIT_18 => INIT_18, INIT_19 => INIT_19, INIT_1A => INIT_1A, INIT_1B => INIT_1B, INIT_1C => INIT_1C, INIT_1D => INIT_1D, INIT_1E => INIT_1E, INIT_1F => INIT_1F, INIT_20 => INIT_20, INIT_21 => INIT_21, INIT_22 => INIT_22, INIT_23 => INIT_23, INIT_24 => INIT_24, INIT_25 => INIT_25, INIT_26 => INIT_26, INIT_27 => INIT_27, INIT_28 => INIT_28, INIT_29 => INIT_29, INIT_2A => INIT_2A, INIT_2B => INIT_2B, INIT_2C => INIT_2C, INIT_2D => INIT_2D, INIT_2E => INIT_2E, INIT_2F => INIT_2F, INIT_30 => INIT_30, INIT_31 => INIT_31, INIT_32 => INIT_32, INIT_33 => INIT_33, INIT_34 => INIT_34, INIT_35 => INIT_35, INIT_36 => INIT_36, INIT_37 => INIT_37, INIT_38 => INIT_38, INIT_39 => INIT_39, INIT_3A => INIT_3A, INIT_3B => INIT_3B, INIT_3C => INIT_3C, INIT_3D => INIT_3D, INIT_3E => INIT_3E, INIT_3F => INIT_3F, INITP_00 => INITP_00, INITP_01 => INITP_01, INITP_02 => INITP_02, INITP_03 => INITP_03, INITP_04 => INITP_04, INITP_05 => INITP_05, INITP_06 => INITP_06, INITP_07 => INITP_07, SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, SRVAL_A => SRVAL_A, SRVAL_B => SRVAL_B, WRITE_MODE_A => WRITE_MODE_A, WRITE_MODE_B => WRITE_MODE_B, BRAM_MODE => "TRUE_DUAL_PORT", BRAM_SIZE => 16, RAM_EXTENSION_A => RAM_EXTENSION_A, RAM_EXTENSION_B => RAM_EXTENSION_B, READ_WIDTH_A => READ_WIDTH_A, READ_WIDTH_B => READ_WIDTH_B, WRITE_WIDTH_A => WRITE_WIDTH_A, WRITE_WIDTH_B => WRITE_WIDTH_B ) port map ( ADDRA => addra_int, ADDRB => addrb_int, CLKA => clka_tmp, CLKB => clkb_tmp, DIA(31 downto 0) => DIA, DIA(63 downto 32) => GND_32, DIB(31 downto 0) => DIB, DIB(63 downto 32) => GND_32, DIPA(3 downto 0) => DIPA, DIPA(7 downto 4) => GND_4, DIPB(3 downto 0) => DIPB, DIPB(7 downto 4) => GND_4, ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB, WEA => wea_int, WEB => web_int, DOA(31 downto 0) => doa_dly, DOA(63 downto 32) => OPEN_32, DOB(31 downto 0) => dob_dly, DOB(63 downto 32) => OPEN_32, DOPA(3 downto 0) => dopa_dly, DOPA(7 downto 4) => OPEN_4, DOPB(3 downto 0) => dopb_dly, DOPB(7 downto 4) => OPEN_4, CASCADEOUTLATA => cascadeouta_dly, CASCADEOUTLATB => cascadeoutb_dly, CASCADEOUTREGA => open, CASCADEOUTREGB => open, CASCADEINLATA => CASCADEINA, CASCADEINLATB => CASCADEINB, CASCADEINREGA => CASCADEINA, CASCADEINREGB => CASCADEINB, REGCLKA => clka_wire, REGCLKB => clkb_wire, REGCEA => REGCEA, REGCEB => REGCEB ); prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeouta_dly, cascadeoutb_dly) begin -- process prcs_output_wtiming CASCADEOUTA <= cascadeouta_dly after SYNC_PATH_DELAY; CASCADEOUTB <= cascadeoutb_dly after SYNC_PATH_DELAY; DOA <= doa_dly after SYNC_PATH_DELAY; DOPA <= dopa_dly after SYNC_PATH_DELAY; DOB <= dob_dly after SYNC_PATH_DELAY; DOPB <= dopb_dly after SYNC_PATH_DELAY; end process prcs_output_wtiming; end RAMB16_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity RAM64X1D is generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000" ); port ( DPO : out std_ulogic; SPO : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic; D : in std_ulogic; DPRA0 : in std_ulogic; DPRA1 : in std_ulogic; DPRA2 : in std_ulogic; DPRA3 : in std_ulogic; DPRA4 : in std_ulogic; DPRA5 : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic ); end RAM64X1D; architecture RAM64X1D_V of RAM64X1D is signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); begin VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM) variable Index_SP : integer := 64; variable Index_DP : integer := 64; variable Raddress : std_logic_vector (5 downto 0); variable Waddress : std_logic_vector (5 downto 0); begin Waddress := (A5, A4, A3, A2, A1, A0); Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0); Index_SP := SLV_TO_INT(SLV => Waddress); Index_DP := SLV_TO_INT(SLV => Raddress); SPO <= MEM(Index_SP); DPO <= MEM(Index_DP); end process VITALReadBehavior; VITALWriteBehavior : process(WCLK) variable Index_SP : integer := 32; variable Index_DP : integer := 32; variable Address : std_logic_vector( 5 downto 0); begin Address := (A5, A4, A3, A2, A1, A0); Index_SP := SLV_TO_INT(SLV => Address ); if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then MEM(Index_SP) <= D after 100 ps; end if; end process VITALWriteBehavior; end RAM64X1D_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUXF8 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end MUXF8; architecture MUXF8_V of MUXF8 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; elsif (S = '1') then O <= I1; end if; end process; end MUXF8_V; library IEEE; use IEEE.STD_LOGIC_1164.all; entity BUF is port( O : out std_ulogic; I : in std_ulogic ); end BUF; architecture BUF_V of BUF is begin O <= TO_X01(I); end BUF_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT5 is generic( INIT : bit_vector := X"00000000" ); port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic; I4 : in std_ulogic ); end LUT5; architecture LUT5_V of LUT5 is function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) return std_logic is variable lut6_mux8_o : std_logic; function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_f : std_logic; begin if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then lut4_mux4_f := df(SLV_TO_INT(sf)); elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' and (df(0) xor df(2)) = '0') then lut4_mux4_f := df(0); elsif ((sf(1) = '0') and (df(0) = df(1))) then lut4_mux4_f := df(0); elsif ((sf(1) = '1') and (df(2) = df(3))) then lut4_mux4_f := df(2); elsif ((sf(0) = '0') and (df(0) = df(2))) then lut4_mux4_f := df(0); elsif ((sf(0) = '1') and (df(1) = df(3))) then lut4_mux4_f := df(1); else lut4_mux4_f := 'X'; end if; return (lut4_mux4_f); end function lut4_mux4f; begin if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then lut6_mux8_o := d(SLV_TO_INT(s)); else lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); end if; return (lut6_mux8_o); end function lut6_mux8; function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' and (d(0) xor d(2)) = '0') then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3, I4) variable I_reg : std_logic_vector(4 downto 0); begin I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then O <= INIT_reg(SLV_TO_INT(I_reg)); else O <= lut4_mux4 ( (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), I_reg(4 downto 3)); end if; end process; end LUT5_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT5_L is generic( INIT : bit_vector := X"00000000" ); port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic; I4 : in std_ulogic ); end LUT5_L; architecture LUT5_L_V of LUT5_L is function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) return std_logic is variable lut6_mux8_o : std_logic; function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_f : std_logic; begin if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then lut4_mux4_f := df(SLV_TO_INT(sf)); elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' and (df(0) xor df(2)) = '0') then lut4_mux4_f := df(0); elsif ((sf(1) = '0') and (df(0) = df(1))) then lut4_mux4_f := df(0); elsif ((sf(1) = '1') and (df(2) = df(3))) then lut4_mux4_f := df(2); elsif ((sf(0) = '0') and (df(0) = df(2))) then lut4_mux4_f := df(0); elsif ((sf(0) = '1') and (df(1) = df(3))) then lut4_mux4_f := df(1); else lut4_mux4_f := 'X'; end if; return (lut4_mux4_f); end function lut4_mux4f; begin if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then lut6_mux8_o := d(SLV_TO_INT(s)); else lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); end if; return (lut6_mux8_o); end function lut6_mux8; function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_o : std_logic; begin if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then lut4_mux4_o := d(SLV_TO_INT(s)); elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' and (d(0) xor d(2)) = '0') then lut4_mux4_o := d(0); elsif ((s(1) = '0') and (d(0) = d(1))) then lut4_mux4_o := d(0); elsif ((s(1) = '1') and (d(2) = d(3))) then lut4_mux4_o := d(2); elsif ((s(0) = '0') and (d(0) = d(2))) then lut4_mux4_o := d(0); elsif ((s(0) = '1') and (d(1) = d(3))) then lut4_mux4_o := d(1); else lut4_mux4_o := 'X'; end if; return (lut4_mux4_o); end function lut4_mux4; constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3, I4) variable INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); variable I_reg : std_logic_vector(4 downto 0); begin I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then LO <= INIT_reg(SLV_TO_INT(I_reg)); else LO <= lut4_mux4 ( (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), I_reg(4 downto 3)); end if; end process; end LUT5_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT6 is generic( INIT : bit_vector := X"0000000000000000" ); port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic; I4 : in std_ulogic; I5 : in std_ulogic ); end LUT6; architecture LUT6_V of LUT6 is function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) ) return std_logic is variable lut6_mux8_o : std_logic; function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_f : std_logic; begin if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then lut4_mux4_f := df(SLV_TO_INT(sf)); elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' and (df(0) xor df(2)) = '0') then lut4_mux4_f := df(0); elsif ((sf(1) = '0') and (df(0) = df(1))) then lut4_mux4_f := df(0); elsif ((sf(1) = '1') and (df(2) = df(3))) then lut4_mux4_f := df(2); elsif ((sf(0) = '0') and (df(0) = df(2))) then lut4_mux4_f := df(0); elsif ((sf(0) = '1') and (df(1) = df(3))) then lut4_mux4_f := df(1); else lut4_mux4_f := 'X'; end if; return (lut4_mux4_f); end function lut4_mux4f; begin if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then lut6_mux8_o := d(SLV_TO_INT(s)); else lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); end if; return (lut6_mux8_o); end function lut6_mux8; constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3, I4, I5) variable I_reg : std_logic_vector(5 downto 0); begin I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0); if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then O <= INIT_reg(SLV_TO_INT(I_reg)); else O <= lut6_mux8 ( (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), I_reg(5 downto 3)); end if; end process; end LUT6_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VPKG.all; use unisim.VCOMPONENTS.all; entity LUT6_L is generic( INIT : bit_vector := X"0000000000000000" ); port( LO : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; I2 : in std_ulogic; I3 : in std_ulogic; I4 : in std_ulogic; I5 : in std_ulogic ); end LUT6_L; architecture LUT6_L_V of LUT6_L is function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) ) return std_logic is variable lut6_mux8_o : std_logic; function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) return std_logic is variable lut4_mux4_f : std_logic; begin if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then lut4_mux4_f := df(SLV_TO_INT(sf)); elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' and (df(0) xor df(2)) = '0') then lut4_mux4_f := df(0); elsif ((sf(1) = '0') and (df(0) = df(1))) then lut4_mux4_f := df(0); elsif ((sf(1) = '1') and (df(2) = df(3))) then lut4_mux4_f := df(2); elsif ((sf(0) = '0') and (df(0) = df(2))) then lut4_mux4_f := df(0); elsif ((sf(0) = '1') and (df(1) = df(3))) then lut4_mux4_f := df(1); else lut4_mux4_f := 'X'; end if; return (lut4_mux4_f); end function lut4_mux4f; begin if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then lut6_mux8_o := d(SLV_TO_INT(s)); else lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); end if; return (lut6_mux8_o); end function lut6_mux8; constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); begin lut_p : process (I0, I1, I2, I3, I4, I5) variable I_reg : std_logic_vector(5 downto 0); begin I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0); if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then LO <= INIT_reg(SLV_TO_INT(I_reg)); else LO <= lut6_mux8 ( (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), I_reg(5 downto 3)); end if; end process; end LUT6_L_V; library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.VPKG.all; entity RAM128X1S is generic ( INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" ); port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic; A6 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic ); end RAM128X1S; architecture RAM128X1S_V of RAM128X1S is signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); begin VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, A6, MEM) Variable Index : integer := 128; variable Address : std_logic_vector( 6 downto 0); begin Address := (A6, A5, A4, A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Address); O <= MEM(Index); end process VITALReadBehavior; VITALWriteBehavior : process(WCLK) Variable Index : integer := 128; variable Address : std_logic_vector (6 downto 0); begin if (rising_edge(WCLK)) then if (WE = '1') then Address := (A6, A5, A4, A3, A2, A1, A0); Index := SLV_TO_INT(SLV => Address); MEM(Index) <= D after 100 ps; end if; end if; end process VITALWriteBehavior; end RAM128X1S_V; -- pragma translate_on

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/ZPUino_Papilio_Pro_V1.vhd

13

45307

-- -- -- ZPUINO implementation on Gadget Factory 'Papilio Pro' Board -- -- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com> -- -- Vanilla Variant -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.zpuino_config.all; use board.wishbonepkg.all; library work; use work.pad.all; use work.papilio_pkg.all; entity ZPUino_Papilio_Pro_V1 is port ( --32Mhz input clock is converted to a 96Mhz clock CLK: in std_logic; --Clock outputs to be used in schematic clk_96Mhz: out std_logic; --This is the clock that the system runs on. clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip. clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator. -- Connection to the main SPI flash SPI_SCK: out std_logic; SPI_MISO: in std_logic; SPI_MOSI: out std_logic; SPI_CS: out std_logic; gpio_bus_in : in std_logic_vector(97 downto 0); gpio_bus_out : out std_logic_vector(147 downto 0); -- UART (FTDI) connection TXD: out std_logic; RXD: in std_logic; DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC; -- The LED LED: out std_logic; --There are more bits in the address for this wishbone connection wishbone_slot_video_in : in std_logic_vector(63 downto 0); wishbone_slot_video_out : out std_logic_vector(33 downto 0); vgaclkout: out std_logic; --Input and output reversed for the master wishbone_slot_5_in : out std_logic_vector(61 downto 0); wishbone_slot_5_out : in std_logic_vector(33 downto 0); wishbone_slot_6_in : out std_logic_vector(61 downto 0); wishbone_slot_6_out : in std_logic_vector(33 downto 0); wishbone_slot_8_in : out std_logic_vector(61 downto 0); wishbone_slot_8_out : in std_logic_vector(33 downto 0); wishbone_slot_9_in : out std_logic_vector(61 downto 0); wishbone_slot_9_out : in std_logic_vector(33 downto 0); wishbone_slot_10_in : out std_logic_vector(61 downto 0); wishbone_slot_10_out : in std_logic_vector(33 downto 0); wishbone_slot_11_in : out std_logic_vector(61 downto 0); wishbone_slot_11_out : in std_logic_vector(33 downto 0); wishbone_slot_12_in : out std_logic_vector(61 downto 0); wishbone_slot_12_out : in std_logic_vector(33 downto 0); wishbone_slot_13_in : out std_logic_vector(61 downto 0); wishbone_slot_13_out : in std_logic_vector(33 downto 0); wishbone_slot_14_in : out std_logic_vector(61 downto 0); wishbone_slot_14_out : in std_logic_vector(33 downto 0) -- wishbone_slot_15_in : out std_logic_vector(61 downto 0); -- wishbone_slot_15_out : in std_logic_vector(33 downto 0) ); -- attribute PERIOD: string; -- attribute PERIOD of CLK: signal is "31.25ns"; -- -- attribute LOC: string; -- attribute LOC of CLK: signal is "P94"; -- attribute LOC of RXD: signal is "P101"; -- attribute LOC of TXD: signal is "P105"; -- attribute LOC of SPI_CS: signal is "P38"; -- attribute LOC of SPI_SCK: signal is "P70"; -- attribute LOC of SPI_MISO: signal is "P65"; -- attribute LOC of SPI_MOSI: signal is "P64"; -- attribute LOC of DRAM_ADDR: signal is "P34 P35 P141 P40 P41 P43 P44 P45 P46 P137 P138 P139 P140"; -- attribute LOC of DRAM_DQ: signal is "P30 P29 P27 P26 P24 P23 P22 P21 P8 P16 P15 P14 P12 P11 P10 P9"; -- attribute LOC of DRAM_DQM: signal is "P17 P7"; -- attribute LOC of DRAM_BA: signal is "P142 P143"; -- attribute LOC of DRAM_WE_N: signal is "P6"; -- attribute LOC of DRAM_CAS_N: signal is "P5"; -- attribute LOC of DRAM_RAS_N: signal is "P2"; -- attribute LOC of DRAM_CS_N: signal is "P1"; -- attribute LOC of DRAM_CLK: signal is "P32"; -- attribute LOC of DRAM_CKE: signal is "P33"; -- -- attribute SLEW: string; -- attribute SLEW of DRAM_ADDR: signal is "FAST"; -- attribute SLEW of DRAM_DQ: signal is "FAST"; -- attribute SLEW of DRAM_DQM: signal is "FAST"; -- attribute SLEW of DRAM_BA: signal is "FAST"; -- attribute SLEW of DRAM_WE_N: signal is "FAST"; -- attribute SLEW of DRAM_CAS_N: signal is "FAST"; -- attribute SLEW of DRAM_RAS_N: signal is "FAST"; -- attribute SLEW of DRAM_CS_N: signal is "FAST"; -- attribute SLEW of DRAM_CLK: signal is "FAST"; -- attribute SLEW of DRAM_CKE: signal is "FAST"; end entity ZPUino_Papilio_Pro_V1; architecture behave of ZPUino_Papilio_Pro_V1 is component zpuino_debug_jtag_spartan6 is port ( jtag_data_chain_in: in std_logic_vector(98 downto 0); jtag_ctrl_chain_out: out std_logic_vector(11 downto 0) ); end component; signal jtag_data_chain_in: std_logic_vector(98 downto 0); signal jtag_ctrl_chain_out: std_logic_vector(11 downto 0); component clkgen is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout1: out std_logic; clkout2: out std_logic; clk_1Mhz_out: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end component; component wb_bootloader is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(11 downto 2); wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_stall_o: out std_logic; wb2_dat_o: out std_logic_vector(31 downto 0); wb2_adr_i: in std_logic_vector(11 downto 2); wb2_cyc_i: in std_logic; wb2_stb_i: in std_logic; wb2_ack_o: out std_logic; wb2_stall_o: out std_logic ); end component; signal sysrst: std_logic; signal sysclk: std_logic; signal clkgen_rst: std_logic; signal wb_clk_i: std_logic; signal wb_rst_i: std_logic; -- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0); signal gpio_o_reg: std_logic_vector(48 downto 0); constant spp_cap_in: std_logic_vector(48 downto 0) := "0" & -- SPI CS "0000000000000000" & -- Wing C "0000000000000000" & -- Wing B "0000000000000000"; -- Wing A constant spp_cap_out: std_logic_vector(48 downto 0) := "0" & -- SPI CS "0000000000000000" & -- Wing C "0000000000000000" & -- Wing B "0000000000000000"; -- Wing A -- constant spp_cap_in: std_logic_vector(48 downto 0) := -- "0" & -- SPI CS -- "1111111111111111" & -- Wing C -- "1111111111111111" & -- Wing B -- "1111111111111111"; -- Wing A -- -- constant spp_cap_out: std_logic_vector(48 downto 0) := -- "0" & -- SPI CS -- "1111111111111111" & -- Wing C -- "1111111111111111" & -- Wing B -- "1111111111111111"; -- Wing A -- I/O Signals signal slot_cyc: slot_std_logic_type; signal slot_we: slot_std_logic_type; signal slot_stb: slot_std_logic_type; signal slot_read: slot_cpuword_type; signal slot_write: slot_cpuword_type; signal slot_address:slot_address_type; signal slot_ack: slot_std_logic_type; signal slot_interrupt: slot_std_logic_type; -- 2nd SPI signals signal spi2_mosi: std_logic; signal spi2_miso: std_logic; signal spi2_sck: std_logic; -- GPIO Periperal Pin Select -- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0); -- Timer connections signal timers_interrupt: std_logic_vector(1 downto 0); signal timers_pwm: std_logic_vector(1 downto 0); -- Sigmadelta output signal sigmadelta_spp_data: std_logic_vector(1 downto 0); -- main SPI signals signal spi_pf_miso: std_logic; signal spi_pf_mosi: std_logic; signal spi_pf_sck: std_logic; -- UART signals signal rx: std_logic; signal tx: std_logic; signal sysclk_sram_we, sysclk_sram_wen: std_ulogic; signal ram_wb_ack_o: std_logic; signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal ram_wb_cyc_i: std_logic; signal ram_wb_stb_i: std_logic; signal ram_wb_sel_i: std_logic_vector(3 downto 0); signal ram_wb_we_i: std_logic; signal ram_wb_stall_o: std_logic; signal np_ram_wb_ack_o: std_logic; signal np_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal np_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal np_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal np_ram_wb_cyc_i: std_logic; signal np_ram_wb_stb_i: std_logic; signal np_ram_wb_sel_i: std_logic_vector(3 downto 0); signal np_ram_wb_we_i: std_logic; signal sram_wb_ack_o: std_logic; signal sram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal sram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal sram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal sram_wb_cyc_i: std_logic; signal sram_wb_stb_i: std_logic; signal sram_wb_we_i: std_logic; signal sram_wb_sel_i: std_logic_vector(3 downto 0); signal sram_wb_stall_o: std_logic; signal rom_wb_ack_o: std_logic; signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal rom_wb_cyc_i: std_logic; signal rom_wb_stb_i: std_logic; signal rom_wb_cti_i: std_logic_vector(2 downto 0); signal rom_wb_stall_o: std_logic; signal sram_rom_wb_ack_o: std_logic; signal sram_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal sram_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2); signal sram_rom_wb_cyc_i: std_logic; signal sram_rom_wb_stb_i: std_logic; signal sram_rom_wb_cti_i: std_logic_vector(2 downto 0); signal sram_rom_wb_stall_o: std_logic; signal prom_rom_wb_ack_o: std_logic; signal prom_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal prom_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2); signal prom_rom_wb_cyc_i: std_logic; signal prom_rom_wb_stb_i: std_logic; signal prom_rom_wb_cti_i: std_logic_vector(2 downto 0); signal prom_rom_wb_stall_o: std_logic; signal memory_enable: std_logic; component sdram_ctrl is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_dat_i: in std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit); wb_we_i: in std_logic; wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_sel_i: in std_logic_vector(3 downto 0); wb_ack_o: out std_logic; wb_stall_o: out std_logic; -- extra clocking clk_off_3ns: in std_logic; -- SDRAM signals DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC ); end component sdram_ctrl; component wb_master_np_to_slave_p is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master signals m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave signals s_wb_dat_i: in std_logic_vector(31 downto 0); s_wb_dat_o: out std_logic_vector(31 downto 0); s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s_wb_sel_o: out std_logic_vector(3 downto 0); s_wb_cti_o: out std_logic_vector(2 downto 0); s_wb_we_o: out std_logic; s_wb_cyc_o: out std_logic; s_wb_stb_o: out std_logic; s_wb_ack_i: in std_logic; s_wb_stall_i: in std_logic ); end component; signal sigmadelta_spp_en: std_logic_vector(1 downto 0); signal sysclk_1mhz: std_logic; signal wishbone_slot_video_in_record : wishbone_bus_in_type; signal wishbone_slot_video_out_record : wishbone_bus_out_type; signal wishbone_slot_5_in_record : wishbone_bus_in_type; signal wishbone_slot_5_out_record : wishbone_bus_out_type; signal wishbone_slot_6_in_record : wishbone_bus_in_type; signal wishbone_slot_6_out_record : wishbone_bus_out_type; signal wishbone_slot_8_in_record : wishbone_bus_in_type; signal wishbone_slot_8_out_record : wishbone_bus_out_type; signal wishbone_slot_9_in_record : wishbone_bus_in_type; signal wishbone_slot_9_out_record : wishbone_bus_out_type; signal wishbone_slot_10_in_record : wishbone_bus_in_type; signal wishbone_slot_10_out_record : wishbone_bus_out_type; signal wishbone_slot_11_in_record : wishbone_bus_in_type; signal wishbone_slot_11_out_record : wishbone_bus_out_type; signal wishbone_slot_12_in_record : wishbone_bus_in_type; signal wishbone_slot_12_out_record : wishbone_bus_out_type; signal wishbone_slot_13_in_record : wishbone_bus_in_type; signal wishbone_slot_13_out_record : wishbone_bus_out_type; signal wishbone_slot_14_in_record : wishbone_bus_in_type; signal wishbone_slot_14_out_record : wishbone_bus_out_type; -- signal wishbone_slot_15_in_record : wishbone_bus_in_type; -- signal wishbone_slot_15_out_record : wishbone_bus_out_type; signal gpio_bus_in_record : gpio_bus_in_type; signal gpio_bus_out_record : gpio_bus_out_type; -- Papilio Note: Place your signal statements here. #Signal begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- These are backwards for the master. -- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61); -- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60); -- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28); -- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3); -- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2); -- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1); -- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0); -- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o; -- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o; -- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o; wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i; wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i; wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i; wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i; wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i; wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i; wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i; wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2); wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1); wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0); wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i; wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i; wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i; wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i; wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i; wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i; wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i; wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2); wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1); wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0); wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i; wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i; wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i; wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i; wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i; wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i; wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i; wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2); wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1); wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0); wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i; wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i; wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i; wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i; wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i; wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i; wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i; wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2); wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1); wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0); wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i; wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i; wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i; wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i; wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i; wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i; wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i; wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2); wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1); wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0); wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i; wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i; wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i; wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i; wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i; wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i; wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i; wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2); wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1); wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0); wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i; wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i; wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i; wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i; wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i; wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i; wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i; wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2); wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1); wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0); wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i; wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i; wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i; wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i; wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i; wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i; wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i; wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2); wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1); wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0); wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i; wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i; wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i; wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i; wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i; wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i; wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i; wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2); wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1); wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0); gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49); gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0); gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk; gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o; gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t; gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read; gpio_bus_out_record.gpio_o <= gpio_o_reg; gpio_bus_out_record.gpio_clk <= sysclk; LED <= '0'; wb_clk_i <= sysclk; wb_rst_i <= sysrst; --Wishbone 5 wishbone_slot_5_in_record.wb_clk_i <= sysclk; wishbone_slot_5_in_record.wb_rst_i <= sysrst; slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o; wishbone_slot_5_in_record.wb_dat_i <= slot_write(5); wishbone_slot_5_in_record.wb_adr_i <= slot_address(5); wishbone_slot_5_in_record.wb_we_i <= slot_we(5); wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5); wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5); slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o; slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o; --Wishbone 6 wishbone_slot_6_in_record.wb_clk_i <= sysclk; wishbone_slot_6_in_record.wb_rst_i <= sysrst; slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o; wishbone_slot_6_in_record.wb_dat_i <= slot_write(6); wishbone_slot_6_in_record.wb_adr_i <= slot_address(6); wishbone_slot_6_in_record.wb_we_i <= slot_we(6); wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6); wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6); slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o; slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o; --Wishbone 8 wishbone_slot_8_in_record.wb_clk_i <= sysclk; wishbone_slot_8_in_record.wb_rst_i <= sysrst; slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o; wishbone_slot_8_in_record.wb_dat_i <= slot_write(8); wishbone_slot_8_in_record.wb_adr_i <= slot_address(8); wishbone_slot_8_in_record.wb_we_i <= slot_we(8); wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8); wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8); slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o; slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o; --Wishbone 9 wishbone_slot_9_in_record.wb_clk_i <= sysclk; wishbone_slot_9_in_record.wb_rst_i <= sysrst; slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o; wishbone_slot_9_in_record.wb_dat_i <= slot_write(9); wishbone_slot_9_in_record.wb_adr_i <= slot_address(9); wishbone_slot_9_in_record.wb_we_i <= slot_we(9); wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9); wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9); slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o; slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o; --Wishbone 10 wishbone_slot_10_in_record.wb_clk_i <= sysclk; wishbone_slot_10_in_record.wb_rst_i <= sysrst; slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o; wishbone_slot_10_in_record.wb_dat_i <= slot_write(10); wishbone_slot_10_in_record.wb_adr_i <= slot_address(10); wishbone_slot_10_in_record.wb_we_i <= slot_we(10); wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10); wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10); slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o; slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o; --Wishbone 11 wishbone_slot_11_in_record.wb_clk_i <= sysclk; wishbone_slot_11_in_record.wb_rst_i <= sysrst; slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o; wishbone_slot_11_in_record.wb_dat_i <= slot_write(11); wishbone_slot_11_in_record.wb_adr_i <= slot_address(11); wishbone_slot_11_in_record.wb_we_i <= slot_we(11); wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11); wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11); slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o; slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o; --Wishbone 12 wishbone_slot_12_in_record.wb_clk_i <= sysclk; wishbone_slot_12_in_record.wb_rst_i <= sysrst; slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o; wishbone_slot_12_in_record.wb_dat_i <= slot_write(12); wishbone_slot_12_in_record.wb_adr_i <= slot_address(12); wishbone_slot_12_in_record.wb_we_i <= slot_we(12); wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12); wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12); slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o; slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o; --Wishbone 13 wishbone_slot_13_in_record.wb_clk_i <= sysclk; wishbone_slot_13_in_record.wb_rst_i <= sysrst; slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o; wishbone_slot_13_in_record.wb_dat_i <= slot_write(13); wishbone_slot_13_in_record.wb_adr_i <= slot_address(13); wishbone_slot_13_in_record.wb_we_i <= slot_we(13); wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13); wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13); slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o; slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o; --Wishbone 14 wishbone_slot_14_in_record.wb_clk_i <= sysclk; wishbone_slot_14_in_record.wb_rst_i <= sysrst; slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o; wishbone_slot_14_in_record.wb_dat_i <= slot_write(14); wishbone_slot_14_in_record.wb_adr_i <= slot_address(14); wishbone_slot_14_in_record.wb_we_i <= slot_we(14); wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14); wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14); slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o; slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o; rstgen: zpuino_serialreset generic map ( SYSTEM_CLOCK_MHZ => 96 ) port map ( clk => sysclk, rx => rx, rstin => clkgen_rst, rstout => sysrst ); clkgen_inst: clkgen port map ( clkin => clk, rstin => '0' , clkout => sysclk, clkout1 => sysclk_sram_we, clkout2 => sysclk_sram_wen, clk_1Mhz_out => clk_1Mhz, clk_osc_32Mhz => clk_osc_32Mhz, vgaclkout => vgaclkout, rstout => clkgen_rst ); clk_96Mhz <= sysclk; -- Other ports are special, we need to avoid outputs on input-only pins ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk ); ibufmiso: IPAD port map ( PAD => SPI_MISO, O => spi_pf_miso, C => sysclk ); obuftx: OPAD port map ( I => tx, PAD => TXD ); ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_SCK ); ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_CS ); ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_MOSI ); --oled: OPAD port map ( I => gpio_o_reg(49), PAD => LED ); zpuino:zpuino_top_icache port map ( clk => sysclk, rst => sysrst, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt, m_wb_dat_o => open, m_wb_dat_i => (others => 'X'), m_wb_adr_i => (others => 'X'), m_wb_we_i => '0', m_wb_cyc_i => '0', m_wb_stb_i => '0', m_wb_ack_o => open, memory_enable => memory_enable, ram_wb_ack_i => np_ram_wb_ack_o, ram_wb_stall_i => '0',--np_ram_wb_stall_o, ram_wb_dat_o => np_ram_wb_dat_i, ram_wb_dat_i => np_ram_wb_dat_o, ram_wb_adr_o => np_ram_wb_adr_i(maxAddrBit downto 0), ram_wb_cyc_o => np_ram_wb_cyc_i, ram_wb_stb_o => np_ram_wb_stb_i, ram_wb_sel_o => np_ram_wb_sel_i, ram_wb_we_o => np_ram_wb_we_i, rom_wb_ack_i => rom_wb_ack_o, rom_wb_stall_i => rom_wb_stall_o, rom_wb_dat_i => rom_wb_dat_o, rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_i, rom_wb_stb_o => rom_wb_stb_i, -- No debug unit connected dbg_reset => open, jtag_data_chain_out => open, --jtag_data_chain_in, jtag_ctrl_chain_in => (others => '0') --jtag_ctrl_chain_out ); --dbg: zpuino_debug_jtag_spartan6 -- port map ( -- jtag_data_chain_in => jtag_data_chain_in, -- jtag_ctrl_chain_out => jtag_ctrl_chain_out -- ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBit, ADDRESS_LOW => 2 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, m0_wb_dat_o => ram_wb_dat_o, m0_wb_dat_i => ram_wb_dat_i, m0_wb_adr_i => ram_wb_adr_i(maxAddrBit downto 2), m0_wb_sel_i => ram_wb_sel_i, m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => ram_wb_we_i, m0_wb_cyc_i => ram_wb_cyc_i, m0_wb_stb_i => ram_wb_stb_i, m0_wb_ack_o => ram_wb_ack_o, m0_wb_stall_o => ram_wb_stall_o, m1_wb_dat_o => sram_rom_wb_dat_o, m1_wb_dat_i => (others => DontCareValue), m1_wb_adr_i => sram_rom_wb_adr_i(maxAddrBit downto 2), m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => '0',--rom_wb_we_i, m1_wb_cyc_i => sram_rom_wb_cyc_i, m1_wb_stb_i => sram_rom_wb_stb_i, m1_wb_ack_o => sram_rom_wb_ack_o, m1_wb_stall_o => sram_rom_wb_stall_o, s0_wb_dat_i => sram_wb_dat_o, s0_wb_dat_o => sram_wb_dat_i, s0_wb_adr_o => sram_wb_adr_i(maxAddrBit downto 2), s0_wb_sel_o => sram_wb_sel_i, s0_wb_cti_o => open, s0_wb_we_o => sram_wb_we_i, s0_wb_cyc_o => sram_wb_cyc_i, s0_wb_stb_o => sram_wb_stb_i, s0_wb_ack_i => sram_wb_ack_o, s0_wb_stall_i => sram_wb_stall_o ); bootmux: wbbootloadermux generic map ( address_high => maxAddrBit ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, sel => memory_enable, -- Master m_wb_dat_o => rom_wb_dat_o, m_wb_dat_i => (others => DontCareValue), m_wb_adr_i => rom_wb_adr_i(maxAddrBit downto 2), m_wb_sel_i => (others => '1'), m_wb_cti_i => CTI_CYCLE_CLASSIC, m_wb_we_i => '0', m_wb_cyc_i => rom_wb_cyc_i, m_wb_stb_i => rom_wb_stb_i, m_wb_ack_o => rom_wb_ack_o, m_wb_stall_o => rom_wb_stall_o, -- Slave 0 signals s0_wb_dat_i => sram_rom_wb_dat_o, s0_wb_dat_o => open, s0_wb_adr_o => sram_rom_wb_adr_i, s0_wb_sel_o => open, s0_wb_cti_o => open, s0_wb_we_o => open, s0_wb_cyc_o => sram_rom_wb_cyc_i, s0_wb_stb_o => sram_rom_wb_stb_i, s0_wb_ack_i => sram_rom_wb_ack_o, s0_wb_stall_i => sram_rom_wb_stall_o, -- Slave 1 signals s1_wb_dat_i => prom_rom_wb_dat_o, s1_wb_dat_o => open, s1_wb_adr_o => prom_rom_wb_adr_i(11 downto 2), s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => open, s1_wb_cyc_o => prom_rom_wb_cyc_i, s1_wb_stb_o => prom_rom_wb_stb_i, s1_wb_ack_i => prom_rom_wb_ack_o, s1_wb_stall_i => prom_rom_wb_stall_o ); npnadapt: wb_master_np_to_slave_p generic map ( ADDRESS_HIGH => maxAddrBitIncIO, ADDRESS_LOW => 0 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, -- Master signals m_wb_dat_o => np_ram_wb_dat_o, m_wb_dat_i => np_ram_wb_dat_i, m_wb_adr_i => np_ram_wb_adr_i, m_wb_sel_i => np_ram_wb_sel_i, m_wb_cti_i => CTI_CYCLE_CLASSIC, m_wb_we_i => np_ram_wb_we_i, m_wb_cyc_i => np_ram_wb_cyc_i, m_wb_stb_i => np_ram_wb_stb_i, m_wb_ack_o => np_ram_wb_ack_o, -- Slave signals s_wb_dat_i => ram_wb_dat_o, s_wb_dat_o => ram_wb_dat_i, s_wb_adr_o => ram_wb_adr_i, s_wb_sel_o => ram_wb_sel_i, s_wb_cti_o => open, s_wb_we_o => ram_wb_we_i, s_wb_cyc_o => ram_wb_cyc_i, s_wb_stb_o => ram_wb_stb_i, s_wb_ack_i => ram_wb_ack_o, s_wb_stall_i => ram_wb_stall_o ); -- PROM prom: wb_bootloader port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => prom_rom_wb_dat_o, wb_adr_i => prom_rom_wb_adr_i(11 downto 2), wb_cyc_i => prom_rom_wb_cyc_i, wb_stb_i => prom_rom_wb_stb_i, wb_ack_o => prom_rom_wb_ack_o, wb_stall_o => prom_rom_wb_stall_o, wb2_dat_o => slot_read(15), wb2_adr_i => slot_address(15)(11 downto 2), wb2_cyc_i => slot_cyc(15), wb2_stb_i => slot_stb(15), wb2_ack_o => slot_ack(15), wb2_stall_o => open ); -- -- IO SLOT 0 -- slot0: zpuino_spi port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(0), wb_dat_i => slot_write(0), wb_adr_i => slot_address(0), wb_we_i => slot_we(0), wb_cyc_i => slot_cyc(0), wb_stb_i => slot_stb(0), wb_ack_o => slot_ack(0), wb_inta_o => slot_interrupt(0), mosi => spi_pf_mosi, miso => spi_pf_miso, sck => spi_pf_sck, enabled => open ); -- -- IO SLOT 1 -- uart_inst: zpuino_uart port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(1), wb_dat_i => slot_write(1), wb_adr_i => slot_address(1), wb_we_i => slot_we(1), wb_cyc_i => slot_cyc(1), wb_stb_i => slot_stb(1), wb_ack_o => slot_ack(1), wb_inta_o => slot_interrupt(1), enabled => open, tx => tx, rx => rx ); -- -- IO SLOT 2 -- gpio_inst: zpuino_gpio generic map ( gpio_count => 49 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(2), wb_dat_i => slot_write(2), wb_adr_i => slot_address(2), wb_we_i => slot_we(2), wb_cyc_i => slot_cyc(2), wb_stb_i => slot_stb(2), wb_ack_o => slot_ack(2), wb_inta_o => slot_interrupt(2), spp_data => gpio_bus_in_record.gpio_spp_data, spp_read => gpio_bus_out_record.gpio_spp_read, gpio_i => gpio_bus_in_record.gpio_i, gpio_t => gpio_bus_out_record.gpio_t, gpio_o => gpio_o_reg, spp_cap_in => spp_cap_in, spp_cap_out => spp_cap_out ); -- -- IO SLOT 3 -- timers_inst: zpuino_timers generic map ( A_TSCENABLED => true, A_PWMCOUNT => 1, A_WIDTH => 16, A_PRESCALER_ENABLED => true, A_BUFFERS => true, B_TSCENABLED => false, B_PWMCOUNT => 1, B_WIDTH => 8,--24, B_PRESCALER_ENABLED => false, B_BUFFERS => false ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(3), wb_dat_i => slot_write(3), wb_adr_i => slot_address(3), wb_we_i => slot_we(3), wb_cyc_i => slot_cyc(3), wb_stb_i => slot_stb(3), wb_ack_o => slot_ack(3), wb_inta_o => slot_interrupt(3), -- We use two interrupt lines wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4 pwm_a_out => timers_pwm(0 downto 0), pwm_b_out => timers_pwm(1 downto 1) ); -- -- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller) -- -- -- IO SLOT 5 -- -- sigmadelta_inst: zpuino_sigmadelta -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(5), -- wb_dat_i => slot_write(5), -- wb_adr_i => slot_address(5), -- wb_we_i => slot_we(5), -- wb_cyc_i => slot_cyc(5), -- wb_stb_i => slot_stb(5), -- wb_ack_o => slot_ack(5), -- wb_inta_o => slot_interrupt(5), -- spp_data => sigmadelta_spp_data, -- spp_en => open, -- sync_in => '1' -- ); -- -- IO SLOT 6 -- -- slot1: zpuino_spi -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(6), -- wb_dat_i => slot_write(6), -- wb_adr_i => slot_address(6), -- wb_we_i => slot_we(6), -- wb_cyc_i => slot_cyc(6), -- wb_stb_i => slot_stb(6), -- wb_ack_o => slot_ack(6), -- wb_inta_o => slot_interrupt(6), -- -- mosi => spi2_mosi, -- miso => spi2_miso, -- sck => spi2_sck, -- enabled => open -- ); -- -- IO SLOT 7 -- crc16_inst: zpuino_crc16 port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(7), wb_dat_i => slot_write(7), wb_adr_i => slot_address(7), wb_we_i => slot_we(7), wb_cyc_i => slot_cyc(7), wb_stb_i => slot_stb(7), wb_ack_o => slot_ack(7), wb_inta_o => slot_interrupt(7) ); sram_inst: sdram_ctrl port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => sram_wb_dat_o, wb_dat_i => sram_wb_dat_i, wb_adr_i => sram_wb_adr_i(maxIObit downto minIObit), wb_we_i => sram_wb_we_i, wb_cyc_i => sram_wb_cyc_i, wb_stb_i => sram_wb_stb_i, wb_sel_i => sram_wb_sel_i, --wb_cti_i => CTI_CYCLE_CLASSIC, wb_ack_o => sram_wb_ack_o, wb_stall_o => sram_wb_stall_o, clk_off_3ns => sysclk_sram_we, DRAM_ADDR => DRAM_ADDR(11 downto 0), DRAM_BA => DRAM_BA, DRAM_CAS_N => DRAM_CAS_N, DRAM_CKE => DRAM_CKE, DRAM_CLK => DRAM_CLK, DRAM_CS_N => DRAM_CS_N, DRAM_DQ => DRAM_DQ, DRAM_DQM => DRAM_DQM, DRAM_RAS_N => DRAM_RAS_N, DRAM_WE_N => DRAM_WE_N ); DRAM_ADDR(12) <= '0'; -- Papilio Note: Place your Wishbone components here. #Wishbone -- Look at the ZPUino User Guide for what Wishbone components are available: -- http://www.papilio.cc/index.php?n=Papilio.ZPUinoUserGuide#Reference -- -- IO SLOT 8 -- -- slot8: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(8), -- wb_dat_i => slot_write(8), -- wb_adr_i => slot_address(8), -- wb_we_i => slot_we(8), -- wb_cyc_i => slot_cyc(8), -- wb_stb_i => slot_stb(8), -- wb_ack_o => slot_ack(8), -- wb_inta_o => slot_interrupt(8) -- ); -- -- IO SLOT 9 -- -- slot9: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(9), -- wb_dat_i => slot_write(9), -- wb_adr_i => slot_address(9), -- wb_we_i => slot_we(9), -- wb_cyc_i => slot_cyc(9), -- wb_stb_i => slot_stb(9), -- wb_ack_o => slot_ack(9), -- wb_inta_o => slot_interrupt(9) -- ); -- -- IO SLOT 10 -- -- slot10: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(10), -- wb_dat_i => slot_write(10), -- wb_adr_i => slot_address(10), -- wb_we_i => slot_we(10), -- wb_cyc_i => slot_cyc(10), -- wb_stb_i => slot_stb(10), -- wb_ack_o => slot_ack(10), -- wb_inta_o => slot_interrupt(10) -- ); -- -- IO SLOT 11 -- -- slot11: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(11), -- wb_dat_i => slot_write(11), -- wb_adr_i => slot_address(11), -- wb_we_i => slot_we(11), -- wb_cyc_i => slot_cyc(11), -- wb_stb_i => slot_stb(11), -- wb_ack_o => slot_ack(11), -- wb_inta_o => slot_interrupt(11) -- ); -- -- IO SLOT 12 -- -- slot12: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(12), -- wb_dat_i => slot_write(12), -- wb_adr_i => slot_address(12), -- wb_we_i => slot_we(12), -- wb_cyc_i => slot_cyc(12), -- wb_stb_i => slot_stb(12), -- wb_ack_o => slot_ack(12), -- wb_inta_o => slot_interrupt(12) -- ); -- -- IO SLOT 13 -- -- slot13: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(13), -- wb_dat_i => slot_write(13), -- wb_adr_i => slot_address(13), -- wb_we_i => slot_we(13), -- wb_cyc_i => slot_cyc(13), -- wb_stb_i => slot_stb(13), -- wb_ack_o => slot_ack(13), -- wb_inta_o => slot_interrupt(13) -- ); -- -- IO SLOT 14 -- -- slot14: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(14), -- wb_dat_i => slot_write(14), -- wb_adr_i => slot_address(14), -- wb_we_i => slot_we(14), -- wb_cyc_i => slot_cyc(14), -- wb_stb_i => slot_stb(14), -- wb_ack_o => slot_ack(14), -- wb_inta_o => slot_interrupt(14) -- ); -- -- IO SLOT 15 - do not use -- -- process(gpio_spp_read, spi_pf_mosi, spi_pf_sck, -- sigmadelta_spp_data,timers_pwm, -- spi2_mosi,spi2_sck) -- begin -- gpio_spp_data <= (others => DontCareValue); -- -- PPS Outputs -- gpio_spp_data(0) <= sigmadelta_spp_data(0); -- PPS0 : SIGMADELTA DATA -- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0 -- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1 -- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI -- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK -- gpio_spp_data(5) <= sigmadelta_spp_data(1); -- PPS5 : SIGMADELTA1 DATA -- -- PPS inputs -- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO -- end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/ZPUino_Papilio_Pro_V1.vhd

13

45307

-- -- -- ZPUINO implementation on Gadget Factory 'Papilio Pro' Board -- -- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com> -- -- Vanilla Variant -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.zpuino_config.all; use board.wishbonepkg.all; library work; use work.pad.all; use work.papilio_pkg.all; entity ZPUino_Papilio_Pro_V1 is port ( --32Mhz input clock is converted to a 96Mhz clock CLK: in std_logic; --Clock outputs to be used in schematic clk_96Mhz: out std_logic; --This is the clock that the system runs on. clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip. clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator. -- Connection to the main SPI flash SPI_SCK: out std_logic; SPI_MISO: in std_logic; SPI_MOSI: out std_logic; SPI_CS: out std_logic; gpio_bus_in : in std_logic_vector(97 downto 0); gpio_bus_out : out std_logic_vector(147 downto 0); -- UART (FTDI) connection TXD: out std_logic; RXD: in std_logic; DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC; -- The LED LED: out std_logic; --There are more bits in the address for this wishbone connection wishbone_slot_video_in : in std_logic_vector(63 downto 0); wishbone_slot_video_out : out std_logic_vector(33 downto 0); vgaclkout: out std_logic; --Input and output reversed for the master wishbone_slot_5_in : out std_logic_vector(61 downto 0); wishbone_slot_5_out : in std_logic_vector(33 downto 0); wishbone_slot_6_in : out std_logic_vector(61 downto 0); wishbone_slot_6_out : in std_logic_vector(33 downto 0); wishbone_slot_8_in : out std_logic_vector(61 downto 0); wishbone_slot_8_out : in std_logic_vector(33 downto 0); wishbone_slot_9_in : out std_logic_vector(61 downto 0); wishbone_slot_9_out : in std_logic_vector(33 downto 0); wishbone_slot_10_in : out std_logic_vector(61 downto 0); wishbone_slot_10_out : in std_logic_vector(33 downto 0); wishbone_slot_11_in : out std_logic_vector(61 downto 0); wishbone_slot_11_out : in std_logic_vector(33 downto 0); wishbone_slot_12_in : out std_logic_vector(61 downto 0); wishbone_slot_12_out : in std_logic_vector(33 downto 0); wishbone_slot_13_in : out std_logic_vector(61 downto 0); wishbone_slot_13_out : in std_logic_vector(33 downto 0); wishbone_slot_14_in : out std_logic_vector(61 downto 0); wishbone_slot_14_out : in std_logic_vector(33 downto 0) -- wishbone_slot_15_in : out std_logic_vector(61 downto 0); -- wishbone_slot_15_out : in std_logic_vector(33 downto 0) ); -- attribute PERIOD: string; -- attribute PERIOD of CLK: signal is "31.25ns"; -- -- attribute LOC: string; -- attribute LOC of CLK: signal is "P94"; -- attribute LOC of RXD: signal is "P101"; -- attribute LOC of TXD: signal is "P105"; -- attribute LOC of SPI_CS: signal is "P38"; -- attribute LOC of SPI_SCK: signal is "P70"; -- attribute LOC of SPI_MISO: signal is "P65"; -- attribute LOC of SPI_MOSI: signal is "P64"; -- attribute LOC of DRAM_ADDR: signal is "P34 P35 P141 P40 P41 P43 P44 P45 P46 P137 P138 P139 P140"; -- attribute LOC of DRAM_DQ: signal is "P30 P29 P27 P26 P24 P23 P22 P21 P8 P16 P15 P14 P12 P11 P10 P9"; -- attribute LOC of DRAM_DQM: signal is "P17 P7"; -- attribute LOC of DRAM_BA: signal is "P142 P143"; -- attribute LOC of DRAM_WE_N: signal is "P6"; -- attribute LOC of DRAM_CAS_N: signal is "P5"; -- attribute LOC of DRAM_RAS_N: signal is "P2"; -- attribute LOC of DRAM_CS_N: signal is "P1"; -- attribute LOC of DRAM_CLK: signal is "P32"; -- attribute LOC of DRAM_CKE: signal is "P33"; -- -- attribute SLEW: string; -- attribute SLEW of DRAM_ADDR: signal is "FAST"; -- attribute SLEW of DRAM_DQ: signal is "FAST"; -- attribute SLEW of DRAM_DQM: signal is "FAST"; -- attribute SLEW of DRAM_BA: signal is "FAST"; -- attribute SLEW of DRAM_WE_N: signal is "FAST"; -- attribute SLEW of DRAM_CAS_N: signal is "FAST"; -- attribute SLEW of DRAM_RAS_N: signal is "FAST"; -- attribute SLEW of DRAM_CS_N: signal is "FAST"; -- attribute SLEW of DRAM_CLK: signal is "FAST"; -- attribute SLEW of DRAM_CKE: signal is "FAST"; end entity ZPUino_Papilio_Pro_V1; architecture behave of ZPUino_Papilio_Pro_V1 is component zpuino_debug_jtag_spartan6 is port ( jtag_data_chain_in: in std_logic_vector(98 downto 0); jtag_ctrl_chain_out: out std_logic_vector(11 downto 0) ); end component; signal jtag_data_chain_in: std_logic_vector(98 downto 0); signal jtag_ctrl_chain_out: std_logic_vector(11 downto 0); component clkgen is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout1: out std_logic; clkout2: out std_logic; clk_1Mhz_out: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end component; component wb_bootloader is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(11 downto 2); wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_stall_o: out std_logic; wb2_dat_o: out std_logic_vector(31 downto 0); wb2_adr_i: in std_logic_vector(11 downto 2); wb2_cyc_i: in std_logic; wb2_stb_i: in std_logic; wb2_ack_o: out std_logic; wb2_stall_o: out std_logic ); end component; signal sysrst: std_logic; signal sysclk: std_logic; signal clkgen_rst: std_logic; signal wb_clk_i: std_logic; signal wb_rst_i: std_logic; -- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0); signal gpio_o_reg: std_logic_vector(48 downto 0); constant spp_cap_in: std_logic_vector(48 downto 0) := "0" & -- SPI CS "0000000000000000" & -- Wing C "0000000000000000" & -- Wing B "0000000000000000"; -- Wing A constant spp_cap_out: std_logic_vector(48 downto 0) := "0" & -- SPI CS "0000000000000000" & -- Wing C "0000000000000000" & -- Wing B "0000000000000000"; -- Wing A -- constant spp_cap_in: std_logic_vector(48 downto 0) := -- "0" & -- SPI CS -- "1111111111111111" & -- Wing C -- "1111111111111111" & -- Wing B -- "1111111111111111"; -- Wing A -- -- constant spp_cap_out: std_logic_vector(48 downto 0) := -- "0" & -- SPI CS -- "1111111111111111" & -- Wing C -- "1111111111111111" & -- Wing B -- "1111111111111111"; -- Wing A -- I/O Signals signal slot_cyc: slot_std_logic_type; signal slot_we: slot_std_logic_type; signal slot_stb: slot_std_logic_type; signal slot_read: slot_cpuword_type; signal slot_write: slot_cpuword_type; signal slot_address:slot_address_type; signal slot_ack: slot_std_logic_type; signal slot_interrupt: slot_std_logic_type; -- 2nd SPI signals signal spi2_mosi: std_logic; signal spi2_miso: std_logic; signal spi2_sck: std_logic; -- GPIO Periperal Pin Select -- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0); -- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0); -- Timer connections signal timers_interrupt: std_logic_vector(1 downto 0); signal timers_pwm: std_logic_vector(1 downto 0); -- Sigmadelta output signal sigmadelta_spp_data: std_logic_vector(1 downto 0); -- main SPI signals signal spi_pf_miso: std_logic; signal spi_pf_mosi: std_logic; signal spi_pf_sck: std_logic; -- UART signals signal rx: std_logic; signal tx: std_logic; signal sysclk_sram_we, sysclk_sram_wen: std_ulogic; signal ram_wb_ack_o: std_logic; signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal ram_wb_cyc_i: std_logic; signal ram_wb_stb_i: std_logic; signal ram_wb_sel_i: std_logic_vector(3 downto 0); signal ram_wb_we_i: std_logic; signal ram_wb_stall_o: std_logic; signal np_ram_wb_ack_o: std_logic; signal np_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal np_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal np_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal np_ram_wb_cyc_i: std_logic; signal np_ram_wb_stb_i: std_logic; signal np_ram_wb_sel_i: std_logic_vector(3 downto 0); signal np_ram_wb_we_i: std_logic; signal sram_wb_ack_o: std_logic; signal sram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal sram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal sram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal sram_wb_cyc_i: std_logic; signal sram_wb_stb_i: std_logic; signal sram_wb_we_i: std_logic; signal sram_wb_sel_i: std_logic_vector(3 downto 0); signal sram_wb_stall_o: std_logic; signal rom_wb_ack_o: std_logic; signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal rom_wb_cyc_i: std_logic; signal rom_wb_stb_i: std_logic; signal rom_wb_cti_i: std_logic_vector(2 downto 0); signal rom_wb_stall_o: std_logic; signal sram_rom_wb_ack_o: std_logic; signal sram_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal sram_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2); signal sram_rom_wb_cyc_i: std_logic; signal sram_rom_wb_stb_i: std_logic; signal sram_rom_wb_cti_i: std_logic_vector(2 downto 0); signal sram_rom_wb_stall_o: std_logic; signal prom_rom_wb_ack_o: std_logic; signal prom_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal prom_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2); signal prom_rom_wb_cyc_i: std_logic; signal prom_rom_wb_stb_i: std_logic; signal prom_rom_wb_cti_i: std_logic_vector(2 downto 0); signal prom_rom_wb_stall_o: std_logic; signal memory_enable: std_logic; component sdram_ctrl is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_dat_i: in std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit); wb_we_i: in std_logic; wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_sel_i: in std_logic_vector(3 downto 0); wb_ack_o: out std_logic; wb_stall_o: out std_logic; -- extra clocking clk_off_3ns: in std_logic; -- SDRAM signals DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC ); end component sdram_ctrl; component wb_master_np_to_slave_p is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master signals m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave signals s_wb_dat_i: in std_logic_vector(31 downto 0); s_wb_dat_o: out std_logic_vector(31 downto 0); s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s_wb_sel_o: out std_logic_vector(3 downto 0); s_wb_cti_o: out std_logic_vector(2 downto 0); s_wb_we_o: out std_logic; s_wb_cyc_o: out std_logic; s_wb_stb_o: out std_logic; s_wb_ack_i: in std_logic; s_wb_stall_i: in std_logic ); end component; signal sigmadelta_spp_en: std_logic_vector(1 downto 0); signal sysclk_1mhz: std_logic; signal wishbone_slot_video_in_record : wishbone_bus_in_type; signal wishbone_slot_video_out_record : wishbone_bus_out_type; signal wishbone_slot_5_in_record : wishbone_bus_in_type; signal wishbone_slot_5_out_record : wishbone_bus_out_type; signal wishbone_slot_6_in_record : wishbone_bus_in_type; signal wishbone_slot_6_out_record : wishbone_bus_out_type; signal wishbone_slot_8_in_record : wishbone_bus_in_type; signal wishbone_slot_8_out_record : wishbone_bus_out_type; signal wishbone_slot_9_in_record : wishbone_bus_in_type; signal wishbone_slot_9_out_record : wishbone_bus_out_type; signal wishbone_slot_10_in_record : wishbone_bus_in_type; signal wishbone_slot_10_out_record : wishbone_bus_out_type; signal wishbone_slot_11_in_record : wishbone_bus_in_type; signal wishbone_slot_11_out_record : wishbone_bus_out_type; signal wishbone_slot_12_in_record : wishbone_bus_in_type; signal wishbone_slot_12_out_record : wishbone_bus_out_type; signal wishbone_slot_13_in_record : wishbone_bus_in_type; signal wishbone_slot_13_out_record : wishbone_bus_out_type; signal wishbone_slot_14_in_record : wishbone_bus_in_type; signal wishbone_slot_14_out_record : wishbone_bus_out_type; -- signal wishbone_slot_15_in_record : wishbone_bus_in_type; -- signal wishbone_slot_15_out_record : wishbone_bus_out_type; signal gpio_bus_in_record : gpio_bus_in_type; signal gpio_bus_out_record : gpio_bus_out_type; -- Papilio Note: Place your signal statements here. #Signal begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- These are backwards for the master. -- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61); -- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60); -- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28); -- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3); -- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2); -- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1); -- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0); -- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o; -- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o; -- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o; wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i; wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i; wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i; wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i; wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i; wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i; wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i; wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2); wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1); wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0); wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i; wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i; wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i; wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i; wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i; wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i; wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i; wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2); wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1); wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0); wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i; wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i; wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i; wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i; wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i; wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i; wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i; wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2); wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1); wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0); wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i; wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i; wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i; wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i; wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i; wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i; wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i; wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2); wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1); wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0); wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i; wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i; wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i; wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i; wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i; wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i; wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i; wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2); wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1); wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0); wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i; wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i; wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i; wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i; wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i; wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i; wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i; wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2); wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1); wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0); wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i; wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i; wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i; wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i; wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i; wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i; wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i; wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2); wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1); wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0); wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i; wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i; wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i; wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i; wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i; wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i; wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i; wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2); wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1); wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0); wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i; wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i; wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i; wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i; wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i; wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i; wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i; wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2); wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1); wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0); gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49); gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0); gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk; gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o; gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t; gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read; gpio_bus_out_record.gpio_o <= gpio_o_reg; gpio_bus_out_record.gpio_clk <= sysclk; LED <= '0'; wb_clk_i <= sysclk; wb_rst_i <= sysrst; --Wishbone 5 wishbone_slot_5_in_record.wb_clk_i <= sysclk; wishbone_slot_5_in_record.wb_rst_i <= sysrst; slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o; wishbone_slot_5_in_record.wb_dat_i <= slot_write(5); wishbone_slot_5_in_record.wb_adr_i <= slot_address(5); wishbone_slot_5_in_record.wb_we_i <= slot_we(5); wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5); wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5); slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o; slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o; --Wishbone 6 wishbone_slot_6_in_record.wb_clk_i <= sysclk; wishbone_slot_6_in_record.wb_rst_i <= sysrst; slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o; wishbone_slot_6_in_record.wb_dat_i <= slot_write(6); wishbone_slot_6_in_record.wb_adr_i <= slot_address(6); wishbone_slot_6_in_record.wb_we_i <= slot_we(6); wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6); wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6); slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o; slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o; --Wishbone 8 wishbone_slot_8_in_record.wb_clk_i <= sysclk; wishbone_slot_8_in_record.wb_rst_i <= sysrst; slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o; wishbone_slot_8_in_record.wb_dat_i <= slot_write(8); wishbone_slot_8_in_record.wb_adr_i <= slot_address(8); wishbone_slot_8_in_record.wb_we_i <= slot_we(8); wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8); wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8); slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o; slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o; --Wishbone 9 wishbone_slot_9_in_record.wb_clk_i <= sysclk; wishbone_slot_9_in_record.wb_rst_i <= sysrst; slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o; wishbone_slot_9_in_record.wb_dat_i <= slot_write(9); wishbone_slot_9_in_record.wb_adr_i <= slot_address(9); wishbone_slot_9_in_record.wb_we_i <= slot_we(9); wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9); wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9); slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o; slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o; --Wishbone 10 wishbone_slot_10_in_record.wb_clk_i <= sysclk; wishbone_slot_10_in_record.wb_rst_i <= sysrst; slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o; wishbone_slot_10_in_record.wb_dat_i <= slot_write(10); wishbone_slot_10_in_record.wb_adr_i <= slot_address(10); wishbone_slot_10_in_record.wb_we_i <= slot_we(10); wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10); wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10); slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o; slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o; --Wishbone 11 wishbone_slot_11_in_record.wb_clk_i <= sysclk; wishbone_slot_11_in_record.wb_rst_i <= sysrst; slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o; wishbone_slot_11_in_record.wb_dat_i <= slot_write(11); wishbone_slot_11_in_record.wb_adr_i <= slot_address(11); wishbone_slot_11_in_record.wb_we_i <= slot_we(11); wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11); wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11); slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o; slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o; --Wishbone 12 wishbone_slot_12_in_record.wb_clk_i <= sysclk; wishbone_slot_12_in_record.wb_rst_i <= sysrst; slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o; wishbone_slot_12_in_record.wb_dat_i <= slot_write(12); wishbone_slot_12_in_record.wb_adr_i <= slot_address(12); wishbone_slot_12_in_record.wb_we_i <= slot_we(12); wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12); wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12); slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o; slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o; --Wishbone 13 wishbone_slot_13_in_record.wb_clk_i <= sysclk; wishbone_slot_13_in_record.wb_rst_i <= sysrst; slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o; wishbone_slot_13_in_record.wb_dat_i <= slot_write(13); wishbone_slot_13_in_record.wb_adr_i <= slot_address(13); wishbone_slot_13_in_record.wb_we_i <= slot_we(13); wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13); wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13); slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o; slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o; --Wishbone 14 wishbone_slot_14_in_record.wb_clk_i <= sysclk; wishbone_slot_14_in_record.wb_rst_i <= sysrst; slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o; wishbone_slot_14_in_record.wb_dat_i <= slot_write(14); wishbone_slot_14_in_record.wb_adr_i <= slot_address(14); wishbone_slot_14_in_record.wb_we_i <= slot_we(14); wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14); wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14); slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o; slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o; rstgen: zpuino_serialreset generic map ( SYSTEM_CLOCK_MHZ => 96 ) port map ( clk => sysclk, rx => rx, rstin => clkgen_rst, rstout => sysrst ); clkgen_inst: clkgen port map ( clkin => clk, rstin => '0' , clkout => sysclk, clkout1 => sysclk_sram_we, clkout2 => sysclk_sram_wen, clk_1Mhz_out => clk_1Mhz, clk_osc_32Mhz => clk_osc_32Mhz, vgaclkout => vgaclkout, rstout => clkgen_rst ); clk_96Mhz <= sysclk; -- Other ports are special, we need to avoid outputs on input-only pins ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk ); ibufmiso: IPAD port map ( PAD => SPI_MISO, O => spi_pf_miso, C => sysclk ); obuftx: OPAD port map ( I => tx, PAD => TXD ); ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_SCK ); ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_CS ); ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_MOSI ); --oled: OPAD port map ( I => gpio_o_reg(49), PAD => LED ); zpuino:zpuino_top_icache port map ( clk => sysclk, rst => sysrst, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt, m_wb_dat_o => open, m_wb_dat_i => (others => 'X'), m_wb_adr_i => (others => 'X'), m_wb_we_i => '0', m_wb_cyc_i => '0', m_wb_stb_i => '0', m_wb_ack_o => open, memory_enable => memory_enable, ram_wb_ack_i => np_ram_wb_ack_o, ram_wb_stall_i => '0',--np_ram_wb_stall_o, ram_wb_dat_o => np_ram_wb_dat_i, ram_wb_dat_i => np_ram_wb_dat_o, ram_wb_adr_o => np_ram_wb_adr_i(maxAddrBit downto 0), ram_wb_cyc_o => np_ram_wb_cyc_i, ram_wb_stb_o => np_ram_wb_stb_i, ram_wb_sel_o => np_ram_wb_sel_i, ram_wb_we_o => np_ram_wb_we_i, rom_wb_ack_i => rom_wb_ack_o, rom_wb_stall_i => rom_wb_stall_o, rom_wb_dat_i => rom_wb_dat_o, rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_i, rom_wb_stb_o => rom_wb_stb_i, -- No debug unit connected dbg_reset => open, jtag_data_chain_out => open, --jtag_data_chain_in, jtag_ctrl_chain_in => (others => '0') --jtag_ctrl_chain_out ); --dbg: zpuino_debug_jtag_spartan6 -- port map ( -- jtag_data_chain_in => jtag_data_chain_in, -- jtag_ctrl_chain_out => jtag_ctrl_chain_out -- ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBit, ADDRESS_LOW => 2 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, m0_wb_dat_o => ram_wb_dat_o, m0_wb_dat_i => ram_wb_dat_i, m0_wb_adr_i => ram_wb_adr_i(maxAddrBit downto 2), m0_wb_sel_i => ram_wb_sel_i, m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => ram_wb_we_i, m0_wb_cyc_i => ram_wb_cyc_i, m0_wb_stb_i => ram_wb_stb_i, m0_wb_ack_o => ram_wb_ack_o, m0_wb_stall_o => ram_wb_stall_o, m1_wb_dat_o => sram_rom_wb_dat_o, m1_wb_dat_i => (others => DontCareValue), m1_wb_adr_i => sram_rom_wb_adr_i(maxAddrBit downto 2), m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => '0',--rom_wb_we_i, m1_wb_cyc_i => sram_rom_wb_cyc_i, m1_wb_stb_i => sram_rom_wb_stb_i, m1_wb_ack_o => sram_rom_wb_ack_o, m1_wb_stall_o => sram_rom_wb_stall_o, s0_wb_dat_i => sram_wb_dat_o, s0_wb_dat_o => sram_wb_dat_i, s0_wb_adr_o => sram_wb_adr_i(maxAddrBit downto 2), s0_wb_sel_o => sram_wb_sel_i, s0_wb_cti_o => open, s0_wb_we_o => sram_wb_we_i, s0_wb_cyc_o => sram_wb_cyc_i, s0_wb_stb_o => sram_wb_stb_i, s0_wb_ack_i => sram_wb_ack_o, s0_wb_stall_i => sram_wb_stall_o ); bootmux: wbbootloadermux generic map ( address_high => maxAddrBit ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, sel => memory_enable, -- Master m_wb_dat_o => rom_wb_dat_o, m_wb_dat_i => (others => DontCareValue), m_wb_adr_i => rom_wb_adr_i(maxAddrBit downto 2), m_wb_sel_i => (others => '1'), m_wb_cti_i => CTI_CYCLE_CLASSIC, m_wb_we_i => '0', m_wb_cyc_i => rom_wb_cyc_i, m_wb_stb_i => rom_wb_stb_i, m_wb_ack_o => rom_wb_ack_o, m_wb_stall_o => rom_wb_stall_o, -- Slave 0 signals s0_wb_dat_i => sram_rom_wb_dat_o, s0_wb_dat_o => open, s0_wb_adr_o => sram_rom_wb_adr_i, s0_wb_sel_o => open, s0_wb_cti_o => open, s0_wb_we_o => open, s0_wb_cyc_o => sram_rom_wb_cyc_i, s0_wb_stb_o => sram_rom_wb_stb_i, s0_wb_ack_i => sram_rom_wb_ack_o, s0_wb_stall_i => sram_rom_wb_stall_o, -- Slave 1 signals s1_wb_dat_i => prom_rom_wb_dat_o, s1_wb_dat_o => open, s1_wb_adr_o => prom_rom_wb_adr_i(11 downto 2), s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => open, s1_wb_cyc_o => prom_rom_wb_cyc_i, s1_wb_stb_o => prom_rom_wb_stb_i, s1_wb_ack_i => prom_rom_wb_ack_o, s1_wb_stall_i => prom_rom_wb_stall_o ); npnadapt: wb_master_np_to_slave_p generic map ( ADDRESS_HIGH => maxAddrBitIncIO, ADDRESS_LOW => 0 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, -- Master signals m_wb_dat_o => np_ram_wb_dat_o, m_wb_dat_i => np_ram_wb_dat_i, m_wb_adr_i => np_ram_wb_adr_i, m_wb_sel_i => np_ram_wb_sel_i, m_wb_cti_i => CTI_CYCLE_CLASSIC, m_wb_we_i => np_ram_wb_we_i, m_wb_cyc_i => np_ram_wb_cyc_i, m_wb_stb_i => np_ram_wb_stb_i, m_wb_ack_o => np_ram_wb_ack_o, -- Slave signals s_wb_dat_i => ram_wb_dat_o, s_wb_dat_o => ram_wb_dat_i, s_wb_adr_o => ram_wb_adr_i, s_wb_sel_o => ram_wb_sel_i, s_wb_cti_o => open, s_wb_we_o => ram_wb_we_i, s_wb_cyc_o => ram_wb_cyc_i, s_wb_stb_o => ram_wb_stb_i, s_wb_ack_i => ram_wb_ack_o, s_wb_stall_i => ram_wb_stall_o ); -- PROM prom: wb_bootloader port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => prom_rom_wb_dat_o, wb_adr_i => prom_rom_wb_adr_i(11 downto 2), wb_cyc_i => prom_rom_wb_cyc_i, wb_stb_i => prom_rom_wb_stb_i, wb_ack_o => prom_rom_wb_ack_o, wb_stall_o => prom_rom_wb_stall_o, wb2_dat_o => slot_read(15), wb2_adr_i => slot_address(15)(11 downto 2), wb2_cyc_i => slot_cyc(15), wb2_stb_i => slot_stb(15), wb2_ack_o => slot_ack(15), wb2_stall_o => open ); -- -- IO SLOT 0 -- slot0: zpuino_spi port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(0), wb_dat_i => slot_write(0), wb_adr_i => slot_address(0), wb_we_i => slot_we(0), wb_cyc_i => slot_cyc(0), wb_stb_i => slot_stb(0), wb_ack_o => slot_ack(0), wb_inta_o => slot_interrupt(0), mosi => spi_pf_mosi, miso => spi_pf_miso, sck => spi_pf_sck, enabled => open ); -- -- IO SLOT 1 -- uart_inst: zpuino_uart port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(1), wb_dat_i => slot_write(1), wb_adr_i => slot_address(1), wb_we_i => slot_we(1), wb_cyc_i => slot_cyc(1), wb_stb_i => slot_stb(1), wb_ack_o => slot_ack(1), wb_inta_o => slot_interrupt(1), enabled => open, tx => tx, rx => rx ); -- -- IO SLOT 2 -- gpio_inst: zpuino_gpio generic map ( gpio_count => 49 ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(2), wb_dat_i => slot_write(2), wb_adr_i => slot_address(2), wb_we_i => slot_we(2), wb_cyc_i => slot_cyc(2), wb_stb_i => slot_stb(2), wb_ack_o => slot_ack(2), wb_inta_o => slot_interrupt(2), spp_data => gpio_bus_in_record.gpio_spp_data, spp_read => gpio_bus_out_record.gpio_spp_read, gpio_i => gpio_bus_in_record.gpio_i, gpio_t => gpio_bus_out_record.gpio_t, gpio_o => gpio_o_reg, spp_cap_in => spp_cap_in, spp_cap_out => spp_cap_out ); -- -- IO SLOT 3 -- timers_inst: zpuino_timers generic map ( A_TSCENABLED => true, A_PWMCOUNT => 1, A_WIDTH => 16, A_PRESCALER_ENABLED => true, A_BUFFERS => true, B_TSCENABLED => false, B_PWMCOUNT => 1, B_WIDTH => 8,--24, B_PRESCALER_ENABLED => false, B_BUFFERS => false ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(3), wb_dat_i => slot_write(3), wb_adr_i => slot_address(3), wb_we_i => slot_we(3), wb_cyc_i => slot_cyc(3), wb_stb_i => slot_stb(3), wb_ack_o => slot_ack(3), wb_inta_o => slot_interrupt(3), -- We use two interrupt lines wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4 pwm_a_out => timers_pwm(0 downto 0), pwm_b_out => timers_pwm(1 downto 1) ); -- -- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller) -- -- -- IO SLOT 5 -- -- sigmadelta_inst: zpuino_sigmadelta -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(5), -- wb_dat_i => slot_write(5), -- wb_adr_i => slot_address(5), -- wb_we_i => slot_we(5), -- wb_cyc_i => slot_cyc(5), -- wb_stb_i => slot_stb(5), -- wb_ack_o => slot_ack(5), -- wb_inta_o => slot_interrupt(5), -- spp_data => sigmadelta_spp_data, -- spp_en => open, -- sync_in => '1' -- ); -- -- IO SLOT 6 -- -- slot1: zpuino_spi -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(6), -- wb_dat_i => slot_write(6), -- wb_adr_i => slot_address(6), -- wb_we_i => slot_we(6), -- wb_cyc_i => slot_cyc(6), -- wb_stb_i => slot_stb(6), -- wb_ack_o => slot_ack(6), -- wb_inta_o => slot_interrupt(6), -- -- mosi => spi2_mosi, -- miso => spi2_miso, -- sck => spi2_sck, -- enabled => open -- ); -- -- IO SLOT 7 -- crc16_inst: zpuino_crc16 port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(7), wb_dat_i => slot_write(7), wb_adr_i => slot_address(7), wb_we_i => slot_we(7), wb_cyc_i => slot_cyc(7), wb_stb_i => slot_stb(7), wb_ack_o => slot_ack(7), wb_inta_o => slot_interrupt(7) ); sram_inst: sdram_ctrl port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => sram_wb_dat_o, wb_dat_i => sram_wb_dat_i, wb_adr_i => sram_wb_adr_i(maxIObit downto minIObit), wb_we_i => sram_wb_we_i, wb_cyc_i => sram_wb_cyc_i, wb_stb_i => sram_wb_stb_i, wb_sel_i => sram_wb_sel_i, --wb_cti_i => CTI_CYCLE_CLASSIC, wb_ack_o => sram_wb_ack_o, wb_stall_o => sram_wb_stall_o, clk_off_3ns => sysclk_sram_we, DRAM_ADDR => DRAM_ADDR(11 downto 0), DRAM_BA => DRAM_BA, DRAM_CAS_N => DRAM_CAS_N, DRAM_CKE => DRAM_CKE, DRAM_CLK => DRAM_CLK, DRAM_CS_N => DRAM_CS_N, DRAM_DQ => DRAM_DQ, DRAM_DQM => DRAM_DQM, DRAM_RAS_N => DRAM_RAS_N, DRAM_WE_N => DRAM_WE_N ); DRAM_ADDR(12) <= '0'; -- Papilio Note: Place your Wishbone components here. #Wishbone -- Look at the ZPUino User Guide for what Wishbone components are available: -- http://www.papilio.cc/index.php?n=Papilio.ZPUinoUserGuide#Reference -- -- IO SLOT 8 -- -- slot8: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(8), -- wb_dat_i => slot_write(8), -- wb_adr_i => slot_address(8), -- wb_we_i => slot_we(8), -- wb_cyc_i => slot_cyc(8), -- wb_stb_i => slot_stb(8), -- wb_ack_o => slot_ack(8), -- wb_inta_o => slot_interrupt(8) -- ); -- -- IO SLOT 9 -- -- slot9: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(9), -- wb_dat_i => slot_write(9), -- wb_adr_i => slot_address(9), -- wb_we_i => slot_we(9), -- wb_cyc_i => slot_cyc(9), -- wb_stb_i => slot_stb(9), -- wb_ack_o => slot_ack(9), -- wb_inta_o => slot_interrupt(9) -- ); -- -- IO SLOT 10 -- -- slot10: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(10), -- wb_dat_i => slot_write(10), -- wb_adr_i => slot_address(10), -- wb_we_i => slot_we(10), -- wb_cyc_i => slot_cyc(10), -- wb_stb_i => slot_stb(10), -- wb_ack_o => slot_ack(10), -- wb_inta_o => slot_interrupt(10) -- ); -- -- IO SLOT 11 -- -- slot11: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(11), -- wb_dat_i => slot_write(11), -- wb_adr_i => slot_address(11), -- wb_we_i => slot_we(11), -- wb_cyc_i => slot_cyc(11), -- wb_stb_i => slot_stb(11), -- wb_ack_o => slot_ack(11), -- wb_inta_o => slot_interrupt(11) -- ); -- -- IO SLOT 12 -- -- slot12: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(12), -- wb_dat_i => slot_write(12), -- wb_adr_i => slot_address(12), -- wb_we_i => slot_we(12), -- wb_cyc_i => slot_cyc(12), -- wb_stb_i => slot_stb(12), -- wb_ack_o => slot_ack(12), -- wb_inta_o => slot_interrupt(12) -- ); -- -- IO SLOT 13 -- -- slot13: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(13), -- wb_dat_i => slot_write(13), -- wb_adr_i => slot_address(13), -- wb_we_i => slot_we(13), -- wb_cyc_i => slot_cyc(13), -- wb_stb_i => slot_stb(13), -- wb_ack_o => slot_ack(13), -- wb_inta_o => slot_interrupt(13) -- ); -- -- IO SLOT 14 -- -- slot14: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(14), -- wb_dat_i => slot_write(14), -- wb_adr_i => slot_address(14), -- wb_we_i => slot_we(14), -- wb_cyc_i => slot_cyc(14), -- wb_stb_i => slot_stb(14), -- wb_ack_o => slot_ack(14), -- wb_inta_o => slot_interrupt(14) -- ); -- -- IO SLOT 15 - do not use -- -- process(gpio_spp_read, spi_pf_mosi, spi_pf_sck, -- sigmadelta_spp_data,timers_pwm, -- spi2_mosi,spi2_sck) -- begin -- gpio_spp_data <= (others => DontCareValue); -- -- PPS Outputs -- gpio_spp_data(0) <= sigmadelta_spp_data(0); -- PPS0 : SIGMADELTA DATA -- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0 -- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1 -- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI -- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK -- gpio_spp_data(5) <= sigmadelta_spp_data(1); -- PPS5 : SIGMADELTA1 DATA -- -- PPS inputs -- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO -- end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/ZPUino_Papilio_One_V1.vhd

13

42659

-- -- ZPUINO implementation on Gadget Factory 'Papilio One' Board -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library zpuino; use zpuino.pad.all; use zpuino.papilio_pkg.all; library board; use board.zpuino_config.all; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; library unisim; use unisim.vcomponents.all; entity ZPUino_Papilio_One_V1 is port ( --32Mhz input clock is converted to a 96Mhz clock CLK: in std_logic; --RST: in std_logic; -- No reset on papilio --Clock outputs to be used in schematic clk_96Mhz: out std_logic; --This is the clock that the system runs on. clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip. clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator. -- Connection to the main SPI flash SPI_FLASH_SCK: out std_logic; SPI_FLASH_MISO: in std_logic; SPI_FLASH_MOSI: out std_logic; SPI_FLASH_CS: inout std_logic; gpio_bus_in : in std_logic_vector(97 downto 0); gpio_bus_out : out std_logic_vector(147 downto 0); -- UART (FTDI) connection TXD: out std_logic; RXD: in std_logic; --There are more bits in the address for this wishbone connection wishbone_slot_video_in : in std_logic_vector(63 downto 0); wishbone_slot_video_out : out std_logic_vector(33 downto 0); vgaclkout: out std_logic; -- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array. -- This is a little cumbersome but is better then dealing with all the signals in the schematic editor. -- This is what the original record base approach looked like: -- -- type wishbone_bus_in_type is record -- wb_clk_i: std_logic; -- Wishbone clock -- wb_rst_i: std_logic; -- Wishbone reset (synchronous) -- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) -- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) -- wb_we_i: std_logic; -- Wishbone write enable signal -- wb_cyc_i: std_logic; -- Wishbone cycle signal -- wb_stb_i: std_logic; -- Wishbone strobe signal -- end record; -- -- type wishbone_bus_out_type is record -- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) -- wb_ack_o: std_logic; -- Wishbone acknowledge out signal -- wb_inta_o: std_logic; -- end record; -- -- Turning them into an array looks like this: -- -- wishbone_in : in std_logic_vector(61 downto 0); -- -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out : out std_logic_vector(33 downto 0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; --Input and output reversed for the master wishbone_slot_5_in : out std_logic_vector(61 downto 0); wishbone_slot_5_out : in std_logic_vector(33 downto 0); wishbone_slot_6_in : out std_logic_vector(61 downto 0); wishbone_slot_6_out : in std_logic_vector(33 downto 0); wishbone_slot_8_in : out std_logic_vector(61 downto 0); wishbone_slot_8_out : in std_logic_vector(33 downto 0); wishbone_slot_9_in : out std_logic_vector(61 downto 0); wishbone_slot_9_out : in std_logic_vector(33 downto 0); wishbone_slot_10_in : out std_logic_vector(61 downto 0); wishbone_slot_10_out : in std_logic_vector(33 downto 0); wishbone_slot_11_in : out std_logic_vector(61 downto 0); wishbone_slot_11_out : in std_logic_vector(33 downto 0); wishbone_slot_12_in : out std_logic_vector(61 downto 0); wishbone_slot_12_out : in std_logic_vector(33 downto 0); wishbone_slot_13_in : out std_logic_vector(61 downto 0); wishbone_slot_13_out : in std_logic_vector(33 downto 0); wishbone_slot_14_in : out std_logic_vector(61 downto 0); wishbone_slot_14_out : in std_logic_vector(33 downto 0); wishbone_slot_15_in : out std_logic_vector(61 downto 0); wishbone_slot_15_out : in std_logic_vector(33 downto 0) ); -- attribute LOC: string; -- attribute LOC of CLK: signal is "P89"; -- attribute LOC of RXD: signal is "P88"; -- attribute LOC of TXD: signal is "P90"; -- attribute LOC of SPI_FLASH_CS: signal is "P24"; -- attribute LOC of SPI_FLASH_SCK: signal is "P50"; -- attribute LOC of SPI_FLASH_MISO: signal is "P44"; -- attribute LOC of SPI_FLASH_MOSI: signal is "P27"; -- -- attribute IOSTANDARD: string; -- attribute IOSTANDARD of CLK: signal is "LVCMOS33"; -- attribute IOSTANDARD of RXD: signal is "LVCMOS33"; -- attribute IOSTANDARD of TXD: signal is "LVCMOS33"; -- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33"; -- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33"; -- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33"; -- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33"; -- -- attribute PERIOD: string; -- attribute PERIOD of CLK: signal is "31.00ns"; end entity ZPUino_Papilio_One_V1; architecture behave of ZPUino_Papilio_One_V1 is component clkgen is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout_1mhz: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end component clkgen; component zpuino_serialreset is generic ( SYSTEM_CLOCK_MHZ: integer := 96 ); port ( clk: in std_logic; rx: in std_logic; rstin: in std_logic; rstout: out std_logic ); end component zpuino_serialreset; signal sysrst: std_logic; signal sysclk: std_logic; signal sysclk_1mhz: std_logic; signal dbg_reset: std_logic; signal clkgen_rst: std_logic; signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0); signal rx: std_logic; signal tx: std_logic; constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) := "0" & "0000000000000000" & "0000000000000000" & "0000000000000000"; constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) := "0" & "0000000000000000" & "0000000000000000" & "0000000000000000"; -- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) := -- "0" & -- "1111111111111111" & -- "1111111111111111" & -- "1111111111111111"; -- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) := -- "0" & -- "1111111111111111" & -- "1111111111111111" & -- "1111111111111111"; -- I/O Signals signal slot_cyc: slot_std_logic_type; signal slot_we: slot_std_logic_type; signal slot_stb: slot_std_logic_type; signal slot_read: slot_cpuword_type; signal slot_write: slot_cpuword_type; signal slot_address: slot_address_type; signal slot_ack: slot_std_logic_type; signal slot_interrupt: slot_std_logic_type; signal spi_enabled: std_logic; signal uart_enabled: std_logic; signal timers_interrupt: std_logic_vector(1 downto 0); signal timers_pwm: std_logic_vector(1 downto 0); signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0); signal sigmadelta_spp_en: std_logic_vector(1 downto 0); signal sigmadelta_spp_data: std_logic_vector(1 downto 0); -- For busy-implementation signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0); signal write_save_q: std_logic_vector(wordSize-1 downto 0); signal spi_pf_miso: std_logic; signal spi_pf_mosi: std_logic; signal spi_pf_sck: std_logic; signal adc_mosi: std_logic; signal adc_miso: std_logic; signal adc_sck: std_logic; signal adc_seln: std_logic; signal adc_enabled: std_logic; signal wb_clk_i: std_logic; signal wb_rst_i: std_logic; signal uart2_tx, uart2_rx: std_logic; signal jtag_data_chain_out: std_logic_vector(98 downto 0); signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0); signal wishbone_slot_video_in_record : wishbone_bus_in_type; signal wishbone_slot_video_out_record : wishbone_bus_out_type; signal wishbone_slot_5_in_record : wishbone_bus_in_type; signal wishbone_slot_5_out_record : wishbone_bus_out_type; signal wishbone_slot_6_in_record : wishbone_bus_in_type; signal wishbone_slot_6_out_record : wishbone_bus_out_type; signal wishbone_slot_8_in_record : wishbone_bus_in_type; signal wishbone_slot_8_out_record : wishbone_bus_out_type; signal wishbone_slot_9_in_record : wishbone_bus_in_type; signal wishbone_slot_9_out_record : wishbone_bus_out_type; signal wishbone_slot_10_in_record : wishbone_bus_in_type; signal wishbone_slot_10_out_record : wishbone_bus_out_type; signal wishbone_slot_11_in_record : wishbone_bus_in_type; signal wishbone_slot_11_out_record : wishbone_bus_out_type; signal wishbone_slot_12_in_record : wishbone_bus_in_type; signal wishbone_slot_12_out_record : wishbone_bus_out_type; signal wishbone_slot_13_in_record : wishbone_bus_in_type; signal wishbone_slot_13_out_record : wishbone_bus_out_type; signal wishbone_slot_14_in_record : wishbone_bus_in_type; signal wishbone_slot_14_out_record : wishbone_bus_out_type; signal wishbone_slot_15_in_record : wishbone_bus_in_type; signal wishbone_slot_15_out_record : wishbone_bus_out_type; signal gpio_bus_in_record : gpio_bus_in_type; signal gpio_bus_out_record : gpio_bus_out_type; component zpuino_debug_spartan3e is port ( TCK: out std_logic; TDI: out std_logic; CAPTUREIR: out std_logic; UPDATEIR: out std_logic; SHIFTIR: out std_logic; CAPTUREDR: out std_logic; UPDATEDR: out std_logic; SHIFTDR: out std_logic; TLR: out std_logic; TDO_IR: in std_logic; TDO_DR: in std_logic ); end component; begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- These are backwards for the master. -- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61); -- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60); -- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28); -- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3); -- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2); -- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1); -- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0); -- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o; -- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o; -- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o; wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i; wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i; wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i; wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i; wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i; wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i; wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i; wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2); wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1); wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0); wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i; wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i; wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i; wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i; wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i; wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i; wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i; wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2); wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1); wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0); wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i; wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i; wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i; wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i; wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i; wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i; wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i; wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2); wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1); wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0); wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i; wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i; wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i; wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i; wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i; wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i; wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i; wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2); wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1); wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0); wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i; wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i; wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i; wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i; wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i; wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i; wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i; wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2); wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1); wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0); wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i; wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i; wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i; wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i; wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i; wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i; wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i; wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2); wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1); wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0); wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i; wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i; wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i; wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i; wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i; wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i; wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i; wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2); wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1); wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0); wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i; wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i; wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i; wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i; wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i; wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i; wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i; wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2); wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1); wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0); wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i; wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i; wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i; wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i; wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i; wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i; wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i; wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2); wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1); wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0); wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i; wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i; wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i; wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i; wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i; wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i; wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i; wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2); wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1); wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0); gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49); gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0); gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk; gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o; gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t; gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read; gpio_bus_out_record.gpio_o <= gpio_o_reg; gpio_bus_out_record.gpio_clk <= sysclk; wb_clk_i <= sysclk; wb_rst_i <= sysrst; --Wishbone 5 wishbone_slot_5_in_record.wb_clk_i <= sysclk; wishbone_slot_5_in_record.wb_rst_i <= sysrst; slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o; wishbone_slot_5_in_record.wb_dat_i <= slot_write(5); wishbone_slot_5_in_record.wb_adr_i <= slot_address(5); wishbone_slot_5_in_record.wb_we_i <= slot_we(5); wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5); wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5); slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o; slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o; --Wishbone 6 wishbone_slot_6_in_record.wb_clk_i <= sysclk; wishbone_slot_6_in_record.wb_rst_i <= sysrst; slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o; wishbone_slot_6_in_record.wb_dat_i <= slot_write(6); wishbone_slot_6_in_record.wb_adr_i <= slot_address(6); wishbone_slot_6_in_record.wb_we_i <= slot_we(6); wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6); wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6); slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o; slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o; --Wishbone 8 wishbone_slot_8_in_record.wb_clk_i <= sysclk; wishbone_slot_8_in_record.wb_rst_i <= sysrst; slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o; wishbone_slot_8_in_record.wb_dat_i <= slot_write(8); wishbone_slot_8_in_record.wb_adr_i <= slot_address(8); wishbone_slot_8_in_record.wb_we_i <= slot_we(8); wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8); wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8); slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o; slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o; --Wishbone 9 wishbone_slot_9_in_record.wb_clk_i <= sysclk; wishbone_slot_9_in_record.wb_rst_i <= sysrst; slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o; wishbone_slot_9_in_record.wb_dat_i <= slot_write(9); wishbone_slot_9_in_record.wb_adr_i <= slot_address(9); wishbone_slot_9_in_record.wb_we_i <= slot_we(9); wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9); wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9); slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o; slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o; --Wishbone 10 wishbone_slot_10_in_record.wb_clk_i <= sysclk; wishbone_slot_10_in_record.wb_rst_i <= sysrst; slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o; wishbone_slot_10_in_record.wb_dat_i <= slot_write(10); wishbone_slot_10_in_record.wb_adr_i <= slot_address(10); wishbone_slot_10_in_record.wb_we_i <= slot_we(10); wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10); wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10); slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o; slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o; --Wishbone 11 wishbone_slot_11_in_record.wb_clk_i <= sysclk; wishbone_slot_11_in_record.wb_rst_i <= sysrst; slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o; wishbone_slot_11_in_record.wb_dat_i <= slot_write(11); wishbone_slot_11_in_record.wb_adr_i <= slot_address(11); wishbone_slot_11_in_record.wb_we_i <= slot_we(11); wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11); wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11); slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o; slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o; --Wishbone 12 wishbone_slot_12_in_record.wb_clk_i <= sysclk; wishbone_slot_12_in_record.wb_rst_i <= sysrst; slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o; wishbone_slot_12_in_record.wb_dat_i <= slot_write(12); wishbone_slot_12_in_record.wb_adr_i <= slot_address(12); wishbone_slot_12_in_record.wb_we_i <= slot_we(12); wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12); wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12); slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o; slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o; --Wishbone 13 wishbone_slot_13_in_record.wb_clk_i <= sysclk; wishbone_slot_13_in_record.wb_rst_i <= sysrst; slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o; wishbone_slot_13_in_record.wb_dat_i <= slot_write(13); wishbone_slot_13_in_record.wb_adr_i <= slot_address(13); wishbone_slot_13_in_record.wb_we_i <= slot_we(13); wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13); wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13); slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o; slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o; --Wishbone 14 wishbone_slot_14_in_record.wb_clk_i <= sysclk; wishbone_slot_14_in_record.wb_rst_i <= sysrst; slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o; wishbone_slot_14_in_record.wb_dat_i <= slot_write(14); wishbone_slot_14_in_record.wb_adr_i <= slot_address(14); wishbone_slot_14_in_record.wb_we_i <= slot_we(14); wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14); wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14); slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o; slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o; --Wishbone 15 wishbone_slot_15_in_record.wb_clk_i <= sysclk; wishbone_slot_15_in_record.wb_rst_i <= sysrst; slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o; wishbone_slot_15_in_record.wb_dat_i <= slot_write(15); wishbone_slot_15_in_record.wb_adr_i <= slot_address(15); wishbone_slot_15_in_record.wb_we_i <= slot_we(15); wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15); wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15); slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o; slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o; rstgen: zpuino_serialreset generic map ( SYSTEM_CLOCK_MHZ => 96 ) port map ( clk => sysclk, rx => rx, rstin => clkgen_rst, rstout => sysrst ); --sysrst <= clkgen_rst; clkgen_inst: clkgen port map ( clkin => clk, rstin => dbg_reset, clkout => sysclk, vgaclkout => vgaclkout, clkout_1mhz => clk_1Mhz, clk_osc_32Mhz => clk_osc_32Mhz, rstout => clkgen_rst ); clk_96Mhz <= sysclk; zpuino:zpuino_top port map ( clk => sysclk, rst => sysrst, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt, --Be careful the order for this is different then the other wishbone bus connections. --The address array is bigger so we moved the single signals to the top of the array. m_wb_dat_o => wishbone_slot_video_out(33 downto 2), m_wb_dat_i => wishbone_slot_video_in(59 downto 28), m_wb_adr_i => wishbone_slot_video_in(27 downto 0), m_wb_we_i => wishbone_slot_video_in(62), m_wb_cyc_i => wishbone_slot_video_in(61), m_wb_stb_i => wishbone_slot_video_in(60), m_wb_ack_o => wishbone_slot_video_out(1), dbg_reset => dbg_reset, jtag_data_chain_out => open,--jtag_data_chain_out, jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in ); -- -- -- ---------------- I/O connection to devices -------------------- -- -- -- -- IO SLOT 0 For SPI FLash -- slot0: zpuino_spi port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(0), wb_dat_i => slot_write(0), wb_adr_i => slot_address(0), wb_we_i => slot_we(0), wb_cyc_i => slot_cyc(0), wb_stb_i => slot_stb(0), wb_ack_o => slot_ack(0), wb_inta_o => slot_interrupt(0), mosi => spi_pf_mosi, miso => spi_pf_miso, sck => spi_pf_sck, enabled => spi_enabled ); -- -- IO SLOT 1 -- uart_inst: zpuino_uart port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(1), wb_dat_i => slot_write(1), wb_adr_i => slot_address(1), wb_we_i => slot_we(1), wb_cyc_i => slot_cyc(1), wb_stb_i => slot_stb(1), wb_ack_o => slot_ack(1), wb_inta_o => slot_interrupt(1), enabled => uart_enabled, tx => tx, rx => rx ); -- -- IO SLOT 2 -- gpio_inst: zpuino_gpio generic map ( gpio_count => zpuino_gpio_count ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(2), wb_dat_i => slot_write(2), wb_adr_i => slot_address(2), wb_we_i => slot_we(2), wb_cyc_i => slot_cyc(2), wb_stb_i => slot_stb(2), wb_ack_o => slot_ack(2), wb_inta_o => slot_interrupt(2), spp_data => gpio_bus_in_record.gpio_spp_data, spp_read => gpio_bus_out_record.gpio_spp_read, gpio_i => gpio_bus_in_record.gpio_i, gpio_t => gpio_bus_out_record.gpio_t, gpio_o => gpio_o_reg, spp_cap_in => spp_cap_in, spp_cap_out => spp_cap_out ); -- -- IO SLOT 3 -- timers_inst: zpuino_timers generic map ( A_TSCENABLED => true, A_PWMCOUNT => 1, A_WIDTH => 16, A_PRESCALER_ENABLED => true, A_BUFFERS => true, B_TSCENABLED => false, B_PWMCOUNT => 1, B_WIDTH => 8, B_PRESCALER_ENABLED => false, B_BUFFERS => false ) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(3), wb_dat_i => slot_write(3), wb_adr_i => slot_address(3), wb_we_i => slot_we(3), wb_cyc_i => slot_cyc(3), wb_stb_i => slot_stb(3), wb_ack_o => slot_ack(3), wb_inta_o => slot_interrupt(3), -- We use two interrupt lines wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4 pwm_a_out => timers_pwm(0 downto 0), pwm_b_out => timers_pwm(1 downto 1) ); -- -- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller) -- -- -- IO SLOT 5 -- -- -- sigmadelta_inst: zpuino_sigmadelta -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(5), -- wb_dat_i => slot_write(5), -- wb_adr_i => slot_address(5), -- wb_we_i => slot_we(5), -- wb_cyc_i => slot_cyc(5), -- wb_stb_i => slot_stb(5), -- wb_ack_o => slot_ack(5), -- wb_inta_o => slot_interrupt(5), -- -- raw_out => sigmadelta_raw, -- spp_data => sigmadelta_spp_data, -- spp_en => sigmadelta_spp_en, -- sync_in => '1' -- ); -- -- IO SLOT 6 -- -- slot1: zpuino_spi -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(6), -- wb_dat_i => slot_write(6), -- wb_adr_i => slot_address(6), -- wb_we_i => slot_we(6), -- wb_cyc_i => slot_cyc(6), -- wb_stb_i => slot_stb(6), -- wb_ack_o => slot_ack(6), -- wb_inta_o => slot_interrupt(6), -- -- mosi => spi2_mosi, -- miso => spi2_miso, -- sck => spi2_sck, -- enabled => open -- ); -- -- -- -- -- IO SLOT 7 -- crc16_inst: zpuino_crc16 port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(7), wb_dat_i => slot_write(7), wb_adr_i => slot_address(7), wb_we_i => slot_we(7), wb_cyc_i => slot_cyc(7), wb_stb_i => slot_stb(7), wb_ack_o => slot_ack(7), wb_inta_o => slot_interrupt(7) ); -- -- IO SLOT 8 (optional) -- -- adc_inst: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(8), -- wb_dat_i => slot_write(8), -- wb_adr_i => slot_address(8), -- wb_we_i => slot_we(8), -- wb_cyc_i => slot_cyc(8), -- wb_stb_i => slot_stb(8), -- wb_ack_o => slot_ack(8), -- wb_inta_o => slot_interrupt(8) -- ); -- -- -- -- -- IO SLOT 9 -- -- -- -- slot9: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(9), -- wb_dat_i => slot_write(9), -- wb_adr_i => slot_address(9), -- wb_we_i => slot_we(9), -- wb_cyc_i => slot_cyc(9), -- wb_stb_i => slot_stb(9), -- wb_ack_o => slot_ack(9), -- wb_inta_o => slot_interrupt(9) -- ); -- -- -- -- -- IO SLOT 10 -- -- -- -- slot10: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(10), -- wb_dat_i => slot_write(10), -- wb_adr_i => slot_address(10), -- wb_we_i => slot_we(10), -- wb_cyc_i => slot_cyc(10), -- wb_stb_i => slot_stb(10), -- wb_ack_o => slot_ack(10), -- wb_inta_o => slot_interrupt(10) -- ); -- -- -- -- -- IO SLOT 11 -- -- -- -- slot11: zpuino_empty_device ---- generic map ( ---- bits => 4 ---- ) -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(11), -- wb_dat_i => slot_write(11), -- wb_adr_i => slot_address(11), -- wb_we_i => slot_we(11), -- wb_cyc_i => slot_cyc(11), -- wb_stb_i => slot_stb(11), -- wb_ack_o => slot_ack(11), -- -- wb_inta_o => slot_interrupt(11) -- ---- tx => uart2_tx, ---- rx => uart2_rx -- ); -- -- -- -- -- IO SLOT 12 -- -- -- -- slot12: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(12), -- wb_dat_i => slot_write(12), -- wb_adr_i => slot_address(12), -- wb_we_i => slot_we(12), -- wb_cyc_i => slot_cyc(12), -- wb_stb_i => slot_stb(12), -- wb_ack_o => slot_ack(12), -- wb_inta_o => slot_interrupt(12) -- ); -- -- -- -- -- IO SLOT 13 -- -- -- -- slot13: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(13), -- wb_dat_i => slot_write(13), -- wb_adr_i => slot_address(13), -- wb_we_i => slot_we(13), -- wb_cyc_i => slot_cyc(13), -- wb_stb_i => slot_stb(13), -- wb_ack_o => slot_ack(13), -- wb_inta_o => slot_interrupt(13) -- ---- data_out => ym2149_audio_data -- ); -- -- -- -- -- IO SLOT 14 -- -- -- -- slot14: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(14), -- wb_dat_i => slot_write(14), -- wb_adr_i => slot_address(14), -- wb_we_i => slot_we(14), -- wb_cyc_i => slot_cyc(14), -- wb_stb_i => slot_stb(14), -- wb_ack_o => slot_ack(14), -- wb_inta_o => slot_interrupt(14) -- ---- clk_1MHZ => sysclk_1mhz, ---- audio_data => sid_audio_data -- -- ); -- -- -- -- -- IO SLOT 15 -- -- -- -- slot15: zpuino_empty_device -- port map ( -- wb_clk_i => wb_clk_i, -- wb_rst_i => wb_rst_i, -- wb_dat_o => slot_read(15), -- wb_dat_i => slot_write(15), -- wb_adr_i => slot_address(15), -- wb_we_i => slot_we(15), -- wb_cyc_i => slot_cyc(15), -- wb_stb_i => slot_stb(15), -- wb_ack_o => slot_ack(15), -- wb_inta_o => slot_interrupt(15) -- ); -- -- Audio for SID -- sid_sd: simple_sigmadelta -- generic map ( -- BITS => 18 -- ) -- port map ( -- clk => wb_clk_i, -- rst => wb_rst_i, -- data_in => sid_audio_data, -- data_out => sid_audio -- ); -- Audio output for devices -- ym2149_audio_dac <= ym2149_audio_data & "0000000000"; -- -- mixer: zpuino_io_audiomixer -- port map ( -- clk => wb_clk_i, -- rst => wb_rst_i, -- ena => '1', -- -- data_in1 => sid_audio_data, -- data_in2 => ym2149_audio_dac, -- data_in3 => sigmadelta_raw, -- -- audio_out => platform_audio_sd -- ); -- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) ); -- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) ); -- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) ); -- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) ); -- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) ); -- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) ); -- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) ); -- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) ); -- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) ); -- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) ); -- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) ); -- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) ); -- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) ); -- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) ); -- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) ); -- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) ); -- -- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) ); -- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) ); -- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) ); -- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) ); -- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) ); -- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) ); -- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) ); -- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) ); -- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) ); -- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) ); -- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) ); -- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) ); -- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) ); -- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) ); -- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) ); -- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) ); -- -- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) ); -- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) ); -- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) ); -- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) ); -- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) ); -- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) ); -- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) ); -- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) ); -- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) ); -- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) ); -- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) ); -- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) ); -- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) ); -- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) ); -- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) ); -- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) ); -- Other ports are special, we need to avoid outputs on input-only pins ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk ); ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk ); obuftx: OPAD port map ( I => tx, PAD => TXD ); ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK ); ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS ); ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI ); -- process(gpio_spp_read, -- sigmadelta_spp_data, -- timers_pwm, -- spi2_mosi,spi2_sck) -- begin -- -- gpio_spp_data <= (others => DontCareValue); -- ---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA -- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0 -- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1 -- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI -- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK ---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA -- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA ---- gpio_spp_data(8) <= platform_audio_sd; -- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO ---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO -- -- end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen_hyperion.vhd

13

10525

-- -- System Clock generator for ZPUINO (papilio one) -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- -- This is a clockgen file for the Hyperion board type to be used with a Papilio One 500K. The sysclock runs at 92Mhz instead of 96Mhz. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity clkgen_hyperion is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout_1mhz: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end entity clkgen_hyperion; architecture behave of clkgen_hyperion is signal dcmlocked: std_logic; signal dcmlocked_1mhz: std_logic; signal dcmclock: std_logic; signal dcmclock_1mhz: std_logic; signal rst1_q: std_logic; signal rst2_q: std_logic; signal clkout_i: std_logic; signal clkin_i: std_logic; signal clkfb: std_logic; signal clk0: std_logic; signal clkin_i_1mhz: std_logic; signal clkfb_1mhz: std_logic; signal clk0_1mhz: std_logic; signal clkin_i_2: std_logic; signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic; begin clk_osc_32Mhz <= clkin_i; clkout <= clkout_i; rstout <= rst1_q; process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin) begin if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then rst1_q <= '1'; rst2_q <= '1'; else if rising_edge(clkout_i) then rst1_q <= rst2_q; rst2_q <= '0'; end if; end if; end process; -- Clock buffers clkfx_inst: BUFG port map ( I => dcmclock, O => clkout_i ); clkin_inst: IBUFG port map ( I => clkin, O => clkin_i ); clkfb_inst: BUFG port map ( I=> clk0, O=> clkfb ); DCM_inst : DCM generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 8,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 23,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => dcmclock, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb, -- DCM clock feedback CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); DCM_inst_1mhz : DCM generic map ( CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked_1mhz, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb_1mhz, -- DCM clock feedback CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); clkfx_inst_1mhz: BUFG port map ( I => dcmclock_1mhz, O => clkout_1mhz ); --clkin_inst_1mhz: IBUFG -- port map ( -- I => clkin, -- O => clkin_i_1mhz -- ); clkin_i_1mhz <= clk0; clkin_i_2 <= clk0; clkfb_inst_1mhz: BUFG port map ( I=> clk0_1mhz, O=> clkfb_1mhz ); vgaclkout <= '0'; -- vgaclkfx_inst: BUFG -- port map ( -- I => vgaclk_fx_b, -- O => vgaclkout -- ); -- VGADCM_inst : DCM -- Generate 50Mhz -- generic map ( -- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 -- CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32 -- CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32 -- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature -- CLKIN_PERIOD => 31.25, -- Specify period of input clock -- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE -- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X -- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 -- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis -- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL -- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE -- FACTORY_JF => X"C080", -- FACTORY JF Values -- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 -- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE -- ) -- port map ( -- CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput -- CLK180 => open, -- 180 degree DCM CLK output -- CLK270 => open, -- 270 degree DCM CLK output -- CLK2X => open, -- 2X DCM CLK output -- CLK2X180 => open, -- 2X, 180 degree DCM CLK out -- CLK90 => open, -- 90 degree DCM CLK output -- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) -- CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D) -- CLKFX180 => open, -- 180 degree CLK synthesis out -- LOCKED => open,--dcmlocked_b, -- DCM LOCK status output -- PSDONE => open, -- Dynamic phase adjust done output -- STATUS => open, -- 8-bit DCM status bits output -- CLKFB => '0',--vgaclk_fb, -- DCM clock feedback -- CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM) -- PSCLK => '0', -- Dynamic phase adjust clock input -- PSEN => '0', -- Dynamic phase adjust enable input -- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement -- RST => '0' -- DCM asynchronous reset input -- ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen_hyperion.vhd

13

10525

-- -- System Clock generator for ZPUINO (papilio one) -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- -- This is a clockgen file for the Hyperion board type to be used with a Papilio One 500K. The sysclock runs at 92Mhz instead of 96Mhz. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity clkgen_hyperion is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout_1mhz: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end entity clkgen_hyperion; architecture behave of clkgen_hyperion is signal dcmlocked: std_logic; signal dcmlocked_1mhz: std_logic; signal dcmclock: std_logic; signal dcmclock_1mhz: std_logic; signal rst1_q: std_logic; signal rst2_q: std_logic; signal clkout_i: std_logic; signal clkin_i: std_logic; signal clkfb: std_logic; signal clk0: std_logic; signal clkin_i_1mhz: std_logic; signal clkfb_1mhz: std_logic; signal clk0_1mhz: std_logic; signal clkin_i_2: std_logic; signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic; begin clk_osc_32Mhz <= clkin_i; clkout <= clkout_i; rstout <= rst1_q; process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin) begin if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then rst1_q <= '1'; rst2_q <= '1'; else if rising_edge(clkout_i) then rst1_q <= rst2_q; rst2_q <= '0'; end if; end if; end process; -- Clock buffers clkfx_inst: BUFG port map ( I => dcmclock, O => clkout_i ); clkin_inst: IBUFG port map ( I => clkin, O => clkin_i ); clkfb_inst: BUFG port map ( I=> clk0, O=> clkfb ); DCM_inst : DCM generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 8,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 23,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => dcmclock, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb, -- DCM clock feedback CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); DCM_inst_1mhz : DCM generic map ( CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked_1mhz, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb_1mhz, -- DCM clock feedback CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); clkfx_inst_1mhz: BUFG port map ( I => dcmclock_1mhz, O => clkout_1mhz ); --clkin_inst_1mhz: IBUFG -- port map ( -- I => clkin, -- O => clkin_i_1mhz -- ); clkin_i_1mhz <= clk0; clkin_i_2 <= clk0; clkfb_inst_1mhz: BUFG port map ( I=> clk0_1mhz, O=> clkfb_1mhz ); vgaclkout <= '0'; -- vgaclkfx_inst: BUFG -- port map ( -- I => vgaclk_fx_b, -- O => vgaclkout -- ); -- VGADCM_inst : DCM -- Generate 50Mhz -- generic map ( -- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 -- CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32 -- CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32 -- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature -- CLKIN_PERIOD => 31.25, -- Specify period of input clock -- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE -- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X -- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 -- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis -- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL -- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE -- FACTORY_JF => X"C080", -- FACTORY JF Values -- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 -- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE -- ) -- port map ( -- CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput -- CLK180 => open, -- 180 degree DCM CLK output -- CLK270 => open, -- 270 degree DCM CLK output -- CLK2X => open, -- 2X DCM CLK output -- CLK2X180 => open, -- 2X, 180 degree DCM CLK out -- CLK90 => open, -- 90 degree DCM CLK output -- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) -- CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D) -- CLKFX180 => open, -- 180 degree CLK synthesis out -- LOCKED => open,--dcmlocked_b, -- DCM LOCK status output -- PSDONE => open, -- Dynamic phase adjust done output -- STATUS => open, -- 8-bit DCM status bits output -- CLKFB => '0',--vgaclk_fb, -- DCM clock feedback -- CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM) -- PSCLK => '0', -- Dynamic phase adjust clock input -- PSEN => '0', -- Dynamic phase adjust enable input -- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement -- RST => '0' -- DCM asynchronous reset input -- ); end behave;

mit

sinkswim/DLX-Pro

synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.f-IF_ID_Reg.vhd

1

2812

-------------------------------------------------------------------------------------------- -- IF/ID Pipeline register -- It recieves as input data coming from the fetch stage: -- - PC +4 -- - Instruction fetched -- Then flush signal in case it has been requested to flush the pipeline, the IFDWrite -- driven by the Hazard Detection Unit (it is used to freeze the regiter in case of stall) -- The reset is synchronous with respect to the clock, whereas the flush is asynchronous -------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.globals.all; -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- entity ifid_reg is port ( -- INPUTS pc_4 : in std_logic_vector(31 downto 0); -- PC + 4 coming from the fetch stage instruction_fetch : in std_logic_vector(31 downto 0); -- Instruction to be decoded flush : in std_logic; -- flush control signal ifid_write : in std_logic; -- write enable clk : in std_logic; -- clock signal rst : in std_logic; -- reset signal -- OUTPUTS instruction_decode : out std_logic_vector(31 downto 0); -- Instruction for the decode stage new_pc : out std_logic_vector(31 downto 0) -- PC + 4 directed to the next pipeline register ); end ifid_reg; -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- architecture behavioral of ifid_reg is begin ---------------------------- -- Name: Reg_Proc -- Type: Sequential -- Purpose: Implement the -- behavior of the pipeline -- register. Reset is -- synchronous. ---------------------------- Reg_proc:process(clk, flush) begin if (flush = '1') then new_pc <= (others => '0'); -- the value is not important since we are forcing a nop, thus this value will be never used instruction_decode <= N_TYPE_NOP & "00000000000000000000000000"; elsif (clk = '1' and clk'event) then if (rst = '1') then new_pc <= (others => '0'); instruction_decode <= N_TYPE_NOP & "00000000000000000000000000"; elsif (ifid_write = '1') then new_pc <= pc_4; instruction_decode <= instruction_fetch; end if; end if; end process; end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/trigger.vhd

13

3583

---------------------------------------------------------------------------------- -- trigger.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Complex 4 stage 32 channel trigger. -- -- All commands are passed on to the stages. This file only maintains -- the global trigger level and it outputs the run condition if it is set -- by any of the stages. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity trigger is port( la_input : in std_logic_vector (31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector (31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic_vector (3 downto 0); wrValue : in std_logic_vector (3 downto 0); wrConfig : in std_logic_vector (3 downto 0); arm : in std_logic; demuxed : in std_logic; run : out std_logic; ExtTriggerIn : in std_logic ); end trigger; architecture behavioral of trigger is component stage port( la_input : in std_logic_vector(31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector(31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic; wrValue : in std_logic; wrConfig : in std_logic; arm : in std_logic; level : in std_logic_vector(1 downto 0); demuxed : in std_logic; run : out std_logic; match : out std_logic ); end component; signal stageMatch : std_logic_vector(3 downto 0); signal stageRun : std_logic_vector(4 downto 0); signal levelReg : std_logic_vector(1 downto 0); begin --Connect ExtTriggerIn to the last stageRun --stageRun(4) <= ExtTriggerIn; --Disable external trigger -- create stages stages: for i in 0 to 3 generate Inst_stage: stage port map( la_input => la_input, la_inputReady => la_inputReady, data => data, clock => clock, reset => reset, wrMask => wrMask(i), wrValue => wrValue(i), wrConfig => wrConfig(i), arm => arm, level => levelReg, demuxed => demuxed, run => stageRun(i), match => stageMatch(i) ); end generate; -- increase level on match process(clock, arm) variable tmp : std_logic; begin if arm = '1' then levelReg <= "00"; elsif rising_edge(clock) then tmp := stageMatch(0); for i in 1 to 3 loop tmp := tmp or stageMatch(i); end loop; if tmp = '1' then levelReg <= levelReg + 1; end if; end if; end process; -- if any of the stages set run, capturing starts process(stageRun) variable tmp : std_logic; begin tmp := stageRun(0); for i in 1 to 4 loop tmp := tmp or stageRun(i); end loop; run <= tmp; end process; end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Benchy/trigger.vhd

13

3583

---------------------------------------------------------------------------------- -- trigger.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Complex 4 stage 32 channel trigger. -- -- All commands are passed on to the stages. This file only maintains -- the global trigger level and it outputs the run condition if it is set -- by any of the stages. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity trigger is port( la_input : in std_logic_vector (31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector (31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic_vector (3 downto 0); wrValue : in std_logic_vector (3 downto 0); wrConfig : in std_logic_vector (3 downto 0); arm : in std_logic; demuxed : in std_logic; run : out std_logic; ExtTriggerIn : in std_logic ); end trigger; architecture behavioral of trigger is component stage port( la_input : in std_logic_vector(31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector(31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic; wrValue : in std_logic; wrConfig : in std_logic; arm : in std_logic; level : in std_logic_vector(1 downto 0); demuxed : in std_logic; run : out std_logic; match : out std_logic ); end component; signal stageMatch : std_logic_vector(3 downto 0); signal stageRun : std_logic_vector(4 downto 0); signal levelReg : std_logic_vector(1 downto 0); begin --Connect ExtTriggerIn to the last stageRun --stageRun(4) <= ExtTriggerIn; --Disable external trigger -- create stages stages: for i in 0 to 3 generate Inst_stage: stage port map( la_input => la_input, la_inputReady => la_inputReady, data => data, clock => clock, reset => reset, wrMask => wrMask(i), wrValue => wrValue(i), wrConfig => wrConfig(i), arm => arm, level => levelReg, demuxed => demuxed, run => stageRun(i), match => stageMatch(i) ); end generate; -- increase level on match process(clock, arm) variable tmp : std_logic; begin if arm = '1' then levelReg <= "00"; elsif rising_edge(clock) then tmp := stageMatch(0); for i in 1 to 3 loop tmp := tmp or stageMatch(i); end loop; if tmp = '1' then levelReg <= levelReg + 1; end if; end if; end process; -- if any of the stages set run, capturing starts process(stageRun) variable tmp : std_logic; begin tmp := stageRun(0); for i in 1 to 4 loop tmp := tmp or stageRun(i); end loop; run <= tmp; end process; end behavioral;

mit

ordepmalo/matrizled

rtl/vhdl/interface/interface.vhd

1

3840

------------------------------------------------------------------------------- -- Title : Interface to Hardware -- Project : ------------------------------------------------------------------------------- -- File : interface.vhd -- Author : Pedro Messias Jose da Cunha Bastos -- Company : -- Created : 2015-04-17 -- Last update : 2015-05-19 -- Target Device : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description : Interface Implementation ------------------------------------------------------------------------------- -- Copyright (c) 2015 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2015-04-17 1.0 Ordep Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.functions_pkg.all; entity interface is generic ( MAX_VALUE : natural := 32; MAX_VALUE_BITS : natural := 5 ); port ( sysclk : in std_logic; -- clock global module DE2 reset_n : in std_logic; -- reset global en_i : in std_logic; -- signal do clk_divider ctrl_o : out std_logic_vector(MAX_VALUE_BITS - 1 downto 0); -- signal que vai para o sel_i stb_o : out std_logic; clk : out std_logic ); end interface; architecture interface_rtl of interface is type INTERFACE_ST_TYPE is (ST_INIT, ST_SET_CLK, ST_SET_CLK_LOW, ST_VERIFY, ST_SET_STB, ST_SET_STB_LOW); attribute syn_enconding : string; attribute syn_enconding of INTERFACE_ST_TYPE : type is "safe"; -- FSM para n signal state_reg : INTERFACE_ST_TYPE; signal state_next : INTERFACE_ST_TYPE; signal count_reg : unsigned(MAX_VALUE_BITS - 1 downto 0); signal count_next : unsigned(MAX_VALUE_BITS - 1 downto 0); signal clk_reg : std_logic; signal clk_next : std_logic; signal stb_reg : std_logic; signal stb_next : std_logic; begin ctrl_o <= std_logic_vector(count_reg); clk <= clk_reg; stb_o <= stb_reg; process(reset_n, sysclk) begin if reset_n = '0' then state_reg <= ST_INIT; count_reg <= (others => '0'); clk_reg <= '0'; stb_reg <= '0'; elsif rising_edge(sysclk) then -- sysclk = 50.000.000 (frequency of FPGA on DE2 module) state_reg <= state_next; count_reg <= count_next; clk_reg <= clk_next; stb_reg <= stb_next; end if; end process; process(clk_reg, count_reg, en_i, state_reg, stb_reg) begin state_next <= state_reg; count_next <= count_reg; clk_next <= clk_reg; stb_next <= stb_reg; case state_reg is when ST_INIT => state_next <= ST_SET_CLK; count_next <= (others => '0'); -- zerar o contador clk_next <= '0'; stb_next <= '0'; when ST_SET_CLK => if en_i = '1' then clk_next <= '1'; state_next <= ST_SET_CLK_LOW; end if; when ST_SET_CLK_LOW => if en_i = '1' then state_next <= ST_VERIFY; clk_next <= '0'; end if; when ST_VERIFY => if count_reg = MAX_VALUE - 1 then state_next <= ST_SET_STB; else count_next <= count_reg + 1; state_next <= ST_SET_CLK; end if; when ST_SET_STB => if en_i = '1' then stb_next <= '1'; state_next <= ST_SET_STB_LOW; end if; when ST_SET_STB_LOW => if en_i = '1' then stb_next <= '0'; state_next <= ST_INIT; end if; end case; end process; end interface_rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/sampler.vhd

13

3330

---------------------------------------------------------------------------------- -- sampler.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Produces samples from la_input applying a programmable divider to the clock. -- Sampling rate can be calculated by: -- -- r = f / (d + 1) -- -- Where r is the sampling rate, f is the clock frequency and d is the value -- programmed into the divider register. -- -- As of version 0.6 sampling on an external clock is also supported. If external -- is set '1', the external clock will be used to sample data. (Divider is -- ignored for this.) -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sampler is port( la_input : in std_logic_vector(31 downto 0); -- 32 la_input channels clock : in std_logic; -- internal clock exClock : in std_logic; -- external clock external : in std_logic; -- clock selection data : in std_logic_vector(23 downto 0); -- configuration data wrDivider : in std_logic; -- write divider register sample : out std_logic_vector(31 downto 0); -- sampled data ready : out std_logic; -- new sample ready trig_delay : out std_logic_vector(1 downto 0); num_scheme : in std_logic ); end sampler; architecture behavioral of sampler is signal divider, counter : std_logic_vector (23 downto 0); signal lastExClock, syncExClock : std_logic; signal la_input_i : std_logic_vector(31 downto 0); begin trig_delay <= "01" when divider = 0 else "10" when divider = 1 else "00"; process(la_input, num_scheme) begin if num_scheme = '1' then for i in 31 downto 0 loop la_input_i(i) <= la_input(31 - i); end loop; else la_input_i <= la_input; end if; end process; -- sample data process(clock) begin if rising_edge(clock) then syncExClock <= exClock; if wrDivider = '1' then divider <= data(23 downto 0); counter <= (others => '0'); ready <= '0'; elsif external = '1' then if syncExClock = '0' and lastExClock = '1' then ready <= '1'; else sample <= la_input_i; ready <= '0'; end if; lastExClock <= syncExClock; elsif counter = divider then sample <= la_input_i; counter <= (others => '0'); ready <= '1'; else counter <= counter + 1; ready <= '0'; end if; end if; end process; end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Benchy/Mem_Gen_36bit.vhd

13

2918

---------------------------------------------------------------------------------- -- Mem_Gen_36bit.vhd -- -- Copyright (C) 2013 Jack Gassett -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://papilio.cc -- -- Single Ported RAM, 36bit wide, depth is configurable. -- -- Set the depth by setting the brams generic variable. -- Depth will be 512 x brams so 12 brams will be 6K depth. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity Mem_Gen_36bit is generic ( brams: integer := 12 ); Port ( CLK : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR (12 downto 0); WE : in STD_LOGIC; DOUT : out STD_LOGIC_VECTOR (35 downto 0); DIN : in STD_LOGIC_VECTOR (35 downto 0)); end Mem_Gen_36bit; architecture Behavioral of Mem_Gen_36bit is type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector((brams-1) downto 0); begin BlockRAMS: for i in 0 to (brams-1) generate RAMB16_S36_inst : RAMB16_S36 generic map ( INIT => X"0", -- Value of output RAM registers at startup SRVAL => X"0", -- Ouput value upon SSR assertion WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE ) port map ( DO => RAMBlDOut(i)(31 downto 0), DOP => RAMBlDOut(i)(35 downto 32), ADDR => ADDR(8 downto 0), -- 8-bit Address Input CLK => CLK, -- Clock DI => DIN(31 downto 0), DIP => DIN(35 downto 32), EN => '1', -- RAM Enable Input SSR => '0', -- Synchronous Set/Reset Input WE => WEB(i) -- Write Enable Input ); end generate; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0'; end generate ; dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9))); end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/clk_32to100_pll.vhd

13

5098

-- file: clk_32to100_pll.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to100_pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to100_pll; architecture xilinx of clk_32to100_pll is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_pll,clk_wiz_v3_6,{component_name=clk_32to100_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering / unused connectors signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1_unused : std_logic; signal clkout2_unused : std_logic; signal clkout3_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; -- Unused status signals signal locked_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1 <= CLK_IN1; -- Clocking primitive -------------------------------------- -- Instantiation of the PLL primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 2, CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 31.250, REF_JITTER => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKOUT0 => clkout0, CLKOUT1 => clkout1_unused, CLKOUT2 => clkout2_unused, CLKOUT3 => clkout3_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, LOCKED => locked_unused, RST => '0', -- Input clock control CLKFBIN => clkfbout, CLKIN => clkin1); -- Output buffering ------------------------------------- clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkout0); end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/clk_32to100_pll.vhd

13

5098

-- file: clk_32to100_pll.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to100_pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to100_pll; architecture xilinx of clk_32to100_pll is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_pll,clk_wiz_v3_6,{component_name=clk_32to100_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering / unused connectors signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1_unused : std_logic; signal clkout2_unused : std_logic; signal clkout3_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; -- Unused status signals signal locked_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1 <= CLK_IN1; -- Clocking primitive -------------------------------------- -- Instantiation of the PLL primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 2, CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 31.250, REF_JITTER => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKOUT0 => clkout0, CLKOUT1 => clkout1_unused, CLKOUT2 => clkout2_unused, CLKOUT3 => clkout3_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, LOCKED => locked_unused, RST => '0', -- Input clock control CLKFBIN => clkfbout, CLKIN => clkin1); -- Output buffering ------------------------------------- clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkout0); end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Wishbone_Peripherals/clk_32to100_pll.vhd

13

5098

-- file: clk_32to100_pll.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to100_pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to100_pll; architecture xilinx of clk_32to100_pll is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to100_pll,clk_wiz_v3_6,{component_name=clk_32to100_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering / unused connectors signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1_unused : std_logic; signal clkout2_unused : std_logic; signal clkout3_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; -- Unused status signals signal locked_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1 <= CLK_IN1; -- Clocking primitive -------------------------------------- -- Instantiation of the PLL primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 2, CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 31.250, REF_JITTER => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKOUT0 => clkout0, CLKOUT1 => clkout1_unused, CLKOUT2 => clkout2_unused, CLKOUT3 => clkout3_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, LOCKED => locked_unused, RST => '0', -- Input clock control CLKFBIN => clkfbout, CLKIN => clkin1); -- Output buffering ------------------------------------- clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkout0); end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/MISC_zpuino_sa_splitter4.vhd

13

1175

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09:01:17 11/27/2013 -- Design Name: -- Module Name: MISC_zpuino_sa_splitter4 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MISC_zpuino_sa_splitter4 is Port ( in1 : in STD_LOGIC; out1 : out STD_LOGIC; out2 : out STD_LOGIC; out3 : out STD_LOGIC; out4 : out STD_LOGIC); end MISC_zpuino_sa_splitter4; architecture Behavioral of MISC_zpuino_sa_splitter4 is begin out1 <= in1; out2 <= in1; out3 <= in1; out4 <= in1; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/wbbootloadermux.vhd

13

2734

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbbootloadermux is generic ( address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; sel: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; m_wb_stall_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; s0_wb_stall_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(11 downto 2); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic; s1_wb_stall_i: in std_logic ); end entity wbbootloadermux; architecture behave of wbbootloadermux is signal select_zero: std_logic; begin select_zero<='0' when sel='1' else '1'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i(11 downto 2); s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i,s0_wb_stall_i,s1_wb_stall_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; m_wb_stall_o<=s1_wb_stall_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; m_wb_stall_o<=s0_wb_stall_i; end if; end process; end behave;

mit

mwswartwout/EECS318

hw3/problem1/CSA.vhd

1

281

entity CSA is port ( Sout : out bit; Cout : out bit; Sin : in bit; A : in bit; B : in bit; Cin : in bit); end CSA; architecture CSA_arch of CSA is begin Sout <= (A AND B) XOR Sin XOR Cin; Cout <= ((A AND B) AND Sin) OR (Cin AND ((A AND B) XOR Sin)); end CSA_arch;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/spi_receiver.vhd

13

4025

---------------------------------------------------------------------------------- -- spi_receiver.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Receives commands from the SPI port. The first byte is the command -- opcode, the following (optional) four byte are the command data. -- Commands that do not have the highest bit in their opcode set are -- considered short commands without data (1 byte long). All other commands are -- long commands which are 5 bytes long. -- -- After a full command has been received the data it will be latched until the -- next command is issued. A valid command can be detected by checking if the -- execute output is set. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity spi_receiver is port( rx : in std_logic; clock : in std_logic; sclk : in std_logic; cmd : out std_logic_vector (39 downto 0); execute : out std_logic; reset : in std_logic; cs : in std_logic ); end spi_receiver; architecture behavioral of spi_receiver is type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA); signal state: states; signal rx_buf : std_logic_vector(7 downto 0); signal data_buf : std_logic_vector(31 downto 0); signal bits : integer range 0 to 8; signal bytes : integer range 0 to 4; signal code : std_logic_vector (7 downto 0); signal data : std_logic_vector (31 downto 0); signal exec : std_logic := '0'; signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0); begin cmd <= data & code; process(clock) begin if rising_edge(clock) then execute <= exec; rsync_sclk <= rsync_sclk(0) & sclk; rsync_cs <= rsync_cs(0) & cs; case state is when IDLE => -- cs falling edge starts rx if rsync_cs = "10" then state <= READ_OPCODE; end if; rx_buf <= (others => '0'); data_buf <= (others => '0'); bits <= 0; bytes <= 0; exec <= '0'; when READ_OPCODE => -- read bit at sclk rising edge if reset = '1' then state <= IDLE; elsif rsync_sclk = "01" then rx_buf <= rx_buf(6 downto 0) & rx; bits <= bits + 1; elsif bits = 8 then -- if hi bit is set then wait for cmd data if rx_buf(7) = '1' then state <= WAIT_CS; else state <= IDLE; exec <= '1'; end if; code <= rx_buf; end if; when WAIT_CS => -- wait for cs falling edge before reading next data if reset = '1' then state <= IDLE; elsif rsync_cs = "10" then state <= READ_DATA; bytes <= bytes + 1; elsif bytes = 4 then state <= IDLE; data <= data_buf; exec <= '1'; end if; rx_buf <= (others => '0'); bits <= 0; when READ_DATA => -- read bit at sclk rising edge if reset = '1' then state <= IDLE; elsif rsync_sclk = "01" then rx_buf <= rx_buf(6 downto 0) & rx; bits <= bits + 1; elsif bits = 8 then state <= WAIT_CS; data_buf <= rx_buf & data_buf(31 downto 8); end if; end case; end if; end process; end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_250k/zpuino_config.vhd

13

2570

-- -- Configuration file for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpuino_config is -- General ZPUino configuration type zpu_core_type is ( small, large ); -- ZPUino large is buggy, don't use it. constant zpuinocore: zpu_core_type := small; -- Set iobusyinput to 'true' to allow registered input to IO core. This also allows for IO -- to become busy without needing to register its inputs. However, an extra clock-cycle is -- required to access IO if this is used. constant zpuino_iobusyinput: boolean := true; -- For SPI blocking operation, you need to define also iobusyinput constant zpuino_spiblocking: boolean := true; -- Number of GPIO to map (number of FPGA pins) constant zpuino_gpio_count: integer := 49; -- Peripheral Pin Select constant zpuino_pps_enabled: boolean := false; -- Internal SPI ADC constant zpuino_adc_enabled: boolean := true; -- Number of IO select bits. Maps to maximum number of IO devices constant zpuino_number_io_select_bits: integer := 4; end package zpuino_config;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/clk_32to288_dcm.vhd

13

6306

-- file: clk_32to288_dcm.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1____50.000______0.000______50.0______600.000____150.000 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary__________32.000____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to288_dcm is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to288_dcm; architecture xilinx of clk_32to288_dcm is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering signal clkfb : std_logic; signal clk0 : std_logic; signal clkfx : std_logic; signal clkfbout : std_logic; signal locked_internal : std_logic; signal status_internal : std_logic_vector(7 downto 0); begin -- Input buffering -------------------------------------- --clkin1 <= CLK_IN1; clkin2_inst: BUFG port map ( I => CLK_IN1, O => clkin1 ); -- Clocking primitive -------------------------------------- -- Instantiation of the DCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused dcm_sp_inst: DCM_SP generic map (CLKDV_DIVIDE => 2.000, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 9, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.25, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map -- Input clock (CLKIN => clkin1, CLKFB => clkfb, -- Output clocks CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKFX => clkfx, CLKFX180 => open, CLKDV => open, -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => locked_internal, STATUS => status_internal, RST => '0', -- Unused pin, tie low DSSEN => '0'); -- Output buffering ------------------------------------- -- no phase alignment active, connect to ground clkfb <= '0'; -- clkout1_buf : BUFG -- port map -- (O => CLK_OUT1, -- I => clkfx); CLK_OUT1 <= clkfx; end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Benchy/flags.vhd

13

2535

---------------------------------------------------------------------------------- -- flags.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Flags register. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity flags is port( data : in std_logic_vector(10 downto 0); clock : in std_logic; write : in std_logic; demux : out std_logic; filter : out std_logic; external : out std_logic; inverted : out std_logic; disabledGroups : out std_logic_vector (3 downto 0); rle : out std_logic; test_mode : out std_logic; data_size : out std_logic_vector (1 downto 0); num_scheme : out std_logic ); end flags; architecture behavioral of flags is signal ds : std_logic_vector (1 downto 0); begin -- write flags process (clock) begin if rising_edge(clock) then if write = '1' then demux <= data(0); filter <= data(1); external <= data(6); inverted <= data(7); disabledGroups <= data(5 downto 2); rle <= data(8); num_scheme <= data(9); test_mode <= data(10); data_size <= ds; end if; end if; end process; ds <= "01" when data(5 downto 2) = "1110" else "01" when data(5 downto 2) = "1101" else "01" when data(5 downto 2) = "1011" else "01" when data(5 downto 2) = "0111" else "10" when data(5 downto 2) = "1100" else "10" when data(5 downto 2) = "1010" else "10" when data(5 downto 2) = "0110" else "10" when data(5 downto 2) = "1001" else "10" when data(5 downto 2) = "0101" else "10" when data(5 downto 2) = "0011" else "00"; end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_Pro/sdram_hamster.vhd

14

25283

------------------------------------------------------ -- FSM for a SDRAM controller -- -- Version 0.1 - Ready to simulate -- -- Author: Mike Field (hamster@snap.net.nz) -- -- Feel free to use it however you would like, but -- just drop me an email to say thanks. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sdram_controller is generic ( HIGH_BIT: integer := 24; MHZ: integer := 96; REFRESH_CYCLES: integer := 4096; ADDRESS_BITS: integer := 12 ); PORT ( clock_100: in std_logic; clock_100_delayed_3ns: in std_logic; rst: in std_logic; -- Signals to/from the SDRAM chip DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC; pending: out std_logic; --- Inputs from rest of the system address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); req_read : IN STD_LOGIC; req_write : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR (31 downto 0); data_out_valid : OUT STD_LOGIC; data_in : IN STD_LOGIC_VECTOR (31 downto 0); data_mask : IN STD_LOGIC_VECTOR (3 downto 0) ); end entity; architecture rtl of sdram_controller is type reg is record address : std_logic_vector(ADDRESS_BITS-1 downto 0); bank : std_logic_vector( 1 downto 0); init_counter : std_logic_vector(14 downto 0); rf_counter : integer; rf_pending : std_logic; rd_pending : std_logic; wr_pending : std_logic; act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); act_ba : std_logic_vector(1 downto 0); data_out_low : std_logic_vector(15 downto 0); req_addr_q : std_logic_vector(HIGH_BIT downto 2); req_data_write: std_logic_vector(31 downto 0); req_mask : std_logic_vector(3 downto 0); data_out_valid: std_logic; dq_masks : std_logic_vector(1 downto 0); tristate : std_logic; end record; signal r : reg; signal n : reg; signal rstate : std_logic_vector(8 downto 0); signal nstate : std_logic_vector(8 downto 0); signal rdata_write : std_logic_vector(15 downto 0); signal ndata_write : std_logic_vector(15 downto 0); -- Vectors for each SDRAM 'command' --- CS_N, RAS_N, CAS_N, WE_N constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. constant cmd_write : std_logic_vector(3 downto 0) := "0100"; constant cmd_act : std_logic_vector(3 downto 0) := "0011"; constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set -- State assignments constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); signal addr_bank: std_logic_vector(1 downto 0); constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width signal addr_col : std_logic_vector(7 downto 0); signal captured : std_logic_vector(15 downto 0); signal busy: std_logic; constant tOPD: time := 2.1 ns; constant tHZ: time := 8 ns; signal dram_dq_dly : std_logic_vector(15 downto 0); -- Debug only signal debug_cmd: std_logic_vector(3 downto 0); signal not_clock_100_delayed_3ns: std_logic; constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; attribute IOB: string; signal i_DRAM_CS_N: std_logic; attribute IOB of i_DRAM_CS_N: signal is "true"; signal i_DRAM_RAS_N: std_logic; attribute IOB of i_DRAM_RAS_N: signal is "true"; signal i_DRAM_CAS_N: std_logic; attribute IOB of i_DRAM_CAS_N: signal is "true"; signal i_DRAM_WE_N: std_logic; attribute IOB of i_DRAM_WE_N: signal is "true"; signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); attribute IOB of i_DRAM_ADDR: signal is "true"; signal i_DRAM_BA: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_BA: signal is "true"; signal i_DRAM_DQM: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_DQM: signal is "true"; attribute IOB of rdata_write: signal is "true"; attribute IOB of captured: signal is "true"; signal i_DRAM_CLK: std_logic; attribute fsm_encoding: string; attribute fsm_encoding of nstate: signal is "user"; attribute fsm_encoding of rstate: signal is "user"; begin debug_cmd <= rstate(3 downto 0); -- Addressing is in 32 bit words - twice that of the DRAM width, -- so each burst of four access two system words. --addr_row <= address(23 downto 11); --addr_bank <= address(10 downto 9); process(r.req_addr_q) begin addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); -- (24-2) downto (24-2 - 2 - 13 - 1) -- 22 downto 6 addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); r.req_addr_q(ADDRESS_BITS-1+9 downto 9); addr_col <= (others => '0'); addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; r.req_addr_q(8 downto 2) & "0"; end process; not_clock_100_delayed_3ns <= not clock_100_delayed_3ns; clock: ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "ASYNC") port map ( D0 => '1', D1 => '0', Q => i_DRAM_CLK, C0 => clock_100_delayed_3ns, C1 => not_clock_100_delayed_3ns, CE => '1', R => '0', S => '0' ); DRAM_CKE <= '1'; DRAM_CLK <= transport i_DRAM_CLK after tOPD; i_DRAM_CS_N <= transport rstate(3) after tOPD; DRAM_CS_N <= i_DRAM_CS_N; i_DRAM_RAS_N <= transport rstate(2) after tOPD; DRAM_RAS_N <= i_DRAM_RAS_N; i_DRAM_CAS_N <= transport rstate(1) after tOPD; DRAM_CAS_N <= i_DRAM_CAS_N; i_DRAM_WE_N <= transport rstate(0) after tOPD; DRAM_WE_N <= i_DRAM_WE_N; i_DRAM_ADDR <= transport r.address after tOPD; DRAM_ADDR <= i_DRAM_ADDR; i_DRAM_BA <= transport r.bank after tOPD; DRAM_BA <= i_DRAM_BA; i_DRAM_DQM <= transport r.dq_masks after tOPD; DRAM_DQM <= i_DRAM_DQM; DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; data_out_valid <= r.data_out_valid; DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) begin -- copy the existing values n <= r; nstate <= rstate; ndata_write <= rdata_write; if req_read = '1' then n.rd_pending <= '1'; if r.rd_pending='0' then n.req_addr_q <= address; end if; end if; if req_write = '1' then n.wr_pending <= '1'; if r.wr_pending='0' then n.req_addr_q <= address; -- Queue data here n.req_data_write <= data_in; n.req_mask <= data_mask; end if; end if; n.dq_masks <= "11"; -- first off, do we need to perform a refresh cycle ASAP? if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns n.rf_counter <= 0; n.rf_pending <= '1'; else -- only start looking for refreshes outside of the initialisation state. if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then n.rf_counter <= r.rf_counter + 1; end if; end if; -- Set the data bus into HIZ, high and low bytes masked --DRAM_DQ <= (others => 'Z'); n.tristate <= '0'; n.init_counter <= r.init_counter-1; --ndata_write <= (others => DontCareValue); n.data_out_valid <= '0'; -- alvie- here, no ? -- Process the FSM case rstate(8 downto 4) is when s_init_nop_id => --s_init_nop(8 downto 4) => nstate <= s_init_nop; n.address <= (others => '0'); n.bank <= (others => '0'); n.act_ba <= (others => '0'); n.rf_counter <= 0; -- n.data_out_valid <= '1'; -- alvie- not here -- T-130, precharge all banks. if r.init_counter = "000000010000010" then nstate <= s_init_pre; n.address(10) <= '1'; end if; -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then nstate <= s_init_ref; end if; -- T-3, the load mode register if r.init_counter = 3 then nstate <= s_init_mrs; -- Mode register is as follows: -- resvd wr_b OpMd CAS=3 Seq bust=1 n.address <= "00" & "0" & "00" & "011" & "0" & "000"; -- resvd n.bank <= "00"; end if; -- T-1 The switch to the FSM (first command will be a NOP if r.init_counter = 1 then nstate <= s_idle; end if; ------------------------------ -- The Idle section ------------------------------ when s_idle_id => nstate <= s_idle; -- do we have to activate a row? if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; -- refreshes take priority over everything if r.rf_pending = '1' then nstate <= s_rf0; n.rf_pending <= '0'; end if; ------------------------------ -- Row activation -- s_ra2 is also the "idle with active row" state and provides -- a resting point between operations on the same row ------------------------------ when s_ra0_id => nstate <= s_ra1; when s_ra1_id => nstate <= s_ra2; when s_ra2_id=> -- we can stay in this state until we have something to do nstate <= s_ra2; n.tristate<='0'; if r.rf_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; else -- If there is a read pending, deactivate the row if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; end if; -- unless we have a read to perform on the same row? do that instead if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_rd0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks <= "00"; n.rd_pending <= '0'; --n.tristate<='1'; end if; -- unless we have a write on the same row? writes take priroty over reads if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_wr0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; ndata_write <= r.req_data_write(31 downto 16); n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= not r.req_mask(3 downto 2); n.wr_pending <= '0'; --n.tristate <= '0'; end if; end if; -- nstate <= s_dr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- n.wr_pending <= r.wr_pending; --n.tristate <= '0'; --end if; ------------------------------------------------------ -- Deactivate the current row and return to idle state ------------------------------------------------------ when s_dr0_id => nstate <= s_dr1; when s_dr1_id => nstate <= s_idle; ------------------------------ -- The Refresh section ------------------------------ when s_rf0_id => nstate <= s_rf1; when s_rf1_id => nstate <= s_rf2; when s_rf2_id => nstate <= s_rf3; when s_rf3_id => nstate <= s_rf4; when s_rf4_id => nstate <= s_rf5; when s_rf5_id => nstate <= s_idle; ------------------------------ -- The Write section ------------------------------ when s_wr0_id => nstate <= s_wr3; n.bank <= addr_bank; n.address(0) <= '1'; ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); --DRAM_DQ <= rdata_write; n.dq_masks<= not r.req_mask(1 downto 0); n.tristate <= '0'; when s_wr1_id => null; when s_wr2_id => nstate <= s_dr0; n.address(10) <= '1'; when s_wr3_id => -- Default to the idle+row active state nstate <= s_ra2; --DRAM_DQ <= rdata_write; n.data_out_valid<='1'; -- alvie- ack write n.tristate <= '0'; n.dq_masks<= "11"; -- If there is a read or write then deactivate the row --if r.rd_pending = '1' or r.wr_pending = '1' then -- nstate <= s_dr0; -- n.address(10) <= '1'; --end if; -- But if there is a read pending in the same row, do that --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_rd0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; -- --n.act_ba <= addr_bank; -- n.dq_masks <= "00"; -- n.rd_pending <= '0'; --end if; -- unless there is a write pending in the same row, do that --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_wr0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; --n.act_ba <= addr_bank; -- n.dq_masks<= "00"; -- n.wr_pending <= '0'; --end if; -- But always try and refresh if one is pending! if r.rf_pending = '1' then nstate <= s_wr2; --dr0; --n.address(10) <= '1'; end if; ------------------------------ -- The Read section ------------------------------ when s_rd0_id => -- 10001 nstate <= s_rd1; n.tristate<='1'; n.dq_masks <= "00"; n.address(0)<='1'; when s_rd1_id => -- 10010 nstate <= s_rd2; n.dq_masks <= "00"; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd3; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; end if; when s_rd2_id => -- 10011 nstate <= s_rd7; n.dq_masks <= "00"; n.tristate<='1'; when s_rd3_id => -- 10100 nstate <= s_rd4; n.dq_masks <= "00"; n.address(0) <= '1'; n.tristate<='1'; -- Data is still not ready... when s_rd4_id => -- 10101 nstate <= s_rd5; n.dq_masks <= "00"; --n.address(0)<='1'; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd5; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; else nstate <= s_rd6; -- NOTE: not correct end if; --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- Keep request --end if; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_rd5_id => -- If a refresh is pending then always deactivate the row --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; --end if; n.address(0) <= '1'; nstate <= s_rd4; -- Another request came, and we can pipeline - n.dq_masks <= "00"; n.tristate<='1'; when s_rd6_id => nstate <= s_rd7; n.dq_masks<= "00"; n.tristate<='1'; when s_rd7_id => nstate <= s_ra2; n.data_out_low <= captured; n.data_out_valid <= '1'; n.tristate<='1'; when s_rd8_id => null; when s_rd9_id => null; -- The Deactivate row during read section ------------------------------ when s_drdr0_id => nstate <= s_drdr1; when s_drdr1_id => nstate <= s_drdr2; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_drdr2_id => nstate <= s_idle; if r.rf_pending = '1' then nstate <= s_rf0; end if; if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; when others => nstate <= s_init_nop; end case; end process; --- The clock driven logic process (clock_100, n) begin if clock_100'event and clock_100 = '1' then if rst='1' then rstate <= (others => '0'); r.address <= (others => '0'); r.bank <= (others => '0'); r.init_counter <= "100000000000000"; -- synopsys translate_off r.init_counter <= "000000100000000"; -- synopsys translate_on r.rf_counter <= 0; r.rf_pending <= '0'; r.rd_pending <= '0'; r.wr_pending <= '0'; r.act_row <= (others => '0'); r.data_out_low <= (others => '0'); r.data_out_valid <= '0'; r.dq_masks <= "11"; r.tristate<='1'; else r <= n; rstate <= nstate; rdata_write <= ndata_write; end if; end if; end process; dram_dq_dly <= transport dram_dq after 1.9 ns; -- process (clock_100_delayed_3ns, dram_dq_dly) -- begin -- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then -- captured <= dram_dq_dly; -- end if; -- end process; process (clock_100) begin if falling_edge(clock_100) then captured <= dram_dq_dly; end if; end process; end rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/board_Papilio_Pro/sdram_hamster.vhd

14

25283

------------------------------------------------------ -- FSM for a SDRAM controller -- -- Version 0.1 - Ready to simulate -- -- Author: Mike Field (hamster@snap.net.nz) -- -- Feel free to use it however you would like, but -- just drop me an email to say thanks. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sdram_controller is generic ( HIGH_BIT: integer := 24; MHZ: integer := 96; REFRESH_CYCLES: integer := 4096; ADDRESS_BITS: integer := 12 ); PORT ( clock_100: in std_logic; clock_100_delayed_3ns: in std_logic; rst: in std_logic; -- Signals to/from the SDRAM chip DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC; pending: out std_logic; --- Inputs from rest of the system address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); req_read : IN STD_LOGIC; req_write : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR (31 downto 0); data_out_valid : OUT STD_LOGIC; data_in : IN STD_LOGIC_VECTOR (31 downto 0); data_mask : IN STD_LOGIC_VECTOR (3 downto 0) ); end entity; architecture rtl of sdram_controller is type reg is record address : std_logic_vector(ADDRESS_BITS-1 downto 0); bank : std_logic_vector( 1 downto 0); init_counter : std_logic_vector(14 downto 0); rf_counter : integer; rf_pending : std_logic; rd_pending : std_logic; wr_pending : std_logic; act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); act_ba : std_logic_vector(1 downto 0); data_out_low : std_logic_vector(15 downto 0); req_addr_q : std_logic_vector(HIGH_BIT downto 2); req_data_write: std_logic_vector(31 downto 0); req_mask : std_logic_vector(3 downto 0); data_out_valid: std_logic; dq_masks : std_logic_vector(1 downto 0); tristate : std_logic; end record; signal r : reg; signal n : reg; signal rstate : std_logic_vector(8 downto 0); signal nstate : std_logic_vector(8 downto 0); signal rdata_write : std_logic_vector(15 downto 0); signal ndata_write : std_logic_vector(15 downto 0); -- Vectors for each SDRAM 'command' --- CS_N, RAS_N, CAS_N, WE_N constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. constant cmd_write : std_logic_vector(3 downto 0) := "0100"; constant cmd_act : std_logic_vector(3 downto 0) := "0011"; constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set -- State assignments constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); signal addr_bank: std_logic_vector(1 downto 0); constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width signal addr_col : std_logic_vector(7 downto 0); signal captured : std_logic_vector(15 downto 0); signal busy: std_logic; constant tOPD: time := 2.1 ns; constant tHZ: time := 8 ns; signal dram_dq_dly : std_logic_vector(15 downto 0); -- Debug only signal debug_cmd: std_logic_vector(3 downto 0); signal not_clock_100_delayed_3ns: std_logic; constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; attribute IOB: string; signal i_DRAM_CS_N: std_logic; attribute IOB of i_DRAM_CS_N: signal is "true"; signal i_DRAM_RAS_N: std_logic; attribute IOB of i_DRAM_RAS_N: signal is "true"; signal i_DRAM_CAS_N: std_logic; attribute IOB of i_DRAM_CAS_N: signal is "true"; signal i_DRAM_WE_N: std_logic; attribute IOB of i_DRAM_WE_N: signal is "true"; signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); attribute IOB of i_DRAM_ADDR: signal is "true"; signal i_DRAM_BA: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_BA: signal is "true"; signal i_DRAM_DQM: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_DQM: signal is "true"; attribute IOB of rdata_write: signal is "true"; attribute IOB of captured: signal is "true"; signal i_DRAM_CLK: std_logic; attribute fsm_encoding: string; attribute fsm_encoding of nstate: signal is "user"; attribute fsm_encoding of rstate: signal is "user"; begin debug_cmd <= rstate(3 downto 0); -- Addressing is in 32 bit words - twice that of the DRAM width, -- so each burst of four access two system words. --addr_row <= address(23 downto 11); --addr_bank <= address(10 downto 9); process(r.req_addr_q) begin addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); -- (24-2) downto (24-2 - 2 - 13 - 1) -- 22 downto 6 addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); r.req_addr_q(ADDRESS_BITS-1+9 downto 9); addr_col <= (others => '0'); addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; r.req_addr_q(8 downto 2) & "0"; end process; not_clock_100_delayed_3ns <= not clock_100_delayed_3ns; clock: ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "ASYNC") port map ( D0 => '1', D1 => '0', Q => i_DRAM_CLK, C0 => clock_100_delayed_3ns, C1 => not_clock_100_delayed_3ns, CE => '1', R => '0', S => '0' ); DRAM_CKE <= '1'; DRAM_CLK <= transport i_DRAM_CLK after tOPD; i_DRAM_CS_N <= transport rstate(3) after tOPD; DRAM_CS_N <= i_DRAM_CS_N; i_DRAM_RAS_N <= transport rstate(2) after tOPD; DRAM_RAS_N <= i_DRAM_RAS_N; i_DRAM_CAS_N <= transport rstate(1) after tOPD; DRAM_CAS_N <= i_DRAM_CAS_N; i_DRAM_WE_N <= transport rstate(0) after tOPD; DRAM_WE_N <= i_DRAM_WE_N; i_DRAM_ADDR <= transport r.address after tOPD; DRAM_ADDR <= i_DRAM_ADDR; i_DRAM_BA <= transport r.bank after tOPD; DRAM_BA <= i_DRAM_BA; i_DRAM_DQM <= transport r.dq_masks after tOPD; DRAM_DQM <= i_DRAM_DQM; DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; data_out_valid <= r.data_out_valid; DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) begin -- copy the existing values n <= r; nstate <= rstate; ndata_write <= rdata_write; if req_read = '1' then n.rd_pending <= '1'; if r.rd_pending='0' then n.req_addr_q <= address; end if; end if; if req_write = '1' then n.wr_pending <= '1'; if r.wr_pending='0' then n.req_addr_q <= address; -- Queue data here n.req_data_write <= data_in; n.req_mask <= data_mask; end if; end if; n.dq_masks <= "11"; -- first off, do we need to perform a refresh cycle ASAP? if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns n.rf_counter <= 0; n.rf_pending <= '1'; else -- only start looking for refreshes outside of the initialisation state. if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then n.rf_counter <= r.rf_counter + 1; end if; end if; -- Set the data bus into HIZ, high and low bytes masked --DRAM_DQ <= (others => 'Z'); n.tristate <= '0'; n.init_counter <= r.init_counter-1; --ndata_write <= (others => DontCareValue); n.data_out_valid <= '0'; -- alvie- here, no ? -- Process the FSM case rstate(8 downto 4) is when s_init_nop_id => --s_init_nop(8 downto 4) => nstate <= s_init_nop; n.address <= (others => '0'); n.bank <= (others => '0'); n.act_ba <= (others => '0'); n.rf_counter <= 0; -- n.data_out_valid <= '1'; -- alvie- not here -- T-130, precharge all banks. if r.init_counter = "000000010000010" then nstate <= s_init_pre; n.address(10) <= '1'; end if; -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then nstate <= s_init_ref; end if; -- T-3, the load mode register if r.init_counter = 3 then nstate <= s_init_mrs; -- Mode register is as follows: -- resvd wr_b OpMd CAS=3 Seq bust=1 n.address <= "00" & "0" & "00" & "011" & "0" & "000"; -- resvd n.bank <= "00"; end if; -- T-1 The switch to the FSM (first command will be a NOP if r.init_counter = 1 then nstate <= s_idle; end if; ------------------------------ -- The Idle section ------------------------------ when s_idle_id => nstate <= s_idle; -- do we have to activate a row? if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; -- refreshes take priority over everything if r.rf_pending = '1' then nstate <= s_rf0; n.rf_pending <= '0'; end if; ------------------------------ -- Row activation -- s_ra2 is also the "idle with active row" state and provides -- a resting point between operations on the same row ------------------------------ when s_ra0_id => nstate <= s_ra1; when s_ra1_id => nstate <= s_ra2; when s_ra2_id=> -- we can stay in this state until we have something to do nstate <= s_ra2; n.tristate<='0'; if r.rf_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; else -- If there is a read pending, deactivate the row if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; end if; -- unless we have a read to perform on the same row? do that instead if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_rd0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks <= "00"; n.rd_pending <= '0'; --n.tristate<='1'; end if; -- unless we have a write on the same row? writes take priroty over reads if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_wr0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; ndata_write <= r.req_data_write(31 downto 16); n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= not r.req_mask(3 downto 2); n.wr_pending <= '0'; --n.tristate <= '0'; end if; end if; -- nstate <= s_dr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- n.wr_pending <= r.wr_pending; --n.tristate <= '0'; --end if; ------------------------------------------------------ -- Deactivate the current row and return to idle state ------------------------------------------------------ when s_dr0_id => nstate <= s_dr1; when s_dr1_id => nstate <= s_idle; ------------------------------ -- The Refresh section ------------------------------ when s_rf0_id => nstate <= s_rf1; when s_rf1_id => nstate <= s_rf2; when s_rf2_id => nstate <= s_rf3; when s_rf3_id => nstate <= s_rf4; when s_rf4_id => nstate <= s_rf5; when s_rf5_id => nstate <= s_idle; ------------------------------ -- The Write section ------------------------------ when s_wr0_id => nstate <= s_wr3; n.bank <= addr_bank; n.address(0) <= '1'; ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); --DRAM_DQ <= rdata_write; n.dq_masks<= not r.req_mask(1 downto 0); n.tristate <= '0'; when s_wr1_id => null; when s_wr2_id => nstate <= s_dr0; n.address(10) <= '1'; when s_wr3_id => -- Default to the idle+row active state nstate <= s_ra2; --DRAM_DQ <= rdata_write; n.data_out_valid<='1'; -- alvie- ack write n.tristate <= '0'; n.dq_masks<= "11"; -- If there is a read or write then deactivate the row --if r.rd_pending = '1' or r.wr_pending = '1' then -- nstate <= s_dr0; -- n.address(10) <= '1'; --end if; -- But if there is a read pending in the same row, do that --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_rd0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; -- --n.act_ba <= addr_bank; -- n.dq_masks <= "00"; -- n.rd_pending <= '0'; --end if; -- unless there is a write pending in the same row, do that --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_wr0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; --n.act_ba <= addr_bank; -- n.dq_masks<= "00"; -- n.wr_pending <= '0'; --end if; -- But always try and refresh if one is pending! if r.rf_pending = '1' then nstate <= s_wr2; --dr0; --n.address(10) <= '1'; end if; ------------------------------ -- The Read section ------------------------------ when s_rd0_id => -- 10001 nstate <= s_rd1; n.tristate<='1'; n.dq_masks <= "00"; n.address(0)<='1'; when s_rd1_id => -- 10010 nstate <= s_rd2; n.dq_masks <= "00"; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd3; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; end if; when s_rd2_id => -- 10011 nstate <= s_rd7; n.dq_masks <= "00"; n.tristate<='1'; when s_rd3_id => -- 10100 nstate <= s_rd4; n.dq_masks <= "00"; n.address(0) <= '1'; n.tristate<='1'; -- Data is still not ready... when s_rd4_id => -- 10101 nstate <= s_rd5; n.dq_masks <= "00"; --n.address(0)<='1'; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd5; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; else nstate <= s_rd6; -- NOTE: not correct end if; --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- Keep request --end if; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_rd5_id => -- If a refresh is pending then always deactivate the row --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; --end if; n.address(0) <= '1'; nstate <= s_rd4; -- Another request came, and we can pipeline - n.dq_masks <= "00"; n.tristate<='1'; when s_rd6_id => nstate <= s_rd7; n.dq_masks<= "00"; n.tristate<='1'; when s_rd7_id => nstate <= s_ra2; n.data_out_low <= captured; n.data_out_valid <= '1'; n.tristate<='1'; when s_rd8_id => null; when s_rd9_id => null; -- The Deactivate row during read section ------------------------------ when s_drdr0_id => nstate <= s_drdr1; when s_drdr1_id => nstate <= s_drdr2; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_drdr2_id => nstate <= s_idle; if r.rf_pending = '1' then nstate <= s_rf0; end if; if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; when others => nstate <= s_init_nop; end case; end process; --- The clock driven logic process (clock_100, n) begin if clock_100'event and clock_100 = '1' then if rst='1' then rstate <= (others => '0'); r.address <= (others => '0'); r.bank <= (others => '0'); r.init_counter <= "100000000000000"; -- synopsys translate_off r.init_counter <= "000000100000000"; -- synopsys translate_on r.rf_counter <= 0; r.rf_pending <= '0'; r.rd_pending <= '0'; r.wr_pending <= '0'; r.act_row <= (others => '0'); r.data_out_low <= (others => '0'); r.data_out_valid <= '0'; r.dq_masks <= "11"; r.tristate<='1'; else r <= n; rstate <= nstate; rdata_write <= ndata_write; end if; end if; end process; dram_dq_dly <= transport dram_dq after 1.9 ns; -- process (clock_100_delayed_3ns, dram_dq_dly) -- begin -- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then -- captured <= dram_dq_dly; -- end if; -- end process; process (clock_100) begin if falling_edge(clock_100) then captured <= dram_dq_dly; end if; end process; end rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_Pro/sdram_hamster.vhd

14

25283

------------------------------------------------------ -- FSM for a SDRAM controller -- -- Version 0.1 - Ready to simulate -- -- Author: Mike Field (hamster@snap.net.nz) -- -- Feel free to use it however you would like, but -- just drop me an email to say thanks. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sdram_controller is generic ( HIGH_BIT: integer := 24; MHZ: integer := 96; REFRESH_CYCLES: integer := 4096; ADDRESS_BITS: integer := 12 ); PORT ( clock_100: in std_logic; clock_100_delayed_3ns: in std_logic; rst: in std_logic; -- Signals to/from the SDRAM chip DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0); DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); DRAM_CAS_N : OUT STD_LOGIC; DRAM_CKE : OUT STD_LOGIC; DRAM_CLK : OUT STD_LOGIC; DRAM_CS_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); DRAM_RAS_N : OUT STD_LOGIC; DRAM_WE_N : OUT STD_LOGIC; pending: out std_logic; --- Inputs from rest of the system address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2); req_read : IN STD_LOGIC; req_write : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR (31 downto 0); data_out_valid : OUT STD_LOGIC; data_in : IN STD_LOGIC_VECTOR (31 downto 0); data_mask : IN STD_LOGIC_VECTOR (3 downto 0) ); end entity; architecture rtl of sdram_controller is type reg is record address : std_logic_vector(ADDRESS_BITS-1 downto 0); bank : std_logic_vector( 1 downto 0); init_counter : std_logic_vector(14 downto 0); rf_counter : integer; rf_pending : std_logic; rd_pending : std_logic; wr_pending : std_logic; act_row : std_logic_vector(ADDRESS_BITS-1 downto 0); act_ba : std_logic_vector(1 downto 0); data_out_low : std_logic_vector(15 downto 0); req_addr_q : std_logic_vector(HIGH_BIT downto 2); req_data_write: std_logic_vector(31 downto 0); req_mask : std_logic_vector(3 downto 0); data_out_valid: std_logic; dq_masks : std_logic_vector(1 downto 0); tristate : std_logic; end record; signal r : reg; signal n : reg; signal rstate : std_logic_vector(8 downto 0); signal nstate : std_logic_vector(8 downto 0); signal rdata_write : std_logic_vector(15 downto 0); signal ndata_write : std_logic_vector(15 downto 0); -- Vectors for each SDRAM 'command' --- CS_N, RAS_N, CAS_N, WE_N constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. constant cmd_write : std_logic_vector(3 downto 0) := "0100"; constant cmd_act : std_logic_vector(3 downto 0) := "0011"; constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set -- State assignments constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000"; constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop; constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre; constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref; constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs; constant s_idle_id: std_logic_vector(4 downto 0) := "00001"; constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop; constant s_rf0_id: std_logic_vector(4 downto 0) := "00010"; constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref; constant s_rf1_id: std_logic_vector(4 downto 0) := "00011"; constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; constant s_rf2_id: std_logic_vector(4 downto 0) := "00100"; constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; constant s_rf3_id: std_logic_vector(4 downto 0) := "00101"; constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; constant s_rf4_id: std_logic_vector(4 downto 0) := "00110"; constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; constant s_rf5_id: std_logic_vector(4 downto 0) := "00111"; constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; constant s_ra0_id: std_logic_vector(4 downto 0) := "01000"; constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; constant s_ra1_id: std_logic_vector(4 downto 0) := "01001"; constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; constant s_ra2_id: std_logic_vector(4 downto 0) := "01010"; constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; constant s_dr0_id: std_logic_vector(4 downto 0) := "01011"; constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; constant s_dr1_id: std_logic_vector(4 downto 0) := "01100"; constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; constant s_wr0_id: std_logic_vector(4 downto 0) := "01101"; constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; constant s_wr1_id: std_logic_vector(4 downto 0) := "01110"; constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; constant s_wr2_id: std_logic_vector(4 downto 0) := "01111"; constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; constant s_wr3_id: std_logic_vector(4 downto 0) := "10000"; constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write; constant s_rd0_id: std_logic_vector(4 downto 0) := "10001"; constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; constant s_rd1_id: std_logic_vector(4 downto 0) := "10010"; constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read; constant s_rd2_id: std_logic_vector(4 downto 0) := "10011"; constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; constant s_rd3_id: std_logic_vector(4 downto 0) := "10100"; constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read; constant s_rd4_id: std_logic_vector(4 downto 0) := "10101"; constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; constant s_rd5_id: std_logic_vector(4 downto 0) := "10110"; constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read; constant s_rd6_id: std_logic_vector(4 downto 0) := "10111"; constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; constant s_rd7_id: std_logic_vector(4 downto 0) := "11000"; constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; constant s_rd8_id: std_logic_vector(4 downto 0) := "11001"; constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; constant s_rd9_id: std_logic_vector(4 downto 0) := "11011"; constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101"; constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110"; constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111"; constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0); signal addr_bank: std_logic_vector(1 downto 0); constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width signal addr_col : std_logic_vector(7 downto 0); signal captured : std_logic_vector(15 downto 0); signal busy: std_logic; constant tOPD: time := 2.1 ns; constant tHZ: time := 8 ns; signal dram_dq_dly : std_logic_vector(15 downto 0); -- Debug only signal debug_cmd: std_logic_vector(3 downto 0); signal not_clock_100_delayed_3ns: std_logic; constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10; attribute IOB: string; signal i_DRAM_CS_N: std_logic; attribute IOB of i_DRAM_CS_N: signal is "true"; signal i_DRAM_RAS_N: std_logic; attribute IOB of i_DRAM_RAS_N: signal is "true"; signal i_DRAM_CAS_N: std_logic; attribute IOB of i_DRAM_CAS_N: signal is "true"; signal i_DRAM_WE_N: std_logic; attribute IOB of i_DRAM_WE_N: signal is "true"; signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0); attribute IOB of i_DRAM_ADDR: signal is "true"; signal i_DRAM_BA: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_BA: signal is "true"; signal i_DRAM_DQM: std_logic_vector(1 downto 0); attribute IOB of i_DRAM_DQM: signal is "true"; attribute IOB of rdata_write: signal is "true"; attribute IOB of captured: signal is "true"; signal i_DRAM_CLK: std_logic; attribute fsm_encoding: string; attribute fsm_encoding of nstate: signal is "user"; attribute fsm_encoding of rstate: signal is "user"; begin debug_cmd <= rstate(3 downto 0); -- Addressing is in 32 bit words - twice that of the DRAM width, -- so each burst of four access two system words. --addr_row <= address(23 downto 11); --addr_bank <= address(10 downto 9); process(r.req_addr_q) begin addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1); -- (24-2) downto (24-2 - 2 - 13 - 1) -- 22 downto 6 addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2); r.req_addr_q(ADDRESS_BITS-1+9 downto 9); addr_col <= (others => '0'); addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0"; r.req_addr_q(8 downto 2) & "0"; end process; not_clock_100_delayed_3ns <= not clock_100_delayed_3ns; clock: ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "ASYNC") port map ( D0 => '1', D1 => '0', Q => i_DRAM_CLK, C0 => clock_100_delayed_3ns, C1 => not_clock_100_delayed_3ns, CE => '1', R => '0', S => '0' ); DRAM_CKE <= '1'; DRAM_CLK <= transport i_DRAM_CLK after tOPD; i_DRAM_CS_N <= transport rstate(3) after tOPD; DRAM_CS_N <= i_DRAM_CS_N; i_DRAM_RAS_N <= transport rstate(2) after tOPD; DRAM_RAS_N <= i_DRAM_RAS_N; i_DRAM_CAS_N <= transport rstate(1) after tOPD; DRAM_CAS_N <= i_DRAM_CAS_N; i_DRAM_WE_N <= transport rstate(0) after tOPD; DRAM_WE_N <= i_DRAM_WE_N; i_DRAM_ADDR <= transport r.address after tOPD; DRAM_ADDR <= i_DRAM_ADDR; i_DRAM_BA <= transport r.bank after tOPD; DRAM_BA <= i_DRAM_BA; i_DRAM_DQM <= transport r.dq_masks after tOPD; DRAM_DQM <= i_DRAM_DQM; DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured; data_out_valid <= r.data_out_valid; DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write; pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0'; process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured) begin -- copy the existing values n <= r; nstate <= rstate; ndata_write <= rdata_write; if req_read = '1' then n.rd_pending <= '1'; if r.rd_pending='0' then n.req_addr_q <= address; end if; end if; if req_write = '1' then n.wr_pending <= '1'; if r.wr_pending='0' then n.req_addr_q <= address; -- Queue data here n.req_data_write <= data_in; n.req_mask <= data_mask; end if; end if; n.dq_masks <= "11"; -- first off, do we need to perform a refresh cycle ASAP? if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns n.rf_counter <= 0; n.rf_pending <= '1'; else -- only start looking for refreshes outside of the initialisation state. if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then n.rf_counter <= r.rf_counter + 1; end if; end if; -- Set the data bus into HIZ, high and low bytes masked --DRAM_DQ <= (others => 'Z'); n.tristate <= '0'; n.init_counter <= r.init_counter-1; --ndata_write <= (others => DontCareValue); n.data_out_valid <= '0'; -- alvie- here, no ? -- Process the FSM case rstate(8 downto 4) is when s_init_nop_id => --s_init_nop(8 downto 4) => nstate <= s_init_nop; n.address <= (others => '0'); n.bank <= (others => '0'); n.act_ba <= (others => '0'); n.rf_counter <= 0; -- n.data_out_valid <= '1'; -- alvie- not here -- T-130, precharge all banks. if r.init_counter = "000000010000010" then nstate <= s_init_pre; n.address(10) <= '1'; end if; -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then nstate <= s_init_ref; end if; -- T-3, the load mode register if r.init_counter = 3 then nstate <= s_init_mrs; -- Mode register is as follows: -- resvd wr_b OpMd CAS=3 Seq bust=1 n.address <= "00" & "0" & "00" & "011" & "0" & "000"; -- resvd n.bank <= "00"; end if; -- T-1 The switch to the FSM (first command will be a NOP if r.init_counter = 1 then nstate <= s_idle; end if; ------------------------------ -- The Idle section ------------------------------ when s_idle_id => nstate <= s_idle; -- do we have to activate a row? if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; -- refreshes take priority over everything if r.rf_pending = '1' then nstate <= s_rf0; n.rf_pending <= '0'; end if; ------------------------------ -- Row activation -- s_ra2 is also the "idle with active row" state and provides -- a resting point between operations on the same row ------------------------------ when s_ra0_id => nstate <= s_ra1; when s_ra1_id => nstate <= s_ra2; when s_ra2_id=> -- we can stay in this state until we have something to do nstate <= s_ra2; n.tristate<='0'; if r.rf_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; else -- If there is a read pending, deactivate the row if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_dr0; n.address(10) <= '1'; end if; -- unless we have a read to perform on the same row? do that instead if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_rd0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks <= "00"; n.rd_pending <= '0'; --n.tristate<='1'; end if; -- unless we have a write on the same row? writes take priroty over reads if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then nstate <= s_wr0; n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; ndata_write <= r.req_data_write(31 downto 16); n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= not r.req_mask(3 downto 2); n.wr_pending <= '0'; --n.tristate <= '0'; end if; end if; -- nstate <= s_dr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- n.wr_pending <= r.wr_pending; --n.tristate <= '0'; --end if; ------------------------------------------------------ -- Deactivate the current row and return to idle state ------------------------------------------------------ when s_dr0_id => nstate <= s_dr1; when s_dr1_id => nstate <= s_idle; ------------------------------ -- The Refresh section ------------------------------ when s_rf0_id => nstate <= s_rf1; when s_rf1_id => nstate <= s_rf2; when s_rf2_id => nstate <= s_rf3; when s_rf3_id => nstate <= s_rf4; when s_rf4_id => nstate <= s_rf5; when s_rf5_id => nstate <= s_idle; ------------------------------ -- The Write section ------------------------------ when s_wr0_id => nstate <= s_wr3; n.bank <= addr_bank; n.address(0) <= '1'; ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16); --DRAM_DQ <= rdata_write; n.dq_masks<= not r.req_mask(1 downto 0); n.tristate <= '0'; when s_wr1_id => null; when s_wr2_id => nstate <= s_dr0; n.address(10) <= '1'; when s_wr3_id => -- Default to the idle+row active state nstate <= s_ra2; --DRAM_DQ <= rdata_write; n.data_out_valid<='1'; -- alvie- ack write n.tristate <= '0'; n.dq_masks<= "11"; -- If there is a read or write then deactivate the row --if r.rd_pending = '1' or r.wr_pending = '1' then -- nstate <= s_dr0; -- n.address(10) <= '1'; --end if; -- But if there is a read pending in the same row, do that --if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_rd0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; -- --n.act_ba <= addr_bank; -- n.dq_masks <= "00"; -- n.rd_pending <= '0'; --end if; -- unless there is a write pending in the same row, do that --if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then -- nstate <= s_wr0; -- n.address <= (others => '0'); -- n.address(addr_col'HIGH downto 0) <= addr_col; -- n.bank <= addr_bank; --n.act_ba <= addr_bank; -- n.dq_masks<= "00"; -- n.wr_pending <= '0'; --end if; -- But always try and refresh if one is pending! if r.rf_pending = '1' then nstate <= s_wr2; --dr0; --n.address(10) <= '1'; end if; ------------------------------ -- The Read section ------------------------------ when s_rd0_id => -- 10001 nstate <= s_rd1; n.tristate<='1'; n.dq_masks <= "00"; n.address(0)<='1'; when s_rd1_id => -- 10010 nstate <= s_rd2; n.dq_masks <= "00"; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd3; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; end if; when s_rd2_id => -- 10011 nstate <= s_rd7; n.dq_masks <= "00"; n.tristate<='1'; when s_rd3_id => -- 10100 nstate <= s_rd4; n.dq_masks <= "00"; n.address(0) <= '1'; n.tristate<='1'; -- Data is still not ready... when s_rd4_id => -- 10101 nstate <= s_rd5; n.dq_masks <= "00"; --n.address(0)<='1'; n.tristate<='1'; if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then nstate <= s_rd5; -- Another request came, and we can pipeline - n.address <= (others => '0'); n.address(addr_col'HIGH downto 0) <= addr_col; n.bank <= addr_bank; n.act_ba <= addr_bank; n.dq_masks<= "00"; n.rd_pending <= '0'; else nstate <= s_rd6; -- NOTE: not correct end if; --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; -- n.rd_pending <= r.rd_pending; -- Keep request --end if; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_rd5_id => -- If a refresh is pending then always deactivate the row --if r.rf_pending = '1' then -- nstate <= s_drdr0; -- n.address(10) <= '1'; --end if; n.address(0) <= '1'; nstate <= s_rd4; -- Another request came, and we can pipeline - n.dq_masks <= "00"; n.tristate<='1'; when s_rd6_id => nstate <= s_rd7; n.dq_masks<= "00"; n.tristate<='1'; when s_rd7_id => nstate <= s_ra2; n.data_out_low <= captured; n.data_out_valid <= '1'; n.tristate<='1'; when s_rd8_id => null; when s_rd9_id => null; -- The Deactivate row during read section ------------------------------ when s_drdr0_id => nstate <= s_drdr1; when s_drdr1_id => nstate <= s_drdr2; n.data_out_low <= captured; n.data_out_valid <= '1'; when s_drdr2_id => nstate <= s_idle; if r.rf_pending = '1' then nstate <= s_rf0; end if; if r.rd_pending = '1' or r.wr_pending = '1' then nstate <= s_ra0; n.address <= addr_row; n.act_row <= addr_row; n.bank <= addr_bank; end if; when others => nstate <= s_init_nop; end case; end process; --- The clock driven logic process (clock_100, n) begin if clock_100'event and clock_100 = '1' then if rst='1' then rstate <= (others => '0'); r.address <= (others => '0'); r.bank <= (others => '0'); r.init_counter <= "100000000000000"; -- synopsys translate_off r.init_counter <= "000000100000000"; -- synopsys translate_on r.rf_counter <= 0; r.rf_pending <= '0'; r.rd_pending <= '0'; r.wr_pending <= '0'; r.act_row <= (others => '0'); r.data_out_low <= (others => '0'); r.data_out_valid <= '0'; r.dq_masks <= "11"; r.tristate<='1'; else r <= n; rstate <= nstate; rdata_write <= ndata_write; end if; end if; end process; dram_dq_dly <= transport dram_dq after 1.9 ns; -- process (clock_100_delayed_3ns, dram_dq_dly) -- begin -- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then -- captured <= dram_dq_dly; -- end if; -- end process; process (clock_100) begin if falling_edge(clock_100) then captured <= dram_dq_dly; end if; end process; end rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_Pro/stack.vhd

14

1802

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library work; use work.zpu_config.all; use work.zpupkg.all; library UNISIM; use UNISIM.vcomponents.all; entity zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic_vector(3 downto 0); stack_a_enable: in std_logic; stack_b_writeenable: in std_logic_vector(3 downto 0); stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2) ); end entity zpuino_stack; architecture behave of zpuino_stack is signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0'); begin stackram: for i in 0 to 3 generate stackmem: RAMB16_S9_S9 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", SIM_COLLISION_CHECK => "NONE" ) port map ( DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)), DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)), DOPA => open, DOPB => open, ADDRA => stack_a_addr(stackSize_bits-1 downto 2), ADDRB => stack_b_addr(stackSize_bits-1 downto 2), CLKA => stack_clk, CLKB => stack_clk, DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)), DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)), DIPA => dipa, DIPB => dipb, ENA => stack_a_enable, ENB => stack_b_enable, SSRA => '0', SSRB => '0', WEA => stack_a_writeenable(i), WEB => stack_b_writeenable(i) ); end generate; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd

13

8523

-- -- SPI interface for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpuino_config.all; use board.zpupkg.all; use board.zpupkg.all; use board.zpuinopkg.all; entity COMM_zpuino_wb_SPI is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); mosi: out std_logic; -- Master Out Slave In miso: in std_logic; -- Master In Slave Out sck: out std_logic; -- SPI Clock enabled: out std_logic -- An output that is active high when the SPI is not in a reset state ); end entity COMM_zpuino_wb_SPI; architecture behave of COMM_zpuino_wb_SPI is component spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic ); end component spi; component spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end component spiclkgen; signal spi_read: std_logic_vector(31 downto 0); signal spi_en: std_logic; signal spi_ready: std_logic; signal spi_clk_en: std_logic; signal spi_clkrise: std_logic; signal spi_clkfall: std_logic; signal spi_clk_pres: std_logic_vector(2 downto 0); signal spi_samprise: std_logic; signal spi_enable_q: std_logic; signal spi_txblock_q: std_logic; signal cpol: std_logic; signal miso_i: std_logic; signal spi_transfersize_q: std_logic_vector(1 downto 0); signal trans: std_logic; signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; zspi: spi port map ( clk => wb_clk_i, rst => wb_rst_i, din => wb_dat_i, dout => spi_read, en => spi_en, ready => spi_ready, transfersize => spi_transfersize_q, miso => miso_i, mosi => mosi, clk_en => spi_clk_en, clkrise => spi_clkrise, clkfall => spi_clkfall, samprise => spi_samprise ); zspiclk: spiclkgen port map ( clk => wb_clk_i, rst => wb_rst_i, en => spi_clk_en, pres => spi_clk_pres, clkrise => spi_clkrise, clkfall => spi_clkfall, spiclk => sck, cpol => cpol ); -- Simulation only miso_i <= '0' when miso='Z' else miso; -- Direct access (write) to SPI --spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; busygen: if zpuino_spiblocking=true generate process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then wb_ack_o <= '0'; spi_en <= '0'; trans <= '0'; else wb_ack_o <= '0'; spi_en <= '0'; trans <='0'; if trans='0' then if (wb_cyc_i='1' and wb_stb_i='1') then if wb_adr_i(2)='1' then if spi_txblock_q='1' then if spi_ready='1' then if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; wb_ack_o <= '1'; trans <= '1'; end if; else if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; trans <= '1'; wb_ack_o <= '1'; end if; else trans <= '1'; wb_ack_o <= '1'; end if; end if; end if; end if; end if; end process; --busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0'; end generate; nobusygen: if zpuino_spiblocking=false generate --busy <= '0'; spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; end generate; wb_inta_o <= '0'; enabled <= spi_enable_q; -- Prescaler write process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then spi_enable_q<='0'; spi_txblock_q<='1'; --spi_transfersize_q<=(others => '0'); else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then if wb_adr_i(2)='0' then spi_clk_pres <= wb_dat_i(3 downto 1); cpol <= wb_dat_i(4); spi_samprise <= wb_dat_i(5); spi_enable_q <= wb_dat_i(6); spi_txblock_q <= wb_dat_i(7); --spi_transfersize_q <= wb_dat_i(9 downto 8); end if; end if; end if; end if; end process; process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q) begin wb_dat_o <= (others =>Undefined); case wb_adr_i(2) is when '0' => wb_dat_o(0) <= spi_ready; wb_dat_o(3 downto 1) <= spi_clk_pres; wb_dat_o(4) <= cpol; wb_dat_o(5) <= spi_samprise; wb_dat_o(6) <= spi_enable_q; wb_dat_o(7) <= spi_txblock_q; wb_dat_o(9 downto 8) <= spi_transfersize_q; when '1' => wb_dat_o <= spi_read; when others => wb_dat_o <= (others => DontCareValue); end case; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd

13

8523

-- -- SPI interface for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpuino_config.all; use board.zpupkg.all; use board.zpupkg.all; use board.zpuinopkg.all; entity COMM_zpuino_wb_SPI is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); mosi: out std_logic; -- Master Out Slave In miso: in std_logic; -- Master In Slave Out sck: out std_logic; -- SPI Clock enabled: out std_logic -- An output that is active high when the SPI is not in a reset state ); end entity COMM_zpuino_wb_SPI; architecture behave of COMM_zpuino_wb_SPI is component spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic ); end component spi; component spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end component spiclkgen; signal spi_read: std_logic_vector(31 downto 0); signal spi_en: std_logic; signal spi_ready: std_logic; signal spi_clk_en: std_logic; signal spi_clkrise: std_logic; signal spi_clkfall: std_logic; signal spi_clk_pres: std_logic_vector(2 downto 0); signal spi_samprise: std_logic; signal spi_enable_q: std_logic; signal spi_txblock_q: std_logic; signal cpol: std_logic; signal miso_i: std_logic; signal spi_transfersize_q: std_logic_vector(1 downto 0); signal trans: std_logic; signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; zspi: spi port map ( clk => wb_clk_i, rst => wb_rst_i, din => wb_dat_i, dout => spi_read, en => spi_en, ready => spi_ready, transfersize => spi_transfersize_q, miso => miso_i, mosi => mosi, clk_en => spi_clk_en, clkrise => spi_clkrise, clkfall => spi_clkfall, samprise => spi_samprise ); zspiclk: spiclkgen port map ( clk => wb_clk_i, rst => wb_rst_i, en => spi_clk_en, pres => spi_clk_pres, clkrise => spi_clkrise, clkfall => spi_clkfall, spiclk => sck, cpol => cpol ); -- Simulation only miso_i <= '0' when miso='Z' else miso; -- Direct access (write) to SPI --spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; busygen: if zpuino_spiblocking=true generate process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then wb_ack_o <= '0'; spi_en <= '0'; trans <= '0'; else wb_ack_o <= '0'; spi_en <= '0'; trans <='0'; if trans='0' then if (wb_cyc_i='1' and wb_stb_i='1') then if wb_adr_i(2)='1' then if spi_txblock_q='1' then if spi_ready='1' then if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; wb_ack_o <= '1'; trans <= '1'; end if; else if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; trans <= '1'; wb_ack_o <= '1'; end if; else trans <= '1'; wb_ack_o <= '1'; end if; end if; end if; end if; end if; end process; --busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0'; end generate; nobusygen: if zpuino_spiblocking=false generate --busy <= '0'; spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; end generate; wb_inta_o <= '0'; enabled <= spi_enable_q; -- Prescaler write process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then spi_enable_q<='0'; spi_txblock_q<='1'; --spi_transfersize_q<=(others => '0'); else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then if wb_adr_i(2)='0' then spi_clk_pres <= wb_dat_i(3 downto 1); cpol <= wb_dat_i(4); spi_samprise <= wb_dat_i(5); spi_enable_q <= wb_dat_i(6); spi_txblock_q <= wb_dat_i(7); --spi_transfersize_q <= wb_dat_i(9 downto 8); end if; end if; end if; end if; end process; process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q) begin wb_dat_o <= (others =>Undefined); case wb_adr_i(2) is when '0' => wb_dat_o(0) <= spi_ready; wb_dat_o(3 downto 1) <= spi_clk_pres; wb_dat_o(4) <= cpol; wb_dat_o(5) <= spi_samprise; wb_dat_o(6) <= spi_enable_q; wb_dat_o(7) <= spi_txblock_q; wb_dat_o(9 downto 8) <= spi_transfersize_q; when '1' => wb_dat_o <= spi_read; when others => wb_dat_o <= (others => DontCareValue); end case; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/spiclkgen.vhd

14

3739

-- -- SPI Clock generator -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end entity spiclkgen; architecture behave of spiclkgen is signal running_q: std_logic; signal clkrise_i: std_logic; signal clkfall_i: std_logic; component prescaler is port ( clk: in std_logic; rst: in std_logic; prescale: in std_logic_vector(2 downto 0); event: out std_logic ); end component prescaler; signal prescale_q: std_logic_vector(2 downto 0); signal clk_i: std_logic; signal prescale_event: std_logic; signal prescale_reset: std_logic; begin clkrise <= clkrise_i; clkfall <= clkfall_i; pr: prescaler port map ( clk => clk, rst => prescale_reset, prescale => prescale_q, event => prescale_event ); genclk: process(clk) begin if rising_edge(clk) then if rst='1' or en='0' then spiclk <= cpol; else if clkrise_i='1' then spiclk<=not cpol; end if; if clkfall_i='1' then spiclk<=cpol; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then prescale_q <= (others => '0'); running_q <= '0'; prescale_reset <= '0'; else if en='1' then prescale_reset<='0'; running_q <= '1'; if running_q='0' then prescale_q <= pres; prescale_reset<='1'; end if; else running_q <= '0'; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then clkrise_i<='0'; clkfall_i<='0'; clk_i<='0'; else clkrise_i <= '0'; clkfall_i <= '0'; if running_q='1' and en='1' then if prescale_event='1' then clk_i <= not clk_i; if clk_i='0' then clkrise_i <= '1'; else clkfall_i <= '1'; end if; end if; else clk_i <= '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/spiclkgen.vhd

14

3739

-- -- SPI Clock generator -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end entity spiclkgen; architecture behave of spiclkgen is signal running_q: std_logic; signal clkrise_i: std_logic; signal clkfall_i: std_logic; component prescaler is port ( clk: in std_logic; rst: in std_logic; prescale: in std_logic_vector(2 downto 0); event: out std_logic ); end component prescaler; signal prescale_q: std_logic_vector(2 downto 0); signal clk_i: std_logic; signal prescale_event: std_logic; signal prescale_reset: std_logic; begin clkrise <= clkrise_i; clkfall <= clkfall_i; pr: prescaler port map ( clk => clk, rst => prescale_reset, prescale => prescale_q, event => prescale_event ); genclk: process(clk) begin if rising_edge(clk) then if rst='1' or en='0' then spiclk <= cpol; else if clkrise_i='1' then spiclk<=not cpol; end if; if clkfall_i='1' then spiclk<=cpol; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then prescale_q <= (others => '0'); running_q <= '0'; prescale_reset <= '0'; else if en='1' then prescale_reset<='0'; running_q <= '1'; if running_q='0' then prescale_q <= pres; prescale_reset<='1'; end if; else running_q <= '0'; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then clkrise_i<='0'; clkfall_i<='0'; clk_i<='0'; else clkrise_i <= '0'; clkfall_i <= '0'; if running_q='1' and en='1' then if prescale_event='1' then clk_i <= not clk_i; if clk_i='0' then clkrise_i <= '1'; else clkfall_i <= '1'; end if; end if; else clk_i <= '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/spiclkgen.vhd

14

3739

-- -- SPI Clock generator -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end entity spiclkgen; architecture behave of spiclkgen is signal running_q: std_logic; signal clkrise_i: std_logic; signal clkfall_i: std_logic; component prescaler is port ( clk: in std_logic; rst: in std_logic; prescale: in std_logic_vector(2 downto 0); event: out std_logic ); end component prescaler; signal prescale_q: std_logic_vector(2 downto 0); signal clk_i: std_logic; signal prescale_event: std_logic; signal prescale_reset: std_logic; begin clkrise <= clkrise_i; clkfall <= clkfall_i; pr: prescaler port map ( clk => clk, rst => prescale_reset, prescale => prescale_q, event => prescale_event ); genclk: process(clk) begin if rising_edge(clk) then if rst='1' or en='0' then spiclk <= cpol; else if clkrise_i='1' then spiclk<=not cpol; end if; if clkfall_i='1' then spiclk<=cpol; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then prescale_q <= (others => '0'); running_q <= '0'; prescale_reset <= '0'; else if en='1' then prescale_reset<='0'; running_q <= '1'; if running_q='0' then prescale_q <= pres; prescale_reset<='1'; end if; else running_q <= '0'; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then clkrise_i<='0'; clkfall_i<='0'; clk_i<='0'; else clkrise_i <= '0'; clkfall_i <= '0'; if running_q='1' and en='1' then if prescale_event='1' then clk_i <= not clk_i; if clk_i='0' then clkrise_i <= '1'; else clkfall_i <= '1'; end if; end if; else clk_i <= '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_250k/stack.vhd

13

1535

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library work; use work.zpu_config.all; use work.zpupkg.all; library UNISIM; use UNISIM.vcomponents.all; entity zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic; stack_b_writeenable: in std_logic; stack_a_enable: in std_logic; stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0) ); end entity zpuino_stack; architecture behave of zpuino_stack is signal dipa,dipb: std_logic_vector(3 downto 0) := (others => '0'); begin stack: RAMB16_S36_S36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", SIM_COLLISION_CHECK => "NONE" ) port map ( DOA => stack_a_read, DOB => stack_b_read, DOPA => open, DOPB => open, ADDRA => stack_a_addr, ADDRB => stack_b_addr, CLKA => stack_clk, CLKB => stack_clk, DIA => stack_a_write, DIB => stack_b_write, DIPA => dipa, DIPB => dipb, ENA => stack_a_enable, ENB => stack_b_enable, SSRA => '0', SSRB => '0', WEA => stack_a_writeenable, WEB => stack_b_writeenable ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/clk_32to200_pll.vhd

13

5100

-- file: clk_32to200_pll.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to200_pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to200_pll; architecture xilinx of clk_32to200_pll is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to200_pll,clk_wiz_v3_6,{component_name=clk_32to200_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering / unused connectors signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1_unused : std_logic; signal clkout2_unused : std_logic; signal clkout3_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; -- Unused status signals signal locked_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1 <= CLK_IN1; -- Clocking primitive -------------------------------------- -- Instantiation of the PLL primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 2.0, CLKFBOUT_MULT => 4, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 31.250, REF_JITTER => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKOUT0 => clkout0, CLKOUT1 => clkout1_unused, CLKOUT2 => clkout2_unused, CLKOUT3 => clkout3_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, LOCKED => locked_unused, RST => '0', -- Input clock control CLKFBIN => clkfbout, CLKIN => clkin1); -- Output buffering ------------------------------------- clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkout0); end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/clk_32to200_pll.vhd

13

5100

-- file: clk_32to200_pll.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to200_pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to200_pll; architecture xilinx of clk_32to200_pll is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to200_pll,clk_wiz_v3_6,{component_name=clk_32to200_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering / unused connectors signal clkfbout : std_logic; signal clkout0 : std_logic; signal clkout1_unused : std_logic; signal clkout2_unused : std_logic; signal clkout3_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; -- Unused status signals signal locked_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1 <= CLK_IN1; -- Clocking primitive -------------------------------------- -- Instantiation of the PLL primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused pll_base_inst : PLL_BASE generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 2.0, CLKFBOUT_MULT => 4, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 31.250, REF_JITTER => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKOUT0 => clkout0, CLKOUT1 => clkout1_unused, CLKOUT2 => clkout2_unused, CLKOUT3 => clkout3_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, LOCKED => locked_unused, RST => '0', -- Input clock control CLKFBIN => clkfbout, CLKIN => clkin1); -- Output buffering ------------------------------------- clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkout0); end xilinx;

mit

chcbaram/FPGA

ZPUino_miniSpartan6_plus/ipcore_dir/frame_buffer/simulation/checker.vhd

69

5607

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/i2c_master_byte_ctrl.vhd

15

12630

--------------------------------------------------------------------- ---- ---- ---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- ---- ---- ---- ---- ---- Author: Richard Herveille ---- ---- richard@asics.ws ---- ---- www.asics.ws ---- ---- ---- ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ---- ---- --------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2000 Richard Herveille ---- ---- richard@asics.ws ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer.---- ---- ---- ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ---- POSSIBILITY OF SUCH DAMAGE. ---- ---- ---- --------------------------------------------------------------------- -- CVS Log -- -- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $ -- -- $Date: 2004-02-18 11:41:48 $ -- $Revision: 1.5 $ -- $Author: rherveille $ -- $Locker: $ -- $State: Exp $ -- -- Change History: -- $Log: not supported by cvs2svn $ -- Revision 1.4 2003/08/09 07:01:13 rherveille -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -- Fixed a potential bug in the byte controller's host-acknowledge generation. -- -- Revision 1.3 2002/12/26 16:05:47 rherveille -- Core is now a Multimaster I2C controller. -- -- Revision 1.2 2002/11/30 22:24:37 rherveille -- Cleaned up code -- -- Revision 1.1 2001/11/05 12:02:33 rherveille -- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. -- Code updated, is now up-to-date to doc. rev.0.4. -- Added headers. -- -- ------------------------------------------ -- Byte controller section ------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity i2c_master_byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; -- command done ack_out : out std_logic; i2c_busy : out std_logic; -- arbitration lost i2c_al : out std_logic; -- i2c bus busy dout : out std_logic_vector(7 downto 0); -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end entity i2c_master_byte_ctrl; architecture structural of i2c_master_byte_ctrl is component i2c_master_bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- clock prescale value cmd : in std_logic_vector(3 downto 0); cmd_ack : out std_logic; -- command done busy : out std_logic; -- i2c bus busy al : out std_logic; -- arbitration lost din : in std_logic; dout : out std_logic; -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end component i2c_master_bit_ctrl; -- commands for bit_controller block constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; -- signals for bit_controller signal core_cmd : std_logic_vector(3 downto 0); signal core_ack, core_txd, core_rxd : std_logic; signal al : std_logic; -- signals for shift register signal sr : std_logic_vector(7 downto 0); -- 8bit shift register signal shift, ld : std_logic; -- signals for state machine signal go, host_ack : std_logic; signal dcnt : unsigned(2 downto 0); -- data counter signal cnt_done : std_logic; begin -- hookup bit_controller bit_ctrl: i2c_master_bit_ctrl port map( clk => clk, rst => rst, nReset => nReset, ena => ena, clk_cnt => clk_cnt, cmd => core_cmd, cmd_ack => core_ack, busy => i2c_busy, al => al, din => core_txd, dout => core_rxd, scl_i => scl_i, scl_o => scl_o, scl_oen => scl_oen, sda_i => sda_i, sda_o => sda_o, sda_oen => sda_oen ); i2c_al <= al; -- generate host-command-acknowledge cmd_ack <= host_ack; -- generate go-signal go <= (read or write or stop) and not host_ack; -- assign Dout output to shift-register dout <= sr; -- generate shift register shift_register: process(clk, nReset) begin if (nReset = '0') then sr <= (others => '0'); elsif (clk'event and clk = '1') then if (rst = '1') then sr <= (others => '0'); elsif (ld = '1') then sr <= din; elsif (shift = '1') then sr <= (sr(6 downto 0) & core_rxd); end if; end if; end process shift_register; -- generate data-counter data_cnt: process(clk, nReset) begin if (nReset = '0') then dcnt <= (others => '0'); elsif (clk'event and clk = '1') then if (rst = '1') then dcnt <= (others => '0'); elsif (ld = '1') then dcnt <= (others => '1'); -- load counter with 7 elsif (shift = '1') then dcnt <= dcnt -1; end if; end if; end process data_cnt; cnt_done <= '1' when (dcnt = 0) else '0'; -- -- state machine -- statemachine : block type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); signal c_state : states; begin -- -- command interpreter, translate complex commands into simpler I2C commands -- nxt_state_decoder: process(clk, nReset) begin if (nReset = '0') then core_cmd <= I2C_CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; host_ack <= '0'; c_state <= st_idle; ack_out <= '0'; elsif (clk'event and clk = '1') then if (rst = '1' or al = '1') then core_cmd <= I2C_CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; host_ack <= '0'; c_state <= st_idle; ack_out <= '0'; else -- initialy reset all signal core_txd <= sr(7); shift <= '0'; ld <= '0'; host_ack <= '0'; case c_state is when st_idle => if (go = '1') then if (start = '1') then c_state <= st_start; core_cmd <= I2C_CMD_START; elsif (read = '1') then c_state <= st_read; core_cmd <= I2C_CMD_READ; elsif (write = '1') then c_state <= st_write; core_cmd <= I2C_CMD_WRITE; else -- stop c_state <= st_stop; core_cmd <= I2C_CMD_STOP; end if; ld <= '1'; end if; when st_start => if (core_ack = '1') then if (read = '1') then c_state <= st_read; core_cmd <= I2C_CMD_READ; else c_state <= st_write; core_cmd <= I2C_CMD_WRITE; end if; ld <= '1'; end if; when st_write => if (core_ack = '1') then if (cnt_done = '1') then c_state <= st_ack; core_cmd <= I2C_CMD_READ; else c_state <= st_write; -- stay in same state core_cmd <= I2C_CMD_WRITE; -- write next bit shift <= '1'; end if; end if; when st_read => if (core_ack = '1') then if (cnt_done = '1') then c_state <= st_ack; core_cmd <= I2C_CMD_WRITE; else c_state <= st_read; -- stay in same state core_cmd <= I2C_CMD_READ; -- read next bit end if; shift <= '1'; core_txd <= ack_in; end if; when st_ack => if (core_ack = '1') then -- check for stop; Should a STOP command be generated ? if (stop = '1') then c_state <= st_stop; core_cmd <= I2C_CMD_STOP; else c_state <= st_idle; core_cmd <= I2C_CMD_NOP; -- generate command acknowledge signal host_ack <= '1'; end if; -- assign ack_out output to core_rxd (contains last received bit) ack_out <= core_rxd; core_txd <= '1'; else core_txd <= ack_in; end if; when st_stop => if (core_ack = '1') then c_state <= st_idle; core_cmd <= I2C_CMD_NOP; -- generate command acknowledge signal host_ack <= '1'; end if; when others => -- illegal states c_state <= st_idle; core_cmd <= I2C_CMD_NOP; report ("Byte controller entered illegal state."); end case; end if; end if; end process nxt_state_decoder; end block statemachine; end architecture structural;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd

13

7180

-- -- 7 segment driver for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity MISC_zpuino_wb_SevenSeg is generic ( BITS: integer := 2; EXTRASIZE: integer := 32; FREQ_PER_DISPLAY: integer := 120; MHZ: integer := 96; INVERT: boolean := true ); port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); segdata: out std_logic_vector(6 downto 0); dot: out std_logic; extra: out std_logic_vector(EXTRASIZE-1 downto 0); enable: out std_logic_vector((2**BITS)-1 downto 0) ); end entity MISC_zpuino_wb_SevenSeg; architecture behave of MISC_zpuino_wb_SevenSeg is -- Timer constant COUNT: integer := 2**BITS; constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control signal counter: integer range 0 to DELAY; signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0'); subtype segvaltype is std_logic_vector(7 downto 0); type segstype is array(COUNT-1 downto 0) of segvaltype; signal segs: segstype; signal current_display: integer range 0 to COUNT-1; -- same as enashift signal ack_q: std_logic; signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0); signal brightctl: unsigned(3 downto 0); signal brightcount: unsigned(3 downto 0); signal pwm: std_logic; signal invsig: std_logic; signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; -- Finish unpacking Wishbone signals. invsig <= '1' when INVERT=true else '0'; enloop: for i in 0 to COUNT-1 generate enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig; end generate; pwm <= '1' when brightcount >= brightctl else '0'; outdata: for i in 0 to 6 generate segdata(i) <= segs(current_display)(i) xor invsig; end generate; dot <= segs(current_display)(7) xor invsig; wb_ack_o <= ack_q; wb_inta_o <= '0'; extra <= extra_q when current_display=0 and pwm='1' else (others => '0'); process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then counter <= DELAY; current_display<=0; brightcount <= "1111"; else if counter=0 then counter <= DELAY; if brightcount="0000" then brightcount <= "1111"; if current_display=0 then current_display <= COUNT-1; else current_display <= current_display - 1; end if; else brightcount <= brightcount - 1; end if; else counter <= counter - 1; end if; end if; end if; end process; process(wb_clk_i) variable idx: std_logic_vector(BITS-1 downto 0); variable int_idx: integer range 0 to COUNT-1; begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then ack_q<='0'; enabled <= (others => '1'); else ack_q <= '0'; -- Wishbone write if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then ack_q<='1'; if wb_adr_i(BITS+2)='1' then -- Display access -- idx := wb_adr_i(BITS+1 downto 2); int_idx := conv_integer(idx); segs(int_idx) <= wb_dat_i(segvaltype'RANGE); else case wb_adr_i(2) is when '0' => enabled <= wb_dat_i(enabled'RANGE); brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16)); when '1' => extra_q <= wb_dat_i(extra_q'RANGE); when others => null; end case; end if; end if; end if; end if; end process; -- REad process(wb_adr_i,enabled,brightctl,extra_q) variable idx: std_logic_vector(BITS-1 downto 0); variable int_idx: integer range 0 to COUNT-1; begin wb_dat_o <= (others => DontCareValue); if wb_adr_i(BITS+2)='1' then -- Display access -- idx := wb_adr_i(BITS+1 downto 2); int_idx := conv_integer(idx); wb_dat_o(segvaltype'RANGE)<=segs(int_idx); else case wb_adr_i(2) is when '0' => wb_dat_o(enabled'RANGE) <= enabled; wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl); when '1' => wb_dat_o(extra_q'RANGE) <= extra_q; when others => null; end case; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd

13

7180

-- -- 7 segment driver for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity MISC_zpuino_wb_SevenSeg is generic ( BITS: integer := 2; EXTRASIZE: integer := 32; FREQ_PER_DISPLAY: integer := 120; MHZ: integer := 96; INVERT: boolean := true ); port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); segdata: out std_logic_vector(6 downto 0); dot: out std_logic; extra: out std_logic_vector(EXTRASIZE-1 downto 0); enable: out std_logic_vector((2**BITS)-1 downto 0) ); end entity MISC_zpuino_wb_SevenSeg; architecture behave of MISC_zpuino_wb_SevenSeg is -- Timer constant COUNT: integer := 2**BITS; constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control signal counter: integer range 0 to DELAY; signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0'); subtype segvaltype is std_logic_vector(7 downto 0); type segstype is array(COUNT-1 downto 0) of segvaltype; signal segs: segstype; signal current_display: integer range 0 to COUNT-1; -- same as enashift signal ack_q: std_logic; signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0); signal brightctl: unsigned(3 downto 0); signal brightcount: unsigned(3 downto 0); signal pwm: std_logic; signal invsig: std_logic; signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; -- Finish unpacking Wishbone signals. invsig <= '1' when INVERT=true else '0'; enloop: for i in 0 to COUNT-1 generate enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig; end generate; pwm <= '1' when brightcount >= brightctl else '0'; outdata: for i in 0 to 6 generate segdata(i) <= segs(current_display)(i) xor invsig; end generate; dot <= segs(current_display)(7) xor invsig; wb_ack_o <= ack_q; wb_inta_o <= '0'; extra <= extra_q when current_display=0 and pwm='1' else (others => '0'); process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then counter <= DELAY; current_display<=0; brightcount <= "1111"; else if counter=0 then counter <= DELAY; if brightcount="0000" then brightcount <= "1111"; if current_display=0 then current_display <= COUNT-1; else current_display <= current_display - 1; end if; else brightcount <= brightcount - 1; end if; else counter <= counter - 1; end if; end if; end if; end process; process(wb_clk_i) variable idx: std_logic_vector(BITS-1 downto 0); variable int_idx: integer range 0 to COUNT-1; begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then ack_q<='0'; enabled <= (others => '1'); else ack_q <= '0'; -- Wishbone write if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then ack_q<='1'; if wb_adr_i(BITS+2)='1' then -- Display access -- idx := wb_adr_i(BITS+1 downto 2); int_idx := conv_integer(idx); segs(int_idx) <= wb_dat_i(segvaltype'RANGE); else case wb_adr_i(2) is when '0' => enabled <= wb_dat_i(enabled'RANGE); brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16)); when '1' => extra_q <= wb_dat_i(extra_q'RANGE); when others => null; end case; end if; end if; end if; end if; end process; -- REad process(wb_adr_i,enabled,brightctl,extra_q) variable idx: std_logic_vector(BITS-1 downto 0); variable int_idx: integer range 0 to COUNT-1; begin wb_dat_o <= (others => DontCareValue); if wb_adr_i(BITS+2)='1' then -- Display access -- idx := wb_adr_i(BITS+1 downto 2); int_idx := conv_integer(idx); wb_dat_o(segvaltype'RANGE)<=segs(int_idx); else case wb_adr_i(2) is when '0' => wb_dat_o(enabled'RANGE) <= enabled; wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl); when '1' => wb_dat_o(extra_q'RANGE) <= extra_q; when others => null; end case; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/Wing_VGA8.vhd

13

1470

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:54:01 11/26/2013 -- Design Name: -- Module Name: Wing_VGA8 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wing_VGA8 is port ( vga_hsync : in std_logic; vga_vsync : in std_logic; vga_red1 : in std_logic; vga_red0 : in std_logic; vga_green1 : in std_logic; vga_green0 : in std_logic; vga_blue1 : in std_logic; vga_blue0 : in std_logic; wt_miso: inout std_logic_vector(7 downto 0); wt_mosi: inout std_logic_vector(7 downto 0) ); end Wing_VGA8; architecture Behavioral of Wing_VGA8 is begin wt_miso(0) <= vga_vsync; wt_miso(1) <= vga_hsync; wt_miso(2) <= vga_blue0; wt_miso(3) <= vga_blue1; wt_miso(4) <= vga_green1; wt_miso(5) <= vga_red1; wt_miso(6) <= vga_green0; wt_miso(7) <= vga_red0; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/Wing_VGA8.vhd

13

1470

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:54:01 11/26/2013 -- Design Name: -- Module Name: Wing_VGA8 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wing_VGA8 is port ( vga_hsync : in std_logic; vga_vsync : in std_logic; vga_red1 : in std_logic; vga_red0 : in std_logic; vga_green1 : in std_logic; vga_green0 : in std_logic; vga_blue1 : in std_logic; vga_blue0 : in std_logic; wt_miso: inout std_logic_vector(7 downto 0); wt_mosi: inout std_logic_vector(7 downto 0) ); end Wing_VGA8; architecture Behavioral of Wing_VGA8 is begin wt_miso(0) <= vga_vsync; wt_miso(1) <= vga_hsync; wt_miso(2) <= vga_blue0; wt_miso(3) <= vga_blue1; wt_miso(4) <= vga_green1; wt_miso(5) <= vga_red1; wt_miso(6) <= vga_green0; wt_miso(7) <= vga_red0; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/zpuino_top_icache.vhd

13

15630

-- -- Top module for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.zpuino_config.all; use board.wishbonepkg.all; entity zpuino_top_icache is port ( clk: in std_logic; rst: in std_logic; -- Connection to board IO module slot_cyc: out slot_std_logic_type; slot_we: out slot_std_logic_type; slot_stb: out slot_std_logic_type; slot_read: in slot_cpuword_type; slot_write: out slot_cpuword_type; slot_address: out slot_address_type; slot_ack: in slot_std_logic_type; slot_interrupt: in slot_std_logic_type; dbg_reset: out std_logic; memory_enable: out std_logic; -- Memory accesses (for DMA) -- This is a master interface m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; m_wb_stall_o: out std_logic; -- Memory connection ram_wb_ack_i: in std_logic; ram_wb_stall_i: in std_logic; ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0); ram_wb_cyc_o: out std_logic; ram_wb_stb_o: out std_logic; ram_wb_sel_o: out std_logic_vector(3 downto 0); ram_wb_we_o: out std_logic; rom_wb_ack_i: in std_logic; rom_wb_stall_i: in std_logic; rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0); rom_wb_cyc_o: out std_logic; rom_wb_cti_o: out std_logic_vector(2 downto 0); rom_wb_stb_o: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end entity zpuino_top_icache; architecture behave of zpuino_top_icache is component zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic_vector(3 downto 0); stack_a_enable: in std_logic; stack_b_writeenable: in std_logic_vector(3 downto 0); stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2) ); end component zpuino_stack; component wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_ack_o: out std_logic; m0_wb_stall_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; m1_wb_stall_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; s0_wb_stall_i: in std_logic ); end component; component zpuino_debug_core is port ( clk: in std_logic; rst: in std_logic; dbg_in: in zpu_dbg_out_type; dbg_out: out zpu_dbg_in_type; dbg_reset: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end component; component wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end component wbmux2; signal io_read: std_logic_vector(wordSize-1 downto 0); signal io_write: std_logic_vector(wordSize-1 downto 0); signal io_address: std_logic_vector(maxAddrBitIncIO downto 0); signal io_stb: std_logic; signal io_cyc: std_logic; signal io_we: std_logic; signal io_ack: std_logic; signal wb_read: std_logic_vector(wordSize-1 downto 0); signal wb_write: std_logic_vector(wordSize-1 downto 0); signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0); signal wb_stb: std_logic; signal wb_cyc: std_logic; signal wb_sel: std_logic_vector(3 downto 0); signal wb_we: std_logic; signal wb_ack: std_logic; signal interrupt: std_logic; signal poppc_inst: std_logic; signal dbg_pc: std_logic_vector(maxAddrBit downto 0); signal dbg_opcode: std_logic_vector(7 downto 0); signal dbg_opcode_in: std_logic_vector(7 downto 0); signal dbg_sp: std_logic_vector(10 downto 2); signal dbg_brk: std_logic; signal dbg_stacka: std_logic_vector(wordSize-1 downto 0); signal dbg_stackb: std_logic_vector(wordSize-1 downto 0); signal dbg_step: std_logic := '0'; signal dbg_freeze: std_logic; signal dbg_flush: std_logic; signal dbg_valid: std_logic; signal dbg_ready: std_logic; signal dbg_inject: std_logic; signal dbg_injectmode: std_logic; signal dbg_idim: std_logic; signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits-1 downto 2); signal stack_a_writeenable, stack_b_writeenable: std_logic_vector(3 downto 0); signal stack_a_enable,stack_b_enable: std_logic; signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0); signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0); signal stack_clk: std_logic; signal cache_flush: std_logic; --signal memory_enable: std_logic; signal cpu_ram_wb_clk_i: std_logic; signal cpu_ram_wb_rst_i: std_logic; signal cpu_ram_wb_ack_o: std_logic; signal cpu_ram_wb_stall_o: std_logic; signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal cpu_ram_wb_cyc_i: std_logic; signal cpu_ram_wb_stb_i: std_logic; signal cpu_ram_wb_sel_i: std_logic_vector(3 downto 0); signal cpu_ram_wb_we_i: std_logic; signal dbg_to_zpu: zpu_dbg_in_type; signal dbg_from_zpu: zpu_dbg_out_type; begin core: zpu_core_extreme_icache port map ( wb_clk_i => clk, wb_rst_i => rst, wb_ack_i => wb_ack, wb_dat_i => wb_read, wb_dat_o => wb_write, wb_adr_o => wb_address, wb_cyc_o => wb_cyc, wb_stb_o => wb_stb, wb_sel_o => wb_sel, wb_we_o => wb_we, wb_inta_i => interrupt, poppc_inst => poppc_inst, break => open, cache_flush => cache_flush, stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr, rom_wb_ack_i => rom_wb_ack_i, rom_wb_dat_i => rom_wb_dat_i, rom_wb_adr_o => rom_wb_adr_o(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_o, rom_wb_stb_o => rom_wb_stb_o, rom_wb_cti_o => rom_wb_cti_o, rom_wb_stall_i => rom_wb_stall_i, dbg_in => dbg_to_zpu, dbg_out => dbg_from_zpu ); stack: zpuino_stack port map ( stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr ); dbg: zpuino_debug_core port map ( clk => clk, rst => rst, dbg_out => dbg_to_zpu, dbg_in => dbg_from_zpu, dbg_reset => dbg_reset, jtag_data_chain_out => jtag_data_chain_out, jtag_ctrl_chain_in => jtag_ctrl_chain_in ); io: zpuino_io port map ( wb_clk_i => clk, wb_rst_i => rst, wb_dat_o => io_read, wb_dat_i => io_write, wb_adr_i => io_address, wb_cyc_i => io_cyc, wb_stb_i => io_stb, wb_ack_o => io_ack, wb_we_i => io_we, wb_inta_o => interrupt, intready => poppc_inst, cache_flush => cache_flush, memory_enable => memory_enable, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt ); iomemmux: wbmux2 generic map ( select_line => maxAddrBitIncIO, address_high =>maxAddrBitIncIO, address_low=>0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master m_wb_dat_o => wb_read, m_wb_dat_i => wb_write, m_wb_adr_i => wb_address, m_wb_sel_i => wb_sel, m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti, m_wb_we_i => wb_we, m_wb_cyc_i => wb_cyc, m_wb_stb_i => wb_stb, m_wb_ack_o => wb_ack, -- Slave 0 signals s0_wb_dat_i => cpu_ram_wb_dat_o, s0_wb_dat_o => cpu_ram_wb_dat_i, s0_wb_adr_o => cpu_ram_wb_adr_i, s0_wb_sel_o => cpu_ram_wb_sel_i, s0_wb_cti_o => open,--cpu_ram_wb_sel_i, s0_wb_we_o => cpu_ram_wb_we_i, s0_wb_cyc_o => cpu_ram_wb_cyc_i, s0_wb_stb_o => cpu_ram_wb_stb_i, s0_wb_ack_i => cpu_ram_wb_ack_o, -- Slave 1 signals s1_wb_dat_i => io_read, s1_wb_dat_o => io_write, s1_wb_adr_o => io_address, s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => io_we, s1_wb_cyc_o => io_cyc, s1_wb_stb_o => io_stb, s1_wb_ack_i => io_ack ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBit, ADDRESS_LOW => 0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master 0 signals (CPU) m0_wb_dat_o => cpu_ram_wb_dat_o, m0_wb_dat_i => cpu_ram_wb_dat_i, m0_wb_adr_i => cpu_ram_wb_adr_i(maxAddrBit downto 0), m0_wb_sel_i => cpu_ram_wb_sel_i, m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => cpu_ram_wb_we_i, m0_wb_cyc_i => cpu_ram_wb_cyc_i, m0_wb_stb_i => cpu_ram_wb_stb_i, m0_wb_ack_o => cpu_ram_wb_ack_o, m0_wb_stall_o => cpu_ram_wb_stall_o, -- Master 1 signals m1_wb_dat_o => m_wb_dat_o, m1_wb_dat_i => m_wb_dat_i, m1_wb_adr_i => m_wb_adr_i(maxAddrBit downto 0), m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => m_wb_we_i, m1_wb_cyc_i => m_wb_cyc_i, m1_wb_stb_i => m_wb_stb_i, m1_wb_ack_o => m_wb_ack_o, m1_wb_stall_o => m_wb_stall_o, -- Slave signals s0_wb_dat_i => ram_wb_dat_i, s0_wb_dat_o => ram_wb_dat_o, s0_wb_adr_o => ram_wb_adr_o(maxAddrBit downto 0), s0_wb_sel_o => ram_wb_sel_o, s0_wb_cti_o => open, s0_wb_we_o => ram_wb_we_o, s0_wb_cyc_o => ram_wb_cyc_o, s0_wb_stb_o => ram_wb_stb_o, s0_wb_ack_i => ram_wb_ack_i, s0_wb_stall_i => ram_wb_stall_i ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/zpuino_top_icache.vhd

13

15630

-- -- Top module for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.zpuino_config.all; use board.wishbonepkg.all; entity zpuino_top_icache is port ( clk: in std_logic; rst: in std_logic; -- Connection to board IO module slot_cyc: out slot_std_logic_type; slot_we: out slot_std_logic_type; slot_stb: out slot_std_logic_type; slot_read: in slot_cpuword_type; slot_write: out slot_cpuword_type; slot_address: out slot_address_type; slot_ack: in slot_std_logic_type; slot_interrupt: in slot_std_logic_type; dbg_reset: out std_logic; memory_enable: out std_logic; -- Memory accesses (for DMA) -- This is a master interface m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; m_wb_stall_o: out std_logic; -- Memory connection ram_wb_ack_i: in std_logic; ram_wb_stall_i: in std_logic; ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0); ram_wb_cyc_o: out std_logic; ram_wb_stb_o: out std_logic; ram_wb_sel_o: out std_logic_vector(3 downto 0); ram_wb_we_o: out std_logic; rom_wb_ack_i: in std_logic; rom_wb_stall_i: in std_logic; rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0); rom_wb_cyc_o: out std_logic; rom_wb_cti_o: out std_logic_vector(2 downto 0); rom_wb_stb_o: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end entity zpuino_top_icache; architecture behave of zpuino_top_icache is component zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic_vector(3 downto 0); stack_a_enable: in std_logic; stack_b_writeenable: in std_logic_vector(3 downto 0); stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2) ); end component zpuino_stack; component wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_ack_o: out std_logic; m0_wb_stall_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; m1_wb_stall_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; s0_wb_stall_i: in std_logic ); end component; component zpuino_debug_core is port ( clk: in std_logic; rst: in std_logic; dbg_in: in zpu_dbg_out_type; dbg_out: out zpu_dbg_in_type; dbg_reset: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end component; component wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end component wbmux2; signal io_read: std_logic_vector(wordSize-1 downto 0); signal io_write: std_logic_vector(wordSize-1 downto 0); signal io_address: std_logic_vector(maxAddrBitIncIO downto 0); signal io_stb: std_logic; signal io_cyc: std_logic; signal io_we: std_logic; signal io_ack: std_logic; signal wb_read: std_logic_vector(wordSize-1 downto 0); signal wb_write: std_logic_vector(wordSize-1 downto 0); signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0); signal wb_stb: std_logic; signal wb_cyc: std_logic; signal wb_sel: std_logic_vector(3 downto 0); signal wb_we: std_logic; signal wb_ack: std_logic; signal interrupt: std_logic; signal poppc_inst: std_logic; signal dbg_pc: std_logic_vector(maxAddrBit downto 0); signal dbg_opcode: std_logic_vector(7 downto 0); signal dbg_opcode_in: std_logic_vector(7 downto 0); signal dbg_sp: std_logic_vector(10 downto 2); signal dbg_brk: std_logic; signal dbg_stacka: std_logic_vector(wordSize-1 downto 0); signal dbg_stackb: std_logic_vector(wordSize-1 downto 0); signal dbg_step: std_logic := '0'; signal dbg_freeze: std_logic; signal dbg_flush: std_logic; signal dbg_valid: std_logic; signal dbg_ready: std_logic; signal dbg_inject: std_logic; signal dbg_injectmode: std_logic; signal dbg_idim: std_logic; signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits-1 downto 2); signal stack_a_writeenable, stack_b_writeenable: std_logic_vector(3 downto 0); signal stack_a_enable,stack_b_enable: std_logic; signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0); signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0); signal stack_clk: std_logic; signal cache_flush: std_logic; --signal memory_enable: std_logic; signal cpu_ram_wb_clk_i: std_logic; signal cpu_ram_wb_rst_i: std_logic; signal cpu_ram_wb_ack_o: std_logic; signal cpu_ram_wb_stall_o: std_logic; signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal cpu_ram_wb_cyc_i: std_logic; signal cpu_ram_wb_stb_i: std_logic; signal cpu_ram_wb_sel_i: std_logic_vector(3 downto 0); signal cpu_ram_wb_we_i: std_logic; signal dbg_to_zpu: zpu_dbg_in_type; signal dbg_from_zpu: zpu_dbg_out_type; begin core: zpu_core_extreme_icache port map ( wb_clk_i => clk, wb_rst_i => rst, wb_ack_i => wb_ack, wb_dat_i => wb_read, wb_dat_o => wb_write, wb_adr_o => wb_address, wb_cyc_o => wb_cyc, wb_stb_o => wb_stb, wb_sel_o => wb_sel, wb_we_o => wb_we, wb_inta_i => interrupt, poppc_inst => poppc_inst, break => open, cache_flush => cache_flush, stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr, rom_wb_ack_i => rom_wb_ack_i, rom_wb_dat_i => rom_wb_dat_i, rom_wb_adr_o => rom_wb_adr_o(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_o, rom_wb_stb_o => rom_wb_stb_o, rom_wb_cti_o => rom_wb_cti_o, rom_wb_stall_i => rom_wb_stall_i, dbg_in => dbg_to_zpu, dbg_out => dbg_from_zpu ); stack: zpuino_stack port map ( stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr ); dbg: zpuino_debug_core port map ( clk => clk, rst => rst, dbg_out => dbg_to_zpu, dbg_in => dbg_from_zpu, dbg_reset => dbg_reset, jtag_data_chain_out => jtag_data_chain_out, jtag_ctrl_chain_in => jtag_ctrl_chain_in ); io: zpuino_io port map ( wb_clk_i => clk, wb_rst_i => rst, wb_dat_o => io_read, wb_dat_i => io_write, wb_adr_i => io_address, wb_cyc_i => io_cyc, wb_stb_i => io_stb, wb_ack_o => io_ack, wb_we_i => io_we, wb_inta_o => interrupt, intready => poppc_inst, cache_flush => cache_flush, memory_enable => memory_enable, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt ); iomemmux: wbmux2 generic map ( select_line => maxAddrBitIncIO, address_high =>maxAddrBitIncIO, address_low=>0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master m_wb_dat_o => wb_read, m_wb_dat_i => wb_write, m_wb_adr_i => wb_address, m_wb_sel_i => wb_sel, m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti, m_wb_we_i => wb_we, m_wb_cyc_i => wb_cyc, m_wb_stb_i => wb_stb, m_wb_ack_o => wb_ack, -- Slave 0 signals s0_wb_dat_i => cpu_ram_wb_dat_o, s0_wb_dat_o => cpu_ram_wb_dat_i, s0_wb_adr_o => cpu_ram_wb_adr_i, s0_wb_sel_o => cpu_ram_wb_sel_i, s0_wb_cti_o => open,--cpu_ram_wb_sel_i, s0_wb_we_o => cpu_ram_wb_we_i, s0_wb_cyc_o => cpu_ram_wb_cyc_i, s0_wb_stb_o => cpu_ram_wb_stb_i, s0_wb_ack_i => cpu_ram_wb_ack_o, -- Slave 1 signals s1_wb_dat_i => io_read, s1_wb_dat_o => io_write, s1_wb_adr_o => io_address, s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => io_we, s1_wb_cyc_o => io_cyc, s1_wb_stb_o => io_stb, s1_wb_ack_i => io_ack ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBit, ADDRESS_LOW => 0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master 0 signals (CPU) m0_wb_dat_o => cpu_ram_wb_dat_o, m0_wb_dat_i => cpu_ram_wb_dat_i, m0_wb_adr_i => cpu_ram_wb_adr_i(maxAddrBit downto 0), m0_wb_sel_i => cpu_ram_wb_sel_i, m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => cpu_ram_wb_we_i, m0_wb_cyc_i => cpu_ram_wb_cyc_i, m0_wb_stb_i => cpu_ram_wb_stb_i, m0_wb_ack_o => cpu_ram_wb_ack_o, m0_wb_stall_o => cpu_ram_wb_stall_o, -- Master 1 signals m1_wb_dat_o => m_wb_dat_o, m1_wb_dat_i => m_wb_dat_i, m1_wb_adr_i => m_wb_adr_i(maxAddrBit downto 0), m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => m_wb_we_i, m1_wb_cyc_i => m_wb_cyc_i, m1_wb_stb_i => m_wb_stb_i, m1_wb_ack_o => m_wb_ack_o, m1_wb_stall_o => m_wb_stall_o, -- Slave signals s0_wb_dat_i => ram_wb_dat_i, s0_wb_dat_o => ram_wb_dat_o, s0_wb_adr_o => ram_wb_adr_o(maxAddrBit downto 0), s0_wb_sel_o => ram_wb_sel_o, s0_wb_cti_o => open, s0_wb_we_o => ram_wb_we_o, s0_wb_cyc_o => ram_wb_cyc_o, s0_wb_stb_o => ram_wb_stb_o, s0_wb_ack_i => ram_wb_ack_i, s0_wb_stall_i => ram_wb_stall_i ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/demux.vhd

13

1810

---------------------------------------------------------------------------------- -- demux.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Demultiplexes 16 la_input channels into 32 output channels, -- thus doubling the sampling rate for those channels. -- -- This module barely does anything anymore, but is kept for historical reasons. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux is port( la_input : in std_logic_vector (15 downto 0); la_input180 : in std_logic_vector (15 downto 0); clock : in std_logic; output : out std_logic_vector (31 downto 0) ); end demux; architecture behavioral of demux is begin output(15 downto 0) <= la_input; process (clock) begin if rising_edge(clock) then output(31 downto 16) <= la_input180; end if; end process; end behavioral;

mit

sinkswim/DLX-Pro

synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.c-branch_circ.vhd

1

887

library ieee; use ieee.std_logic_1164.all; -- determines wether a branch is to be taken: -- if we have BEQZ and ALU result is zero then output = 1 -- also if we have BNEZ and ALU result is not zero then output = 1 -- in all other cases out = 0 entity branch_circ is port( -- inputs branch_type : in std_logic; -- BNEZ is branch_type = '1', BEQZ is branch_type = '0' zero : in std_logic; -- from ALU, 1 when the result of an operation yields zero -- outputs branch_taken : out std_logic -- 1 means the branch has to be taken ); end branch_circ; architecture rtl of branch_circ is begin process(branch_type, zero) begin if((branch_type = '0' and zero = '1') or (branch_type = '1' and zero = '0')) then branch_taken <= '1'; else branch_taken <= '0'; end if; end process; end rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/pad.vhd

14

3980

-- -- ZPUINO IO pads -- -- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; package pad is component iopad is port( I: in std_logic; O: out std_logic; T: in std_logic; C: in std_logic; PAD: inout std_logic ); end component iopad; component ipad is port ( O: out std_logic; C: in std_logic; PAD: in std_logic ); end component ipad; component opad is port ( I: in std_logic; O: out std_logic; PAD: out std_logic ); end component opad; component isync is port ( I: in std_logic; O: out std_logic; C: in std_logic ); end component isync; end package pad; -- -- Start -- library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity isync is port ( I: in std_logic; O: out std_logic; C: in std_logic ); end entity isync; architecture behave of isync is signal s: std_logic; begin -- latch: ILD -- port map ( -- D => I, -- Q => s, -- G => C -- ); ff1: FD port map ( D => I, Q => s, C => C ); ff2: FD port map ( D => s, Q => O, C => C ); end behave; library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use work.pad.all; library unisim; use unisim.vcomponents.all; entity iopad is port ( I: in std_logic; O: out std_logic; T: in std_logic; C: in std_logic; PAD: inout std_logic ); end entity iopad; architecture behave of iopad is begin sync: isync port map ( I => PAD, O => O, C => C ); -- Tristate generator process(I,T) begin if T='1' then PAD<='Z'; else PAD<=I; end if; end process; end behave; library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use work.pad.all; library unisim; use unisim.vcomponents.all; entity ipad is port ( O: out std_logic; C: in std_logic; PAD: in std_logic ); end entity ipad; architecture behave of ipad is signal s: std_logic; begin sync: isync port map ( I => PAD, O => O, C => C ); end behave; library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use work.pad.all; library unisim; use unisim.vcomponents.all; entity opad is port ( I: in std_logic; O: out std_logic; PAD: out std_logic ); end entity opad; architecture behave of opad is begin obufi: OBUF port map ( I => I, O => PAD ); O <= I; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/muldex.vhd

13

5375

---------------------------------------------------------------------------------- -- muldex.vhd -- -- Copyright (C) 2011 Kinsa -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, data_wr to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Performs dynamic sample depth. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity muldex is port( clock : in std_logic; reset : in std_logic; data_inp : in std_logic_vector (32 downto 0); data_out : out std_logic_vector (32 downto 0); data_rd : in std_logic; data_wr : in std_logic; mem_inp : in std_logic_vector (35 downto 0); mem_out : out std_logic_vector (35 downto 0); mem_rd : out std_logic; mem_wr : out std_logic; data_size : in std_logic_vector(1 downto 0); rdstate : in std_logic; data_ready : out std_logic ); end muldex; architecture behavioral of muldex is component muldex_16 port( clock : in std_logic; reset : in std_logic; data_inp : in std_logic_vector (15 downto 0); data_out : out std_logic_vector (15 downto 0); data_wr : in std_logic; data_rd : in std_logic; mem_inp : in std_logic_vector (33 downto 0); mem_out : out std_logic_vector (33 downto 0); mem_wr : out std_logic; mem_rd : out std_logic; rle_in : in std_logic; rle_out : out std_logic ); end component; component muldex_8 port( clock : in std_logic; reset : in std_logic; data_inp : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0); data_wr : in std_logic; data_rd : in std_logic; mem_inp : in std_logic_vector (35 downto 0); mem_out : out std_logic_vector (35 downto 0); mem_wr : out std_logic; mem_rd : out std_logic; rle_in : in std_logic; rle_out : out std_logic ); end component; signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic; signal data_out_8 : std_logic_vector (7 downto 0); signal data_out_16 : std_logic_vector (15 downto 0); signal mem_out_8 : std_logic_vector (35 downto 0); signal mem_out_16 : std_logic_vector (33 downto 0); signal rle_out_8, rle_out_16 : std_logic; signal data_out_i : std_logic_vector (32 downto 0); signal mem_wr_i, mem_rd_i : std_logic; begin -- generate data_ready after 3 clk cycles from data_rd output_block: block signal a : std_logic_vector (2 downto 0); begin process(clock) begin if rising_edge(clock) then a <= a(1 downto 0) & data_rd; data_ready <= a(2); if a(2) = '1' then data_out <= data_out_i; end if; end if; end process; end block; -- generate extra mem_rd pulse when there is a previous mem_wr pulse sync_mem_block: block signal a, b : std_logic; begin mem_rd <= mem_rd_i or (not mem_wr_i and b) ; mem_wr <= mem_wr_i; process(clock) begin if rising_edge(clock) then a <= rdstate; -- check for rdstate rising edge if a = '0' and rdstate = '1' then b <= '1'; else --extend only when dynamic sample depth is enabled if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then b <= '1'; else b <= '0'; end if; end if; end if; end process; end block; mem_out <= mem_out_8 when data_size = "01" else "00" & mem_out_16 when data_size = "10" else "000" & data_inp when data_size = "00" else (others => 'X'); mem_rd_i <= mem_rd_8 when data_size = "01" else mem_rd_16 when data_size = "10" else data_rd when data_size = "00" else 'X'; mem_wr_i <= mem_wr_8 when data_size = "01" else mem_wr_16 when data_size = "10" else data_wr when data_size = "00" else 'X'; data_out_i <= rle_out_8 & x"000000" & data_out_8 when data_size = "01" else rle_out_16 & x"0000" & data_out_16 when data_size = "10" else mem_inp(32 downto 0) when data_size = "00" else (others => 'X'); rle_in <= data_inp(32); Inst_m16: muldex_16 port map( clock => clock, reset => reset, data_inp => data_inp(15 downto 0), data_out => data_out_16, data_wr => data_wr, data_rd => data_rd, mem_inp => mem_inp(33 downto 0), mem_out => mem_out_16, mem_wr => mem_wr_16, mem_rd => mem_rd_16, rle_in => rle_in, rle_out => rle_out_16 ); Inst_m8: muldex_8 port map( clock => clock, reset => reset, data_inp => data_inp(7 downto 0), data_out => data_out_8, data_wr => data_wr, data_rd => data_rd, mem_inp => mem_inp, mem_out => mem_out_8, mem_wr => mem_wr_8, mem_rd => mem_rd_8, rle_in => rle_in, rle_out => rle_out_8 ); end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/MISC_zpuino_sa_splitter2.vhd

13

1093

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09:01:17 11/27/2013 -- Design Name: -- Module Name: MISC_zpuino_sa_splitter2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MISC_zpuino_sa_splitter2 is Port ( in1 : in STD_LOGIC; out1 : out STD_LOGIC; out2 : out STD_LOGIC); end MISC_zpuino_sa_splitter2; architecture Behavioral of MISC_zpuino_sa_splitter2 is begin out1 <= in1; out2 <= in1; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/zpuino_debug_core_hyperion.vhd

13

5403

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpuino_config.all; use board.zpu_config_hyperion.all; use board.zpupkg_hyperion.all; use board.zpuinopkg.all; entity zpuino_debug_core_hyperion is port ( clk: in std_logic; rst: in std_logic; dbg_in: in zpu_dbg_out_type; dbg_out: out zpu_dbg_in_type; dbg_reset: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end entity; architecture behave of zpuino_debug_core_hyperion is signal enter_ss: std_logic :='0'; signal step: std_logic := '0'; signal status_injection_ready: std_logic; signal status_injectmode: std_logic; type state_type is ( state_idle, state_debug, state_enter_inject, state_flush, state_inject, state_leave_inject, state_step ); type dbgregs_type is record state: state_type; step: std_logic; inject: std_logic; freeze: std_logic; injectmode: std_logic; reset: std_logic; flush: std_logic; opcode: std_logic_vector(7 downto 0); end record; signal dbgr: dbgregs_type; signal injected: std_logic; signal inject_q_in: std_logic := '0'; signal inject_q: std_logic := '0'; alias jtag_debug: std_logic is jtag_ctrl_chain_in(0); alias jtag_inject: std_logic is jtag_ctrl_chain_in(1); alias jtag_step: std_logic is jtag_ctrl_chain_in(2); alias jtag_reset: std_logic is jtag_ctrl_chain_in(3); alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4); signal pc_i: std_logic_vector(wordSize-1 downto 0); signal sp_i: std_logic_vector(wordSize-1 downto 0); begin pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0'); pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc; sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0'); sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp; sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0'); -- jtag chain output jtag_data_chain_out <= dbg_in.idim & sp_i & dbg_in.stacka & pc_i & dbg_in.brk & status_injection_ready ; status_injection_ready <= '1' when dbgr.state = state_debug else '0'; process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode, inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in) variable w: dbgregs_type; begin w := dbgr; if rst='1' then w.state := state_idle; w.reset := '0'; w.flush := '0'; w.injectmode := '0'; w.inject := '0'; w.step := '0'; w.freeze := '0'; injected <= '0'; else injected <= '0'; case dbgr.state is when state_idle => w.freeze := '0'; --if jtag_debug='1' then -- w.freeze := '1'; -- w.state := state_debug; --end if; if jtag_debug='1' then --if dbg_ready='1' then w.injectmode := '1'; --w.opcode := jtag_opcode; -- end if; -- Wait for pipeline to finish if dbg_in.valid='0' and dbg_in.ready='1' then --report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note; w.state:=state_debug; end if; --end if; end if; when state_debug => w.step := '0'; if inject_q='1' then w.state := state_enter_inject; w.injectmode := '1'; w.opcode := jtag_opcode; elsif jtag_debug='0' then w.flush:='1'; w.state := state_leave_inject; end if; when state_leave_inject => w.flush := '0'; w.injectmode:='0'; w.state := state_idle; when state_enter_inject => -- w.state := state_flush; w.state := state_inject; when state_flush => w.flush := '1'; w.state := state_inject; when state_inject => w.inject := '1'; w.flush := '0'; -- Here ? injected <= '1'; w.state := state_step; when state_step => injected <= '0'; w.inject := '0'; if dbg_in.valid='1' then -- w.step := '1'; w.state := state_debug; end if; when others => end case; end if; if rising_edge(clk) then dbgr <= w; end if; end process; dbg_out.freeze <= dbgr.freeze; --dbg_reset <= dbgr.reset; dbg_out.inject <= dbgr.inject; dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready; dbg_out.step <= dbgr.step; dbg_out.flush <= dbgr.flush; dbg_out.opcode <= dbgr.opcode; process(clk) begin if rising_edge(clk) then dbg_reset <= jtag_ctrl_chain_in(3); end if; end process; -- Synchronization stuff process(jtag_inject, clk, injected, inject_q_in) begin if injected='1' then inject_q <= '0'; inject_q_in <= '0'; else if rising_edge(jtag_inject) then inject_q_in <= '1'; --else -- inject_q_in <= inject_q_in; end if; if rising_edge(clk) then inject_q <= inject_q_in; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/clk_32to25_dcm.vhd

13

6302

-- file: clk_32to25_dcm.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1____50.000______0.000______50.0______600.000____150.000 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary__________32.000____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_32to25_dcm is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end clk_32to25_dcm; architecture xilinx of clk_32to25_dcm is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to25_dcm,clk_wiz_v3_6,{component_name=clk_32to25_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering signal clkfb : std_logic; signal clk0 : std_logic; signal clkfx : std_logic; signal clkfbout : std_logic; signal locked_internal : std_logic; signal status_internal : std_logic_vector(7 downto 0); begin -- Input buffering -------------------------------------- --clkin1 <= CLK_IN1; clkin2_inst: BUFG port map ( I => CLK_IN1, O => clkin1 ); -- Clocking primitive -------------------------------------- -- Instantiation of the DCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused dcm_sp_inst: DCM_SP generic map (CLKDV_DIVIDE => 2.000, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.25, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map -- Input clock (CLKIN => clkin1, CLKFB => clkfb, -- Output clocks CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKFX => clkfx, CLKFX180 => open, CLKDV => open, -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => locked_internal, STATUS => status_internal, RST => '0', -- Unused pin, tie low DSSEN => '0'); -- Output buffering ------------------------------------- -- no phase alignment active, connect to ground clkfb <= '0'; -- clkout1_buf : BUFG -- port map -- (O => CLK_OUT1, -- I => clkfx); CLK_OUT1 <= clkfx; end xilinx;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Benchy/receiver.vhd

13

6114

---------------------------------------------------------------------------------- -- receiver.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Receives commands from the serial port. The first byte is the commands -- opcode, the following (optional) four byte are the command data. -- Commands that do not have the highest bit in their opcode set are -- considered short commands without data (1 byte long). All other commands are -- long commands which are 5 bytes long. -- -- After a full command has been received it will be kept available for 10 cycles -- on the op and data outputs. A valid command can be detected by checking if the -- execute output is set. After 10 cycles the registers will be cleared -- automatically and the receiver waits for new data from the serial port. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity receiver is generic ( FREQ : integer; RATE : integer ); Port ( rx : in STD_LOGIC; clock : in STD_LOGIC; trxClock : IN std_logic; reset : in STD_LOGIC; op : out STD_LOGIC_VECTOR (7 downto 0); data : out STD_LOGIC_VECTOR (31 downto 0); execute : out STD_LOGIC ); end receiver; architecture Behavioral of receiver is type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY); -- constant BITLENGTH : integer := FREQ / RATE; constant BITLENGTH : integer := 16; signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command signal state, nstate : UART_STATES; -- receiver state signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword begin op <= opcode; data <= dataBuf; process(clock, reset) begin if reset = '1' then state <= INIT; elsif rising_edge(clock) then counter <= ncounter; bitcount <= nbitcount; bytecount <= nbytecount; dataBuf <= ndataBuf; opcode <= nopcode; state <= nstate; end if; end process; process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx) begin case state is -- reset uart when INIT => ncounter <= 0; nbitcount <= 0; nbytecount <= 0; nopcode <= (others => '0'); ndataBuf <= (others => '0'); nstate <= WAITSTOP; -- wait for stop bit when WAITSTOP => ncounter <= 0; nbitcount <= 0; nbytecount <= bytecount; nopcode <= opcode; ndataBuf <= dataBuf; if rx = '1' then nstate <= WAITSTART; else nstate <= state; end if; -- wait for start bit when WAITSTART => ncounter <= 0; nbitcount <= 0; nbytecount <= bytecount; nopcode <= opcode; ndataBuf <= dataBuf; if rx = '0' then nstate <= WAITBEGIN; else nstate <= state; end if; -- wait for first half of start bit when WAITBEGIN => nbitcount <= 0; nbytecount <= bytecount; nopcode <= opcode; ndataBuf <= dataBuf; if counter = BITLENGTH / 2 then ncounter <= 0; nstate <= READBYTE; else if trxClock = '1' then ncounter <= counter + 1; else ncounter <= counter; end if; nstate <= state; end if; -- receive byte when READBYTE => if counter = BITLENGTH then ncounter <= 0; nbitcount <= bitcount + 1; if bitcount = 8 then nbytecount <= bytecount + 1; nstate <= ANALYZE; nopcode <= opcode; ndataBuf <= dataBuf; else nbytecount <= bytecount; if bytecount = 0 then nopcode <= rx & opcode(7 downto 1); ndataBuf <= dataBuf; else nopcode <= opcode; ndataBuf <= rx & dataBuf(31 downto 1); end if; nstate <= state; end if; else if trxClock = '1' then ncounter <= counter + 1; else ncounter <= counter; end if; nbitcount <= bitcount; nbytecount <= bytecount; nopcode <= opcode; ndataBuf <= dataBuf; nstate <= state; end if; -- check if long or short command has been fully received when ANALYZE => ncounter <= 0; nbitcount <= 0; nbytecount <= bytecount; nopcode <= opcode; ndataBuf <= dataBuf; -- long command when 5 bytes have been received if bytecount = 5 then nstate <= READY; -- short command when set flag not set elsif opcode(7) = '0' then nstate <= READY; -- otherwise continue receiving else nstate <= WAITSTOP; end if; -- done, give 10 cycles for processing when READY => ncounter <= counter + 1; nbitcount <= 0; nbytecount <= 0; nopcode <= opcode; ndataBuf <= dataBuf; if counter = 10 then nstate <= INIT; else nstate <= state; end if; end case; end process; -- set execute flag properly process(state) begin if state = READY then execute <= '1'; else execute <= '0'; end if; end process; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Benchy/BRAM6k36bit.vhd

13

3666

---------------------------------------------------------------------------------- -- BRAM8k32bit.vhd -- -- Copyright (C) 2007 Jonas Diemer -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Single Ported RAM, 32bit wide, 8k deep. -- -- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are -- concatenated to form a 32bit wide, 8k deep RAM. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity BRAM6k36bit is Port ( CLK : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR (12 downto 0); WE : in STD_LOGIC; DOUT : out STD_LOGIC_VECTOR (35 downto 0); DIN : in STD_LOGIC_VECTOR (35 downto 0)); end BRAM6k36bit; architecture Behavioral of BRAM6k36bit is type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; --signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0); signal WEB : std_logic_vector(11 downto 0); begin -- BlockRAMS: for i in 0 to 11 generate -- RAMB16_S2_inst : RAMB16_S2 -- generic map ( -- INIT => X"0", -- Value of output RAM registers at startup -- SRVAL => X"0", -- Ouput value upon SSR assertion -- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE -- ) -- port map ( -- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output -- ADDR => ADDR, -- 13-bit Address Input -- CLK => CLK, -- Clock -- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input -- EN => '1', -- RAM Enable Input -- SSR => '0', -- Synchronous Set/Reset Input -- WE => WE -- Write Enable Input -- ); -- end generate; BlockRAMS: for i in 0 to 11 generate RAMB16_S36_inst : RAMB16_S36 generic map ( INIT => X"0", -- Value of output RAM registers at startup SRVAL => X"0", -- Ouput value upon SSR assertion WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE ) port map ( DO => RAMBlDOut(i)(31 downto 0), DOP => RAMBlDOut(i)(35 downto 32), ADDR => ADDR(8 downto 0), -- 8-bit Address Input CLK => CLK, -- Clock DI => DIN(31 downto 0), DIP => DIN(35 downto 32), EN => '1', -- RAM Enable Input SSR => '0', -- Synchronous Set/Reset Input WE => WEB(i) -- Write Enable Input ); end generate; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0'; end generate ; dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9))); end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/wbarb2_1.vhd

13

3656

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_stall_o: out std_logic; m0_wb_ack_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; m1_wb_stall_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; s0_wb_stall_i: in std_logic ); end entity wbarb2_1; architecture behave of wbarb2_1 is signal current_master: std_logic; signal next_master: std_logic; begin process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then current_master <= '0'; else current_master <= next_master; end if; end if; end process; process(current_master, m0_wb_cyc_i, m1_wb_cyc_i) begin next_master <= current_master; case current_master is when '0' => if m0_wb_cyc_i='0' then if m1_wb_cyc_i='1' then next_master <= '1'; end if; end if; when '1' => if m1_wb_cyc_i='0' then if m0_wb_cyc_i='1' then next_master <= '0'; end if; end if; when others => end case; end process; -- Muxers for slave process(current_master, m0_wb_dat_i, m0_wb_adr_i, m0_wb_sel_i, m0_wb_cti_i, m0_wb_we_i, m0_wb_cyc_i, m0_wb_stb_i, m1_wb_dat_i, m1_wb_adr_i, m1_wb_sel_i, m1_wb_cti_i, m1_wb_we_i, m1_wb_cyc_i, m1_wb_stb_i) begin case current_master is when '0' => s0_wb_dat_o <= m0_wb_dat_i; s0_wb_adr_o <= m0_wb_adr_i; s0_wb_sel_o <= m0_wb_sel_i; s0_wb_cti_o <= m0_wb_cti_i; s0_wb_we_o <= m0_wb_we_i; s0_wb_cyc_o <= m0_wb_cyc_i; s0_wb_stb_o <= m0_wb_stb_i; when '1' => s0_wb_dat_o <= m1_wb_dat_i; s0_wb_adr_o <= m1_wb_adr_i; s0_wb_sel_o <= m1_wb_sel_i; s0_wb_cti_o <= m1_wb_cti_i; s0_wb_we_o <= m1_wb_we_i; s0_wb_cyc_o <= m1_wb_cyc_i; s0_wb_stb_o <= m1_wb_stb_i; when others => null; end case; end process; -- Muxers/sel for masters m0_wb_dat_o <= s0_wb_dat_i; m1_wb_dat_o <= s0_wb_dat_i; -- Ack m0_wb_ack_o <= s0_wb_ack_i when current_master='0' else '0'; m1_wb_ack_o <= s0_wb_ack_i when current_master='1' else '0'; m0_wb_stall_o <= s0_wb_stall_i when current_master='0' else '1'; m1_wb_stall_o <= s0_wb_stall_i when current_master='1' else '1'; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/wbarb2_1.vhd

13

3656

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_stall_o: out std_logic; m0_wb_ack_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; m1_wb_stall_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; s0_wb_stall_i: in std_logic ); end entity wbarb2_1; architecture behave of wbarb2_1 is signal current_master: std_logic; signal next_master: std_logic; begin process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then current_master <= '0'; else current_master <= next_master; end if; end if; end process; process(current_master, m0_wb_cyc_i, m1_wb_cyc_i) begin next_master <= current_master; case current_master is when '0' => if m0_wb_cyc_i='0' then if m1_wb_cyc_i='1' then next_master <= '1'; end if; end if; when '1' => if m1_wb_cyc_i='0' then if m0_wb_cyc_i='1' then next_master <= '0'; end if; end if; when others => end case; end process; -- Muxers for slave process(current_master, m0_wb_dat_i, m0_wb_adr_i, m0_wb_sel_i, m0_wb_cti_i, m0_wb_we_i, m0_wb_cyc_i, m0_wb_stb_i, m1_wb_dat_i, m1_wb_adr_i, m1_wb_sel_i, m1_wb_cti_i, m1_wb_we_i, m1_wb_cyc_i, m1_wb_stb_i) begin case current_master is when '0' => s0_wb_dat_o <= m0_wb_dat_i; s0_wb_adr_o <= m0_wb_adr_i; s0_wb_sel_o <= m0_wb_sel_i; s0_wb_cti_o <= m0_wb_cti_i; s0_wb_we_o <= m0_wb_we_i; s0_wb_cyc_o <= m0_wb_cyc_i; s0_wb_stb_o <= m0_wb_stb_i; when '1' => s0_wb_dat_o <= m1_wb_dat_i; s0_wb_adr_o <= m1_wb_adr_i; s0_wb_sel_o <= m1_wb_sel_i; s0_wb_cti_o <= m1_wb_cti_i; s0_wb_we_o <= m1_wb_we_i; s0_wb_cyc_o <= m1_wb_cyc_i; s0_wb_stb_o <= m1_wb_stb_i; when others => null; end case; end process; -- Muxers/sel for masters m0_wb_dat_o <= s0_wb_dat_i; m1_wb_dat_o <= s0_wb_dat_i; -- Ack m0_wb_ack_o <= s0_wb_ack_i when current_master='0' else '0'; m1_wb_ack_o <= s0_wb_ack_i when current_master='1' else '0'; m0_wb_stall_o <= s0_wb_stall_i when current_master='0' else '1'; m1_wb_stall_o <= s0_wb_stall_i when current_master='1' else '1'; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8.vhd

13

6645

---------------------------------------------------------------------------------- -- Papilio_Logic.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- Logic Analyzer top level module. It connects the core with the hardware -- dependent IO modules and defines all la_inputs and outputs that represent -- phyisical pins of the fpga. -- -- It defines two constants FREQ and RATE. The first is the clock frequency -- used for receiver and transmitter for generating the proper baud rate. -- The second defines the speed at which to operate the serial port. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity BENCHY_sa_SumpBlaze_LogicAnalyzer8 is generic ( brams: integer := 12 ); port( clk_32Mhz : in std_logic; --extClockIn : in std_logic; -- extClockOut : out std_logic; --extTriggerIn : in std_logic; --extTriggerOut : out std_logic; --la_input : in std_logic_vector(31 downto 0); la0 : in std_logic; la1 : in std_logic; la2 : in std_logic; la3 : in std_logic; la4 : in std_logic; la5 : in std_logic; la6 : in std_logic; la7 : in std_logic; rx : in std_logic; tx : out std_logic -- miso : out std_logic; -- mosi : in std_logic; -- sclk : in std_logic; -- cs : in std_logic; -- dataReady : out std_logic; -- adc_cs_n : inout std_logic; --armLED : out std_logic; --triggerLED : out std_logic ); end BENCHY_sa_SumpBlaze_LogicAnalyzer8; architecture behavioral of BENCHY_sa_SumpBlaze_LogicAnalyzer8 is component clockman port( clkin : in STD_LOGIC; clk0 : out std_logic ); end component; COMPONENT eia232 generic ( FREQ : integer; SCALE : integer; RATE : integer ); PORT( clock : IN std_logic; reset : in std_logic; speed : IN std_logic_vector(1 downto 0); rx : IN std_logic; data : IN std_logic_vector(31 downto 0); send : IN std_logic; tx : OUT std_logic; cmd : OUT std_logic_vector(39 downto 0); execute : OUT std_logic; busy : OUT std_logic ); END COMPONENT; component spi_slave port( clock : in std_logic; data : in std_logic_vector(31 downto 0); send : in std_logic; mosi : in std_logic; sclk : in std_logic; cs : in std_logic; miso : out std_logic; cmd : out std_logic_vector(39 downto 0); execute : out std_logic; busy : out std_logic; dataReady : out std_logic; tx_bytes : in integer range 0 to 4 ); end component; component core port( clock : in std_logic; cmd : in std_logic_vector(39 downto 0); execute : in std_logic; la_input : in std_logic_vector(31 downto 0); la_inputClock : in std_logic; output : out std_logic_vector (31 downto 0); outputSend : out std_logic; outputBusy : in std_logic; memoryIn : in std_logic_vector(35 downto 0); memoryOut : out std_logic_vector(35 downto 0); memoryRead : out std_logic; memoryWrite : out std_logic; extTriggerIn : in std_logic; extTriggerOut : out std_logic; extClockOut : out std_logic; armLED : out std_logic; triggerLED : out std_logic; tx_bytes : out integer range 0 to 4 ); end component; component sram_bram generic ( brams: integer := 12 ); port( clock : in std_logic; output : out std_logic_vector(35 downto 0); la_input : in std_logic_vector(35 downto 0); read : in std_logic; write : in std_logic ); end component; signal cmd : std_logic_vector (39 downto 0); signal memoryIn, memoryOut : std_logic_vector (35 downto 0); signal output, la_input : std_logic_vector (31 downto 0); signal clock : std_logic; signal read, write, execute, send, busy : std_logic; signal tx_bytes : integer range 0 to 4; signal extClockIn, extTriggerIn : std_logic; --Constants for UART constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM constant TRXSCALE : integer := 54; -- 16 times the desired baud rate. Example 100000000/(16*115200) = 54 constant RATE : integer := 115200; -- maximum & base rate constant SPEED : std_logic_vector (1 downto 0) := "00"; --Sets the speed for UART communications begin --la_input <= (others => '0'); la_input(0) <= la0; la_input(1) <= la1; la_input(2) <= la2; la_input(3) <= la3; la_input(4) <= la4; la_input(5) <= la5; la_input(6) <= la6; la_input(7) <= la7; -- adc_cs_n <= '1'; --Disables ADC Inst_clockman: clockman port map( clkin => clk_32Mhz, clk0 => clock ); Inst_eia232: eia232 generic map ( FREQ => FREQ, SCALE => TRXSCALE, RATE => RATE ) PORT MAP( clock => clock, reset => '0', speed => SPEED, rx => rx, tx => tx, cmd => cmd, execute => execute, data => output, send => send, busy => busy ); -- Inst_spi_slave: spi_slave -- port map( -- clock => clock, -- data => output, -- send => send, -- mosi => mosi, -- sclk => sclk, -- cs => cs, -- miso => miso, -- cmd => cmd, -- execute => execute, -- busy => busy, -- dataReady => dataReady, -- tx_bytes => tx_bytes -- ); extClockIn <= '0'; --External clock disabled extTriggerIn <= '0'; --External trigger disabled Inst_core: core port map( clock => clock, cmd => cmd, execute => execute, la_input => la_input, la_inputClock => extClockIn, output => output, outputSend => send, outputBusy => busy, memoryIn => memoryIn, memoryOut => memoryOut, memoryRead => read, memoryWrite => write, extTriggerIn => extTriggerIn, extTriggerOut => open, extClockOut => open, armLED => open, triggerLED => open, tx_bytes => tx_bytes ); Inst_sram: sram_bram generic map ( brams => brams ) port map( clock => clock, output => memoryIn, la_input => memoryOut, read => read, write => write ); end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Benchy/core.vhd

13

14437

---------------------------------------------------------------------------------- -- core.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- The core contains all "platform independent" modules and provides a -- simple interface to those components. The core makes the analyzer -- memory type and computer interface independent. -- -- This module also provides a better target for test benches as commands can -- be sent to the core easily. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity core is port( clock : in std_logic; cmd : in std_logic_vector (39 downto 0); execute : in std_logic; la_input : in std_logic_vector (31 downto 0); la_inputClock : in std_logic; output : out std_logic_vector (31 downto 0); outputSend : out std_logic; outputBusy : in std_logic; memoryIn : in std_logic_vector (35 downto 0); memoryOut : out std_logic_vector (35 downto 0); memoryRead : out std_logic; memoryWrite : out std_logic; extTriggerIn : in std_logic; extTriggerOut : out std_logic; extClockOut : out std_logic; armLED : out std_logic; triggerLED : out std_logic; reset : out std_logic; tx_bytes : out integer range 0 to 4 ); end core; architecture behavioral of core is component decoder port( opcode : in std_logic_vector (7 downto 0); execute : in std_logic; clock : in std_logic; wrtrigmask : out std_logic_vector(3 downto 0); wrtrigval : out std_logic_vector(3 downto 0); wrtrigcfg : out std_logic_vector(3 downto 0); wrspeed : out std_logic; wrsize : out std_logic; wrFlags : out std_logic; arm : out std_logic; reset : out std_logic; abort : out std_logic; ident : out std_logic; meta : out std_logic ); end component; component flags port( data : in std_logic_vector(10 downto 0); clock : in std_logic; write : in std_logic; demux : out std_logic; filter : out std_logic; external : out std_logic; inverted : out std_logic; disabledGroups : out std_logic_vector (3 downto 0); rle : out std_logic; test_mode : out std_logic; data_size : out std_logic_vector (1 downto 0); num_scheme : out std_logic ); end component; component sync is port( la_input : in std_logic_vector (31 downto 0); clock : in std_logic; enableFilter : in std_logic; enableDemux : in std_logic; falling : in std_logic; output : out std_logic_vector (31 downto 0) ); end component; component testmode is port( clock : in std_logic; enable : in std_logic; la_input : in std_logic_vector (31 downto 0); output : out std_logic_vector (31 downto 0) ); end component; component sampler port( la_input : in std_logic_vector(31 downto 0); clock : in std_logic; exClock : in std_logic; external : in std_logic; data : in std_logic_vector(23 downto 0); wrDivider : in std_logic; sample : out std_logic_vector(31 downto 0); ready : out std_logic; trig_delay : out std_logic_vector(1 downto 0); num_scheme : in std_logic ); end component; component trigger port( la_input : in std_logic_vector(31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector(31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic_vector(3 downto 0); wrValue : in std_logic_vector(3 downto 0); wrConfig : in std_logic_vector(3 downto 0); arm : in std_logic; demuxed : in std_logic; run : out std_logic; ExtTriggerIn : in std_logic ); end component; component group_selector port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end component; component rle port( clock : in std_logic; reset : in std_logic; enable : in std_logic; raw_inp : in std_logic_vector (31 downto 0); raw_inp_valid : in std_logic; rle_out : out std_logic_vector (32 downto 0); rle_out_valid : out std_logic; rle_inp : in std_logic_vector (32 downto 0); rle_inp_valid : in std_logic; fmt_out : out std_logic_vector (31 downto 0); busy : out std_logic; rle_ready : out std_logic; raw_ready : in std_logic; -- start_count : in std_logic; -- data_count : out std_logic_vector(15 downto 0); data_size : in std_logic_vector(1 downto 0) ); end component; component controller port( clock : in std_logic; reset : in std_logic; la_input : in std_logic_vector (32 downto 0); la_inputReady : in std_logic; run : in std_logic; wrSize : in std_logic; data : in std_logic_vector (31 downto 0); busy : in std_logic; send : out std_logic; output : out std_logic_vector (31 downto 0); memoryIn : in std_logic_vector (31 downto 0); memoryOut : out std_logic_vector (32 downto 0); memoryRead : out std_logic; memoryWrite : out std_logic; rle_busy : in std_logic; rle_read : out std_logic; rle_mode : in std_logic; rdstate : out std_logic; data_ready : in std_logic; trig_delay : in std_logic_vector(1 downto 0); abort : in std_logic ); end component; component muldex port( clock : in std_logic; reset : in std_logic; data_inp : in std_logic_vector (32 downto 0); data_out : out std_logic_vector (32 downto 0); data_rd : in std_logic; data_wr : in std_logic; mem_inp : in std_logic_vector (35 downto 0); mem_out : out std_logic_vector (35 downto 0); mem_rd : out std_logic; mem_wr : out std_logic; data_size : in std_logic_vector(1 downto 0); rdstate : in std_logic; data_ready : out std_logic ); end component; signal opcode : std_logic_vector (7 downto 0); signal data : std_logic_vector (31 downto 0); signal sample, syncedla_input : std_logic_vector (31 downto 0); signal sampleClock, run : std_logic; signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0); signal wrDivider, wrsize, arm, resetCmd: std_logic; signal flagDemux, flagFilter, flagExternal, flagInverted : std_logic; signal wrFlags, sampleReady, flagRLE, flagTest : std_logic; signal armLEDreg : std_logic := '0'; signal triggerLEDreg : std_logic := '0'; signal data_rd, data_wr, controller_la_inputReady : std_logic; signal rle_busy, rle_inp_valid, raw_inp_ready : std_logic; signal data_size : std_logic_vector(1 downto 0); signal disabledGroups : std_logic_vector (3 downto 0); signal la_input_sampler : std_logic_vector(31 downto 0); signal controller_memoryIn, raw_inp : std_logic_vector (31 downto 0); signal data_inp, controller_la_input, rle_inp : std_logic_vector (32 downto 0); signal data_ready, raw_ready, rdstate : std_logic := '0'; signal trig_delay : std_logic_vector(1 downto 0); signal num_scheme, abort, ident, meta : std_logic; signal output_i : std_logic_vector (31 downto 0); signal outputSend_i : std_logic; signal tx_bytes_i : integer range 0 to 4; begin data <= cmd(39 downto 8); opcode <= cmd(7 downto 0); reset <= resetCmd; --armLED <= not armLEDreg; --Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on. --triggerLED <= not triggerLEDreg; --extClockOut <= sampleClock; --extTriggerOut <= run; tx_bytes_i <= 1 when data_size = "01" else 2 when data_size = "10" else 3 when disabledGroups = "1000" and flagRLE = '0' else 3 when disabledGroups = "0100" and flagRLE = '0' else 3 when disabledGroups = "0010" and flagRLE = '0' else 3 when disabledGroups = "0001" and flagRLE = '0' else 4; -- process commands process_cmd_block : block constant rom_size : natural := 18; type states is (IDLE, IDENTIFY, METADATA, BUSYWAIT); type rom_type is array (rom_size-1 downto 0) of std_logic_vector (31 downto 0); constant rom : rom_type := ( 0 => x"00000020", 1 => x"00002120", -- 0x20 0x00000020 2 => x"00220018", 3 => x"23001800", -- 0x21 0x00001800 4 => x"00e1f505", 5 => x"00000024", -- 0x22 0x00001800 6 => x"41204002", 7 => x"704f0102", -- 0x23 0x05f5e100 8 => x"65626e65", 9 => x"2068636e", -- 0x24 0x00000002 10 => x"69676f4c", 11 => x"6e532063", -- 0x40 0x20 12 => x"65666669", 13 => x"31762072", -- 0x41 0x02 14 => x"0031302e", 15 => x"302e3302", 16 => x"48560300", others => x"00004c44" ); -- 0x01 "Openbench Logic Sniffer v1.01" -- 0x02 "3.0" -- 0x03 "VHDL" signal state : states; signal send_cmd : std_logic; signal cmd_output : std_logic_vector (31 downto 0); signal addr : integer range 0 to rom_size + 1; begin tx_bytes <= 4 when send_cmd = '1' else tx_bytes_i; output <= cmd_output when send_cmd = '1' else output_i; outputSend <= '1' when send_cmd = '1' else outputSend_i; process(clock) begin if rising_edge(clock) then case state is when IDLE => if outputBusy = '0' then if ident = '1' then state <= IDENTIFY; end if; --Disabled, this was wreaking havoc with SPI slave -- if meta = '1' then -- state <= METADATA; -- end if; end if; send_cmd <= '0'; addr <= 0; when IDENTIFY => send_cmd <= '1'; cmd_output <= x"534c4131"; -- "SLA1" state <= IDLE; when METADATA => send_cmd <= '1'; cmd_output <= rom(addr); addr <= addr + 1; state <= BUSYWAIT; when BUSYWAIT => send_cmd <= '0'; if outputBusy = '0' and send_cmd = '0' then if addr = rom_size then state <= IDLE; else state <= METADATA; end if; end if; end case; end if; end process; end block; --Generates observable trigger and arm LED signals -- process (clock) -- begin -- if rising_edge(clock) then -- if arm = '1' then -- armLEDreg <= '1'; -- triggerLEDreg <= '0'; -- elsif run = '1' then -- armLEDreg <= '0'; -- triggerLEDreg <= '1'; -- end if; -- end if; -- end process; -- select between internal and external sampling clock -- BUFGMUX_intex: BUFGMUX -- port map ( -- O => sampleClock, -- Clock MUX output -- I0 => clock, -- Clock0 la_input -- I1 => la_inputClock, -- Clock1 la_input -- S => flagExternal -- Clock select la_input -- ); sampleClock <= clock; Inst_decoder: decoder port map( opcode => opcode, execute => execute, clock => clock, wrtrigmask => wrtrigmask, wrtrigval => wrtrigval, wrtrigcfg => wrtrigcfg, wrspeed => wrDivider, wrsize => wrsize, wrFlags => wrFlags, arm => arm, reset => resetCmd, abort => abort, ident => ident, meta => meta ); Inst_flags: flags port map( data => data(10 downto 0), clock => clock, write => wrFlags, demux => flagDemux, filter => flagFilter, external => flagExternal, inverted => flagInverted, disabledGroups => disabledGroups, rle => flagRLE, test_mode => flagTest, data_size => data_size, num_scheme => num_scheme ); Inst_sync: sync port map( la_input => la_input, clock => sampleClock, enableFilter => flagFilter, enableDemux => flagDemux, falling => flagInverted, output => syncedla_input ); -- Inst_testmode: testmode -- port map( -- clock => clock, -- enable => flagTest, -- la_input => syncedla_input, -- output => la_input_sampler -- ); Inst_sampler: sampler port map( la_input => syncedla_input, clock => clock, exClock => la_inputClock, external => flagExternal, data => data(23 downto 0), wrDivider => wrDivider, sample => sample, ready => sampleReady, trig_delay => trig_delay, num_scheme => num_scheme ); Inst_trigger: trigger port map( la_input => sample, la_inputReady => sampleReady, data => data, clock => clock, reset => resetCmd, wrMask => wrtrigmask, wrValue => wrtrigval, wrConfig => wrtrigcfg, arm => arm, demuxed => flagDemux, run => run, extTriggerIn => extTriggerIn ); Inst_group_selector: group_selector port map( clock => clock, la_input => sample, la_input_ready => sampleReady, output => raw_inp, output_ready => raw_inp_ready, disabledGroups => disabledGroups ); Inst_rle: rle port map( clock => clock, reset => resetCmd, raw_inp => raw_inp, fmt_out => controller_memoryIn, enable => flagRLE, raw_inp_valid => raw_inp_ready, rle_inp_valid => rle_inp_valid, -- start_count => run, data_size => data_size, rle_out => controller_la_input, rle_inp => rle_inp, rle_out_valid => controller_la_inputReady, busy => rle_busy, rle_ready => data_ready, raw_ready => raw_ready ); Inst_controller: controller port map( clock => clock, reset => resetCmd, la_input => controller_la_input, la_inputReady => controller_la_inputReady, run => run, wrSize => wrSize, data => data, busy => outputBusy, send => outputSend_i, output => output_i, memoryIn => controller_memoryIn, memoryOut => data_inp, memoryRead => data_rd, memoryWrite => data_wr, rle_busy => rle_busy, rle_read => rle_inp_valid, rle_mode => flagRLE, rdstate => rdstate, data_ready => data_ready, trig_delay => trig_delay, abort => abort ); Inst_muldex : muldex port map( clock => clock, reset => resetCmd, data_inp => data_inp, data_out => rle_inp, data_rd => data_rd, data_wr => data_wr, mem_inp => memoryIn, mem_out => memoryOut, mem_rd => memoryRead, mem_wr => memoryWrite, data_size => data_size, rdstate => rdstate, data_ready => raw_ready ); end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Benchy/core.vhd

13

14437

---------------------------------------------------------------------------------- -- core.vhd -- -- Copyright (C) 2006 Michael Poppitz -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- The core contains all "platform independent" modules and provides a -- simple interface to those components. The core makes the analyzer -- memory type and computer interface independent. -- -- This module also provides a better target for test benches as commands can -- be sent to the core easily. -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity core is port( clock : in std_logic; cmd : in std_logic_vector (39 downto 0); execute : in std_logic; la_input : in std_logic_vector (31 downto 0); la_inputClock : in std_logic; output : out std_logic_vector (31 downto 0); outputSend : out std_logic; outputBusy : in std_logic; memoryIn : in std_logic_vector (35 downto 0); memoryOut : out std_logic_vector (35 downto 0); memoryRead : out std_logic; memoryWrite : out std_logic; extTriggerIn : in std_logic; extTriggerOut : out std_logic; extClockOut : out std_logic; armLED : out std_logic; triggerLED : out std_logic; reset : out std_logic; tx_bytes : out integer range 0 to 4 ); end core; architecture behavioral of core is component decoder port( opcode : in std_logic_vector (7 downto 0); execute : in std_logic; clock : in std_logic; wrtrigmask : out std_logic_vector(3 downto 0); wrtrigval : out std_logic_vector(3 downto 0); wrtrigcfg : out std_logic_vector(3 downto 0); wrspeed : out std_logic; wrsize : out std_logic; wrFlags : out std_logic; arm : out std_logic; reset : out std_logic; abort : out std_logic; ident : out std_logic; meta : out std_logic ); end component; component flags port( data : in std_logic_vector(10 downto 0); clock : in std_logic; write : in std_logic; demux : out std_logic; filter : out std_logic; external : out std_logic; inverted : out std_logic; disabledGroups : out std_logic_vector (3 downto 0); rle : out std_logic; test_mode : out std_logic; data_size : out std_logic_vector (1 downto 0); num_scheme : out std_logic ); end component; component sync is port( la_input : in std_logic_vector (31 downto 0); clock : in std_logic; enableFilter : in std_logic; enableDemux : in std_logic; falling : in std_logic; output : out std_logic_vector (31 downto 0) ); end component; component testmode is port( clock : in std_logic; enable : in std_logic; la_input : in std_logic_vector (31 downto 0); output : out std_logic_vector (31 downto 0) ); end component; component sampler port( la_input : in std_logic_vector(31 downto 0); clock : in std_logic; exClock : in std_logic; external : in std_logic; data : in std_logic_vector(23 downto 0); wrDivider : in std_logic; sample : out std_logic_vector(31 downto 0); ready : out std_logic; trig_delay : out std_logic_vector(1 downto 0); num_scheme : in std_logic ); end component; component trigger port( la_input : in std_logic_vector(31 downto 0); la_inputReady : in std_logic; data : in std_logic_vector(31 downto 0); clock : in std_logic; reset : in std_logic; wrMask : in std_logic_vector(3 downto 0); wrValue : in std_logic_vector(3 downto 0); wrConfig : in std_logic_vector(3 downto 0); arm : in std_logic; demuxed : in std_logic; run : out std_logic; ExtTriggerIn : in std_logic ); end component; component group_selector port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end component; component rle port( clock : in std_logic; reset : in std_logic; enable : in std_logic; raw_inp : in std_logic_vector (31 downto 0); raw_inp_valid : in std_logic; rle_out : out std_logic_vector (32 downto 0); rle_out_valid : out std_logic; rle_inp : in std_logic_vector (32 downto 0); rle_inp_valid : in std_logic; fmt_out : out std_logic_vector (31 downto 0); busy : out std_logic; rle_ready : out std_logic; raw_ready : in std_logic; -- start_count : in std_logic; -- data_count : out std_logic_vector(15 downto 0); data_size : in std_logic_vector(1 downto 0) ); end component; component controller port( clock : in std_logic; reset : in std_logic; la_input : in std_logic_vector (32 downto 0); la_inputReady : in std_logic; run : in std_logic; wrSize : in std_logic; data : in std_logic_vector (31 downto 0); busy : in std_logic; send : out std_logic; output : out std_logic_vector (31 downto 0); memoryIn : in std_logic_vector (31 downto 0); memoryOut : out std_logic_vector (32 downto 0); memoryRead : out std_logic; memoryWrite : out std_logic; rle_busy : in std_logic; rle_read : out std_logic; rle_mode : in std_logic; rdstate : out std_logic; data_ready : in std_logic; trig_delay : in std_logic_vector(1 downto 0); abort : in std_logic ); end component; component muldex port( clock : in std_logic; reset : in std_logic; data_inp : in std_logic_vector (32 downto 0); data_out : out std_logic_vector (32 downto 0); data_rd : in std_logic; data_wr : in std_logic; mem_inp : in std_logic_vector (35 downto 0); mem_out : out std_logic_vector (35 downto 0); mem_rd : out std_logic; mem_wr : out std_logic; data_size : in std_logic_vector(1 downto 0); rdstate : in std_logic; data_ready : out std_logic ); end component; signal opcode : std_logic_vector (7 downto 0); signal data : std_logic_vector (31 downto 0); signal sample, syncedla_input : std_logic_vector (31 downto 0); signal sampleClock, run : std_logic; signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0); signal wrDivider, wrsize, arm, resetCmd: std_logic; signal flagDemux, flagFilter, flagExternal, flagInverted : std_logic; signal wrFlags, sampleReady, flagRLE, flagTest : std_logic; signal armLEDreg : std_logic := '0'; signal triggerLEDreg : std_logic := '0'; signal data_rd, data_wr, controller_la_inputReady : std_logic; signal rle_busy, rle_inp_valid, raw_inp_ready : std_logic; signal data_size : std_logic_vector(1 downto 0); signal disabledGroups : std_logic_vector (3 downto 0); signal la_input_sampler : std_logic_vector(31 downto 0); signal controller_memoryIn, raw_inp : std_logic_vector (31 downto 0); signal data_inp, controller_la_input, rle_inp : std_logic_vector (32 downto 0); signal data_ready, raw_ready, rdstate : std_logic := '0'; signal trig_delay : std_logic_vector(1 downto 0); signal num_scheme, abort, ident, meta : std_logic; signal output_i : std_logic_vector (31 downto 0); signal outputSend_i : std_logic; signal tx_bytes_i : integer range 0 to 4; begin data <= cmd(39 downto 8); opcode <= cmd(7 downto 0); reset <= resetCmd; --armLED <= not armLEDreg; --Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on. --triggerLED <= not triggerLEDreg; --extClockOut <= sampleClock; --extTriggerOut <= run; tx_bytes_i <= 1 when data_size = "01" else 2 when data_size = "10" else 3 when disabledGroups = "1000" and flagRLE = '0' else 3 when disabledGroups = "0100" and flagRLE = '0' else 3 when disabledGroups = "0010" and flagRLE = '0' else 3 when disabledGroups = "0001" and flagRLE = '0' else 4; -- process commands process_cmd_block : block constant rom_size : natural := 18; type states is (IDLE, IDENTIFY, METADATA, BUSYWAIT); type rom_type is array (rom_size-1 downto 0) of std_logic_vector (31 downto 0); constant rom : rom_type := ( 0 => x"00000020", 1 => x"00002120", -- 0x20 0x00000020 2 => x"00220018", 3 => x"23001800", -- 0x21 0x00001800 4 => x"00e1f505", 5 => x"00000024", -- 0x22 0x00001800 6 => x"41204002", 7 => x"704f0102", -- 0x23 0x05f5e100 8 => x"65626e65", 9 => x"2068636e", -- 0x24 0x00000002 10 => x"69676f4c", 11 => x"6e532063", -- 0x40 0x20 12 => x"65666669", 13 => x"31762072", -- 0x41 0x02 14 => x"0031302e", 15 => x"302e3302", 16 => x"48560300", others => x"00004c44" ); -- 0x01 "Openbench Logic Sniffer v1.01" -- 0x02 "3.0" -- 0x03 "VHDL" signal state : states; signal send_cmd : std_logic; signal cmd_output : std_logic_vector (31 downto 0); signal addr : integer range 0 to rom_size + 1; begin tx_bytes <= 4 when send_cmd = '1' else tx_bytes_i; output <= cmd_output when send_cmd = '1' else output_i; outputSend <= '1' when send_cmd = '1' else outputSend_i; process(clock) begin if rising_edge(clock) then case state is when IDLE => if outputBusy = '0' then if ident = '1' then state <= IDENTIFY; end if; --Disabled, this was wreaking havoc with SPI slave -- if meta = '1' then -- state <= METADATA; -- end if; end if; send_cmd <= '0'; addr <= 0; when IDENTIFY => send_cmd <= '1'; cmd_output <= x"534c4131"; -- "SLA1" state <= IDLE; when METADATA => send_cmd <= '1'; cmd_output <= rom(addr); addr <= addr + 1; state <= BUSYWAIT; when BUSYWAIT => send_cmd <= '0'; if outputBusy = '0' and send_cmd = '0' then if addr = rom_size then state <= IDLE; else state <= METADATA; end if; end if; end case; end if; end process; end block; --Generates observable trigger and arm LED signals -- process (clock) -- begin -- if rising_edge(clock) then -- if arm = '1' then -- armLEDreg <= '1'; -- triggerLEDreg <= '0'; -- elsif run = '1' then -- armLEDreg <= '0'; -- triggerLEDreg <= '1'; -- end if; -- end if; -- end process; -- select between internal and external sampling clock -- BUFGMUX_intex: BUFGMUX -- port map ( -- O => sampleClock, -- Clock MUX output -- I0 => clock, -- Clock0 la_input -- I1 => la_inputClock, -- Clock1 la_input -- S => flagExternal -- Clock select la_input -- ); sampleClock <= clock; Inst_decoder: decoder port map( opcode => opcode, execute => execute, clock => clock, wrtrigmask => wrtrigmask, wrtrigval => wrtrigval, wrtrigcfg => wrtrigcfg, wrspeed => wrDivider, wrsize => wrsize, wrFlags => wrFlags, arm => arm, reset => resetCmd, abort => abort, ident => ident, meta => meta ); Inst_flags: flags port map( data => data(10 downto 0), clock => clock, write => wrFlags, demux => flagDemux, filter => flagFilter, external => flagExternal, inverted => flagInverted, disabledGroups => disabledGroups, rle => flagRLE, test_mode => flagTest, data_size => data_size, num_scheme => num_scheme ); Inst_sync: sync port map( la_input => la_input, clock => sampleClock, enableFilter => flagFilter, enableDemux => flagDemux, falling => flagInverted, output => syncedla_input ); -- Inst_testmode: testmode -- port map( -- clock => clock, -- enable => flagTest, -- la_input => syncedla_input, -- output => la_input_sampler -- ); Inst_sampler: sampler port map( la_input => syncedla_input, clock => clock, exClock => la_inputClock, external => flagExternal, data => data(23 downto 0), wrDivider => wrDivider, sample => sample, ready => sampleReady, trig_delay => trig_delay, num_scheme => num_scheme ); Inst_trigger: trigger port map( la_input => sample, la_inputReady => sampleReady, data => data, clock => clock, reset => resetCmd, wrMask => wrtrigmask, wrValue => wrtrigval, wrConfig => wrtrigcfg, arm => arm, demuxed => flagDemux, run => run, extTriggerIn => extTriggerIn ); Inst_group_selector: group_selector port map( clock => clock, la_input => sample, la_input_ready => sampleReady, output => raw_inp, output_ready => raw_inp_ready, disabledGroups => disabledGroups ); Inst_rle: rle port map( clock => clock, reset => resetCmd, raw_inp => raw_inp, fmt_out => controller_memoryIn, enable => flagRLE, raw_inp_valid => raw_inp_ready, rle_inp_valid => rle_inp_valid, -- start_count => run, data_size => data_size, rle_out => controller_la_input, rle_inp => rle_inp, rle_out_valid => controller_la_inputReady, busy => rle_busy, rle_ready => data_ready, raw_ready => raw_ready ); Inst_controller: controller port map( clock => clock, reset => resetCmd, la_input => controller_la_input, la_inputReady => controller_la_inputReady, run => run, wrSize => wrSize, data => data, busy => outputBusy, send => outputSend_i, output => output_i, memoryIn => controller_memoryIn, memoryOut => data_inp, memoryRead => data_rd, memoryWrite => data_wr, rle_busy => rle_busy, rle_read => rle_inp_valid, rle_mode => flagRLE, rdstate => rdstate, data_ready => data_ready, trig_delay => trig_delay, abort => abort ); Inst_muldex : muldex port map( clock => clock, reset => resetCmd, data_inp => data_inp, data_out => rle_inp, data_rd => data_rd, data_wr => data_wr, mem_inp => memoryIn, mem_out => memoryOut, mem_rd => memoryRead, mem_wr => memoryWrite, data_size => data_size, rdstate => rdstate, data_ready => raw_ready ); end behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/AUDIO_zpuino_sa_sigmadeltaDAC.vhd

13

3029

-- -- Sigma-delta output -- -- Copyright 2008,2009,2010 Álvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.2 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- Changelog: -- -- 1.2: Adapted from ALZPU to ZPUino -- 1.1: First version, imported from old controller. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity AUDIO_zpuino_sa_sigmadeltaDAC is generic ( BITS: integer := 18 ); port ( clk_96Mhz: in std_logic; --rst: in std_logic; data_in: in std_logic_vector(BITS-1 downto 0); audio_out: out std_logic ); end entity AUDIO_zpuino_sa_sigmadeltaDAC; architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is signal delta_adder: unsigned(BITS+1 downto 0); signal sigma_adder: unsigned(BITS+1 downto 0); signal sigma_latch: unsigned(BITS+1 downto 0); signal delta_b: unsigned(BITS+1 downto 0); signal dat_q: unsigned(BITS+1 downto 0); signal rst: std_logic := '0'; begin dat_q(BITS+1) <= '0'; dat_q(BITS) <= '0'; process(clk_96Mhz) begin if rising_edge(clk_96Mhz) then dat_q(BITS-1 downto 0) <= unsigned(data_in); end if; end process; process(sigma_latch) begin delta_b(BITS+1) <= sigma_latch(BITS+1); delta_b(BITS) <= sigma_latch(BITS+1); delta_b(BITS-1 downto 0) <= (others => '0'); end process; process(dat_q, delta_b) begin delta_adder <= dat_q + delta_b; end process; process(delta_adder,sigma_latch) begin sigma_adder <= delta_adder + sigma_latch; end process; process(clk_96Mhz) begin if rising_edge(clk_96Mhz) then if rst='1' then sigma_latch <= (others => '0'); sigma_latch(BITS+1) <= '1'; audio_out <= '0'; else sigma_latch <= sigma_adder; audio_out <= sigma_latch(BITS+1); end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/zpuino_top.vhd

13

16382

-- -- Top module for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpuino_config.all; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.wishbonepkg.all; entity zpuino_top is port ( clk: in std_logic; rst: in std_logic; -- Connection to board IO module slot_cyc: out slot_std_logic_type; slot_we: out slot_std_logic_type; slot_stb: out slot_std_logic_type; slot_read: in slot_cpuword_type; slot_write: out slot_cpuword_type; slot_address: out slot_address_type; slot_ack: in slot_std_logic_type; slot_interrupt: in slot_std_logic_type; dbg_reset: out std_logic; -- Memory accesses (for DMA) -- This is a master interface m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end entity zpuino_top; architecture behave of zpuino_top is component zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic; stack_a_enable: in std_logic; stack_b_writeenable: in std_logic; stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0) ); end component zpuino_stack; component wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_ack_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic ); end component; component zpuino_debug_core is port ( clk: in std_logic; rst: in std_logic; dbg_in: in zpu_dbg_out_type; dbg_out: out zpu_dbg_in_type; dbg_reset: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end component; component wb_rom_ram is port ( ram_wb_clk_i: in std_logic; ram_wb_rst_i: in std_logic; ram_wb_ack_o: out std_logic; ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); ram_wb_cyc_i: in std_logic; ram_wb_stb_i: in std_logic; ram_wb_we_i: in std_logic; rom_wb_clk_i: in std_logic; rom_wb_rst_i: in std_logic; rom_wb_ack_o: out std_logic; rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); rom_wb_cyc_i: in std_logic; rom_wb_stb_i: in std_logic; rom_wb_cti_i: in std_logic_vector(2 downto 0) ); end component wb_rom_ram; component wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end component wbmux2; signal io_read: std_logic_vector(wordSize-1 downto 0); signal io_write: std_logic_vector(wordSize-1 downto 0); signal io_address: std_logic_vector(maxAddrBitIncIO downto 0); signal io_stb: std_logic; signal io_cyc: std_logic; signal io_we: std_logic; signal io_ack: std_logic; signal wb_read: std_logic_vector(wordSize-1 downto 0); signal wb_write: std_logic_vector(wordSize-1 downto 0); signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0); signal wb_stb: std_logic; signal wb_cyc: std_logic; signal wb_we: std_logic; signal wb_ack: std_logic; signal interrupt: std_logic; signal poppc_inst: std_logic; signal dbg_pc: std_logic_vector(maxAddrBit downto 0); signal dbg_opcode: std_logic_vector(7 downto 0); signal dbg_opcode_in: std_logic_vector(7 downto 0); signal dbg_sp: std_logic_vector(10 downto 2); signal dbg_brk: std_logic; signal dbg_stacka: std_logic_vector(wordSize-1 downto 0); signal dbg_stackb: std_logic_vector(wordSize-1 downto 0); signal dbg_step: std_logic := '0'; signal dbg_freeze: std_logic; signal dbg_flush: std_logic; signal dbg_valid: std_logic; signal dbg_ready: std_logic; signal dbg_inject: std_logic; signal dbg_injectmode: std_logic; signal dbg_idim: std_logic; signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2); signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic; signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0); signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0); signal stack_clk: std_logic; signal ram_wb_clk_i: std_logic; signal ram_wb_rst_i: std_logic; signal ram_wb_ack_o: std_logic; signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal ram_wb_cyc_i: std_logic; signal ram_wb_stb_i: std_logic; signal ram_wb_we_i: std_logic; signal cpu_ram_wb_clk_i: std_logic; signal cpu_ram_wb_rst_i: std_logic; signal cpu_ram_wb_ack_o: std_logic; signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal cpu_ram_wb_cyc_i: std_logic; signal cpu_ram_wb_stb_i: std_logic; signal cpu_ram_wb_we_i: std_logic; signal rom_wb_clk_i: std_logic; signal rom_wb_rst_i: std_logic; signal rom_wb_ack_o: std_logic; signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal rom_wb_cyc_i: std_logic; signal rom_wb_stb_i: std_logic; signal rom_wb_cti_i: std_logic_vector(2 downto 0); signal dbg_to_zpu: zpu_dbg_in_type; signal dbg_from_zpu: zpu_dbg_out_type; begin core: zpu_core_extreme port map ( wb_clk_i => clk, wb_rst_i => rst, wb_ack_i => wb_ack, wb_dat_i => wb_read, wb_dat_o => wb_write, wb_adr_o => wb_address, wb_cyc_o => wb_cyc, wb_stb_o => wb_stb, wb_we_o => wb_we, wb_inta_i => interrupt, poppc_inst => poppc_inst, break => open, stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr, rom_wb_ack_i => rom_wb_ack_o, rom_wb_dat_i => rom_wb_dat_o, rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_i, rom_wb_stb_o => rom_wb_stb_i, rom_wb_cti_o => rom_wb_cti_i, rom_wb_stall_i => '0', dbg_in => dbg_to_zpu, dbg_out => dbg_from_zpu ); stack: zpuino_stack port map ( stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr ); memory: wb_rom_ram port map ( ram_wb_clk_i => clk, ram_wb_rst_i => rst, ram_wb_ack_o => ram_wb_ack_o, ram_wb_dat_i => ram_wb_dat_i, ram_wb_dat_o => ram_wb_dat_o, ram_wb_adr_i => ram_wb_adr_i, ram_wb_cyc_i => ram_wb_cyc_i, ram_wb_stb_i => ram_wb_stb_i, ram_wb_we_i => ram_wb_we_i, rom_wb_clk_i => clk, rom_wb_rst_i => rst, rom_wb_ack_o => rom_wb_ack_o, rom_wb_dat_o => rom_wb_dat_o, rom_wb_adr_i => rom_wb_adr_i, rom_wb_cyc_i => rom_wb_cyc_i, rom_wb_stb_i => rom_wb_stb_i, rom_wb_cti_i => rom_wb_cti_i ); dbg: zpuino_debug_core port map ( clk => clk, rst => rst, dbg_out => dbg_to_zpu, dbg_in => dbg_from_zpu, dbg_reset => dbg_reset, jtag_data_chain_out => jtag_data_chain_out, jtag_ctrl_chain_in => jtag_ctrl_chain_in ); io: zpuino_io port map ( wb_clk_i => clk, wb_rst_i => rst, wb_dat_o => io_read, wb_dat_i => io_write, wb_adr_i => io_address, wb_cyc_i => io_cyc, wb_stb_i => io_stb, wb_ack_o => io_ack, wb_we_i => io_we, wb_inta_o => interrupt, intready => poppc_inst, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt ); iomemmux: wbmux2 generic map ( select_line => maxAddrBitIncIO, address_high =>maxAddrBitIncIO, address_low=>0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master m_wb_dat_o => wb_read, m_wb_dat_i => wb_write, m_wb_adr_i => wb_address, m_wb_sel_i => "1111",--wb_sel, m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti, m_wb_we_i => wb_we, m_wb_cyc_i => wb_cyc, m_wb_stb_i => wb_stb, m_wb_ack_o => wb_ack, -- Slave 0 signals s0_wb_dat_i => cpu_ram_wb_dat_o, s0_wb_dat_o => cpu_ram_wb_dat_i, s0_wb_adr_o => cpu_ram_wb_adr_i, s0_wb_sel_o => open, --ram_wb_sel_i, s0_wb_cti_o => open, --ram_wb_cti_i, s0_wb_we_o => cpu_ram_wb_we_i, s0_wb_cyc_o => cpu_ram_wb_cyc_i, s0_wb_stb_o => cpu_ram_wb_stb_i, s0_wb_ack_i => cpu_ram_wb_ack_o, -- Slave 1 signals s1_wb_dat_i => io_read, s1_wb_dat_o => io_write, s1_wb_adr_o => io_address, s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => io_we, s1_wb_cyc_o => io_cyc, s1_wb_stb_o => io_stb, s1_wb_ack_i => io_ack ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBitIncIO, ADDRESS_LOW => 0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master 0 signals (CPU) m0_wb_dat_o => cpu_ram_wb_dat_o, m0_wb_dat_i => cpu_ram_wb_dat_i, m0_wb_adr_i => cpu_ram_wb_adr_i, m0_wb_sel_i => (others => '1'), m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => cpu_ram_wb_we_i, m0_wb_cyc_i => cpu_ram_wb_cyc_i, m0_wb_stb_i => cpu_ram_wb_stb_i, m0_wb_ack_o => cpu_ram_wb_ack_o, -- Master 1 signals m1_wb_dat_o => m_wb_dat_o, m1_wb_dat_i => m_wb_dat_i, m1_wb_adr_i => m_wb_adr_i, m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => m_wb_we_i, m1_wb_cyc_i => m_wb_cyc_i, m1_wb_stb_i => m_wb_stb_i, m1_wb_ack_o => m_wb_ack_o, -- Slave signals s0_wb_dat_i => ram_wb_dat_o, s0_wb_dat_o => ram_wb_dat_i, s0_wb_adr_o => ram_wb_adr_i, s0_wb_sel_o => open, s0_wb_cti_o => open, s0_wb_we_o => ram_wb_we_i, s0_wb_cyc_o => ram_wb_cyc_i, s0_wb_stb_o => ram_wb_stb_i, s0_wb_ack_i => ram_wb_ack_o ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/zpuino_top.vhd

13

16382

-- -- Top module for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpuino_config.all; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; use board.wishbonepkg.all; entity zpuino_top is port ( clk: in std_logic; rst: in std_logic; -- Connection to board IO module slot_cyc: out slot_std_logic_type; slot_we: out slot_std_logic_type; slot_stb: out slot_std_logic_type; slot_read: in slot_cpuword_type; slot_write: out slot_cpuword_type; slot_address: out slot_address_type; slot_ack: in slot_std_logic_type; slot_interrupt: in slot_std_logic_type; dbg_reset: out std_logic; -- Memory accesses (for DMA) -- This is a master interface m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end entity zpuino_top; architecture behave of zpuino_top is component zpuino_stack is port ( stack_clk: in std_logic; stack_a_read: out std_logic_vector(wordSize-1 downto 0); stack_b_read: out std_logic_vector(wordSize-1 downto 0); stack_a_write: in std_logic_vector(wordSize-1 downto 0); stack_b_write: in std_logic_vector(wordSize-1 downto 0); stack_a_writeenable: in std_logic; stack_a_enable: in std_logic; stack_b_writeenable: in std_logic; stack_b_enable: in std_logic; stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0); stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0) ); end component zpuino_stack; component wbarb2_1 is generic ( ADDRESS_HIGH: integer := maxIObit; ADDRESS_LOW: integer := maxIObit ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master 0 signals m0_wb_dat_o: out std_logic_vector(31 downto 0); m0_wb_dat_i: in std_logic_vector(31 downto 0); m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m0_wb_sel_i: in std_logic_vector(3 downto 0); m0_wb_cti_i: in std_logic_vector(2 downto 0); m0_wb_we_i: in std_logic; m0_wb_cyc_i: in std_logic; m0_wb_stb_i: in std_logic; m0_wb_ack_o: out std_logic; -- Master 1 signals m1_wb_dat_o: out std_logic_vector(31 downto 0); m1_wb_dat_i: in std_logic_vector(31 downto 0); m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); m1_wb_sel_i: in std_logic_vector(3 downto 0); m1_wb_cti_i: in std_logic_vector(2 downto 0); m1_wb_we_i: in std_logic; m1_wb_cyc_i: in std_logic; m1_wb_stb_i: in std_logic; m1_wb_ack_o: out std_logic; -- Slave signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic ); end component; component zpuino_debug_core is port ( clk: in std_logic; rst: in std_logic; dbg_in: in zpu_dbg_out_type; dbg_out: out zpu_dbg_in_type; dbg_reset: out std_logic; jtag_data_chain_out: out std_logic_vector(98 downto 0); jtag_ctrl_chain_in: in std_logic_vector(11 downto 0) ); end component; component wb_rom_ram is port ( ram_wb_clk_i: in std_logic; ram_wb_rst_i: in std_logic; ram_wb_ack_o: out std_logic; ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0); ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); ram_wb_cyc_i: in std_logic; ram_wb_stb_i: in std_logic; ram_wb_we_i: in std_logic; rom_wb_clk_i: in std_logic; rom_wb_rst_i: in std_logic; rom_wb_ack_o: out std_logic; rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0); rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0); rom_wb_cyc_i: in std_logic; rom_wb_stb_i: in std_logic; rom_wb_cti_i: in std_logic_vector(2 downto 0) ); end component wb_rom_ram; component wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end component wbmux2; signal io_read: std_logic_vector(wordSize-1 downto 0); signal io_write: std_logic_vector(wordSize-1 downto 0); signal io_address: std_logic_vector(maxAddrBitIncIO downto 0); signal io_stb: std_logic; signal io_cyc: std_logic; signal io_we: std_logic; signal io_ack: std_logic; signal wb_read: std_logic_vector(wordSize-1 downto 0); signal wb_write: std_logic_vector(wordSize-1 downto 0); signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0); signal wb_stb: std_logic; signal wb_cyc: std_logic; signal wb_we: std_logic; signal wb_ack: std_logic; signal interrupt: std_logic; signal poppc_inst: std_logic; signal dbg_pc: std_logic_vector(maxAddrBit downto 0); signal dbg_opcode: std_logic_vector(7 downto 0); signal dbg_opcode_in: std_logic_vector(7 downto 0); signal dbg_sp: std_logic_vector(10 downto 2); signal dbg_brk: std_logic; signal dbg_stacka: std_logic_vector(wordSize-1 downto 0); signal dbg_stackb: std_logic_vector(wordSize-1 downto 0); signal dbg_step: std_logic := '0'; signal dbg_freeze: std_logic; signal dbg_flush: std_logic; signal dbg_valid: std_logic; signal dbg_ready: std_logic; signal dbg_inject: std_logic; signal dbg_injectmode: std_logic; signal dbg_idim: std_logic; signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2); signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic; signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0); signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0); signal stack_clk: std_logic; signal ram_wb_clk_i: std_logic; signal ram_wb_rst_i: std_logic; signal ram_wb_ack_o: std_logic; signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal ram_wb_cyc_i: std_logic; signal ram_wb_stb_i: std_logic; signal ram_wb_we_i: std_logic; signal cpu_ram_wb_clk_i: std_logic; signal cpu_ram_wb_rst_i: std_logic; signal cpu_ram_wb_ack_o: std_logic; signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal cpu_ram_wb_cyc_i: std_logic; signal cpu_ram_wb_stb_i: std_logic; signal cpu_ram_wb_we_i: std_logic; signal rom_wb_clk_i: std_logic; signal rom_wb_rst_i: std_logic; signal rom_wb_ack_o: std_logic; signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0); signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0); signal rom_wb_cyc_i: std_logic; signal rom_wb_stb_i: std_logic; signal rom_wb_cti_i: std_logic_vector(2 downto 0); signal dbg_to_zpu: zpu_dbg_in_type; signal dbg_from_zpu: zpu_dbg_out_type; begin core: zpu_core_extreme port map ( wb_clk_i => clk, wb_rst_i => rst, wb_ack_i => wb_ack, wb_dat_i => wb_read, wb_dat_o => wb_write, wb_adr_o => wb_address, wb_cyc_o => wb_cyc, wb_stb_o => wb_stb, wb_we_o => wb_we, wb_inta_i => interrupt, poppc_inst => poppc_inst, break => open, stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr, rom_wb_ack_i => rom_wb_ack_o, rom_wb_dat_i => rom_wb_dat_o, rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0), rom_wb_cyc_o => rom_wb_cyc_i, rom_wb_stb_o => rom_wb_stb_i, rom_wb_cti_o => rom_wb_cti_i, rom_wb_stall_i => '0', dbg_in => dbg_to_zpu, dbg_out => dbg_from_zpu ); stack: zpuino_stack port map ( stack_clk => stack_clk, stack_a_read => stack_a_read, stack_b_read => stack_b_read, stack_a_write => stack_a_write, stack_b_write => stack_b_write, stack_a_writeenable => stack_a_writeenable, stack_b_writeenable => stack_b_writeenable, stack_a_enable => stack_a_enable, stack_b_enable => stack_b_enable, stack_a_addr => stack_a_addr, stack_b_addr => stack_b_addr ); memory: wb_rom_ram port map ( ram_wb_clk_i => clk, ram_wb_rst_i => rst, ram_wb_ack_o => ram_wb_ack_o, ram_wb_dat_i => ram_wb_dat_i, ram_wb_dat_o => ram_wb_dat_o, ram_wb_adr_i => ram_wb_adr_i, ram_wb_cyc_i => ram_wb_cyc_i, ram_wb_stb_i => ram_wb_stb_i, ram_wb_we_i => ram_wb_we_i, rom_wb_clk_i => clk, rom_wb_rst_i => rst, rom_wb_ack_o => rom_wb_ack_o, rom_wb_dat_o => rom_wb_dat_o, rom_wb_adr_i => rom_wb_adr_i, rom_wb_cyc_i => rom_wb_cyc_i, rom_wb_stb_i => rom_wb_stb_i, rom_wb_cti_i => rom_wb_cti_i ); dbg: zpuino_debug_core port map ( clk => clk, rst => rst, dbg_out => dbg_to_zpu, dbg_in => dbg_from_zpu, dbg_reset => dbg_reset, jtag_data_chain_out => jtag_data_chain_out, jtag_ctrl_chain_in => jtag_ctrl_chain_in ); io: zpuino_io port map ( wb_clk_i => clk, wb_rst_i => rst, wb_dat_o => io_read, wb_dat_i => io_write, wb_adr_i => io_address, wb_cyc_i => io_cyc, wb_stb_i => io_stb, wb_ack_o => io_ack, wb_we_i => io_we, wb_inta_o => interrupt, intready => poppc_inst, slot_cyc => slot_cyc, slot_we => slot_we, slot_stb => slot_stb, slot_read => slot_read, slot_write => slot_write, slot_address => slot_address, slot_ack => slot_ack, slot_interrupt=> slot_interrupt ); iomemmux: wbmux2 generic map ( select_line => maxAddrBitIncIO, address_high =>maxAddrBitIncIO, address_low=>0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master m_wb_dat_o => wb_read, m_wb_dat_i => wb_write, m_wb_adr_i => wb_address, m_wb_sel_i => "1111",--wb_sel, m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti, m_wb_we_i => wb_we, m_wb_cyc_i => wb_cyc, m_wb_stb_i => wb_stb, m_wb_ack_o => wb_ack, -- Slave 0 signals s0_wb_dat_i => cpu_ram_wb_dat_o, s0_wb_dat_o => cpu_ram_wb_dat_i, s0_wb_adr_o => cpu_ram_wb_adr_i, s0_wb_sel_o => open, --ram_wb_sel_i, s0_wb_cti_o => open, --ram_wb_cti_i, s0_wb_we_o => cpu_ram_wb_we_i, s0_wb_cyc_o => cpu_ram_wb_cyc_i, s0_wb_stb_o => cpu_ram_wb_stb_i, s0_wb_ack_i => cpu_ram_wb_ack_o, -- Slave 1 signals s1_wb_dat_i => io_read, s1_wb_dat_o => io_write, s1_wb_adr_o => io_address, s1_wb_sel_o => open, s1_wb_cti_o => open, s1_wb_we_o => io_we, s1_wb_cyc_o => io_cyc, s1_wb_stb_o => io_stb, s1_wb_ack_i => io_ack ); memarb: wbarb2_1 generic map ( ADDRESS_HIGH => maxAddrBitIncIO, ADDRESS_LOW => 0 ) port map ( wb_clk_i => clk, wb_rst_i => rst, -- Master 0 signals (CPU) m0_wb_dat_o => cpu_ram_wb_dat_o, m0_wb_dat_i => cpu_ram_wb_dat_i, m0_wb_adr_i => cpu_ram_wb_adr_i, m0_wb_sel_i => (others => '1'), m0_wb_cti_i => CTI_CYCLE_CLASSIC, m0_wb_we_i => cpu_ram_wb_we_i, m0_wb_cyc_i => cpu_ram_wb_cyc_i, m0_wb_stb_i => cpu_ram_wb_stb_i, m0_wb_ack_o => cpu_ram_wb_ack_o, -- Master 1 signals m1_wb_dat_o => m_wb_dat_o, m1_wb_dat_i => m_wb_dat_i, m1_wb_adr_i => m_wb_adr_i, m1_wb_sel_i => (others => '1'), m1_wb_cti_i => CTI_CYCLE_CLASSIC, m1_wb_we_i => m_wb_we_i, m1_wb_cyc_i => m_wb_cyc_i, m1_wb_stb_i => m_wb_stb_i, m1_wb_ack_o => m_wb_ack_o, -- Slave signals s0_wb_dat_i => ram_wb_dat_o, s0_wb_dat_o => ram_wb_dat_i, s0_wb_adr_o => ram_wb_adr_i, s0_wb_sel_o => open, s0_wb_cti_o => open, s0_wb_we_o => ram_wb_we_i, s0_wb_cyc_o => ram_wb_cyc_i, s0_wb_stb_o => ram_wb_stb_i, s0_wb_ack_i => ram_wb_ack_o ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/Wishbone_Empty_Slot.vhd

13

3505

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpuino_config.all; use board.zpupkg.all; use board.zpuinopkg.all; library zpuino; use zpuino.papilio_pkg.all; -- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array. -- This is a little cumbersome but is better then dealing with all the signals in the schematic editor. -- This is what the original record base approach looked like: -- -- type wishbone_bus_in_type is record -- wb_clk_i: std_logic; -- Wishbone clock -- wb_rst_i: std_logic; -- Wishbone reset (synchronous) -- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) -- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) -- wb_we_i: std_logic; -- Wishbone write enable signal -- wb_cyc_i: std_logic; -- Wishbone cycle signal -- wb_stb_i: std_logic; -- Wishbone strobe signal -- end record; -- -- type wishbone_bus_out_type is record -- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) -- wb_ack_o: std_logic; -- Wishbone acknowledge out signal -- wb_inta_o: std_logic; -- end record; -- -- Turning them into an array looks like this: -- -- wishbone_in : in std_logic_vector(61 downto 0); -- -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out : out std_logic_vector(33 downto 0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; entity Wishbone_Empty_Slot is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0) ); end entity Wishbone_Empty_Slot; architecture behave of Wishbone_Empty_Slot is -- signal wishbone_in_record : wishbone_bus_in_type; -- signal wishbone_out_record : wishbone_bus_out_type; begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; --Actual code for the module -- wishbone_out_record.wb_ack_o <= wishbone_in_record.wb_cyc_i and wishbone_in_record.wb_stb_i; wishbone_out(1) <= wishbone_in(1) and wishbone_in(0); -- wishbone_out_record.wb_inta_o <= '0'; wishbone_out(0) <= '0'; -- wishbone_out_record.wb_dat_o <= (others => DontCareValue); wishbone_out(33 downto 2) <= (others => DontCareValue); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/Wishbone_Empty_Slot.vhd

13

3505

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpuino_config.all; use board.zpupkg.all; use board.zpuinopkg.all; library zpuino; use zpuino.papilio_pkg.all; -- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array. -- This is a little cumbersome but is better then dealing with all the signals in the schematic editor. -- This is what the original record base approach looked like: -- -- type wishbone_bus_in_type is record -- wb_clk_i: std_logic; -- Wishbone clock -- wb_rst_i: std_logic; -- Wishbone reset (synchronous) -- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) -- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) -- wb_we_i: std_logic; -- Wishbone write enable signal -- wb_cyc_i: std_logic; -- Wishbone cycle signal -- wb_stb_i: std_logic; -- Wishbone strobe signal -- end record; -- -- type wishbone_bus_out_type is record -- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) -- wb_ack_o: std_logic; -- Wishbone acknowledge out signal -- wb_inta_o: std_logic; -- end record; -- -- Turning them into an array looks like this: -- -- wishbone_in : in std_logic_vector(61 downto 0); -- -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out : out std_logic_vector(33 downto 0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; entity Wishbone_Empty_Slot is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0) ); end entity Wishbone_Empty_Slot; architecture behave of Wishbone_Empty_Slot is -- signal wishbone_in_record : wishbone_bus_in_type; -- signal wishbone_out_record : wishbone_bus_out_type; begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; --Actual code for the module -- wishbone_out_record.wb_ack_o <= wishbone_in_record.wb_cyc_i and wishbone_in_record.wb_stb_i; wishbone_out(1) <= wishbone_in(1) and wishbone_in(0); -- wishbone_out_record.wb_inta_o <= '0'; wishbone_out(0) <= '0'; -- wishbone_out_record.wb_dat_o <= (others => DontCareValue); wishbone_out(33 downto 2) <= (others => DontCareValue); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Wishbone_Peripherals/Wishbone_Empty_Slot.vhd

13

3505

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpuino_config.all; use board.zpupkg.all; use board.zpuinopkg.all; library zpuino; use zpuino.papilio_pkg.all; -- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array. -- This is a little cumbersome but is better then dealing with all the signals in the schematic editor. -- This is what the original record base approach looked like: -- -- type wishbone_bus_in_type is record -- wb_clk_i: std_logic; -- Wishbone clock -- wb_rst_i: std_logic; -- Wishbone reset (synchronous) -- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) -- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) -- wb_we_i: std_logic; -- Wishbone write enable signal -- wb_cyc_i: std_logic; -- Wishbone cycle signal -- wb_stb_i: std_logic; -- Wishbone strobe signal -- end record; -- -- type wishbone_bus_out_type is record -- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) -- wb_ack_o: std_logic; -- Wishbone acknowledge out signal -- wb_inta_o: std_logic; -- end record; -- -- Turning them into an array looks like this: -- -- wishbone_in : in std_logic_vector(61 downto 0); -- -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out : out std_logic_vector(33 downto 0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; entity Wishbone_Empty_Slot is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0) ); end entity Wishbone_Empty_Slot; architecture behave of Wishbone_Empty_Slot is -- signal wishbone_in_record : wishbone_bus_in_type; -- signal wishbone_out_record : wishbone_bus_out_type; begin -- Unpack the wishbone array into a record so the modules code is not confusing. -- wishbone_in_record.wb_clk_i <= wishbone_in(61); -- wishbone_in_record.wb_rst_i <= wishbone_in(60); -- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28); -- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3); -- wishbone_in_record.wb_we_i <= wishbone_in(2); -- wishbone_in_record.wb_cyc_i <= wishbone_in(1); -- wishbone_in_record.wb_stb_i <= wishbone_in(0); -- -- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o; -- wishbone_out(1) <= wishbone_out_record.wb_ack_o; -- wishbone_out(0) <= wishbone_out_record.wb_inta_o; --Actual code for the module -- wishbone_out_record.wb_ack_o <= wishbone_in_record.wb_cyc_i and wishbone_in_record.wb_stb_i; wishbone_out(1) <= wishbone_in(1) and wishbone_in(0); -- wishbone_out_record.wb_inta_o <= '0'; wishbone_out(0) <= '0'; -- wishbone_out_record.wb_dat_o <= (others => DontCareValue); wishbone_out(33 downto 2) <= (others => DontCareValue); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_Pro/clkgen.vhd

13

7033

-- -- System Clock generator for ZPUINO (papilio one) -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity clkgen is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout1: out std_logic; clkout2: out std_logic; clk_1Mhz_out: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end entity clkgen; architecture behave of clkgen is signal dcmlocked: std_ulogic; signal dcmlocked_1mhz: std_logic; signal dcmclock: std_ulogic; signal dcmclock_1mhz: std_logic; signal rst1_q: std_logic := '1'; signal rst2_q: std_logic := '1'; signal clkout_i: std_ulogic; signal clkin_i: std_ulogic; signal clkfb: std_ulogic; signal clk0: std_ulogic; signal clk1: std_ulogic; signal clk2: std_ulogic; signal clkin_i_2: std_logic; -- signal clk_div: std_logic; -- signal count: integer; signal clkin_i_1mhz: std_logic; signal clkfb_1mhz: std_logic; signal clk0_1mhz: std_logic; begin clk_osc_32Mhz <= clkin_i; clkout <= clkout_i; rstout <= rst1_q; --process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin) process(dcmlocked, clkout_i, rstin) begin --if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then if dcmlocked='0' or rstin='1' then rst1_q <= '1'; rst2_q <= '1'; else if rising_edge(clkout_i) then rst1_q <= rst2_q; rst2_q <= '0'; end if; end if; end process; -- Clock buffers clkfx_inst: BUFG port map ( I => clk0, O => clkout_i ); clkin_inst: IBUFG port map ( I => clkin, O => clkin_i ); clkfb_inst: BUFG port map ( I=> dcmclock, O=> clkfb ); vgainst: BUFG port map ( I => clkin_i, O => vgaclkout ); clk1_inst: BUFG port map ( I => clk1, O => clkout1 ); clk2_inst: BUFG port map ( I => clk2, O => clkout2 ); pll_base_inst : PLL_ADV generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "SYSTEM_SYNCHRONOUS", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 30, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 10, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 10, CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN1_PERIOD => 31.250, REF_JITTER => 0.010, SIM_DEVICE => "SPARTAN6") port map -- Output clocks (CLKFBOUT => dcmclock, CLKOUT0 => clk0, CLKOUT1 => clk1, CLKOUT2 => clk2, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => dcmlocked, RST => '0', -- Input clock control CLKFBIN => clkfb, CLKIN1 => clkin_i, CLKIN2 => '0', CLKINSEL => '1', DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DWE => '0', REL => '0' ); DCM_inst_1mhz : DCM generic map ( CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked_1mhz, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb_1mhz, -- DCM clock feedback CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); clkfx_inst_1mhz: BUFG port map ( I => dcmclock_1mhz, O => clk_1Mhz_out ); clkin_i_1mhz <= clkout_i; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_Pro/clkgen.vhd

13

7033

-- -- System Clock generator for ZPUINO (papilio one) -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity clkgen is port ( clkin: in std_logic; rstin: in std_logic; clkout: out std_logic; clkout1: out std_logic; clkout2: out std_logic; clk_1Mhz_out: out std_logic; clk_osc_32Mhz: out std_logic; vgaclkout: out std_logic; rstout: out std_logic ); end entity clkgen; architecture behave of clkgen is signal dcmlocked: std_ulogic; signal dcmlocked_1mhz: std_logic; signal dcmclock: std_ulogic; signal dcmclock_1mhz: std_logic; signal rst1_q: std_logic := '1'; signal rst2_q: std_logic := '1'; signal clkout_i: std_ulogic; signal clkin_i: std_ulogic; signal clkfb: std_ulogic; signal clk0: std_ulogic; signal clk1: std_ulogic; signal clk2: std_ulogic; signal clkin_i_2: std_logic; -- signal clk_div: std_logic; -- signal count: integer; signal clkin_i_1mhz: std_logic; signal clkfb_1mhz: std_logic; signal clk0_1mhz: std_logic; begin clk_osc_32Mhz <= clkin_i; clkout <= clkout_i; rstout <= rst1_q; --process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin) process(dcmlocked, clkout_i, rstin) begin --if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then if dcmlocked='0' or rstin='1' then rst1_q <= '1'; rst2_q <= '1'; else if rising_edge(clkout_i) then rst1_q <= rst2_q; rst2_q <= '0'; end if; end if; end process; -- Clock buffers clkfx_inst: BUFG port map ( I => clk0, O => clkout_i ); clkin_inst: IBUFG port map ( I => clkin, O => clkin_i ); clkfb_inst: BUFG port map ( I=> dcmclock, O=> clkfb ); vgainst: BUFG port map ( I => clkin_i, O => vgaclkout ); clk1_inst: BUFG port map ( I => clk1, O => clkout1 ); clk2_inst: BUFG port map ( I => clk2, O => clkout2 ); pll_base_inst : PLL_ADV generic map (BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "SYSTEM_SYNCHRONOUS", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 30, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 10, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 10, CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN1_PERIOD => 31.250, REF_JITTER => 0.010, SIM_DEVICE => "SPARTAN6") port map -- Output clocks (CLKFBOUT => dcmclock, CLKOUT0 => clk0, CLKOUT1 => clk1, CLKOUT2 => clk2, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => dcmlocked, RST => '0', -- Input clock control CLKFBIN => clkfb, CLKIN1 => clkin_i, CLKIN2 => '0', CLKINSEL => '1', DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DWE => '0', REL => '0' ); DCM_inst_1mhz : DCM generic map ( CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32 CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 31.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => dcmlocked_1mhz, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clkfb_1mhz, -- DCM clock feedback CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => '0', -- Dynamic phase adjust clock input PSEN => '0', -- Dynamic phase adjust enable input PSINCDEC => '0', -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); clkfx_inst_1mhz: BUFG port map ( I => dcmclock_1mhz, O => clk_1Mhz_out ); clkin_i_1mhz <= clkout_i; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd

13

4021

-- -- Audio Passthrough -- -- Copyright 2008,2009,2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.2 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- Changelog: -- -- 1.1: First version, adapted from sigma-delta. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpupkg.all; use board.zpu_config.all; use board.zpuinopkg.all; entity AUDIO_zpuino_wb_passthrough is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); -- Connection to GPIO pin raw_out: out std_logic_vector(17 downto 0) ); end entity AUDIO_zpuino_wb_passthrough; architecture behave of AUDIO_zpuino_wb_passthrough is signal dat_q1: unsigned(17 downto 0); signal dat_q2: unsigned(17 downto 0); signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; wb_dat_o <= (others => '0'); wb_inta_o <= '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0)); raw_out(1 downto 0)<=(others => '0'); process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then dat_q1 <= (others =>'0'); dat_q1(15) <= '1'; dat_q2 <= (others =>'0'); dat_q2(15) <= '1'; else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then case wb_adr_i(2) is when '1' => dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0)); dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16)); when others => end case; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd

13

4021

-- -- Audio Passthrough -- -- Copyright 2008,2009,2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.2 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- Changelog: -- -- 1.1: First version, adapted from sigma-delta. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpupkg.all; use board.zpu_config.all; use board.zpuinopkg.all; entity AUDIO_zpuino_wb_passthrough is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0); -- Connection to GPIO pin raw_out: out std_logic_vector(17 downto 0) ); end entity AUDIO_zpuino_wb_passthrough; architecture behave of AUDIO_zpuino_wb_passthrough is signal dat_q1: unsigned(17 downto 0); signal dat_q2: unsigned(17 downto 0); signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; wb_dat_o <= (others => '0'); wb_inta_o <= '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; raw_out(17 downto 2) <= std_logic_vector(dat_q1(15 downto 0)); raw_out(1 downto 0)<=(others => '0'); process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then dat_q1 <= (others =>'0'); dat_q1(15) <= '1'; dat_q2 <= (others =>'0'); dat_q2(15) <= '1'; else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then case wb_adr_i(2) is when '1' => dat_q1(15 downto 0) <= unsigned(wb_dat_i(15 downto 0)); dat_q2(15 downto 0) <= unsigned(wb_dat_i(31 downto 16)); when others => end case; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/zpuino_spi.vhd

13

7384

-- -- SPI interface for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpuino_config.all; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity zpuino_spi is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(wordSize-1 downto 0); wb_dat_i: in std_logic_vector(wordSize-1 downto 0); wb_adr_i: in std_logic_vector(maxIObit downto minIObit); wb_we_i: in std_logic; wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_inta_o:out std_logic; mosi: out std_logic; miso: in std_logic; sck: out std_logic; enabled: out std_logic ); end entity zpuino_spi; architecture behave of zpuino_spi is component spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic ); end component spi; component spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end component spiclkgen; signal spi_read: std_logic_vector(31 downto 0); signal spi_en: std_logic; signal spi_ready: std_logic; signal spi_clk_en: std_logic; signal spi_clkrise: std_logic; signal spi_clkfall: std_logic; signal spi_clk_pres: std_logic_vector(2 downto 0); signal spi_samprise: std_logic; signal spi_enable_q: std_logic; signal spi_txblock_q: std_logic; signal cpol: std_logic; signal miso_i: std_logic; signal spi_transfersize_q: std_logic_vector(1 downto 0); signal trans: std_logic; begin zspi: spi port map ( clk => wb_clk_i, rst => wb_rst_i, din => wb_dat_i, dout => spi_read, en => spi_en, ready => spi_ready, transfersize => spi_transfersize_q, miso => miso_i, mosi => mosi, clk_en => spi_clk_en, clkrise => spi_clkrise, clkfall => spi_clkfall, samprise => spi_samprise ); zspiclk: spiclkgen port map ( clk => wb_clk_i, rst => wb_rst_i, en => spi_clk_en, pres => spi_clk_pres, clkrise => spi_clkrise, clkfall => spi_clkfall, spiclk => sck, cpol => cpol ); -- Simulation only miso_i <= '0' when miso='Z' else miso; -- Direct access (write) to SPI --spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; busygen: if zpuino_spiblocking=true generate process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then wb_ack_o <= '0'; spi_en <= '0'; trans <= '0'; else wb_ack_o <= '0'; spi_en <= '0'; trans <='0'; if trans='0' then if (wb_cyc_i='1' and wb_stb_i='1') then if wb_adr_i(2)='1' then if spi_txblock_q='1' then if spi_ready='1' then if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; wb_ack_o <= '1'; trans <= '1'; end if; else if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; trans <= '1'; wb_ack_o <= '1'; end if; else trans <= '1'; wb_ack_o <= '1'; end if; end if; end if; end if; end if; end process; --busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0'; end generate; nobusygen: if zpuino_spiblocking=false generate --busy <= '0'; spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; end generate; wb_inta_o <= '0'; enabled <= spi_enable_q; -- Prescaler write process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then spi_enable_q<='0'; spi_txblock_q<='1'; --spi_transfersize_q<=(others => '0'); else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then if wb_adr_i(2)='0' then spi_clk_pres <= wb_dat_i(3 downto 1); cpol <= wb_dat_i(4); spi_samprise <= wb_dat_i(5); spi_enable_q <= wb_dat_i(6); spi_txblock_q <= wb_dat_i(7); --spi_transfersize_q <= wb_dat_i(9 downto 8); end if; end if; end if; end if; end process; process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q) begin wb_dat_o <= (others =>Undefined); case wb_adr_i(2) is when '0' => wb_dat_o(0) <= spi_ready; wb_dat_o(3 downto 1) <= spi_clk_pres; wb_dat_o(4) <= cpol; wb_dat_o(5) <= spi_samprise; wb_dat_o(6) <= spi_enable_q; wb_dat_o(7) <= spi_txblock_q; wb_dat_o(9 downto 8) <= spi_transfersize_q; when '1' => wb_dat_o <= spi_read; when others => wb_dat_o <= (others => DontCareValue); end case; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/zpuino_spi.vhd

13

7384

-- -- SPI interface for ZPUINO -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpuino_config.all; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity zpuino_spi is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(wordSize-1 downto 0); wb_dat_i: in std_logic_vector(wordSize-1 downto 0); wb_adr_i: in std_logic_vector(maxIObit downto minIObit); wb_we_i: in std_logic; wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_inta_o:out std_logic; mosi: out std_logic; miso: in std_logic; sck: out std_logic; enabled: out std_logic ); end entity zpuino_spi; architecture behave of zpuino_spi is component spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic ); end component spi; component spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic ); end component spiclkgen; signal spi_read: std_logic_vector(31 downto 0); signal spi_en: std_logic; signal spi_ready: std_logic; signal spi_clk_en: std_logic; signal spi_clkrise: std_logic; signal spi_clkfall: std_logic; signal spi_clk_pres: std_logic_vector(2 downto 0); signal spi_samprise: std_logic; signal spi_enable_q: std_logic; signal spi_txblock_q: std_logic; signal cpol: std_logic; signal miso_i: std_logic; signal spi_transfersize_q: std_logic_vector(1 downto 0); signal trans: std_logic; begin zspi: spi port map ( clk => wb_clk_i, rst => wb_rst_i, din => wb_dat_i, dout => spi_read, en => spi_en, ready => spi_ready, transfersize => spi_transfersize_q, miso => miso_i, mosi => mosi, clk_en => spi_clk_en, clkrise => spi_clkrise, clkfall => spi_clkfall, samprise => spi_samprise ); zspiclk: spiclkgen port map ( clk => wb_clk_i, rst => wb_rst_i, en => spi_clk_en, pres => spi_clk_pres, clkrise => spi_clkrise, clkfall => spi_clkfall, spiclk => sck, cpol => cpol ); -- Simulation only miso_i <= '0' when miso='Z' else miso; -- Direct access (write) to SPI --spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; busygen: if zpuino_spiblocking=true generate process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then wb_ack_o <= '0'; spi_en <= '0'; trans <= '0'; else wb_ack_o <= '0'; spi_en <= '0'; trans <='0'; if trans='0' then if (wb_cyc_i='1' and wb_stb_i='1') then if wb_adr_i(2)='1' then if spi_txblock_q='1' then if spi_ready='1' then if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; wb_ack_o <= '1'; trans <= '1'; end if; else if wb_we_i='1' then spi_en <= '1'; spi_transfersize_q <= wb_adr_i(4 downto 3); end if; trans <= '1'; wb_ack_o <= '1'; end if; else trans <= '1'; wb_ack_o <= '1'; end if; end if; end if; end if; end if; end process; --busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0'; end generate; nobusygen: if zpuino_spiblocking=false generate --busy <= '0'; spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0'; wb_ack_o <= wb_cyc_i and wb_stb_i; end generate; wb_inta_o <= '0'; enabled <= spi_enable_q; -- Prescaler write process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then spi_enable_q<='0'; spi_txblock_q<='1'; --spi_transfersize_q<=(others => '0'); else if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then if wb_adr_i(2)='0' then spi_clk_pres <= wb_dat_i(3 downto 1); cpol <= wb_dat_i(4); spi_samprise <= wb_dat_i(5); spi_enable_q <= wb_dat_i(6); spi_txblock_q <= wb_dat_i(7); --spi_transfersize_q <= wb_dat_i(9 downto 8); end if; end if; end if; end if; end process; process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q) begin wb_dat_o <= (others =>Undefined); case wb_adr_i(2) is when '0' => wb_dat_o(0) <= spi_ready; wb_dat_o(3 downto 1) <= spi_clk_pres; wb_dat_o(4) <= cpol; wb_dat_o(5) <= spi_samprise; wb_dat_o(6) <= spi_enable_q; wb_dat_o(7) <= spi_txblock_q; wb_dat_o(9 downto 8) <= spi_transfersize_q; when '1' => wb_dat_o <= spi_read; when others => wb_dat_o <= (others => DontCareValue); end case; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/sid_6581.vhd

13

16739

------------------------------------------------------------------------------- -- -- SID 6581 -- -- A fully functional SID chip implementation in VHDL -- ------------------------------------------------------------------------------- -- to do: - filter -- - smaller implementation, use multiplexed channels -- -- -- "The Filter was a classic multi-mode (state variable) VCF design. There was -- no way to create a variable transconductance amplifier in our NMOS process, -- so I simply used FETs as voltage-controlled resistors to control the cutoff -- frequency. An 11-bit D/A converter generates the control voltage for the -- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I -- disconnected it!)." -- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each -- bit would turn on one of the weighted resistors and allow a portion of the -- output to feed back to the input. The state-variable design provided -- simultaneous low-pass, band-pass and high-pass outputs. Analog switches -- selected which combination of outputs were sent to the final amplifier (a -- notch filter was created by enabling both the high and low-pass outputs -- simultaneously)." -- "The filter is the worst part of SID because I could not create high-gain -- op-amps in NMOS, which were essential to a resonant filter. In addition, -- the resistance of the FETs varied considerably with processing, so different -- lots of SID chips had different cutoff frequency characteristics. I knew it -- wouldn't work very well, but it was better than nothing and I didn't have -- time to make it better." -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity sid6581 is port ( clk_1MHz : in std_logic; -- main SID clock signal clk32 : in std_logic; -- main clock signal clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results reset : in std_logic; -- high active signal (reset when reset = '1') cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read addr : in std_logic_vector(4 downto 0); -- address lines di : in std_logic_vector(7 downto 0); -- data in (to chip) do : out std_logic_vector(7 downto 0); -- data out (from chip) pot_x : in std_logic; -- paddle input-X pot_y : in std_logic; -- paddle input-Y audio_out : out std_logic; -- this line holds the audio-signal in PWM format audio_data : out std_logic_vector(17 downto 0) ); end sid6581; architecture Behavioral of sid6581 is --Implementation Digital to Analog converter component pwm_sddac is port ( clk_i : in std_logic; -- main clock signal, the higher the better reset : in std_logic; -- reset input active high dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted ); end component; component pwm_sdadc is port ( clk : in std_logic; -- main clock signal (actually the higher the better) reset : in std_logic; -- ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted ADC_in : in std_logic -- "analog" paddle input pin ); end component; -- Implementation of the SID voices (sound channels) component sid_voice is port ( clk_1MHz : in std_logic; -- this line drives the oscilator reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1) Freq_lo : in std_logic_vector(7 downto 0); -- Freq_hi : in std_logic_vector(7 downto 0); -- Pw_lo : in std_logic_vector(7 downto 0); -- Pw_hi : in std_logic_vector(3 downto 0); -- Control : in std_logic_vector(7 downto 0); -- Att_dec : in std_logic_vector(7 downto 0); -- Sus_Rel : in std_logic_vector(7 downto 0); -- PA_MSB_in : in std_logic; -- PA_MSB_out : out std_logic; -- Osc : out std_logic_vector(7 downto 0); -- Env : out std_logic_vector(7 downto 0); -- voice : out std_logic_vector(11 downto 0) -- ); end component; component sid_filters is port ( clk: in std_logic; -- At least 12Mhz rst: in std_logic; -- SID registers. Fc_lo: in std_logic_vector(7 downto 0); Fc_hi: in std_logic_vector(7 downto 0); Res_Filt: in std_logic_vector(7 downto 0); Mode_Vol: in std_logic_vector(7 downto 0); -- Voices - resampled to 13 bit voice1: in signed(12 downto 0); voice2: in signed(12 downto 0); voice3: in signed(12 downto 0); -- input_valid: in std_logic; ext_in: in signed(12 downto 0); sound: out signed(18 downto 0); valid: out std_logic ); end component; ------------------------------------------------------------------------------- --constant <name>: <type> := <value>; -- DC offset required to play samples, this is actually a bug of the real 6581, -- that was converted into an advantage to play samples constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111"; ------------------------------------------------------------------------------- signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0'); signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0'); signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0'); signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0'); signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0'); signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0'); signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0'); signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0'); signal do_buf : std_logic_vector(7 downto 0) := (others => '0'); signal voice_1 : std_logic_vector(11 downto 0) := (others => '0'); signal voice_2 : std_logic_vector(11 downto 0) := (others => '0'); signal voice_3 : std_logic_vector(11 downto 0) := (others => '0'); signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0'); signal voice_volume : std_logic_vector(35 downto 0) := (others => '0'); signal divide_0 : std_logic_vector(31 downto 0) := (others => '0'); signal voice_1_PA_MSB : std_logic := '0'; signal voice_2_PA_MSB : std_logic := '0'; signal voice_3_PA_MSB : std_logic := '0'; ------------------------------------------------------------------------------- begin digital_to_analog: pwm_sddac port map( clk_i => clk_DAC, reset => reset, dac_i => voice_volume(17 downto 8), dac_o => audio_out ); paddle_x: pwm_sdadc port map ( clk => clk_1MHz, reset => reset, ADC_out => Misc_PotX, ADC_in => pot_x ); paddle_y: pwm_sdadc port map ( clk => clk_1MHz, reset => reset, ADC_out => Misc_PotY, ADC_in => pot_y ); sid_voice_1: sid_voice port map( clk_1MHz => clk_1MHz, reset => reset, Freq_lo => Voice_1_Freq_lo, Freq_hi => Voice_1_Freq_hi, Pw_lo => Voice_1_Pw_lo, Pw_hi => Voice_1_Pw_hi, Control => Voice_1_Control, Att_dec => Voice_1_Att_dec, Sus_Rel => Voice_1_Sus_Rel, PA_MSB_in => voice_3_PA_MSB, PA_MSB_out => voice_1_PA_MSB, Osc => Voice_1_Osc, Env => Voice_1_Env, voice => voice_1 ); sid_voice_2: sid_voice port map( clk_1MHz => clk_1MHz, reset => reset, Freq_lo => Voice_2_Freq_lo, Freq_hi => Voice_2_Freq_hi, Pw_lo => Voice_2_Pw_lo, Pw_hi => Voice_2_Pw_hi, Control => Voice_2_Control, Att_dec => Voice_2_Att_dec, Sus_Rel => Voice_2_Sus_Rel, PA_MSB_in => voice_1_PA_MSB, PA_MSB_out => voice_2_PA_MSB, Osc => Voice_2_Osc, Env => Voice_2_Env, voice => voice_2 ); sid_voice_3: sid_voice port map( clk_1MHz => clk_1MHz, reset => reset, Freq_lo => Voice_3_Freq_lo, Freq_hi => Voice_3_Freq_hi, Pw_lo => Voice_3_Pw_lo, Pw_hi => Voice_3_Pw_hi, Control => Voice_3_Control, Att_dec => Voice_3_Att_dec, Sus_Rel => Voice_3_Sus_Rel, PA_MSB_in => voice_2_PA_MSB, PA_MSB_out => voice_3_PA_MSB, Osc => Misc_Osc3_Random, Env => Misc_Env3, voice => voice_3 ); ------------------------------------------------------------------------------------- do <= do_buf; -- SID filters fblk: block signal voice1_signed: signed(12 downto 0); signal voice2_signed: signed(12 downto 0); signal voice3_signed: signed(12 downto 0); constant ext_in_signed: signed(12 downto 0) := to_signed(0,13); signal filtered_audio: signed(18 downto 0); signal tick_q1, tick_q2: std_logic; signal input_valid: std_logic; signal unsigned_audio: std_logic_vector(17 downto 0); signal unsigned_filt: std_logic_vector(18 downto 0); signal ff1: std_logic; begin process (clk_1MHz,reset) begin if reset='1' then ff1<='0'; else if rising_edge(clk_1MHz) then ff1<=not ff1; end if; end if; end process; process(clk32) begin if rising_edge(clk32) then tick_q1 <= ff1; tick_q2 <= tick_q1; end if; end process; input_valid<='1' when tick_q1 /=tick_q2 else '0'; voice1_signed <= signed(voice_1 & "0") - 4096; voice2_signed <= signed(voice_2 & "0") - 4096; voice3_signed <= signed(voice_3 & "0") - 4096; filters: sid_filters port map ( clk => clk32, rst => reset, -- SID registers. Fc_lo => Filter_Fc_lo, Fc_hi => Filter_Fc_hi, Res_Filt => Filter_Res_Filt, Mode_Vol => Filter_Mode_Vol, -- Voices - resampled to 13 bit voice1 => voice1_signed, voice2 => voice2_signed, voice3 => voice3_signed, -- input_valid => input_valid, ext_in => ext_in_signed, sound => filtered_audio, valid => open ); unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000"); unsigned_audio <= unsigned_filt(18 downto 1); audio_data <= unsigned_audio; end block; -- Register decoding register_decoder:process(clk32) begin if rising_edge(clk32) then if (reset = '1') then --------------------------------------- Voice-1 Voice_1_Freq_lo <= (others => '0'); Voice_1_Freq_hi <= (others => '0'); Voice_1_Pw_lo <= (others => '0'); Voice_1_Pw_hi <= (others => '0'); Voice_1_Control <= (others => '0'); Voice_1_Att_dec <= (others => '0'); Voice_1_Sus_Rel <= (others => '0'); --------------------------------------- Voice-2 Voice_2_Freq_lo <= (others => '0'); Voice_2_Freq_hi <= (others => '0'); Voice_2_Pw_lo <= (others => '0'); Voice_2_Pw_hi <= (others => '0'); Voice_2_Control <= (others => '0'); Voice_2_Att_dec <= (others => '0'); Voice_2_Sus_Rel <= (others => '0'); --------------------------------------- Voice-3 Voice_3_Freq_lo <= (others => '0'); Voice_3_Freq_hi <= (others => '0'); Voice_3_Pw_lo <= (others => '0'); Voice_3_Pw_hi <= (others => '0'); Voice_3_Control <= (others => '0'); Voice_3_Att_dec <= (others => '0'); Voice_3_Sus_Rel <= (others => '0'); --------------------------------------- Filter & volume Filter_Fc_lo <= (others => '0'); Filter_Fc_hi <= (others => '0'); Filter_Res_Filt <= (others => '0'); Filter_Mode_Vol <= (others => '0'); else Voice_1_Freq_lo <= Voice_1_Freq_lo; Voice_1_Freq_hi <= Voice_1_Freq_hi; Voice_1_Pw_lo <= Voice_1_Pw_lo; Voice_1_Pw_hi <= Voice_1_Pw_hi; Voice_1_Control <= Voice_1_Control; Voice_1_Att_dec <= Voice_1_Att_dec; Voice_1_Sus_Rel <= Voice_1_Sus_Rel; Voice_2_Freq_lo <= Voice_2_Freq_lo; Voice_2_Freq_hi <= Voice_2_Freq_hi; Voice_2_Pw_lo <= Voice_2_Pw_lo; Voice_2_Pw_hi <= Voice_2_Pw_hi; Voice_2_Control <= Voice_2_Control; Voice_2_Att_dec <= Voice_2_Att_dec; Voice_2_Sus_Rel <= Voice_2_Sus_Rel; Voice_3_Freq_lo <= Voice_3_Freq_lo; Voice_3_Freq_hi <= Voice_3_Freq_hi; Voice_3_Pw_lo <= Voice_3_Pw_lo; Voice_3_Pw_hi <= Voice_3_Pw_hi; Voice_3_Control <= Voice_3_Control; Voice_3_Att_dec <= Voice_3_Att_dec; Voice_3_Sus_Rel <= Voice_3_Sus_Rel; Filter_Fc_lo <= Filter_Fc_lo; Filter_Fc_hi <= Filter_Fc_hi; Filter_Res_Filt <= Filter_Res_Filt; Filter_Mode_Vol <= Filter_Mode_Vol; do_buf <= (others => '0'); if (cs='1') then if (we='1') then -- Write to SID-register ------------------------ case addr is -------------------------------------- Voice-1 when "00000" => Voice_1_Freq_lo <= di; when "00001" => Voice_1_Freq_hi <= di; when "00010" => Voice_1_Pw_lo <= di; when "00011" => Voice_1_Pw_hi <= di(3 downto 0); when "00100" => Voice_1_Control <= di; when "00101" => Voice_1_Att_dec <= di; when "00110" => Voice_1_Sus_Rel <= di; --------------------------------------- Voice-2 when "00111" => Voice_2_Freq_lo <= di; when "01000" => Voice_2_Freq_hi <= di; when "01001" => Voice_2_Pw_lo <= di; when "01010" => Voice_2_Pw_hi <= di(3 downto 0); when "01011" => Voice_2_Control <= di; when "01100" => Voice_2_Att_dec <= di; when "01101" => Voice_2_Sus_Rel <= di; --------------------------------------- Voice-3 when "01110" => Voice_3_Freq_lo <= di; when "01111" => Voice_3_Freq_hi <= di; when "10000" => Voice_3_Pw_lo <= di; when "10001" => Voice_3_Pw_hi <= di(3 downto 0); when "10010" => Voice_3_Control <= di; when "10011" => Voice_3_Att_dec <= di; when "10100" => Voice_3_Sus_Rel <= di; --------------------------------------- Filter & volume when "10101" => Filter_Fc_lo <= di; when "10110" => Filter_Fc_hi <= di; when "10111" => Filter_Res_Filt <= di; when "11000" => Filter_Mode_Vol <= di; -------------------------------------- when others => null; end case; else -- Read from SID-register ------------------------- --case CONV_INTEGER(addr) is case addr is -------------------------------------- Misc when "11001" => do_buf <= Misc_PotX; when "11010" => do_buf <= Misc_PotY; when "11011" => do_buf <= Misc_Osc3_Random; when "11100" => do_buf <= Misc_Env3; -------------------------------------- -- when others => null; when others => do_buf <= (others => '0'); end case; end if; end if; end if; end if; end process; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/wb_bootloader.vhd

14

2328

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library work; use work.zpu_config.all; entity wb_bootloader is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(11 downto 2); wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_stall_o: out std_logic; wb2_dat_o: out std_logic_vector(31 downto 0); wb2_adr_i: in std_logic_vector(11 downto 2); wb2_cyc_i: in std_logic; wb2_stb_i: in std_logic; wb2_ack_o: out std_logic; wb2_stall_o: out std_logic ); end wb_bootloader; architecture behave of wb_bootloader is component bootloader_dp_32 is port ( CLK: in std_logic; WEA: in std_logic; ENA: in std_logic; MASKA: in std_logic_vector(3 downto 0); ADDRA: in std_logic_vector(11 downto 2); DIA: in std_logic_vector(31 downto 0); DOA: out std_logic_vector(31 downto 0); WEB: in std_logic; ENB: in std_logic; ADDRB: in std_logic_vector(11 downto 2); DIB: in std_logic_vector(31 downto 0); MASKB: in std_logic_vector(3 downto 0); DOB: out std_logic_vector(31 downto 0) ); end component bootloader_dp_32; signal ack: std_logic; signal en: std_logic; signal ack2: std_logic; signal en2: std_logic; begin wb_stall_o <= '0'; wb2_stall_o <= '0'; wb_ack_o <= ack; wb2_ack_o <= ack2; en <= wb_cyc_i and wb_stb_i; en2 <= wb2_cyc_i and wb2_stb_i; process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then ack <= '0'; ack2 <= '0'; else ack <= en; ack2 <= en2 and not ack2; end if; end if; end process; rom: bootloader_dp_32 port map ( CLK => wb_clk_i, WEA => '0', ENA => en, MASKA => (others => '1'), ADDRA => wb_adr_i, DIA => (others => DontCareValue), DOA => wb_dat_o, WEB => '0', ENB => en2, ADDRB => wb2_adr_i, DIB => (others => DontCareValue), MASKB => (others => '1'), DOB => wb2_dat_o ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/board_Papilio_Pro/wb_bootloader.vhd

14

2328

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library work; use work.zpu_config.all; entity wb_bootloader is port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; wb_dat_o: out std_logic_vector(31 downto 0); wb_adr_i: in std_logic_vector(11 downto 2); wb_cyc_i: in std_logic; wb_stb_i: in std_logic; wb_ack_o: out std_logic; wb_stall_o: out std_logic; wb2_dat_o: out std_logic_vector(31 downto 0); wb2_adr_i: in std_logic_vector(11 downto 2); wb2_cyc_i: in std_logic; wb2_stb_i: in std_logic; wb2_ack_o: out std_logic; wb2_stall_o: out std_logic ); end wb_bootloader; architecture behave of wb_bootloader is component bootloader_dp_32 is port ( CLK: in std_logic; WEA: in std_logic; ENA: in std_logic; MASKA: in std_logic_vector(3 downto 0); ADDRA: in std_logic_vector(11 downto 2); DIA: in std_logic_vector(31 downto 0); DOA: out std_logic_vector(31 downto 0); WEB: in std_logic; ENB: in std_logic; ADDRB: in std_logic_vector(11 downto 2); DIB: in std_logic_vector(31 downto 0); MASKB: in std_logic_vector(3 downto 0); DOB: out std_logic_vector(31 downto 0) ); end component bootloader_dp_32; signal ack: std_logic; signal en: std_logic; signal ack2: std_logic; signal en2: std_logic; begin wb_stall_o <= '0'; wb2_stall_o <= '0'; wb_ack_o <= ack; wb2_ack_o <= ack2; en <= wb_cyc_i and wb_stb_i; en2 <= wb2_cyc_i and wb2_stb_i; process(wb_clk_i) begin if rising_edge(wb_clk_i) then if wb_rst_i='1' then ack <= '0'; ack2 <= '0'; else ack <= en; ack2 <= en2 and not ack2; end if; end if; end process; rom: bootloader_dp_32 port map ( CLK => wb_clk_i, WEA => '0', ENA => en, MASKA => (others => '1'), ADDRA => wb_adr_i, DIA => (others => DontCareValue), DOA => wb_dat_o, WEB => '0', ENB => en2, ADDRB => wb2_adr_i, DIB => (others => DontCareValue), MASKB => (others => '1'), DOB => wb2_dat_o ); end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/Wing_Analog.vhd

13

1476

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:54:01 11/26/2013 -- Design Name: -- Module Name: Wing_VGA8 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library zpuino; use zpuino.pad.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wing_Analog is port ( miso : out std_logic; mosi : in std_logic; sck : in std_logic; wt_miso: inout std_logic_vector(7 downto 0); wt_mosi: inout std_logic_vector(7 downto 0) ); end Wing_Analog; architecture Behavioral of Wing_Analog is signal T: std_logic; begin T <= '0'; --Outputs wt_miso(0) <= wt_mosi(0); wt_miso(1) <= wt_mosi(1); wt_miso(2) <= wt_mosi(2); wt_miso(3) <= wt_mosi(3); wt_miso(4) <= wt_mosi(4); wt_miso(5) <= sck; wt_miso(6) <= wt_mosi(6); wt_miso(7) <= mosi; --Inputs (be sure to leave the output enabled) miso <= wt_miso(6) when T = '0' else 'Z'; end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/Wing_Audio.vhd

13

1306

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:54:01 11/26/2013 -- Design Name: -- Module Name: Wing_Audio - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wing_Audio is port ( audio_left : in std_logic; audio_right : in std_logic; wt_miso: inout std_logic_vector(7 downto 0); wt_mosi: inout std_logic_vector(7 downto 0) ); end Wing_Audio; architecture Behavioral of Wing_Audio is begin wt_miso(0) <= audio_right; wt_miso(1) <= audio_left; wt_miso(2) <= wt_mosi(2); wt_miso(3) <= wt_mosi(3); wt_miso(4) <= wt_mosi(4); wt_miso(5) <= wt_mosi(5); wt_miso(6) <= wt_mosi(6); wt_miso(7) <= wt_mosi(7); end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/Wing_Audio.vhd

13

1306

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:54:01 11/26/2013 -- Design Name: -- Module Name: Wing_Audio - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wing_Audio is port ( audio_left : in std_logic; audio_right : in std_logic; wt_miso: inout std_logic_vector(7 downto 0); wt_mosi: inout std_logic_vector(7 downto 0) ); end Wing_Audio; architecture Behavioral of Wing_Audio is begin wt_miso(0) <= audio_right; wt_miso(1) <= audio_left; wt_miso(2) <= wt_mosi(2); wt_miso(3) <= wt_mosi(3); wt_miso(4) <= wt_mosi(4); wt_miso(5) <= wt_mosi(5); wt_miso(6) <= wt_mosi(6); wt_miso(7) <= wt_mosi(7); end Behavioral;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/spi.vhd

14

4909

-- -- SPI interface -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic -- Sample on rising edge ); end entity spi; architecture behave of spi is signal read_reg_q: std_logic_vector(31 downto 0); signal write_reg_q: std_logic_vector(31 downto 0); signal ready_q: std_logic; signal count: integer range 0 to 32; --signal count_val_q: integer range 0 to 32; signal sample_event: std_logic; signal do_shift: std_logic; signal ignore_sample_q: std_logic; begin dout <= read_reg_q; process(samprise,clkrise,clkfall) begin sample_event <= '0'; if (clkfall='1' and samprise='0') then sample_event <= '1'; elsif (clkrise='1' and samprise='1') then sample_event <= '1'; end if; end process; process(ready_q, en) begin ready <= ready_q; end process; process(ready_q, clkrise) begin if ready_q='0' and clkrise='1' then do_shift<='1'; else do_shift<='0'; end if; end process; process(clk) begin if rising_edge(clk) then if do_shift='1' then case transfersize is when "00" => MOSI <= write_reg_q(7); -- 8-bit write when "01" => MOSI <= write_reg_q(15); -- 16-bit write when "10" => MOSI <= write_reg_q(23); -- 24-bit write when "11" => MOSI <= write_reg_q(31); -- 32-bit write when others => end case; end if; end if; end process; process(ready_q, clkrise, count) begin if ready_q='1' then clk_en <= '0'; else if count/=0 then clk_en <= '1'; else clk_en <= not clkrise; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then ready_q <= '1'; count <= 0; --count_val_q <= 8; -- Default to 8-bit else if ready_q='1' then if en='1' then write_reg_q <= din(31 downto 0); ignore_sample_q <= samprise; -- Shift the 32-bit register case transfersize is when "00" => count <= 8; when "01" => count <= 16; when "10" => count <= 24; when "11" => count <= 32; when others => end case; ready_q <= '0'; end if; else if count/=0 then if do_shift='1' then count <= count -1; end if; else if clkrise='1' and ready_q='0' then ready_q <= '1'; end if; end if; end if; if ready_q='0' and sample_event='1' then if ignore_sample_q='0' then read_reg_q(31 downto 0) <= read_reg_q(30 downto 0) & MISO; end if; ignore_sample_q<='0'; write_reg_q(31 downto 0) <= write_reg_q(30 downto 0) & '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/Wishbone_Peripherals/spi.vhd

14

4909

-- -- SPI interface -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic -- Sample on rising edge ); end entity spi; architecture behave of spi is signal read_reg_q: std_logic_vector(31 downto 0); signal write_reg_q: std_logic_vector(31 downto 0); signal ready_q: std_logic; signal count: integer range 0 to 32; --signal count_val_q: integer range 0 to 32; signal sample_event: std_logic; signal do_shift: std_logic; signal ignore_sample_q: std_logic; begin dout <= read_reg_q; process(samprise,clkrise,clkfall) begin sample_event <= '0'; if (clkfall='1' and samprise='0') then sample_event <= '1'; elsif (clkrise='1' and samprise='1') then sample_event <= '1'; end if; end process; process(ready_q, en) begin ready <= ready_q; end process; process(ready_q, clkrise) begin if ready_q='0' and clkrise='1' then do_shift<='1'; else do_shift<='0'; end if; end process; process(clk) begin if rising_edge(clk) then if do_shift='1' then case transfersize is when "00" => MOSI <= write_reg_q(7); -- 8-bit write when "01" => MOSI <= write_reg_q(15); -- 16-bit write when "10" => MOSI <= write_reg_q(23); -- 24-bit write when "11" => MOSI <= write_reg_q(31); -- 32-bit write when others => end case; end if; end if; end process; process(ready_q, clkrise, count) begin if ready_q='1' then clk_en <= '0'; else if count/=0 then clk_en <= '1'; else clk_en <= not clkrise; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then ready_q <= '1'; count <= 0; --count_val_q <= 8; -- Default to 8-bit else if ready_q='1' then if en='1' then write_reg_q <= din(31 downto 0); ignore_sample_q <= samprise; -- Shift the 32-bit register case transfersize is when "00" => count <= 8; when "01" => count <= 16; when "10" => count <= 24; when "11" => count <= 32; when others => end case; ready_q <= '0'; end if; else if count/=0 then if do_shift='1' then count <= count -1; end if; else if clkrise='1' and ready_q='0' then ready_q <= '1'; end if; end if; end if; if ready_q='0' and sample_event='1' then if ignore_sample_q='0' then read_reg_q(31 downto 0) <= read_reg_q(30 downto 0) & MISO; end if; ignore_sample_q<='0'; write_reg_q(31 downto 0) <= write_reg_q(30 downto 0) & '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/Wishbone_Peripherals/spi.vhd

14

4909

-- -- SPI interface -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spi is port ( clk: in std_logic; rst: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_logic_vector(31 downto 0); en: in std_logic; ready: out std_logic; transfersize: in std_logic_vector(1 downto 0); miso: in std_logic; mosi: out std_logic; clk_en: out std_logic; clkrise: in std_logic; clkfall: in std_logic; samprise:in std_logic -- Sample on rising edge ); end entity spi; architecture behave of spi is signal read_reg_q: std_logic_vector(31 downto 0); signal write_reg_q: std_logic_vector(31 downto 0); signal ready_q: std_logic; signal count: integer range 0 to 32; --signal count_val_q: integer range 0 to 32; signal sample_event: std_logic; signal do_shift: std_logic; signal ignore_sample_q: std_logic; begin dout <= read_reg_q; process(samprise,clkrise,clkfall) begin sample_event <= '0'; if (clkfall='1' and samprise='0') then sample_event <= '1'; elsif (clkrise='1' and samprise='1') then sample_event <= '1'; end if; end process; process(ready_q, en) begin ready <= ready_q; end process; process(ready_q, clkrise) begin if ready_q='0' and clkrise='1' then do_shift<='1'; else do_shift<='0'; end if; end process; process(clk) begin if rising_edge(clk) then if do_shift='1' then case transfersize is when "00" => MOSI <= write_reg_q(7); -- 8-bit write when "01" => MOSI <= write_reg_q(15); -- 16-bit write when "10" => MOSI <= write_reg_q(23); -- 24-bit write when "11" => MOSI <= write_reg_q(31); -- 32-bit write when others => end case; end if; end if; end process; process(ready_q, clkrise, count) begin if ready_q='1' then clk_en <= '0'; else if count/=0 then clk_en <= '1'; else clk_en <= not clkrise; end if; end if; end process; process(clk) begin if rising_edge(clk) then if rst='1' then ready_q <= '1'; count <= 0; --count_val_q <= 8; -- Default to 8-bit else if ready_q='1' then if en='1' then write_reg_q <= din(31 downto 0); ignore_sample_q <= samprise; -- Shift the 32-bit register case transfersize is when "00" => count <= 8; when "01" => count <= 16; when "10" => count <= 24; when "11" => count <= 32; when others => end case; ready_q <= '0'; end if; else if count/=0 then if do_shift='1' then count <= count -1; end if; else if clkrise='1' and ready_q='0' then ready_q <= '1'; end if; end if; end if; if ready_q='0' and sample_event='1' then if ignore_sample_q='0' then read_reg_q(31 downto 0) <= read_reg_q(30 downto 0) & MISO; end if; ignore_sample_q<='0'; write_reg_q(31 downto 0) <= write_reg_q(30 downto 0) & '0'; end if; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Wishbone_Peripherals/zpuino_uart_rx.vhd

13

4937

-- -- UART for ZPUINO - Receiver unit -- -- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity zpuino_uart_rx is port ( clk: in std_logic; rst: in std_logic; rx: in std_logic; rxclk: in std_logic; read: in std_logic; data: out std_logic_vector(7 downto 0); data_av: out std_logic ); end entity zpuino_uart_rx; architecture behave of zpuino_uart_rx is component zpuino_uart_mv_filter is generic ( bits: natural; threshold: natural ); port ( clk: in std_logic; rst: in std_logic; sin: in std_logic; sout: out std_logic; clear: in std_logic; enable: in std_logic ); end component zpuino_uart_mv_filter; component uart_brgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; count: in std_logic_vector(15 downto 0); clkout: out std_logic ); end component uart_brgen; signal rxf: std_logic; signal baudtick: std_logic; signal rxd: std_logic_vector(7 downto 0); signal datacount: unsigned(2 downto 0); signal baudreset: std_logic; signal filterreset: std_logic; signal datao: std_logic_vector(7 downto 0); signal dataready: std_logic; signal start: std_logic; signal debug_synctick_q: std_logic; signal debug_baudreset_q: std_logic; -- State type uartrxstate is ( rx_idle, rx_start, rx_data, rx_end ); signal state: uartrxstate; begin data <= datao; data_av <= dataready; rxmvfilter: zpuino_uart_mv_filter generic map ( bits => 4, threshold => 10 ) port map ( clk => clk, rst => rst, sin => rx, sout => rxf, clear => filterreset, enable => rxclk ); filterreset <= baudreset or baudtick; --istart <= start; baudgen: uart_brgen port map ( clk => clk, rst => baudreset, en => rxclk, count => x"000f", clkout => baudtick ); process(clk) begin if rising_edge(clk) then if rst='1' then state <= rx_idle; dataready <= '0'; baudreset <= '0'; start<='0'; else baudreset <= '0'; start<='0'; if read='1' then dataready <= '0'; end if; case state is when rx_idle => if rx='0' then -- Start bit state <= rx_start; baudreset <= '1'; start <='1'; end if; when rx_start => if baudtick='1' then -- Check filtered output. if rxf='0' then datacount <= b"111"; state <= rx_data; -- Valid start bit. else state <= rx_idle; end if; end if; when rx_data => if baudtick='1' then rxd(7) <= rxf; rxd(6 downto 0) <= rxd(7 downto 1); datacount <= datacount - 1; if datacount=0 then state <= rx_end; end if; end if; when rx_end => -- Check for framing errors ? -- Do fast recovery here. if rxf='1' then dataready<='1'; datao <= rxd; state <= rx_idle; end if; if baudtick='1' then -- Framing error. state <= rx_idle; end if; when others => end case; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/zpuino_uart_rx.vhd

13

4937

-- -- UART for ZPUINO - Receiver unit -- -- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library board; use board.zpu_config.all; use board.zpupkg.all; use board.zpuinopkg.all; entity zpuino_uart_rx is port ( clk: in std_logic; rst: in std_logic; rx: in std_logic; rxclk: in std_logic; read: in std_logic; data: out std_logic_vector(7 downto 0); data_av: out std_logic ); end entity zpuino_uart_rx; architecture behave of zpuino_uart_rx is component zpuino_uart_mv_filter is generic ( bits: natural; threshold: natural ); port ( clk: in std_logic; rst: in std_logic; sin: in std_logic; sout: out std_logic; clear: in std_logic; enable: in std_logic ); end component zpuino_uart_mv_filter; component uart_brgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; count: in std_logic_vector(15 downto 0); clkout: out std_logic ); end component uart_brgen; signal rxf: std_logic; signal baudtick: std_logic; signal rxd: std_logic_vector(7 downto 0); signal datacount: unsigned(2 downto 0); signal baudreset: std_logic; signal filterreset: std_logic; signal datao: std_logic_vector(7 downto 0); signal dataready: std_logic; signal start: std_logic; signal debug_synctick_q: std_logic; signal debug_baudreset_q: std_logic; -- State type uartrxstate is ( rx_idle, rx_start, rx_data, rx_end ); signal state: uartrxstate; begin data <= datao; data_av <= dataready; rxmvfilter: zpuino_uart_mv_filter generic map ( bits => 4, threshold => 10 ) port map ( clk => clk, rst => rst, sin => rx, sout => rxf, clear => filterreset, enable => rxclk ); filterreset <= baudreset or baudtick; --istart <= start; baudgen: uart_brgen port map ( clk => clk, rst => baudreset, en => rxclk, count => x"000f", clkout => baudtick ); process(clk) begin if rising_edge(clk) then if rst='1' then state <= rx_idle; dataready <= '0'; baudreset <= '0'; start<='0'; else baudreset <= '0'; start<='0'; if read='1' then dataready <= '0'; end if; case state is when rx_idle => if rx='0' then -- Start bit state <= rx_start; baudreset <= '1'; start <='1'; end if; when rx_start => if baudtick='1' then -- Check filtered output. if rxf='0' then datacount <= b"111"; state <= rx_data; -- Valid start bit. else state <= rx_idle; end if; end if; when rx_data => if baudtick='1' then rxd(7) <= rxf; rxd(6 downto 0) <= rxd(7 downto 1); datacount <= datacount - 1; if datacount=0 then state <= rx_end; end if; end if; when rx_end => -- Check for framing errors ? -- Do fast recovery here. if rxf='1' then dataready<='1'; datao <= rxd; state <= rx_idle; end if; if baudtick='1' then -- Framing error. state <= rx_idle; end if; when others => end case; end if; end if; end process; end behave;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/TEMPLATE_zpuino_wb_Wishbone.vhd

13

4365

---------------------------------------------------------------------------------- -- Company: Gadget Factory -- Engineer: Alvaro Lopes -- -- Create Date: 13:56:50 12/10/2013 -- Design Name: -- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- This is an example template to use for your own Wishbone Peripherals. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- -- This example uses asynchronous outputs. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity TEMPLATE_zpuino_wb_Wishbone is port ( wishbone_in : in std_logic_vector(61 downto 0); wishbone_out : out std_logic_vector(33 downto 0) ); end entity TEMPLATE_zpuino_wb_Wishbone; architecture rtl of TEMPLATE_zpuino_wb_Wishbone is --Define your registers here signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits) signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits) --Wishbone signals - Don't touch. signal wb_clk_i: std_logic; -- Wishbone clock signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) signal wb_we_i: std_logic; -- Wishbone write enable signal signal wb_cyc_i: std_logic; -- Wishbone cycle signal signal wb_stb_i: std_logic; -- Wishbone strobe signal signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal signal wb_inta_o: std_logic; begin -- Unpack the wishbone array into signals so the modules code is not confusing. wb_clk_i <= wishbone_in(61); wb_rst_i <= wishbone_in(60); wb_dat_i <= wishbone_in(59 downto 28); wb_adr_i <= wishbone_in(27 downto 3); wb_we_i <= wishbone_in(2); wb_cyc_i <= wishbone_in(1); wb_stb_i <= wishbone_in(0); wishbone_out(33 downto 2) <= wb_dat_o; wishbone_out(1) <= wb_ack_o; wishbone_out(0) <= wb_inta_o; -- End unpacking Wishbone signals -- Asynchronous acknowledge wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0'; -- Multiplex the data output (asynchronous) process(register0,register1,register2, wb_adr_i) begin -- Multiplex the read depending on the address. Use only the 2 lowest bits of addr case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= register0; -- Output register0 when "01" => wb_dat_o <= register1; -- Output register1 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; end process; process(wb_clk_i) begin if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b register0 <= (others => '0'); register1 <= (others => '0'); register2 <= "10101010"; else -- Not reset -- Check if someone is writing if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then -- Yes, it's a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => register0 <= wb_dat_i; -- Set register0 when "01" => register1 <= wb_dat_i; -- Set register1 when "10" => register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2 when others => null; -- Nothing to do for other addresses end case; end if; end if; end if; end process; end rtl;

mit

chcbaram/FPGA

zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/dualport_ram.vhd

13

5091

-- -- ZPUINO memory -- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com> -- -- Version: 1.0 -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigned.all; library board; use board.zpupkg.all; --library UNISIM; --use UNISIM.VCOMPONENTS.all; entity dualport_ram is generic ( maxbit: integer ); port ( clk: in std_logic; memAWriteEnable: in std_logic; memAWriteMask: in std_logic_vector(3 downto 0); memAAddr: in std_logic_vector(maxbit downto 2); memAWrite: in std_logic_vector(31 downto 0); memARead: out std_logic_vector(31 downto 0); memAEnable: in std_logic; memBWriteEnable: in std_logic; memBWriteMask: in std_logic_vector(3 downto 0); memBAddr: in std_logic_vector(maxbit downto 2); memBWrite: in std_logic_vector(31 downto 0); memBRead: out std_logic_vector(31 downto 0); memBEnable: in std_logic; memErr: out std_logic ); end entity dualport_ram; architecture behave of dualport_ram is component prom_generic_dualport is port (ADDRA: in std_logic_vector(maxbit downto 2); CLK : in std_logic; ENA: in std_logic; MASKA: in std_logic_vector(3 downto 0); WEA: in std_logic; -- to avoid a bug in Xilinx ISE DOA: out STD_LOGIC_VECTOR (31 downto 0); ADDRB: in std_logic_vector(maxbit downto 2); DIA: in STD_LOGIC_VECTOR (31 downto 0); -- to avoid a bug in Xilinx ISE WEB: in std_logic; MASKB: in std_logic_vector(3 downto 0); ENB: in std_logic; DOB: out STD_LOGIC_VECTOR (31 downto 0); DIB: in STD_LOGIC_VECTOR (31 downto 0)); end component; signal memAWriteEnable_i: std_logic; signal memBWriteEnable_i: std_logic; constant nullAddr: std_logic_vector(maxbit downto 12) := (others => '0'); constant protectionEnabled: std_logic := '0'; begin -- Boot loader address: 000XXXXXXXXXX -- Disallow any writes to bootloader protected code (first 4096 bytes, 0x1000 hex (0x000 to 0xFFF) memAWriteEnable_i <= memAWriteEnable when ( memAAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0'; memBWriteEnable_i <= memBWriteEnable when ( memBAddr(maxbit downto 12)/=nullAddr or protectionEnabled='0') else '0'; process(memAWriteEnable,memAAddr(maxbit downto 12),memBWriteEnable,memBAddr(maxbit downto 12)) begin memErr <= '0'; if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then memErr<='1'; end if; if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then memErr<='1'; end if; end process; -- Sanity checks for simulation process(clk) begin if rising_edge(clk) then if memAWriteEnable='1' and memAAddr(maxbit downto 12)="000" and protectionEnabled='1' then report "Write to BOOTLOADER port A not allowed!!! " severity note; end if; end if; end process; -- Sanity checks for simulation process(clk) begin if rising_edge(clk) then if memBWriteEnable='1' and memBAddr(maxbit downto 12)="000" and protectionEnabled='1' then report "Write to BOOTLOADER port B not allowed!!!" severity note; end if; end if; end process; ram: prom_generic_dualport port map ( DOA => memARead, ADDRA => memAAddr, CLK => clk, DIA => memAWrite, ENA => memAEnable, MASKA => "1111", WEA => memAWriteEnable, DOB => memBRead, ADDRB => memBAddr, DIB => memBWrite, MASKB => "1111", ENB => memBEnable, WEB => memBWriteEnable ); end behave;

mit