Update README.md

README.md

@@ -1,3 +1,44 @@
----
-license: bsd-3-clause
----
+---
+library_name: transformers
+datasets:
+- scale-lab/MetRex
+base_model:
+- meta-llama/Meta-Llama-3-8B-Instruct
+---
+
+# Model Details
+
+This model is trained on the [MetRex](https://huggingface.co/datasets/scale-lab/MetRex) dataset for estimating static power metrics for Verilog designs. Finetuned from model: [Meta-Llama-3-8B-Instruct](https://huggingface.co/meta-llama/Meta-Llama-3-8B-Instruct)
+
+
+## Prompt 
+
+Set temperature to 0.4. Use the following prompt template: 
+
+```
+Your task is to estimate delay for RTL designs in Skywater 130nm technology node.user
+
+Estimate area for the given RTL design. Reason about the number and type of gates that would be present after synthesis. 
+ # RTL: 
+ module top_module(
+	input in,
+	output out
+);
+	
+	assign out = ~in;
+	
+endmoduleassistant
+```
+
+# Citation 
+
+```
+@INPROCEEDINGS{abdelatty2025metrex,
+    author={M. {Abdelatty} and J. {Ma} and S. {Reda}},
+     booktitle={2025 30th Asia and South Pacific Design Automation Conference (ASP-DAC)},
+     title={MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs},
+     year={2025},
+     volume={},
+     number={},
+}
+```