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| Ticket Name: TDA2SG: TDA2 LCD2 BT656 signal | |
| Query Text: | |
| Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi Sir : TDA2 output BT.656 signal, when converted to BT.601 signal. Hsync will output all the time. If Vsync is low and Hsync is low, how do I set it? | |
| Responses: | |
| Hi, Do you mean, you dont want hsync to be toggling when vsync is low? If this is the case, you could treat DE signal as inverted hsync. DE will toggle only during active video portion. Regards, Brijesh | |
| Hi Brijesh : The hardware only has Hsync and Vsync and PCLK and ATA [7:0] pins, no DE output. The image had the output I wanted. | |
| Hi Pierre Hsieh, hsync will toggle during vsync, this cannot be changed. In this case, you need to use DE line. Regards, Brijesh | |
| Hi Brijesh : I cannot modify the BT656 configuration of TDA2 to output the desired signal? | |
| Hi Pierre Hsieh, Hsync is supposed to toggle even during vsync inactive period.. This behavior cannot be changed. Regards, Brijesh | |
| Hi Brijesh : BT.656 does not have a DE Line specification. How can I convert to BT.601 with DE Line? | |
| Hi Pierre Hsieh, BT656 does not even output hsync and vsync, so we cannot use hsync/vsync signals for BT656. We have to use discrete sync output mode in order to get sync signals. and when we enable discrete sync signals, we will also get DE signal. Regards, Brijesh | |
| Hi Brijesh : This TDA2 hardware configuration, Display Subsystem DPI2 output BT.656, only output Data and PCLK signal lines. Analyze Bt.656, there will still be H Active in V Blanking. TDA2 can output on BT.656, the V Blanking signal is only H Blanking? | |
| Hi Pierre Hsieh, When you say BT656, it is embedded sync output format, and in this format, DSS does not output sync signals, so there will not be any hsync or vsync signals in bt656 output. So can you check if you are configuring DSS for discrete sync output? Regards, Brijesh | |
| Hi Brijesh : BT.605 does not have Hsync and Vsync, so I converted it to BT601 using FPGA. I used FPGA to convert TDA2 output BT.656 signal into BT.601 signal. I found that VBlanking has a HActive signal for BT.601 signal. | |
| Hi Pierre Hsieh, ok, in this case, you need to change FPGA. FPGA should out hsync correctly. This is not DSS question. Regards, Brijesh | |