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| Ticket Name: RTOS/TDA2HV: How to create a shared region (SR0) in OCMC RAM? | |
| Query Text: | |
| Part Number: TDA2HV Other Parts Discussed in Thread: SYSBIOS Tool/software: TI-RTOS Hello all, I'm working on the TDA2xx VAYU EVM XC5777X CPU board. My interest is in the IPU (M4) and DSP (C66) communication. At this point we are using the shared memory region defined in the external memory, described as in the IPC examples from vision SDK 2.12. In order to make things work we created custom platform file and defined the SR_0 region as: ["SR_0", | |
| { | |
| name: "SR_0", | |
| base: 0x8E000000, | |
| len: 0x1000000, | |
| space: "data", | |
| access: "RW", | |
| } | |
| ], And config file capsule ipc.cfg.xs contain the description of region: /* shared region configuration */ | |
| var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion'); | |
| SharedRegion.translate = false; | |
| /* configure SharedRegion #0 (IPC) */ | |
| var SR0Mem = Program.cpu.memoryMap["SR_0"]; | |
| SharedRegion.setEntryMeta(0, | |
| new SharedRegion.Entry({ | |
| name: "SR_0", | |
| base: SR0Mem.base, | |
| len: SR0Mem.len, | |
| ownerProcId: 0, | |
| isValid: true, | |
| cacheLineSize: 128, | |
| cacheEnable: SR0_cacheEnable | |
| }) | |
| ); The SR_0 is owned by the DSP. Now we want to speed up load and stores to the memory, because it hurts our performance, so the plan is to define smaller shared region but in the OCMC RAM chips 2 and 3, which overall has 2 MiB of space. The first question is it possible? Can we map the SR_0 as one region on both of them like this: ["SR_0", | |
| { | |
| name: "SR_0", | |
| base: 0x40400000, | |
| len: 0x00200000, | |
| space: "code/data", | |
| access: "RWX", | |
| } | |
| ], If yes the next question is how to properly configure the AMMU of the IPU to work like this. Since it support only 2 medium pages entries with 256KiB size and they are occupied to map the OCMC RAM1 chip. And large pages entries support only 32M and 512M sizes. I tried to describe it like this: var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU'); | |
| AMMU.configureAmmu = true; | |
| /*********************** Small Pages *************************/ | |
| /* smallPages[0] & smallPages[1] are auto-programmed by h/w */ | |
| /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures | |
| * only 4K */ | |
| AMMU.smallPages[0].pageEnabled = AMMU.Enable_YES; | |
| AMMU.smallPages[0].logicalAddress = 0x00000000; | |
| AMMU.smallPages[0].translatedAddress = 0x55020000; | |
| AMMU.smallPages[0].translationEnabled = AMMU.Enable_YES; | |
| AMMU.smallPages[0].size = AMMU.Small_16K; | |
| AMMU.smallPages[0].volatileQualifier = AMMU.Volatile_FOLLOW; | |
| AMMU.smallPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; | |
| /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures | |
| * only 4K */ | |
| AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES; | |
| AMMU.smallPages[1].logicalAddress = 0x40000000; | |
| AMMU.smallPages[1].translatedAddress = 0x55080000; | |
| AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES; | |
| AMMU.smallPages[1].size = AMMU.Small_16K; | |
| AMMU.smallPages[1].volatileQualifier = AMMU.Volatile_FOLLOW; | |
| /*********************** Medium Pages *************************/ | |
| /* OCMC space is mapped */ | |
| /* Make it L1 cacheable */ | |
| AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES; | |
| AMMU.mediumPages[0].logicalAddress = 0x00300000; | |
| AMMU.mediumPages[0].translatedAddress = 0x40300000; | |
| AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES; | |
| AMMU.mediumPages[0].size = AMMU.Medium_256K; | |
| AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; | |
| AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; | |
| AMMU.mediumPages[0].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; | |
| AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED; | |
| AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES; | |
| AMMU.mediumPages[1].logicalAddress = 0x00340000; | |
| AMMU.mediumPages[1].translatedAddress = 0x40340000; | |
| AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES; | |
| AMMU.mediumPages[1].size = AMMU.Medium_256K; | |
| AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; | |
| AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; | |
| AMMU.mediumPages[0].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; | |
| AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED; | |
| /*********************** Large Pages *************************/ | |
| /* Code/Data: Large page (32M); cacheable */ | |
| AMMU.largePages[0].pageEnabled = AMMU.Enable_YES; | |
| AMMU.largePages[0].logicalAddress = 0x80000000; | |
| AMMU.largePages[0].translationEnabled = AMMU.Enable_NO; | |
| AMMU.largePages[0].size = AMMU.Large_32M; | |
| AMMU.largePages[0].volatileQualifier = AMMU.Volatile_FOLLOW; | |
| AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; | |
| AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED; | |
| AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; | |
| AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED; | |
| /* map SR_0 ammu (non-cacheable) */ | |
| AMMU.largePages[1].pageEnabled = AMMU.Enable_YES; | |
| AMMU.largePages[1].logicalAddress = 0x40400000; // 0x8E000000; | |
| AMMU.largePages[1].translationEnabled = AMMU.Enable_NO; | |
| AMMU.largePages[1].size = AMMU.Large_32M; | |
| AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; | |
| AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED; | |
| AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; | |
| AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED; But at the BIOS startup i'm getting the following problem: [Cortex_M4_IPU1_C0] ti.sysbios.family.arm.m3.Hwi: line 1105: E_hardFault: FORCED ti.sysbios.family.arm.m3.Hwi: line 1182: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 4ae0c204 Exception occurred in background thread at PC = 0x8005510e. Core 0: Exception occurred in ThreadType_Main. Main name: main(), handle: 0x0. Main stack base: 0x800. Main stack size: 0x2000. R0 = 0x4ae0c204 R8 = 0x00000000 R1 = 0x800b3a84 R9 = 0x00000000 R2 = 0x00000010 R10 = 0x00000000 R3 = 0x000027c4 R11 = 0x00000000 R4 = 0x00000000 R12 = 0x00002764 R5 = 0x00000000 SP(R13) = 0x00002758 R6 = 0x00000000 LR(R14) = 0x80055133 R7 = 0x00002800 PC(R15) = 0x8005510e PSR = 0x01000000 ICSR = 0x00400803 MMFSR = 0x00 BFSR = 0x82 UFSR = 0x0000 HFSR = 0x40000000 DFSR = 0x00000001 MMAR = 0x4ae0c204 BFAR = 0x4ae0c204 AFSR = 0x00000000 Sorry for the long post, but it's a lot of thing to describe. Can someone help us with this issue? Best Regards, Pavlo! | |
| Responses: | |
| Pavlo Can't you use vision SDK itself, it has IPC implemented uisng a small SR0 (only notify used from IPC package for inter processor communication). You can customize the SDK interms of features, number of cores etc. let me know if my understanding is not correct? regards, Shiju | |
| Hello Shiju, I'm not really following which projects or examples you mentioned. Is it \vision_sdk\examples folder? At this point we trying to estimate the performance of the system. So we are transferring the data to M4 via Ethernet and via IPC passing pointers to DSP. After DSP perform all calculations pointer passed to the M4 and transferred via Ethernet back to the host. So as you see the memory speed is the core feature here. Best Regards, Pavlo! | |
| Hi Pavlo VSDK is a complete FW for TDA2xx device. If you build for TDA2xx, then by default it enables all the cores of the SoC, set IPC between all these enabled cores, set cache/MMU configuration, set default memory map etc. This basic fetaures are enabled for all usecases present under \vision_sdk\examples folder FYI, Also, Can you please check the IPC profile numbers listed in VisionSDK_DataSheet.pdf section - Inter processor communication (IPC) latency This might help you to get some ball-park numbers. regards, Shiju | |
| Hi Pavlo, Did you check what's teh instruction at teh PC address 0x8005510e? Also looks like the fault happened while accessing BFAR = 0x4ae0c204. Which is CTRL_WKUP_ID_CODE - register used for detecting SIlicon Rev. Can you check and add following entry to AMMU config? /* map L3/L4 peripherals (mailbox, spinlock) into ammu (non-cacheable) */ var entry = AMMU.largePages[3]; entry.pageEnabled = AMMU.Enable_YES; entry.translationEnabled = AMMU.Enable_YES; entry.logicalAddress = 0x60000000; entry.translatedAddress = 0x40000000; entry.size = AMMU.Large_512M; entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; entry.volatileQualifier = AMMU.Volatile_FOLLOW; entry.executeOnly = AMMU.Enable_NO; entry.readOnly = AMMU.Enable_NO; entry.prefetch = AMMU.Enable_NO; entry.exclusion = AMMU.Enable_YES; entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; entry.L1_posted = AMMU.PostedPolicy_NON_POSTED; entry.L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; Regards, RK | |
| Hi RK, Yes I forget to mention that the silicon Rev. check function is indeed the place where error is generated. According to map file: 8004b900 8004b900 0002456c 0002456c r-x .text.1 .text.1 0 8004b900 0002456c 8004b900 000014e8 ti.nsp.drv.gmacsw.aem4 : mdio.oem4 (.text) 8004cde8 00001250 : cpdma.oem4 (.text) 8004e038 00001122 rtsv7M4_T_le_eabi.lib : _printfi.obj (.text) 8004f15a 00000002 hal_userled_stub.aem4 : llled.oem4 (.text:LED_TOGGLE) 8004f15c 000010d8 ti.nsp.drv.gmacsw.aem4 : ale.oem4 (.text) 80050234 000010a4 ti.nsp.drv.ndk2nsp.aem4 : ndk2nsp.oem4 (.text) 800512d8 00000c68 stk.aem4 : tcpin.oem4 (.text:TcpInput) 80051f40 00000b1c ti.nsp.drv.gmacsw.aem4 : port.oem4 (.text) 80052a5c 00000a50 : cpts.oem4 (.text) 800534ac 000009fc ipc.aem4 : Ipc.obj (.text:ti_sdo_ipc_GateMP_Instance_init__E) 80053ea8 000009a8 ti.nsp.drv.gmacsw.aem4 : gmacsw.oem4 (.text) 80054850 000008b8 stk.aem4 : tcpout.oem4 (.text:TcpOutput) 80055108 000007d8 tda2xx_init.obj (.text) 800558e0 00000700 netHooks.obj (.text) So tda2xx_init.obj contain PlatformGetSiliconRev function. But addition of the large page didn't solve the issue Best Regards, Pavlo! | |
| Hello Shiju, I know what the Vision Frame work is, but at this point we are not using it, And I don't know if we will in the end, my zone of responsibility is DSP. At this stage we need the proof of confidence that DSP will provide enough reasonable calculation speed up. Best Regards, Pavlo! | |