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| Ticket Name: TDA2PXEVM: Received CAN messages swap ID | |
| Query Text: | |
| Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi We are developing a system with TDA2px processor and Vision SDK 3.08. TDA2 IPU1-1 is responsible for receiving CAN messages. We did some changes to CAN driver in system_dcan.c so we can use our custom callback to process received messages: system_dcan.c CanFunc canCall; | |
| static Void System_dcanRxMsgHandler(dcanMsg_t *rxMsg) | |
| { | |
| if (rxMsg->appMsgPrms.dataLength) | |
| { | |
| canCall(rxMsg->msgId,(char*)rxMsg->appMsgPrms.msgData, rxMsg->appMsgPrms.dataLength); | |
| } | |
| } | |
| Void System_dcanStart(CanFunc canf) { | |
| canCall = canf; | |
| System_dcanInit(); | |
| } | |
| /*in configuration .c file we init custom callback*/ | |
| void initFunc() | |
| { | |
| /*DCAN init*/ | |
| System_dcanStart(CanRx); | |
| } | |
| /*Custom Callback*/ | |
| void CanRx(UInt32 id, char* data, int len) | |
| { | |
| Vps_printf("ID: %x; queue get data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", id, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]); | |
| ItelmaQueuePut(ItelmaFromIPU11CanQueue, id, len, (uint8_t*)data); | |
| } | |
| We have two IDs: 0x100 and 0x2B0. There is PCAN-View log: 1 11077.569 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 2 11085.616 DT 0100 Rx 8 00 00 01 00 64 19 00 94 | |
| 3 11085.907 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 4 11101.055 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 5 11116.408 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 6 11116.584 DT 0100 Rx 8 00 00 01 00 64 19 10 59 | |
| 7 11116.868 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 8 11131.655 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 9 11147.012 DT 0100 Rx 8 00 00 01 00 64 19 20 13 | |
| 10 11147.270 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 11 11167.198 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 12 11180.228 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 13 11180.788 DT 0100 Rx 8 00 00 01 00 64 19 30 DE | |
| 14 11181.210 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 15 11195.581 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 16 11210.708 DT 0100 Rx 8 00 00 01 00 64 19 40 87 | |
| 17 11211.076 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 18 11230.641 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 19 11241.861 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 20 11242.003 DT 0100 Rx 8 00 00 01 00 64 19 50 4A | |
| 21 11242.441 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 22 11260.299 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 23 11273.488 DT 0100 Rx 8 00 00 01 00 64 19 60 00 | |
| 24 11274.079 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 25 11287.784 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 26 11305.056 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 27 11305.378 DT 0100 Rx 8 00 00 01 00 64 19 70 CD | |
| 28 11305.605 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 29 11324.968 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 30 11335.206 DT 0100 Rx 8 00 00 01 00 64 19 80 B2 | |
| 31 11335.634 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 32 11354.655 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 33 11366.163 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 34 11366.581 DT 0100 Rx 8 00 00 01 00 64 19 90 7F | |
| 35 11366.883 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 36 11382.777 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 37 11397.995 DT 0100 Rx 8 00 00 01 00 64 19 A0 35 | |
| 38 11398.384 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 39 11417.270 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 40 11429.151 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 41 11429.432 DT 0100 Rx 8 00 00 01 00 64 19 B0 F8 | |
| 42 11430.122 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 43 11446.630 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 44 11460.726 DT 0100 Rx 8 00 00 01 00 64 19 C0 A1 | |
| 45 11461.244 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 46 11475.266 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 47 11493.272 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 48 11493.777 DT 0100 Rx 8 00 00 01 00 64 19 D0 6C | |
| 49 11494.024 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 50 11514.524 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 51 11522.679 DT 0100 Rx 8 00 00 01 00 64 19 E0 26 | |
| 52 11522.931 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 53 11542.478 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 54 11553.818 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 55 11554.417 DT 0100 Rx 8 00 00 01 00 64 19 F0 EB | |
| 56 11554.697 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 57 11569.055 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 58 11586.375 DT 0100 Rx 8 00 00 01 00 64 19 00 94 | |
| 59 11586.561 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 60 11600.179 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 61 11617.278 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 62 11617.490 DT 0100 Rx 8 00 00 01 00 64 19 10 59 | |
| 63 11617.698 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 64 11633.420 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 65 11648.123 DT 0100 Rx 8 00 00 01 00 64 19 20 13 | |
| 66 11648.471 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 67 11663.786 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 68 11680.024 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 69 11680.339 DT 0100 Rx 8 00 00 01 00 64 19 30 DE | |
| 70 11680.798 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 71 11701.572 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 72 11710.960 DT 0100 Rx 8 00 00 01 00 64 19 40 87 | |
| 73 11711.329 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 74 11730.904 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 75 11742.882 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 76 11743.295 DT 0100 Rx 8 00 00 01 00 64 19 50 4A | |
| 77 11743.631 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 78 11756.324 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 79 11774.863 DT 0100 Rx 8 00 00 01 00 64 19 60 00 | |
| 80 11775.243 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 81 11794.523 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 82 11803.564 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 83 11804.128 DT 0100 Rx 8 00 00 01 00 64 19 70 CD | |
| 84 11804.491 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 85 11821.204 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 86 11838.586 DT 0100 Rx 8 00 00 01 00 64 19 80 B2 | |
| 87 11838.723 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 88 11852.189 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 89 11866.303 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 90 11866.544 DT 0100 Rx 8 00 00 01 00 64 19 90 7F | |
| 91 11866.826 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 92 11882.040 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 93 11898.120 DT 0100 Rx 8 00 00 01 00 64 19 A0 35 | |
| 94 11898.665 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 95 11912.991 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 96 11930.639 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 97 11930.845 DT 0100 Rx 8 00 00 01 00 64 19 B0 F8 | |
| 98 11931.174 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 99 11944.452 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 100 11962.281 DT 0100 Rx 8 00 00 01 00 64 19 C0 A1 | |
| 101 11962.797 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 102 11976.370 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 103 11991.554 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 104 11992.053 DT 0100 Rx 8 00 00 01 00 64 19 D0 6C | |
| 105 11992.378 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 106 12007.342 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 107 12026.202 DT 0100 Rx 8 00 00 01 00 64 19 E0 26 | |
| 108 12026.499 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 109 12038.768 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 110 12054.335 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 111 12054.605 DT 0100 Rx 8 00 00 01 00 64 19 F0 EB | |
| 112 12054.823 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 113 12073.876 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 114 12086.863 DT 0100 Rx 8 00 00 01 00 64 19 00 94 | |
| 115 12087.302 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 116 12101.409 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 117 12115.641 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 118 12116.064 DT 0100 Rx 8 00 00 01 00 64 19 10 59 | |
| 119 12116.357 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 120 12132.017 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 121 12150.550 DT 0100 Rx 8 00 00 01 00 64 19 20 13 | |
| 122 12150.853 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 123 12167.877 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 124 12178.429 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 125 12178.881 DT 0100 Rx 8 00 00 01 00 64 19 30 DE | |
| 126 12179.411 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 127 12194.654 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 128 12211.630 DT 0100 Rx 8 00 00 01 00 64 19 40 87 | |
| 129 12212.011 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 130 12225.429 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 131 12240.311 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 132 12241.571 DT 0100 Rx 8 00 00 01 00 64 19 50 4A | |
| 133 12241.745 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 134 12257.517 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 135 12273.486 DT 0100 Rx 8 00 00 01 00 64 19 60 00 | |
| 136 12273.921 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 137 12288.339 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 138 12303.300 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 139 12303.614 DT 0100 Rx 8 00 00 01 00 64 19 70 CD | |
| 140 12303.844 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 141 12319.030 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 142 12338.002 DT 0100 Rx 8 00 00 01 00 64 19 80 B2 | |
| 143 12338.338 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 144 12354.495 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 145 12366.287 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 146 12366.585 DT 0100 Rx 8 00 00 01 00 64 19 90 7F | |
| 147 12366.893 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 148 12381.836 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 149 12399.902 DT 0100 Rx 8 00 00 01 00 64 19 A0 35 | |
| 150 12400.206 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 151 12412.740 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 152 12431.749 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 153 12432.519 DT 0100 Rx 8 00 00 01 00 64 19 B0 F8 | |
| 154 12433.141 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 155 12446.026 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 156 12460.990 DT 0100 Rx 8 00 00 01 00 64 19 C0 A1 | |
| 157 12461.248 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 158 12481.603 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 159 12492.686 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 160 12492.929 DT 0100 Rx 8 00 00 01 00 64 19 D0 6C | |
| 161 12493.112 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 162 12506.302 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 163 12527.253 DT 0100 Rx 8 00 00 01 00 64 19 E0 26 | |
| 164 12527.752 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 165 12537.499 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 166 12554.602 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 167 12554.937 DT 0100 Rx 8 00 00 01 00 64 19 F0 EB | |
| 168 12555.367 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 169 12574.157 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 170 12585.609 DT 0100 Rx 8 00 00 01 00 64 19 00 94 | |
| 171 12585.830 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 172 12602.067 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 173 12617.224 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 174 12617.616 DT 0100 Rx 8 00 00 01 00 64 19 10 59 | |
| 175 12617.900 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 176 12633.555 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 177 12647.723 DT 0100 Rx 8 00 00 01 00 64 19 20 13 | |
| 178 12648.124 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 179 12667.754 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 180 12680.113 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 181 12680.421 DT 0100 Rx 8 00 00 01 00 64 19 30 DE | |
| 182 12680.615 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 183 12695.412 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 184 12710.744 DT 0100 Rx 8 00 00 01 00 64 19 40 87 | |
| 185 12711.297 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 186 12728.218 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 187 12741.604 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 188 12742.147 DT 0100 Rx 8 00 00 01 00 64 19 50 4A | |
| 189 12742.542 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 190 12763.008 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 191 12773.222 DT 0100 Rx 8 00 00 01 00 64 19 60 00 | |
| 192 12773.554 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 193 12788.808 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 194 12805.557 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 195 12805.678 DT 0100 Rx 8 00 00 01 00 64 19 70 CD | |
| 196 12805.730 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 197 12820.773 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 198 12835.421 DT 0100 Rx 8 00 00 01 00 64 19 80 B2 | |
| 199 12835.711 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 200 12854.184 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 201 12869.254 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 202 12869.908 DT 0100 Rx 8 00 00 01 00 64 19 90 7F | |
| 203 12870.362 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 204 12882.630 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 205 12900.957 DT 0100 Rx 8 00 00 01 00 64 19 A0 35 | |
| 206 12901.294 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 207 12915.359 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 208 12928.689 DT 0362 Rx 8 00 00 01 00 00 00 01 00 | |
| 209 12928.923 DT 0100 Rx 8 00 00 01 00 64 19 B0 F8 | |
| 210 12929.124 DT 02B0 Rx 5 10 0E 00 03 00 | |
| 211 12949.308 DT 02B0 Rx 5 10 0E 00 03 00 And there is Vps_printf() output from Putty log: [IPU1-1] 171.234063 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.248032 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.262642 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x10 0xe2 | |
| [IPU1-1] 171.262947 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.299884 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x20 0xa8 | |
| [IPU1-1] 171.311809 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.326633 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x30 0x65 | |
| [IPU1-1] 171.326938 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.341243 s: ID: 100; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.355761 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x40 0x3c | |
| [IPU1-1] 171.356432 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.373970 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.390105 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x50 0xf1 | |
| [IPU1-1] 171.407857 s: ID: 100; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.420179 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x60 0xbb | |
| [IPU1-1] 171.420667 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.435124 s: ID: 2b0; queue get data: 0x10 0xe 0x0 0x3 0x0 0x0 0x0 0x0 | |
| [IPU1-1] 171.450283 s: ID: 100; queue get data: 0x0 0x0 0x1 0x0 0x14 0x82 0x70 0x76 These are some most significant parts of the logs. I will add entire files. As you can see in Putty log, some of the messages got corrupted. In PCAN we have ID 0x02B0 with data 0x10 0x0E 0x00 0x03 0x00 and ID 0x0100 with data 0x00 0x00 0x01 0x00 0x64 0x19 0x60 0x0, but in the CanRx callback either message IDs or message data swap, and sometimes we have ID 0x0100 with data 0x10 0x0E 0x00 0x03 0x00. This only happens when messages rate is very hight. I belive data get corrupted somewhere in CAN driver before CanRx callback. What can be the possible reason for such behavior? Maybe you can explain me where is the entry point for CAN messages. Best regards, D.K. Tovmachenko. TDA_callback_log.log PCANView_log.txt | |
| Responses: | |
| Hello? Any suggestions? Maybe something is unclear for you in my question? Regards, D.K. Tovmachenko | |
| Can you check read error status by calling DCANGetErrStatus() after you receive the message? You may also check the message after DCANGetData() in RX ISR, Utils_dcanRxIsrCb(), to see if you are getting the correct message. If the data is correct in ISR, the issue might be the queue handling part. | |
| Hello, Stanley. Actually, now I'm facing one more issue along with ID swap, but I believe this issue and issue described above have same roots. There are 3 CAN ID I'm receiving. These messages have different rate from 10 to 60 msc. After a certain time one of ID messages stops to come to my callback.What did I figured out: There is Utils_dcanRxTsk task, and it is blocked until we receive message, process it in ISR and post appropriate event. When I face that issue, Event_pend in Utils_dcanRxTsk never pends on appropriate message. So problem is that in ISR programm do not post that event, it seems Event_post in ISR doest even calls. Right now I dont have an opportunity to debug it using JTAG, so I'm trying to debug by DCANGetErrStatus() as you adviced me. I have a question: if DCANGetErrStatus() returns 0x10, does it means that ISR processed CAN message, or it just means that DCAN got that message ? Because after I send message to CAN DCANGetErrStatus() return 0x10, but Event_post doesnt call. Also there is UTILS_assert macro, but if I call UTILS_assert(FALSE) there is no any printfs in UART, does it even work? I'm trying to use it for debugging. static void Utils_dcanRxIsrCb(dcanRxMsgObj_t *dcanRxMsgObj, UInt32 mbxId, UInt32 rxMbxIndex) { dcanMsg_t *rxMsg = NULL; struct dcanQueMsgs_s * queMsg = NULL; Int32 retVal; /* Get free can rx msg */ Utils_dcanQueGet(&dcanRxMsgObj->freeQ.handle, &queMsg, &rxMsg, DCAN_MSG_STATE_IN_FREEQ, DCAN_MSG_STATE_ISR); Utils_dcanResetRxMsg(rxMsg); /* Wait for interface to become free */ Utils_dcanWaitForIfReg(UTILS_DCAN_INST, UTILS_DCAN_RX_IF_REG); /* Get data from CAN mailbox */ retVal = DCANGetData(UTILS_DCAN_INST, mbxId, UTILS_DCAN_RX_IF_REG, &rxMsg->appMsgPrms, 0); UTILS_assert(FALSE); // no assert in UART UTILS_assert(((DCANGetErrStatus(UTILS_DCAN_INST) != 0x10) || (DCANGetErrStatus(UTILS_DCAN_INST) != 0x7))); // check for DCAN err status UTILS_assert(retVal == 0); Utils_dcanConfigRxMsgObj(mbxId); /* Copy CAN RX msg to free msg */ rxMsg->msgId = Utils_dcanMapMailboxId2MsgId(mbxId); UTILS_assert(rxMbxIndex < UTILS_ARRAYSIZE(dcanRxMsgObj->rxMsgQ)); /* Put received msg into CAN RX mailbox specific queue */ Utils_dcanQuePut(&dcanRxMsgObj->rxMsgQ[rxMbxIndex].handle, queMsg, DCAN_MSG_STATE_IN_RX_QUE); UTILS_assert(rxMbxIndex < UTILS_ARRAYSIZE(dcanRxMbxId)); Event_post(dcanRxMsgObj->dcanRxEvent, (0x1U << rxMbxIndex)); // doesnt post apropriate event after a certain time } Please make it clear for me. Regards, D.K. Tovmachenko. | |
| Hi, Stanley. I have an additional question. Is there any safe way to restart DCAN during runtime? I'm trying just reinit it: void resetCAN(void) { Utils_dcanDeInit(); Utils_dcanInit(&dcanConfig); } but it doesnt work. Regards, D.K. Tovmachenko. | |
| Hi Stanley. I figured out how to fix UTILS_assert(), but questions about DCANGetErrStatus() function and proper way to reset CAN still exist. Regards, D.K. Tovmachenko. | |
| DCANGetErrStatus() returning 0x10 means the message is received successfully. Regarding restarting CAN driver, we have not tested that. What error did you get from calling your resetCAN()? | |
| Hi Tovmachenko, If I understood your setup correctly, you setup looks like follow: You have TDA2Px DCAN connected to PCAN and PCAN is sending data to DCAN. Issue 1: When you increase a message rate beyond some limit, you see some corruption happening and this is not just random corruption, you see IDs/payload swapped. You don't see any corruption within payload. Correct? Issue 2: Sometimes you also receive a message with third ID, and this happens only for some time. Right? Can you please confirm above points? Thanks & Regards, Vivek Dhande. Texas Instruments (India) Pvt Ltd | |
| Hello, Stanley. After calling resetCAN() CAN stops to respond at all. I didnt really tested it yet, but I think entire DCAN get corrupted. About DCANGetErrStatus(), message is received successfully means that it have been sucsessfully written to some memory register, or does it mean that it have been written to some register and get processed by ISR? Regards, D. Tovmachenko. | |
| Hi Vivek. 1. Yes, but we also have TDA3 and TDA2EVM with the same problem. 2.I have 3 IDs messages which continiously coming from CAN bus to TDA, at any message rate at some moment one or two IDs stops to come, and sometimes these ID data swap, or maybe ID swap between two tipes of messages. Message rate only affects time till problem happens, more hight message frame is, more fast problem will happen. I just fugured out,when IDs stops to come, there is no Utils_dcanRxIsrCb() calling, means ISR stops to execute when messages whith these IDs come. Let me make it clear, I took vsdk308\vision_sdk\apps\src\rtos\modules\dcan\ system_dcan.c and utils_dcan.c example from Vision SDK and modified these files to make TDA receive and send several CAN ID messages. Did you tested your can driver for receiveng several IDs, because there is only one ID to rx and one ID to tx in this example. Also I checked error statuses after CAN IDs stops to come, and DCANGetParityErrStatus() returns 0x13. I count messages with these IDs in ISR like this: static void Utils_dcanRxIsrCb(dcanRxMsgObj_t *dcanRxMsgObj, UInt32 mbxId, UInt32 rxMbxIndex) { dcanMsg_t *rxMsg = NULL; struct dcanQueMsgs_s * queMsg = NULL; Int32 retVal; /* Get free can rx msg */ Utils_dcanQueGet(&dcanRxMsgObj->freeQ.handle, &queMsg, &rxMsg, DCAN_MSG_STATE_IN_FREEQ, DCAN_MSG_STATE_ISR); Utils_dcanResetRxMsg(rxMsg); /*Increment IDs counter*/ if ((rxMsg->appMsgPrms.rxMsgIdentifier) == 1st ID) { speed_id++; } else if ((rxMsg->appMsgPrms.rxMsgIdentifier) == 2nd ID) { angle_id++; } else if ((rxMsg->appMsgPrms.rxMsgIdentifier) == 3rd ID) { corner_id++; } /* Wait for interface to become free */ Utils_dcanWaitForIfReg(UTILS_DCAN_INST, UTILS_DCAN_RX_IF_REG); /* Get data from CAN mailbox */ retVal = DCANGetData(UTILS_DCAN_INST, mbxId, UTILS_DCAN_RX_IF_REG, &rxMsg->appMsgPrms, 0); UTILS_assert(retVal == 0); Utils_dcanConfigRxMsgObj(mbxId); /* Copy CAN RX msg to free msg */ rxMsg->msgId = Utils_dcanMapMailboxId2MsgId(mbxId); UTILS_assert(rxMbxIndex < UTILS_ARRAYSIZE(dcanRxMsgObj->rxMsgQ)); /* Put received msg into CAN RX mailbox specific queue */ Utils_dcanQuePut(&dcanRxMsgObj->rxMsgQ[rxMbxIndex].handle, queMsg, DCAN_MSG_STATE_IN_RX_QUE); UTILS_assert(rxMbxIndex < UTILS_ARRAYSIZE(dcanRxMbxId)); Event_post(dcanRxMsgObj->dcanRxEvent, (0x1U << rxMbxIndex)); } And then I print these counters in separate task. At some moment despite these messages still in CAN bus, these counters stop to increment, means Utils_dcanRxIsrCb() doesnt execute. Regards, D. Tovmachenko | |
| Hello I have some progress in resolving this issue. I created a crutch, a task which continuously checking DCAN queue for stucked messages. This crutch resolved "certain ID messages stops to come" problem, but this is still a crutch. Here is my crutch code: void CrutchTsk(UArg arg0, UArg arg1) { dcanMsg_t* rxMsg = NULL; struct dcanQueMsgs_s* queMsg = NULL; Int32 retVal; int i = 0; dcanRxMsgObj_t* processObj = dcanIsrContext.rxMsgObj; while (1) { for (i = 1stIDindex; i < 3rdIDindex; ++i) { /*This is the place where I get message from DCAN*/ Utils_dcanQueGet(&processObj->freeQ.handle, &queMsg, &rxMsg, DCAN_MSG_STATE_IN_FREEQ, DCAN_MSG_STATE_ISR); Utils_dcanResetRxMsg(rxMsg); /*Then I check message from queue*/ if ((rxMsg->appMsgPrms.rxMsgIdentifier == ID1) || (rxMsg->appMsgPrms.rxMsgIdentifier == ID2) || (rxMsg->appMsgPrms.rxMsgIdentifier == ID3)) { /*If message is valid, I process it and post appropriate event*/ Utils_dcanWaitForIfReg(UTILS_DCAN_INST, UTILS_DCAN_RX_IF_REG); retVal = DCANGetData(UTILS_DCAN_INST, dcanRxMbxId[i], UTILS_DCAN_RX_IF_REG, &rxMsg->appMsgPrms, 0); Utils_dcanConfigRxMsgObj(dcanRxMbxId[i]); rxMsg->msgId = Utils_dcanMapMailboxId2MsgId(dcanRxMbxId[i]); Utils_dcanQuePut(&processObj->rxMsgQ[i].handle, queMsg, DCAN_MSG_STATE_IN_RX_QUE); Event_post(processObj->dcanRxEvent, (0x1U << i)); // post appropriate event } } BspOsal_sleep(SLEEP_VAL); } } The thing is, if after certain ID get blocked I manually check DCAN queue for messages with that ID , this manual check unblocks messages with that ID, and they start to come again(till they get blocked again). So I created the task which do it continuously. But this is not how DCAN is suppose to work. I also checked DCAN_INTPND12 DCAN1 register, there is no interrupt pending, value is always 0. DCAN_CTL register and DCAN_INT register are also OK (i.e. 0). PCAN-View doesnt register any bus-off condition (means TDA get these messages), so the problem is that in DCAN messages queue messages somehow get stuck. Is there any way to deal with it? Regards. D.K. Tovmachenko | |
| Hi Eventually we maybe found a way to resolve this issue. Now all CAN messages comes without blocking, and all data is valid, ID don't swap anymore. Apparently, if several CAN messages with different IDs comes with hight frame rate, some registers don't clean in time (or maybe messageboxes), so ISR doesnt execute when next message with this ID comes again. So we desided to check all messageboxes for messages in ISR, regardless of the received message, and if there is a message in messagebox, search appropriate for this ID mailbox and post event with this mailbox index. That way all works great: /*utils_dcan.c*/ /*Function for searching received ID in mailboxes and if found return index of appropriate mailbox*/ static Int32 Utils_dcanMapMsgId2MailboxIdx(UInt32 msgId) { Int i, j; for (i = 0; i < UTILS_ARRAYSIZE(dcanMbx2MsgIdMap); ++i) { if (dcanMbx2MsgIdMap[i].msgId == msgId) { for (j = 0; j < UTILS_ARRAYSIZE(dcanRxMbxId); ++j) { if (dcanRxMbxId[j] == dcanMbx2MsgIdMap[i].mbxId) { return j; } } break; } } return -1; } /*ISR*/ static void Utils_dcanRxIsrCb(dcanRxMsgObj_t *dcanRxMsgObj, UInt32 mbxId, UInt32 rxMbxIndex) { int i, retVal, rxId; dcanMsg_t* rxMsg; struct dcanQueMsgs_s* queMsg; /*dcanRxMbxId is n size array which contains mailboxes IDs, previously mapped with messages IDs*/ for (i = 0; i < UTILS_ARRAYSIZE(dcanRxMbxId); ++i) { /*Check messagebox for messages*/ if (DCANHasRxMsgArrived(UTILS_DCAN_INST, dcanRxMbxId[i])) { Utils_dcanQueGet(&dcanRxMsgObj->freeQ.handle, &queMsg, &rxMsg, DCAN_MSG_STATE_IN_FREEQ, DCAN_MSG_STATE_ISR); Utils_dcanResetRxMsg(rxMsg); Utils_dcanWaitForIfReg(UTILS_DCAN_INST, UTILS_DCAN_RX_IF_REG); retVal = DCANGetData(UTILS_DCAN_INST, dcanRxMbxId[i], UTILS_DCAN_RX_IF_REG, &rxMsg->appMsgPrms, 0); if (retVal == STW_SOK) { /*Check is CAN waiting for standart or extended messages*/ if (rxMsg->appMsgPrms.rxIdType) { rxMsg->msgId = rxMsg->appMsgPrms.rxMsgIdentifier; } else { rxMsg->msgId = (rxMsg->appMsgPrms.rxMsgIdentifier >> DCAN_SHIFT); } Utils_dcanConfigRxMsgObj(dcanRxMbxId[i]); /*Taking mailbox for message ID*/ rxId = Utils_dcanMapMsgId2MailboxIdx(rxMsg->msgId); if (rxId != -1) { Utils_dcanQuePut(&dcanRxMsgObj->rxMsgQ[rxId].handle, queMsg, DCAN_MSG_STATE_IN_RX_QUE); /*Post event appropriate to mailbox ID*/ Event_post(dcanRxMsgObj->dcanRxEvent, (0x1UL << rxId)); } else { /*misra*/ } } else { Utils_dcanConfigRxMsgObj(dcanRxMbxId[i]); Utils_dcanQuePut(&dcanRxMsgObj->freeQ.handle, queMsg, DCAN_MSG_STATE_IN_FREEQ); } } else { /*misra*/ } } } We resolved this issue that way. What do you think about this solution to the problem? Regards, Dmitriy Tovmachenko. | |
| Hi Dmitriy, Thank you for providing the update. Your fix looks good. Regards, Stanley | |