sample_embedding_folder/1038421.txt

Ticket Name: TDA2EVM5777： How to correctly connect SOC and EMMC when resetting TPS659039

Query Text:
Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2E, TDA2 Hello, Question 1: We measured that the SOC PORZ port was continuously pulled down, and the system was not powered on normally. We need TI experts to help analyze the cause of the failure? Figure 2 is a schematic diagram of the hardware schematic design. The RTC_PORZ, RTC_ISO, PORZ of the PMIC and the external reset IC are connected together; the PORZ reset of the PMIC passes through the A device and the RSTOUTn of the PMIC passes through the B device, combined into an AND gate circuit, and the gate output Connect the reset port of EMMC. Question 2: When the connection between PMIC PORZ and A device is disconnected, the system is powered on normally. Figure 1. The yellow line is the waveform we measured at the PORZ reset port of the PMIC, and the pink line is the waveform measured at the reset port of the EMMC. As shown by the pink line, there is a 5ms pull-up level before EMMC reset. We are worried that it will affect the startup of EMMC. Is it necessary to eliminate it through the AND gate? Model of PMIC: TPS659039 SOC model: TDA2E

Responses:
Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The diagram is not correct, as the PMIC does not have PORz, RTC_PORz, RTC_ISO signals. These are signals on the processor, which is NOT identified in the diagram. Also the processor does not have reset out signal, that is on the PMIC. Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, as that could create a loop where stuck in reset. TI's EVM correctly implements this reset structure. The PMIC reset output feeds the reset inputs of the processor. The processor's reset output (nRSTOUT) is sourced into the PMICs nWARMRESET input.

Hi Robert, Robert Eschler said: Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The block diagram is updated as follows，Can you confirm if there is any problem with the design? Robert Eschler said: Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, According to the TPS659039 specification, the NRESWARM port of TPS659039 is connected to the RETOUTn of SOC，RETOUTn is the Warm reset output of SOC

The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? If you compare with TI EVM, the RESET OUT of PMIC is AND-gate with reset supervisor. Why not replicate the EVM logic, as it is tested/validated? Also - BufferA does not serve any purpose, as any time SoC is reset, nRSTOUT is asserted. Only BufferB is required to reset eMMC device.

Robert Eschler said: BufferA does not serve any purpose According to the TDA2 specification, Buffer A is needed. In our block diagram, buffer A and buffer B form an AND gate Robert Eschler said: The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? YES,Update as shown below

Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? PMIC RESET_OUT should connect directly to SoC's reset input(s). It can be AND-gate with supervisor output, but does not need to be routed through supervisor.

Robert Eschler said: Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? Sorry，I don’t understand what you mean. I want to eliminate the waveform measured by the RSTN reset pin of EMMC when it is powered on, as shown in the red box in the figure below： Initially ，we wanted to achieve the reset architecture as shown in the figure below and the red box truth table results, but the current reset architecture design seems to be problematic, the PORZ pin of the SOC has been pulled low, so I want to confirm whether our reset architecture design correct?

Have you tried a configuration like modified image below? I don't think the issue is with the AND-gate on nRSTOUT. Also - from the waveform, it looks like the logic levels are very low and are just now turning on (with power supplies). Once the power levels and input thresholds are met, the logic starts working as expected. Maybe try an pull-down resistor (or similar) to eliminate the early pulse.

If the reset pin of EMMC remains in this state after power-on, will there be any hidden dangers?

The eMMC is getting a valid reset pulse (low then high), and it appears the final high is full scale (1.8V). I don't see any issue with the final reset. I'm still not clear on the smaller pulse, but again - could be from power just reaching valid logic levels.

I checked the relevant design in the DEMO board, the version is： 516582H_VAYU_EVM_13NOV2015_H As shown in the figure, the DEMO board does not use the AND gate mentioned in the manual, but only uses a buffer. I want to confirm whether the design can also meet the requirements of TDA2?

The AND-gate you are referring only affects the eMMC (or other peripherals), and does not affect the TDA2. The PORz circuit for the TDA2 should not include RSTOUTn, as it is reset output of TDA2.