TI_RAG_Demo_L3.1

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arjunanand13 commited on May 28

Commit

c000ca2

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1 Parent(s): e86990a

Update app.py

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app.py CHANGED Viewed

@@ -201,7 +201,7 @@ css_code = """
         """
-EXAMPLES = ["Can the SSC feature be enabled on DPLL_VIDEO1 using the PLL_SSC_CONFIGURATION1[EN_SSC] register to mitigate EMI issues on VOUT1?",
             "I'm using Code Composer Studio 5.4.0.00091 and enabled FPv4SPD16 floating point support for CortexM4 in TDA2. However, after building the project, the .asm file shows --float_support=vfplib instead of FPv4SPD16. Why is this happening?",
             "Master core in TDA2XX is a15 and in TDA3XX it is m4,so we have to shift all modules that are being used by a15 in TDA2XX to m4 in TDA3xx."]

         """
+EXAMPLES = ["whether TI has plan to do ASIL-B qualification of any TDA2/3",
             "I'm using Code Composer Studio 5.4.0.00091 and enabled FPv4SPD16 floating point support for CortexM4 in TDA2. However, after building the project, the .asm file shows --float_support=vfplib instead of FPv4SPD16. Why is this happening?",
             "Master core in TDA2XX is a15 and in TDA3XX it is m4,so we have to shift all modules that are being used by a15 in TDA2XX to m4 in TDA3xx."]