Ticket Name: TDA2SA: [TDA2S] RGMII port no signal output

Query Text:
Part Number: TDA2SA Other Parts Discussed in Thread: TDA2, DP83TC811, DP83TC811SEVM Dear TI, We use DP83TC811 chip on our TDA2 board, and the link is ok, but we can't measure the signal on RGMII port. What is the reason? Could you please help to check? The dts config: In dra7-evm.dts file: &mac { status = "okay"; #dual_emac; ti,no-idle; }; &davinci_mdio{ status = "okay"; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii"; dual_emac_res_vlan = <2>; }; In dra7.dtsi file: mac: ethernet@48484000 { compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; cpts_clock_mult = <0x784CFE14>; cpts_clock_shift = <29>; reg = <0x48484000 0x1000 0x48485200 0x2E00>; #address-cells = <1>; #size-cells = <1>; /* * Do not allow gating of cpsw clock as workaround * for errata i877. Keeping internal clock disabled * causes the device switching characteristics * to degrade over time and eventually fail to meet * the data manual delay time/skew specs. */ ti,no-idle; /* * rx_thresh_pend * rx_pend * tx_pend * misc_pend */ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; ranges; syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@48485000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "davinci_mdio"; bus_freq = <1000000>; reg = <0x48485000 0x100>; }; cpsw_emac0: slave@48480200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; cpsw_emac1: slave@48480300 { mac-address = [ 00 00 00 00 00 00 ]; }; phy_sel: cpsw-phy-sel@4a002554 { compatible = "ti,dra7xx-cpsw-phy-sel"; reg= <0x4a002554 0x4>; reg-names = "gmii-sel"; }; }; After boot, the link status is connected, use ifconfig command, show info as below: eth0 Link encap:Ethernet HWaddr 00:35:FF:4E:D3:CA inet addr:10.0.0.32 Bcast:10.0.0.255 Mask:255.255.255.0 inet6 addr: fe80::235:ffff:fe4e:d3ca/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:57 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:10411 (10.1 KiB) Interrupt:87 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) When we use ping command, the TX bytes and TX packets are increased as normal. But we can't measure any wave from RGMII TXD port. The registers of GMAC part as below: |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x48484000 | 0x0019010F | | 0x48484004 | 0x00000006 | | 0x48484008 | 0x00000000 | | 0x4848400C | 0x00000007 | | 0x48484010 | 0x00000000 | | 0x48484014 | 0x00000000 | | 0x48484018 | 0x00003003 | | 0x4848401C | 0x0000000B | | 0x48484020 | 0x00000020 | | 0x48484024 | 0x00000007 | | 0x48484028 | 0x81008100 | | 0x4848402C | 0x00000000 | | 0x48484030 | 0x000080E1 | | 0x48484034 | 0x00000000 | |----------------------------| |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x48484100 | 0x00000000 | | 0x48484104 | 0x00000000 | | 0x48484108 | 0x00000104 | | 0x4848410C | 0x00000042 | | 0x48484110 | 0x00000000 | | 0x48484114 | 0x00000000 | | 0x48484118 | 0x33221001 | | 0x4848411C | 0x76543210 | | 0x48484120 | 0x00000000 | | 0x48484124 | 0x00000000 | | 0x48484128 | 0x00000000 | | 0x4848412C | 0x00000000 | | 0x48484130 | 0x00000000 | | 0x48484134 | 0x00000000 | | 0x48484138 | 0x00000000 | | 0x4848413C | 0x00000000 | | 0x48484140 | 0x00000000 | | 0x48484144 | 0x00000000 | | 0x48484148 | 0x00000000 | | 0x4848414C | 0x00000000 | | 0x48484150 | 0x00000000 | | 0x48484154 | 0x00000000 | | 0x48484158 | 0x00000000 | | 0x4848415C | 0x00000000 | | 0x48484160 | 0x00000000 | | 0x48484164 | 0x00000000 | | 0x48484168 | 0x00000000 | | 0x4848416C | 0x00000000 | | 0x48484170 | 0x00000000 | | 0x48484174 | 0x00000000 | | 0x48484178 | 0x00000000 | | 0x4848417C | 0x00000000 | | 0x48484180 | 0x00000000 | | 0x48484184 | 0x00000000 | | 0x48484188 | 0x00000000 | | 0x4848418C | 0x00000000 | | 0x48484190 | 0x00000000 | | 0x48484194 | 0x00000000 | | 0x48484198 | 0x00000000 | | 0x4848419C | 0x00000000 | | 0x484841A0 | 0x00000000 | | 0x484841A4 | 0x00000000 | | 0x484841A8 | 0x00000000 | | 0x484841AC | 0x00000000 | | 0x484841B0 | 0x00000000 | | 0x484841B4 | 0x00000000 | | 0x484841B8 | 0x00000000 | | 0x484841BC | 0x00000000 | | 0x484841C0 | 0x00000000 | | 0x484841C4 | 0x00000000 | | 0x484841C8 | 0x00000000 | | 0x484841CC | 0x00000000 | | 0x484841D0 | 0x00000000 | | 0x484841D4 | 0x00000000 | | 0x484841D8 | 0x00000000 | | 0x484841DC | 0x00000000 | | 0x484841E0 | 0x00000000 | | 0x484841E4 | 0x00000000 | | 0x484841E8 | 0x00000000 | | 0x484841EC | 0x00000000 | | 0x484841F0 | 0x00000000 | | 0x484841F4 | 0x00000000 | | 0x484841F8 | 0x00000000 | | 0x484841FC | 0x00000000 | | 0x48484200 | 0x00000000 | | 0x48484204 | 0x00040000 | | 0x48484208 | 0x000000F5 | | 0x4848420C | 0x00000041 | | 0x48484210 | 0x080040C0 | | 0x48484214 | 0x00000000 | | 0x48484218 | 0x33221100 | | 0x4848421C | 0x001E0000 | | 0x48484220 | 0x0000CAD3 | | 0x48484224 | 0x4EFF3500 | | 0x48484228 | 0x00000000 | | 0x4848422C | 0x00000000 | | 0x48484230 | 0x00000000 | | 0x48484234 | 0x00000000 | | 0x48484238 | 0x00000000 | | 0x4848423C | 0x00000000 | | 0x48484240 | 0x00000000 | | 0x48484244 | 0x00000000 | | 0x48484248 | 0x00000000 | | 0x4848424C | 0x00000000 | | 0x48484250 | 0x00000000 | | 0x48484254 | 0x00000000 | | 0x48484258 | 0x00000000 | | 0x4848425C | 0x00000000 | | 0x48484260 | 0x00000000 | | 0x48484264 | 0x00000000 | | 0x48484268 | 0x00000000 | | 0x4848426C | 0x00000000 | | 0x48484270 | 0x00000000 | | 0x48484274 | 0x00000000 | | 0x48484278 | 0x00000000 | | 0x4848427C | 0x00000000 | | 0x48484280 | 0x00000000 | | 0x48484284 | 0x00000000 | | 0x48484288 | 0x00000000 | | 0x4848428C | 0x00000000 | | 0x48484290 | 0x00000000 | | 0x48484294 | 0x00000000 | | 0x48484298 | 0x00000000 | | 0x4848429C | 0x00000000 | | 0x484842A0 | 0x00000000 | | 0x484842A4 | 0x00000000 | | 0x484842A8 | 0x00000000 | | 0x484842AC | 0x00000000 | | 0x484842B0 | 0x00000000 | | 0x484842B4 | 0x00000000 | | 0x484842B8 | 0x00000000 | | 0x484842BC | 0x00000000 | | 0x484842C0 | 0x00000000 | | 0x484842C4 | 0x00000000 | | 0x484842C8 | 0x00000000 | | 0x484842CC | 0x00000000 | | 0x484842D0 | 0x00000000 | | 0x484842D4 | 0x00000000 | | 0x484842D8 | 0x00000000 | | 0x484842DC | 0x00000000 | | 0x484842E0 | 0x00000000 | | 0x484842E4 | 0x00000000 | | 0x484842E8 | 0x00000000 | | 0x484842EC | 0x00000000 | | 0x484842F0 | 0x00000000 | | 0x484842F4 | 0x00000000 | | 0x484842F8 | 0x00000000 | | 0x484842FC | 0x00000000 | | 0x48484300 | 0x00000000 | | 0x48484304 | 0x00040000 | | 0x48484308 | 0x000000F5 | | 0x4848430C | 0x00000041 | | 0x48484310 | 0x080040C0 | | 0x48484314 | 0x00000000 | | 0x48484318 | 0x33221100 | | 0x4848431C | 0x001E0000 | | 0x48484320 | 0x0000CAD3 | | 0x48484324 | 0x4EFF3500 | | 0x48484328 | 0x00000000 | | 0x4848432C | 0x00000000 | | 0x48484330 | 0x00000000 | | 0x48484334 | 0x00000000 | | 0x48484338 | 0x00000000 | | 0x4848433C | 0x00000000 | | 0x48484340 | 0x00000000 | | 0x48484344 | 0x00000000 | | 0x48484348 | 0x00000000 | | 0x4848434C | 0x00000000 | | 0x48484350 | 0x00000000 | | 0x48484354 | 0x00000000 | |----------------------------| WX

Responses:
The pin mux config as below: {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */

Hi, What is the Linux and SDK version ? Is MDIO functional ? Are you able to query the PHY registers ? Regards Vineet

Hi Vineet, Thanks for you quickly response. The SDK version is VSDK03.08 Linux version is 4.19.73 The PHY can be read OK via MDIO, and the link status is up. WX.

Hi Vineet, We tried ping command on board, and measured the signal output from TX_D0, TX_D1, TX_D2, TX_D3, but the TX_CLK is only 2.5MHz, not 25MHz. WX.

Hi Vineet, After run ethtool, Supported ports: [ TP MII ] Supported link modes: Not reported Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: Not reported Advertised pause frame use: No Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: 100Mb/s Duplex: Full Port: MII PHYAD: 0 Transceiver: internal Auto-negotiation: off Supports Wake-on: gs Wake-on: gs SecureOn password: 00:00:00:00:00:00 Current message level: 0x00000000 (0) Link detected: yes WX.

Hi Vineet, Any update? Why the RGMII TX_CLK is 2.5MHz only? The WR_RGMII_CTL and SL_MACCONTROL registers show below value: WR_RGMII_CTL: 0x4848 5288 = 0x00000000 SL_MACCONTROL: 0x4848 4D84 = 0x0008021 WX.

Hi, Has someone from TI reviewed your HW schematic ? Would be a good idea to check that first. Regards Vineet

Hi Vineet, The schematic is very easy. We connect the TDA2 RGMII pin (RX_DV, RCLK, RXD0, RXD1,RXD2, RXD3, TCLK, TXEN, TXD0, TXD1, TXD2, TXD3) to DP83TC811SEVM board, NOT use the phy chip on our board. So, the HW is same as DP83TC811SEVM. Regards, WX

Hi Vineet, Today, we tried some test, the status as below, 1. Modify dts, add fixed-link node. &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii"; dual_emac_res_vlan = <1>; fixed-link { speed = <100>; full-duplex; }; }; The result is same. WR_RGMII_CTL: 0x4848 5288 = 0x00000000 SL_MACCONTROL: 0x4848 4D84 = 0x0008021 The signal of TX_D0~TX_D3 are OK, TX_CLK is still 2.5MHz, not 25MHz. The signal of RX_D0~RX_D3 are OK, RX_CLK is 25MHz, RX_DV is OK. But, the TDA2 can't received ping package from PC. 2. We tried to correct the cpsw's register value according to which on EVM5777 reference board. But, the RX_CLK is still 2.5MHz, and the TDA2 can't received ping package from PC. Best Regards, WX

Hi, The TX_CLK of 2.5 Mhz is indicative of the problem. It means that either PHY isn't initialized correctly or MAC configuration hasn't been done or there is some HW issue. Let's try to isolate 1. Can you post netstat -i dump ? 2. Please check CTRL_CORE_CONTROL_IO_1 : 0x4A00 2554 value. This selects the RGMII mode for MAC 3. Make sure you have followed the checklist in Section 24.11.5.4 Initialization and Configuration of CPSW of TRM 4. Please post "mii info" output from U-boot Regards Vineet