Ticket Name: TDA2HG: Using GPIO pins as SPI chip select pins

Query Text:
Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 Hi All , We are using TDA2HG in one of our designs for video processing. I have 2 queries regarding the SPI and I2C interface: 1. We need to interface multiple camera companion chip sets through SPI interface for Booting of the companion chip set. we are running out of SPI controller chip select pins.Can we use GPIO pins as chip select pins ?, in that case do the IOSET timings will be preserved? 2. Controlling of Companion chip sets were implemented through I2C interface. Whether sharing the I2C bus between 2 companion chipsets affect the image quality or video processing ability? Thanks in advance , Dhanasekar.c

Responses:
Hi Dhanasekar, I have forwarded your question to an expert for comment. Regards, Yordan

Thanks Yordon

Hi Dhanasekar, 1. No I don't think you can use a GPIO, MCSPI has an internal state machine that drives the CS pins. This allows also to use different settings for each CS to support different types of SPI peripherals on the same bus. There are 4 MSPIs x 4 CS each = 16 CSs in TDA2. They can be less however due the top-level muxing. How much do you have with your muxing configuration? 2. This will depend on your use case. If you need i2c transactions to the two sensors on <perfectly> same time, you will need two I2Cs (TDA2x has 4) . If I2C transactions can be subsequent obviously one I2C is enough. Particularly, the I2C speed will be also a driving factor (e.g. 100k, 400k, 1M or faster) and the sensor should support that speed. Regards, Stan

Dear Stan , Thank you very much for your Prompt reply. Regarding SPI interface , we have already used 2 (SPI2 and SPI3) for Host MCU interfaces(Generic control interface and Lane sensing). Remaining 2 SPI ports were used for companion chipsets(SPI1 for controlling 4 chipsets and SPI4 for controlling two remaining companion chipsets). So we have used all the SPI ports. Can we Keep data and clock common for all camera companion chipsets , and have chip select signals from 2 different SPI ports, Say an example , Common Data and Common clock and 4 chipselect lines from SPI1 port and only 2 chipselect lines from SPI4 .Whether this type of connection is feasible and whether the timings will be preserved? Thanks in advance , Dhanasekar.c

Sounds feasible to me. Most important point is to make sure the one MCSPI is not driving data out and clock while the other MCSPI is driving the bus. I.e. to avoid data out or clock contention if both MCSPIs attempt to drive the bus. Regards, Stan

Dear Stan , Thank you very much for the guidance. Regards , Dhanasekar.c

Dear Stan , Thank you very much for your guidance. I have query regarding the drive strength of SPI lines. We are accessing 6 Companion chip sets in single instant of time: We are using 3.3V logic SPI interface for interfacing SOC to the camera companion chipsets. Datasheet of TDA2HGH does not provide information regarding DC electrical charcteristsics for SPI interface. Can we use Dual voltage LVCMOS characteristics on page no. 166 of SOC datasheet for SPI electrical characterisstics? If yes , then can the output drive current range would be 6mA(minimum) to 3.3V/40 ohms = 82.5mA (Nominal) for each SPI interface pins? 6mA is minimum output drive current as per datasheet for 3.3V Dual voltage LVCMOS interface. 40 ohms is nominal impedance for 3.3V Dual voltage LVCMOS interface as per datasheet. Kindly let me know your suggestions on this. Thanks in advance , Dhanasekar.c

Dear Stan , Thank you very much for your guidance. I have query regarding the drive strength of SPI lines. We are accessing 6 Companion chip sets in single instant of time: We are using 3.3V logic SPI interface for interfacing SOC to the camera companion chipsets. Datasheet of TDA2HGH does not provide information regarding DC electrical charcteristsics for SPI interface. Can we use Dual voltage LVCMOS characteristics on page no. 166 of SOC datasheet for SPI electrical characterisstics? If yes , then can the output drive current range would be 6mA(minimum) to 3.3V/40 ohms = 82.5mA (Nominal) for each SPI interface pins? 6mA is minimum output drive current as per datasheet for 3.3V Dual voltage LVCMOS interface. 40 ohms is nominal output drive impedance for 3.3V Dual voltage LVCMOS interface as per datasheet. I have attached the snap shot of the datasheet. Kindly let me know your suggestions on this. Thanks in advance , Dhanasekar.c

Dhanasekar, Only now I understand you want to transmit data simultaneously to 4 slaves. This is not SPI was intended for, I presume you know it? Is this only a one-way transmission in your use-case?, i.e. SoC to slaves only? Can you draw some sort of schematic diagram so it will be easier to understand the concept? Regarding the pin drive strength, it is 6mA. You cannot source more than 6mA. Regards, Stan

Dear Stan , Thank you very much for your reply on drive current for SPI bus. SPI communication between the SOC and slave devices is as follows: 1. Yes it is a two way communication. 2. We need to drive 6 slaves at a time. 3. SOC (Master) will broadcast the data to all slaves at the same time through MOSI line. 4. Slaves will acknowledge individually to the master through the MISO line. We have used 4 chipselect lines for 4 slaves from SPI1 Port of the SOC and 2 chipselect lines will be used either from SPI3 or SPI2 ports of SOC. We are taking data and clock only from SPI1 port. Data and clock lines of SPI3 or SPI4 port will not be used. As per the datasheet details the chipselect lines were also muxed with GPIO pins. In that scenario can we configure chip select lines as GPIO lines to enable the slave device? Please advice. I have attached a rough sketch of connection details. Regards , Dhanasekar.c

Hi Dhanasekar, My answers inline. 1. Yes it is a two way communication. 2. We need to drive 6 slaves at a time. 3. SOC (Master) will broadcast the data to all slaves at the same time through MOSI line. [Broadcasting is not possible in SPI, you can only access one slave at a time] 4. Slaves will acknowledge individually to the master through the MISO line. [This is fine if you follow my comment for 3.] We have used 4 chipselect lines for 4 slaves from SPI1 Port of the SOC and 2 chipselect lines will be used either from SPI3 or SPI2 ports of SOC. We are taking data and clock only from SPI1 port. Data and clock lines of SPI3 or SPI4 port will not be used. As per the datasheet details the chipselect lines were also muxed with GPIO pins. In that scenario can we configure chip select lines as GPIO lines to enable the slave device? Please advice. [TI An SPI hardware 'knows' that it has only 4 CS-es. I'm thinking of one trick to overcome that: - You can use first 3 CS-es as usual [CS0-CS2] - You must disconnect CS3 from any external hardware (on PCB or via SoC pinmux). In your particular case you can switch (mux) CS3 to a GPIO. - SPI hardware will continue to think of its CS3 as of single device, but you (SW) will do the CS3-CS5 assertions artificially via 3x GPIOs. That is, when you need to access devices CS3-CS5, you need to assert the proper GPIO pin, and then, issue a transfer to CS3 of SPI1. Those above are only thoughts, I cannot guarantee it will work, nor I do know how the slaves work and their requirements to SPI modes and timing.] Best regards, Stan