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latent-consistency
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Real-Time-LCM-ControlNet-Lora-SD1.5

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Real-Time-LCM-ControlNet-Lora-SD1.5 / pipelines /controlnetSDXLTurbo.py

Commit History

use taesd for all models

2951b6b

radames commited on Dec 1, 2023

constraint steps*strength >= 1

74f6ce1

radames commited on Dec 1, 2023

add SDXL Turbo examples

dbe1557

radames commited on Dec 1, 2023