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From 7f41ef32c8c887ee23ca83da4dfd7a4f27e01186 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Wed, 10 Feb 2016 23:09:51 +0100
Subject: [PATCH] sysdep.h: don't assume <error.h> is available on all Linux
platforms
The current logic in sysdep.h assumes that whenever you have __linux__
or __GLIBC__ defined, then <error.h> functionality is
available. However, the <error.h> functionality is a glibc-ism, not
available in more standard-conformant C libraries such as the musl C
library. With musl, __linux__ is defined (but of course not
__GLIBC__). With the current logic, sysdep.h assumes that <error.h> is
available, which isn't the case.
This patch therefore changes the logic to only use <error.h> when
__GLIBC__ is defined. It fixes the following build error:
In file included from tunip.c:87:0:
sysdep.h:41:19: fatal error: error.h: No such file or directory
#include <error.h>
Original patch from
http://git.alpinelinux.org/cgit/aports/tree/testing/vpnc/working.patch.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
sysdep.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/sysdep.h b/sysdep.h
index 137bf6d..fb65b31 100644
--- a/sysdep.h
+++ b/sysdep.h
@@ -38,11 +38,14 @@ int tun_get_hwaddr(int fd, char *dev, uint8_t *hwaddr);
/***************************************************************************/
#if defined(__linux__) || defined(__GLIBC__)
+
+#ifdef __GLIBC__
#include <error.h>
+#define HAVE_ERROR 1
+#endif
#define HAVE_VASPRINTF 1
#define HAVE_ASPRINTF 1
-#define HAVE_ERROR 1
#define HAVE_UNSETENV 1
#define HAVE_SETENV 1
#endif
--
2.6.4
| {
"language": "Assembly"
} |
// RUN: %clang -### -S \
// RUN: --save-temps --undefine-macro=FOO --undefine-macro BAR \
// RUN: --param=FOO --output=FOO %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: "-cc1"
// CHECK: "-E"
// CHECK: "-U" "FOO"
// CHECK: "-U" "BAR"
// CHECK: "-o" "option-aliases.i"
// CHECK-NEXT: "-cc1"
// CHECK: "-S"
// CHECK: "-o" "FOO"
| {
"language": "Assembly"
} |
dnl PowerPC mftb_function -- read time base registers.
dnl Copyright 2002 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C void mftb_function (unsigned a[2]);
C
ASM_START()
PROLOGUE(mftb_function)
C r3 a
L(again):
mftbu r4
mftb r5
mftbu r6
cmpw cr0, r4, r6
bne L(again)
stw r5, 0(r3)
stw r4, 4(r3)
blr
EPILOGUE()
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -newgvn -S | FileCheck %s
@g_20 = external global i32, align 4
define void @test() {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD1:%.*]], [[CRITEDGE:%.*]] ]
; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @g_20, align 4
; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[STOREMERGE]], 0
; CHECK-NEXT: br i1 [[CMP0]], label [[LR_PH:%.*]], label [[CRITEDGE]]
; CHECK: lr.ph:
; CHECK-NEXT: [[LV:%.*]] = load i64, i64* inttoptr (i64 16 to i64*), align 16
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[LV]], 0
; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER_SPLIT:%.*]], label [[CRITEDGE]]
; CHECK: preheader.split:
; CHECK-NEXT: br label [[PREHEADER_SPLIT]]
; CHECK: critedge:
; CHECK-NEXT: [[PHIOFOPS1:%.*]] = phi i1 [ false, [[BB1]] ], [ true, [[LR_PH]] ]
; CHECK-NEXT: [[PHIOFOPS:%.*]] = phi i1 [ [[CMP0]], [[BB1]] ], [ true, [[LR_PH]] ]
; CHECK-NEXT: [[DOT05_LCSSA:%.*]] = phi i32 [ 0, [[BB1]] ], [ -1, [[LR_PH]] ]
; CHECK-NEXT: [[ADD1]] = add nsw i32 [[STOREMERGE]], -1
; CHECK-NEXT: br i1 [[PHIOFOPS]], label [[BB1]], label [[END:%.*]]
; CHECK: end:
; CHECK-NEXT: ret void
;
entry:
br label %bb1
bb1: ; preds = %critedge, %entry
%storemerge = phi i32 [ 0, %entry ], [ %add1, %critedge ]
store i32 %storemerge, i32* @g_20, align 4
%cmp0 = icmp eq i32 %storemerge, 0
br i1 %cmp0, label %lr.ph, label %critedge
lr.ph: ; preds = %bb1
%lv = load i64, i64* inttoptr (i64 16 to i64*), align 16
%cmp1 = icmp eq i64 %lv, 0
br i1 %cmp1, label %preheader.split, label %critedge
preheader.split: ; preds = %lr.ph, %preheader.split
br label %preheader.split
critedge: ; preds = %lr.ph, %bb1
%.05.lcssa = phi i32 [ 0, %bb1 ], [ -1, %lr.ph ]
%cmp2 = icmp ne i32 %.05.lcssa, 0
%brmerge = or i1 %cmp0, %cmp2
%add1 = add nsw i32 %storemerge, -1
br i1 %brmerge, label %bb1, label %end
end:
ret void
}
; In this test case a temporary PhiOfOps node gets moved to BB with more
; predecessors, so a new one needs to be created.
define void @test2() {
; CHECK-LABEL: @test2(
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[ADD:%.*]], [[CRITEDGE:%.*]] ]
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[STOREMERGE]], 0
; CHECK-NEXT: br i1 [[CMP1]], label [[LR_PH:%.*]], label [[CRITEDGE]]
; CHECK: lr.ph:
; CHECK-NEXT: br i1 undef, label [[SPLIT1:%.*]], label [[SPLIT2:%.*]]
; CHECK: split1:
; CHECK-NEXT: br label [[CRITEDGE]]
; CHECK: split2:
; CHECK-NEXT: br label [[CRITEDGE]]
; CHECK: critedge:
; CHECK-NEXT: [[PHIOFOPS1:%.*]] = phi i1 [ false, [[BB1]] ], [ true, [[SPLIT2]] ], [ true, [[SPLIT1]] ]
; CHECK-NEXT: [[PHIOFOPS:%.*]] = phi i1 [ [[CMP1]], [[BB1]] ], [ true, [[SPLIT2]] ], [ true, [[SPLIT1]] ]
; CHECK-NEXT: [[LCSSA:%.*]] = phi i32 [ 0, [[BB1]] ], [ -1, [[SPLIT1]] ], [ -1, [[SPLIT2]] ]
; CHECK-NEXT: [[ADD]] = add nsw i32 [[STOREMERGE]], -1
; CHECK-NEXT: br i1 [[PHIOFOPS]], label [[BB1]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
br label %bb1
bb1: ; preds = %critedge, %0
%storemerge = phi i32 [ 0, %0 ], [ %add, %critedge ]
%cmp1 = icmp eq i32 %storemerge, 0
br i1 %cmp1, label %lr.ph, label %critedge
lr.ph: ; preds = %bb1
br i1 undef, label %split1, label %split2
split1: ; preds = %lr.ph
br label %critedge
split2: ; preds = %lr.ph
br label %critedge
critedge: ; preds = %split1, %split2, %bb1
%lcssa = phi i32 [ 0, %bb1 ], [ -1, %split1 ], [ -1, %split2 ]
%cmp2 = icmp ne i32 %lcssa, 0
%brmerge = or i1 %cmp1, %cmp2
%add = add nsw i32 %storemerge, -1
br i1 %brmerge, label %bb1, label %exit
exit: ; preds = %critedge
ret void
}
| {
"language": "Assembly"
} |
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio6 = GPIO_MODE_GPIO, /* Enable power of SATA channel 0 */
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO, /* Wireless LAN power on */
.gpio10 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO, /* FAN on */
.gpio22 = GPIO_MODE_GPIO, /* FWH WP */
.gpio23 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO, /* GPS on */
.gpio25 = GPIO_MODE_GPIO, /* External Antenna Mux on */
.gpio26 = GPIO_MODE_GPIO, /* BT on */
.gpio27 = GPIO_MODE_GPIO, /* GSM on */
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio6 = GPIO_DIR_OUTPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_OUTPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_OUTPUT,
.gpio26 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
.gpio29 = GPIO_DIR_INPUT,
.gpio31 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio6 = GPIO_LEVEL_LOW,
.gpio9 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_LOW,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_HIGH,
.gpio25 = GPIO_LEVEL_LOW,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
.gpio31 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio7 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio35 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio48 = GPIO_MODE_GPIO, /* FWH TLB# */
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio35 = GPIO_DIR_OUTPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_OUTPUT,
.gpio39 = GPIO_DIR_OUTPUT,
.gpio48 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio35 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_LOW,
.gpio39 = GPIO_LEVEL_LOW,
.gpio48 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
};
| {
"language": "Assembly"
} |
# RUN: llvm-mc -triple i386-unknown-unknown %s -I %p -filetype obj -o - \
# RUN: | llvm-readobj -t | FileCheck %s
rock:
movl $42, %eax
.include "directive_end.s"
hard_place:
movl $42, %ebx
# CHECK: Symbol {
# CHECK: Name: rock
# CHECK-NOT: Name: hard_place
| {
"language": "Assembly"
} |
polygon
1
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1.326330E+01 4.318117E+01
1.326327E+01 4.318097E+01
1.326326E+01 4.318067E+01
1.326359E+01 4.318080E+01
1.326388E+01 4.318103E+01
1.326405E+01 4.318119E+01
1.326432E+01 4.318143E+01
1.326448E+01 4.318160E+01
1.326457E+01 4.318167E+01
1.326469E+01 4.318177E+01
1.326496E+01 4.318197E+01
1.326522E+01 4.318216E+01
1.326544E+01 4.318233E+01
1.326563E+01 4.318243E+01
1.326576E+01 4.318254E+01
1.326591E+01 4.318242E+01
1.326596E+01 4.318234E+01
1.326602E+01 4.318223E+01
1.326615E+01 4.318163E+01
1.326617E+01 4.318155E+01
1.326619E+01 4.318146E+01
1.326632E+01 4.318110E+01
1.326671E+01 4.318051E+01
1.326562E+01 4.317996E+01
1.326589E+01 4.317972E+01
1.326604E+01 4.317954E+01
1.326621E+01 4.317937E+01
1.326634E+01 4.317914E+01
1.326636E+01 4.317885E+01
1.326621E+01 4.317856E+01
1.326597E+01 4.317831E+01
1.326577E+01 4.317805E+01
1.326554E+01 4.317780E+01
1.326538E+01 4.317762E+01
1.326548E+01 4.317737E+01
1.326567E+01 4.317716E+01
1.326597E+01 4.317690E+01
1.326625E+01 4.317670E+01
1.326652E+01 4.317646E+01
1.326671E+01 4.317634E+01
1.326693E+01 4.317622E+01
1.326643E+01 4.317563E+01
1.326711E+01 4.317504E+01
1.326695E+01 4.317476E+01
1.326678E+01 4.317460E+01
1.326650E+01 4.317458E+01
1.326617E+01 4.317452E+01
1.326591E+01 4.317434E+01
1.326572E+01 4.317414E+01
1.326561E+01 4.317393E+01
1.326542E+01 4.317370E+01
1.326518E+01 4.317347E+01
1.326519E+01 4.317328E+01
1.326510E+01 4.317303E+01
1.326497E+01 4.317287E+01
1.326484E+01 4.317274E+01
1.326456E+01 4.317254E+01
1.326492E+01 4.317220E+01
1.326520E+01 4.317197E+01
1.326552E+01 4.317178E+01
1.326581E+01 4.317160E+01
1.326609E+01 4.317135E+01
1.326631E+01 4.317116E+01
1.326660E+01 4.317092E+01
1.326690E+01 4.317069E+01
1.326710E+01 4.317050E+01
1.326733E+01 4.317035E+01
1.326768E+01 4.317010E+01
1.326786E+01 4.316997E+01
1.326809E+01 4.316978E+01
1.326814E+01 4.316951E+01
1.326809E+01 4.316929E+01
1.326801E+01 4.316913E+01
1.326779E+01 4.316901E+01
1.326753E+01 4.316888E+01
1.326733E+01 4.316876E+01
1.326765E+01 4.316845E+01
1.326744E+01 4.316836E+01
1.326725E+01 4.316825E+01
1.326713E+01 4.316812E+01
1.326711E+01 4.316797E+01
1.326705E+01 4.316761E+01
1.326703E+01 4.316754E+01
1.326683E+01 4.316739E+01
1.326666E+01 4.316728E+01
1.326652E+01 4.316718E+01
1.326621E+01 4.316708E+01
1.326601E+01 4.316703E+01
1.326575E+01 4.316701E+01
1.326545E+01 4.316700E+01
1.326522E+01 4.316698E+01
1.326496E+01 4.316697E+01
1.326474E+01 4.316699E+01
1.326422E+01 4.316703E+01
1.326390E+01 4.316703E+01
1.326368E+01 4.316697E+01
1.326344E+01 4.316683E+01
1.326330E+01 4.316663E+01
1.326322E+01 4.316639E+01
1.326320E+01 4.316613E+01
1.326331E+01 4.316577E+01
1.326350E+01 4.316545E+01
1.326372E+01 4.316514E+01
1.326399E+01 4.316491E+01
1.326429E+01 4.316463E+01
1.326470E+01 4.316438E+01
1.326509E+01 4.316422E+01
1.326546E+01 4.316402E+01
1.326589E+01 4.316381E+01
1.326627E+01 4.316356E+01
1.326672E+01 4.316324E+01
1.326720E+01 4.316293E+01
1.326763E+01 4.316269E+01
1.326799E+01 4.316262E+01
1.326844E+01 4.316262E+01
1.326882E+01 4.316272E+01
1.326900E+01 4.316283E+01
1.326912E+01 4.316298E+01
1.326943E+01 4.316291E+01
1.326960E+01 4.316271E+01
1.326995E+01 4.316225E+01
1.327027E+01 4.316195E+01
1.327055E+01 4.316160E+01
1.327089E+01 4.316119E+01
1.327121E+01 4.316087E+01
1.327157E+01 4.316048E+01
1.327188E+01 4.316014E+01
1.327223E+01 4.315968E+01
1.327244E+01 4.315930E+01
1.327270E+01 4.315882E+01
1.327288E+01 4.315838E+01
1.327301E+01 4.315803E+01
1.327315E+01 4.315769E+01
1.327320E+01 4.315738E+01
1.327327E+01 4.315707E+01
1.327347E+01 4.315665E+01
1.327366E+01 4.315633E+01
1.327382E+01 4.315607E+01
1.327393E+01 4.315587E+01
1.327408E+01 4.315573E+01
1.327260E+01 4.315524E+01
1.327352E+01 4.315400E+01
1.327524E+01 4.315469E+01
1.327519E+01 4.315402E+01
1.327515E+01 4.315373E+01
1.327522E+01 4.315347E+01
1.327539E+01 4.315312E+01
1.327553E+01 4.315281E+01
1.327570E+01 4.315249E+01
1.327580E+01 4.315221E+01
1.327575E+01 4.315205E+01
1.327563E+01 4.315191E+01
1.327543E+01 4.315162E+01
1.327541E+01 4.315134E+01
1.327559E+01 4.315096E+01
1.327570E+01 4.315082E+01
1.327579E+01 4.315050E+01
1.327547E+01 4.315031E+01
1.327530E+01 4.315010E+01
1.327521E+01 4.314998E+01
1.327496E+01 4.314999E+01
1.327479E+01 4.315019E+01
1.327462E+01 4.315036E+01
1.327446E+01 4.315053E+01
1.327429E+01 4.315071E+01
1.327415E+01 4.315081E+01
1.327393E+01 4.315105E+01
1.327370E+01 4.315134E+01
1.327356E+01 4.315156E+01
1.327441E+01 4.315204E+01
1.327360E+01 4.315265E+01
1.327299E+01 4.315305E+01
1.327271E+01 4.315318E+01
1.327254E+01 4.315328E+01
1.327243E+01 4.315344E+01
1.327209E+01 4.315338E+01
1.327184E+01 4.315331E+01
1.327151E+01 4.315326E+01
1.327101E+01 4.315316E+01
1.327069E+01 4.315305E+01
1.327039E+01 4.315280E+01
1.327031E+01 4.315258E+01
1.327022E+01 4.315224E+01
1.327011E+01 4.315182E+01
1.326983E+01 4.315178E+01
1.326948E+01 4.315179E+01
1.326893E+01 4.315174E+01
1.326845E+01 4.315170E+01
1.326794E+01 4.315159E+01
1.326760E+01 4.315144E+01
1.326713E+01 4.315120E+01
1.326662E+01 4.315088E+01
1.326623E+01 4.315060E+01
1.326574E+01 4.315023E+01
1.326541E+01 4.314997E+01
1.326361E+01 4.314872E+01
1.326264E+01 4.314789E+01
1.326210E+01 4.314741E+01
1.326177E+01 4.314717E+01
1.326126E+01 4.314686E+01
1.326084E+01 4.314660E+01
1.326039E+01 4.314633E+01
1.326009E+01 4.314615E+01
1.325957E+01 4.314587E+01
1.325917E+01 4.314563E+01
1.325861E+01 4.314546E+01
1.325806E+01 4.314537E+01
1.325737E+01 4.314531E+01
1.325670E+01 4.314526E+01
1.325585E+01 4.314508E+01
1.325547E+01 4.314493E+01
1.325508E+01 4.314477E+01
1.325478E+01 4.314459E+01
1.325435E+01 4.314424E+01
1.325405E+01 4.314397E+01
1.325378E+01 4.314376E+01
1.325352E+01 4.314366E+01
1.325324E+01 4.314363E+01
1.325241E+01 4.314376E+01
1.325181E+01 4.314384E+01
1.325118E+01 4.314384E+01
1.325069E+01 4.314380E+01
1.325036E+01 4.314378E+01
1.325003E+01 4.314350E+01
1.324984E+01 4.314323E+01
1.324973E+01 4.314308E+01
1.324955E+01 4.314294E+01
1.324920E+01 4.314281E+01
1.324893E+01 4.314273E+01
1.324837E+01 4.314275E+01
1.324792E+01 4.314264E+01
1.324748E+01 4.314244E+01
1.324718E+01 4.314229E+01
1.324684E+01 4.314206E+01
1.324670E+01 4.314193E+01
1.324615E+01 4.314214E+01
1.324549E+01 4.314232E+01
1.324502E+01 4.314251E+01
1.324422E+01 4.314277E+01
1.324375E+01 4.314289E+01
1.324306E+01 4.314319E+01
1.324275E+01 4.314329E+01
1.324203E+01 4.314354E+01
1.324148E+01 4.314376E+01
1.324082E+01 4.314401E+01
1.324037E+01 4.314419E+01
1.323986E+01 4.314440E+01
1.323918E+01 4.314463E+01
1.323876E+01 4.314476E+01
1.323816E+01 4.314490E+01
1.323768E+01 4.314494E+01
1.323719E+01 4.314504E+01
1.323675E+01 4.314521E+01
1.323641E+01 4.314543E+01
1.323635E+01 4.314563E+01
1.323639E+01 4.314589E+01
1.323643E+01 4.314612E+01
1.323643E+01 4.314642E+01
1.323635E+01 4.314667E+01
1.323614E+01 4.314684E+01
1.323588E+01 4.314701E+01
1.323562E+01 4.314722E+01
1.323541E+01 4.314742E+01
1.323497E+01 4.314792E+01
1.323477E+01 4.314836E+01
1.323460E+01 4.314858E+01
1.323428E+01 4.314879E+01
1.323410E+01 4.314892E+01
1.323371E+01 4.314915E+01
1.323313E+01 4.314955E+01
1.323270E+01 4.315007E+01
1.323235E+01 4.315030E+01
1.323213E+01 4.315029E+01
1.323180E+01 4.315028E+01
1.323151E+01 4.315030E+01
1.323107E+01 4.315043E+01
1.323082E+01 4.315055E+01
1.323054E+01 4.315071E+01
1.323029E+01 4.315085E+01
1.322986E+01 4.315102E+01
1.322961E+01 4.315113E+01
1.322930E+01 4.315130E+01
1.322897E+01 4.315153E+01
1.322861E+01 4.315177E+01
1.322833E+01 4.315196E+01
1.322792E+01 4.315211E+01
1.322757E+01 4.315234E+01
1.322729E+01 4.315258E+01
1.322699E+01 4.315298E+01
1.322679E+01 4.315319E+01
1.322673E+01 4.315325E+01
1.322649E+01 4.315334E+01
1.322618E+01 4.315339E+01
1.322587E+01 4.315346E+01
1.322531E+01 4.315356E+01
1.322489E+01 4.315365E+01
1.322446E+01 4.315373E+01
1.322393E+01 4.315381E+01
1.322340E+01 4.315387E+01
1.322305E+01 4.315386E+01
1.322266E+01 4.315374E+01
1.322251E+01 4.315354E+01
1.322238E+01 4.315336E+01
1.322236E+01 4.315316E+01
1.322228E+01 4.315291E+01
1.322210E+01 4.315251E+01
1.322202E+01 4.315238E+01
END
END
| {
"language": "Assembly"
} |
.late_rodata
glabel D_8013A3F8
.float 0.01
glabel D_8013A3FC
.float -0.01
glabel D_8013A400
.float 0.6
glabel D_8013A404
.float 0.2
glabel D_8013A408
.float -0.3
glabel D_8013A40C
.float 0.3
glabel D_8013A410
.float 0.09
glabel D_8013A414
.float 0.01
glabel D_8013A418
.float 359.2
glabel D_8013A41C
.float 0.08
glabel D_8013A420
.float 0.45
glabel D_8013A424
.float 0.01
glabel D_8013A428
.float -0.01
glabel D_8013A42C
.float 0.6
glabel D_8013A430
.float 182.041672 # 32768 / PI
.text
glabel func_80058E8C
/* AD002C 80058E8C 27BDFF98 */ addiu $sp, $sp, -0x68
/* AD0030 80058E90 AFBF0024 */ sw $ra, 0x24($sp)
/* AD0034 80058E94 AFB00020 */ sw $s0, 0x20($sp)
/* AD0038 80058E98 F7B40018 */ sdc1 $f20, 0x18($sp)
/* AD003C 80058E9C 84820152 */ lh $v0, 0x152($a0)
/* AD0040 80058EA0 00808025 */ move $s0, $a0
/* AD0044 80058EA4 104000C2 */ beqz $v0, .L800591B0
/* AD0048 80058EA8 304E0004 */ andi $t6, $v0, 4
/* AD004C 80058EAC 11C00019 */ beqz $t6, .L80058F14
/* AD0050 80058EB0 30580008 */ andi $t8, $v0, 8
/* AD0054 80058EB4 3C018014 */ lui $at, %hi(D_8013A3F8)
/* AD0058 80058EB8 C430A3F8 */ lwc1 $f16, %lo(D_8013A3F8)($at)
/* AD005C 80058EBC 3C01432A */ li $at, 0x432A0000 # 0.000000
/* AD0060 80058EC0 44811000 */ mtc1 $at, $f2
/* AD0064 80058EC4 3C018014 */ lui $at, %hi(D_8013A3FC)
/* AD0068 80058EC8 C424A3FC */ lwc1 $f4, %lo(D_8013A3FC)($at)
/* AD006C 80058ECC 3C018014 */ lui $at, %hi(D_8013A400)
/* AD0070 80058ED0 44803000 */ mtc1 $zero, $f6
/* AD0074 80058ED4 C428A400 */ lwc1 $f8, %lo(D_8013A400)($at)
/* AD0078 80058ED8 E7B0003C */ swc1 $f16, 0x3c($sp)
/* AD007C 80058EDC E7A40040 */ swc1 $f4, 0x40($sp)
/* AD0080 80058EE0 E7A60038 */ swc1 $f6, 0x38($sp)
/* AD0084 80058EE4 E7A80034 */ swc1 $f8, 0x34($sp)
/* AD0088 80058EE8 848F0150 */ lh $t7, 0x150($a0)
/* AD008C 80058EEC 3C014270 */ li $at, 0x42700000 # 0.000000
/* AD0090 80058EF0 44813000 */ mtc1 $at, $f6
/* AD0094 80058EF4 448F5000 */ mtc1 $t7, $f10
/* AD0098 80058EF8 3C013F80 */ li $at, 0x3F800000 # 0.000000
/* AD009C 80058EFC 44814000 */ mtc1 $at, $f8
/* AD00A0 80058F00 46805120 */ cvt.s.w $f4, $f10
/* AD00A4 80058F04 44800000 */ mtc1 $zero, $f0
/* AD00A8 80058F08 E7A80060 */ swc1 $f8, 0x60($sp)
/* AD00AC 80058F0C 10000054 */ b .L80059060
/* AD00B0 80058F10 46062503 */ div.s $f20, $f4, $f6
.L80058F14:
/* AD00B4 80058F14 13000019 */ beqz $t8, .L80058F7C
/* AD00B8 80058F18 30480002 */ andi $t0, $v0, 2
/* AD00BC 80058F1C 3C018014 */ lui $at, %hi(D_8013A404)
/* AD00C0 80058F20 C42CA404 */ lwc1 $f12, %lo(D_8013A404)($at)
/* AD00C4 80058F24 3C014378 */ li $at, 0x43780000 # 0.000000
/* AD00C8 80058F28 44810000 */ mtc1 $at, $f0
/* AD00CC 80058F2C 3C01C2B4 */ li $at, 0xC2B40000 # 0.000000
/* AD00D0 80058F30 44811000 */ mtc1 $at, $f2
/* AD00D4 80058F34 3C018014 */ lui $at, %hi(D_8013A408)
/* AD00D8 80058F38 C42AA408 */ lwc1 $f10, %lo(D_8013A408)($at)
/* AD00DC 80058F3C 3C018014 */ lui $at, %hi(D_8013A40C)
/* AD00E0 80058F40 C424A40C */ lwc1 $f4, %lo(D_8013A40C)($at)
/* AD00E4 80058F44 E7AC0038 */ swc1 $f12, 0x38($sp)
/* AD00E8 80058F48 E7AC0034 */ swc1 $f12, 0x34($sp)
/* AD00EC 80058F4C E7AA0040 */ swc1 $f10, 0x40($sp)
/* AD00F0 80058F50 E7A4003C */ swc1 $f4, 0x3c($sp)
/* AD00F4 80058F54 86190150 */ lh $t9, 0x150($s0)
/* AD00F8 80058F58 3C0142A0 */ li $at, 0x42A00000 # 0.000000
/* AD00FC 80058F5C 44815000 */ mtc1 $at, $f10
/* AD0100 80058F60 44993000 */ mtc1 $t9, $f6
/* AD0104 80058F64 3C013F80 */ li $at, 0x3F800000 # 0.000000
/* AD0108 80058F68 44812000 */ mtc1 $at, $f4
/* AD010C 80058F6C 46803220 */ cvt.s.w $f8, $f6
/* AD0110 80058F70 E7A40060 */ swc1 $f4, 0x60($sp)
/* AD0114 80058F74 1000003A */ b .L80059060
/* AD0118 80058F78 460A4503 */ div.s $f20, $f8, $f10
.L80058F7C:
/* AD011C 80058F7C 11000026 */ beqz $t0, .L80059018
/* AD0120 80058F80 30490001 */ andi $t1, $v0, 1
/* AD0124 80058F84 3C018014 */ lui $at, %hi(D_8013A410)
/* AD0128 80058F88 C42EA410 */ lwc1 $f14, %lo(D_8013A410)($at)
/* AD012C 80058F8C 3C018014 */ lui $at, %hi(D_8013A414)
/* AD0130 80058F90 C430A414 */ lwc1 $f16, %lo(D_8013A414)($at)
/* AD0134 80058F94 3C014316 */ li $at, 0x43160000 # 0.000000
/* AD0138 80058F98 44819000 */ mtc1 $at, $f18
/* AD013C 80058F9C 3C018014 */ lui $at, %hi(D_8013A418)
/* AD0140 80058FA0 C420A418 */ lwc1 $f0, %lo(D_8013A418)($at)
/* AD0144 80058FA4 3C01C194 */ li $at, 0xC1940000 # 0.000000
/* AD0148 80058FA8 44811000 */ mtc1 $at, $f2
/* AD014C 80058FAC 3C018014 */ lui $at, %hi(D_8013A41C)
/* AD0150 80058FB0 C426A41C */ lwc1 $f6, %lo(D_8013A41C)($at)
/* AD0154 80058FB4 E7AE0040 */ swc1 $f14, 0x40($sp)
/* AD0158 80058FB8 E7AE003C */ swc1 $f14, 0x3c($sp)
/* AD015C 80058FBC E7B00038 */ swc1 $f16, 0x38($sp)
/* AD0160 80058FC0 E7A60034 */ swc1 $f6, 0x34($sp)
/* AD0164 80058FC4 C60A0060 */ lwc1 $f10, 0x60($s0)
/* AD0168 80058FC8 C6080114 */ lwc1 $f8, 0x114($s0)
/* AD016C 80058FCC 3C013F80 */ li $at, 0x3F800000 # 0.000000
/* AD0170 80058FD0 460A4301 */ sub.s $f12, $f8, $f10
/* AD0174 80058FD4 460C903C */ c.lt.s $f18, $f12
/* AD0178 80058FD8 00000000 */ nop
/* AD017C 80058FDC 45020005 */ bc1fl .L80058FF4
/* AD0180 80058FE0 46126383 */ div.s $f14, $f12, $f18
/* AD0184 80058FE4 44817000 */ mtc1 $at, $f14
/* AD0188 80058FE8 10000002 */ b .L80058FF4
/* AD018C 80058FEC 00000000 */ nop
/* AD0190 80058FF0 46126383 */ div.s $f14, $f12, $f18
.L80058FF4:
/* AD0194 80058FF4 3C018014 */ lui $at, %hi(D_8013A420)
/* AD0198 80058FF8 C42CA420 */ lwc1 $f12, %lo(D_8013A420)($at)
/* AD019C 80058FFC C60600E0 */ lwc1 $f6, 0xe0($s0)
/* AD01A0 80059000 460C7102 */ mul.s $f4, $f14, $f12
/* AD01A4 80059004 00000000 */ nop
/* AD01A8 80059008 460C3202 */ mul.s $f8, $f6, $f12
/* AD01AC 8005900C 46082500 */ add.s $f20, $f4, $f8
/* AD01B0 80059010 10000013 */ b .L80059060
/* AD01B4 80059014 E7B40060 */ swc1 $f20, 0x60($sp)
.L80059018:
/* AD01B8 80059018 1120006F */ beqz $t1, .L800591D8
/* AD01BC 8005901C 3C018014 */ lui $at, %hi(D_8013A424)
/* AD01C0 80059020 C430A424 */ lwc1 $f16, %lo(D_8013A424)($at)
/* AD01C4 80059024 3C014316 */ li $at, 0x43160000 # 0.000000
/* AD01C8 80059028 44811000 */ mtc1 $at, $f2
/* AD01CC 8005902C 3C018014 */ lui $at, %hi(D_8013A428)
/* AD01D0 80059030 C42AA428 */ lwc1 $f10, %lo(D_8013A428)($at)
/* AD01D4 80059034 3C018014 */ lui $at, %hi(D_8013A42C)
/* AD01D8 80059038 C426A42C */ lwc1 $f6, %lo(D_8013A42C)($at)
/* AD01DC 8005903C 3C013F80 */ li $at, 0x3F800000 # 0.000000
/* AD01E0 80059040 44812000 */ mtc1 $at, $f4
/* AD01E4 80059044 44800000 */ mtc1 $zero, $f0
/* AD01E8 80059048 4481A000 */ mtc1 $at, $f20
/* AD01EC 8005904C E7B0003C */ swc1 $f16, 0x3c($sp)
/* AD01F0 80059050 E7B00038 */ swc1 $f16, 0x38($sp)
/* AD01F4 80059054 E7AA0040 */ swc1 $f10, 0x40($sp)
/* AD01F8 80059058 E7A60034 */ swc1 $f6, 0x34($sp)
/* AD01FC 8005905C E7A40060 */ swc1 $f4, 0x60($sp)
.L80059060:
/* AD0200 80059060 3C018014 */ lui $at, %hi(D_8013A430)
/* AD0204 80059064 C42CA430 */ lwc1 $f12, %lo(D_8013A430)($at)
/* AD0208 80059068 3C013F00 */ li $at, 0x3F000000 # 0.000000
/* AD020C 8005906C 44817000 */ mtc1 $at, $f14
/* AD0210 80059070 460C0202 */ mul.s $f8, $f0, $f12
/* AD0214 80059074 3C048012 */ lui $a0, %hi(D_8011DB08) # $a0, 0x8012
/* AD0218 80059078 3C0E8012 */ lui $t6, %hi(D_8011DB0C) # $t6, 0x8012
/* AD021C 8005907C 460C1102 */ mul.s $f4, $f2, $f12
/* AD0220 80059080 8484DB08 */ lh $a0, %lo(D_8011DB08)($a0)
/* AD0224 80059084 85CEDB0C */ lh $t6, %lo(D_8011DB0C)($t6)
/* AD0228 80059088 3C018012 */ lui $at, %hi(D_8011DB0C) # $at, 0x8012
/* AD022C 8005908C 460E4280 */ add.s $f10, $f8, $f14
/* AD0230 80059090 460E2200 */ add.s $f8, $f4, $f14
/* AD0234 80059094 4600518D */ trunc.w.s $f6, $f10
/* AD0238 80059098 4600428D */ trunc.w.s $f10, $f8
/* AD023C 8005909C 440D3000 */ mfc1 $t5, $f6
/* AD0240 800590A0 44085000 */ mfc1 $t0, $f10
/* AD0244 800590A4 008D2021 */ addu $a0, $a0, $t5
/* AD0248 800590A8 00042400 */ sll $a0, $a0, 0x10
/* AD024C 800590AC 01C84821 */ addu $t1, $t6, $t0
/* AD0250 800590B0 A429DB0C */ sh $t1, %lo(D_8011DB0C)($at)
/* AD0254 800590B4 00042403 */ sra $a0, $a0, 0x10
/* AD0258 800590B8 3C018012 */ lui $at, %hi(D_8011DB08) # $at, 0x8012
/* AD025C 800590BC 0C01DE0D */ jal Math_Coss
/* AD0260 800590C0 A424DB08 */ sh $a0, %lo(D_8011DB08)($at)
/* AD0264 800590C4 3C048012 */ lui $a0, %hi(D_8011DB08) # $a0, 0x8012
/* AD0268 800590C8 0C01DE1C */ jal Math_Sins
/* AD026C 800590CC 8484DB08 */ lh $a0, %lo(D_8011DB08)($a0)
/* AD0270 800590D0 3C048012 */ lui $a0, %hi(D_8011DB0C)
/* AD0274 800590D4 0C01DE1C */ jal Math_Sins
/* AD0278 800590D8 8484DB0C */ lh $a0, %lo(D_8011DB0C)($a0)
/* AD027C 800590DC 44801000 */ mtc1 $zero, $f2
/* AD0280 800590E0 8E04008C */ lw $a0, 0x8c($s0)
/* AD0284 800590E4 44051000 */ mfc1 $a1, $f2
/* AD0288 800590E8 44061000 */ mfc1 $a2, $f2
/* AD028C 800590EC 44071000 */ mfc1 $a3, $f2
/* AD0290 800590F0 0C02A9DB */ jal func_800AA76C
/* AD0294 800590F4 248400B8 */ addiu $a0, $a0, 0xb8
/* AD0298 800590F8 3C048012 */ lui $a0, %hi(D_8011DB0C) # $a0, 0x8012
/* AD029C 800590FC 0C01DE1C */ jal Math_Sins
/* AD02A0 80059100 8484DB0C */ lh $a0, %lo(D_8011DB0C)($a0)
/* AD02A4 80059104 3C048012 */ lui $a0, %hi(D_8011DB0C) # $a0, 0x8012
/* AD02A8 80059108 8484DB0C */ lh $a0, %lo(D_8011DB0C)($a0)
/* AD02AC 8005910C 0C01DE0D */ jal Math_Coss
/* AD02B0 80059110 E7A00028 */ swc1 $f0, 0x28($sp)
/* AD02B4 80059114 3C048012 */ lui $a0, %hi(D_8011DB08) # $a0, 0x8012
/* AD02B8 80059118 8484DB08 */ lh $a0, %lo(D_8011DB08)($a0)
/* AD02BC 8005911C 0C01DE0D */ jal Math_Coss
/* AD02C0 80059120 E7A0002C */ swc1 $f0, 0x2c($sp)
/* AD02C4 80059124 C7A40040 */ lwc1 $f4, 0x40($sp)
/* AD02C8 80059128 C7A60028 */ lwc1 $f6, 0x28($sp)
/* AD02CC 8005912C 3C013F80 */ li $at, 0x3F800000 # 0.000000
/* AD02D0 80059130 46142202 */ mul.s $f8, $f4, $f20
/* AD02D4 80059134 44811000 */ mtc1 $at, $f2
/* AD02D8 80059138 8E04008C */ lw $a0, 0x8c($s0)
/* AD02DC 8005913C 248400B8 */ addiu $a0, $a0, 0xb8
/* AD02E0 80059140 46083282 */ mul.s $f10, $f6, $f8
/* AD02E4 80059144 C7A8003C */ lwc1 $f8, 0x3c($sp)
/* AD02E8 80059148 C7A6002C */ lwc1 $f6, 0x2c($sp)
/* AD02EC 8005914C 46025100 */ add.s $f4, $f10, $f2
/* AD02F0 80059150 46144282 */ mul.s $f10, $f8, $f20
/* AD02F4 80059154 44052000 */ mfc1 $a1, $f4
/* AD02F8 80059158 460A3102 */ mul.s $f4, $f6, $f10
/* AD02FC 8005915C C7A60038 */ lwc1 $f6, 0x38($sp)
/* AD0300 80059160 46143282 */ mul.s $f10, $f6, $f20
/* AD0304 80059164 46022200 */ add.s $f8, $f4, $f2
/* AD0308 80059168 460A0102 */ mul.s $f4, $f0, $f10
/* AD030C 8005916C 44064000 */ mfc1 $a2, $f8
/* AD0310 80059170 46022200 */ add.s $f8, $f4, $f2
/* AD0314 80059174 44074000 */ mfc1 $a3, $f8
/* AD0318 80059178 0C02A9E3 */ jal func_800AA78C
/* AD031C 8005917C 00000000 */ nop
/* AD0320 80059180 C7A60034 */ lwc1 $f6, 0x34($sp)
/* AD0324 80059184 C7AA0060 */ lwc1 $f10, 0x60($sp)
/* AD0328 80059188 8E04008C */ lw $a0, 0x8c($s0)
/* AD032C 8005918C 460A3102 */ mul.s $f4, $f6, $f10
/* AD0330 80059190 248400B8 */ addiu $a0, $a0, 0xb8
/* AD0334 80059194 44052000 */ mfc1 $a1, $f4
/* AD0338 80059198 0C02A9EB */ jal func_800AA7AC
/* AD033C 8005919C 00000000 */ nop
/* AD0340 800591A0 860A014C */ lh $t2, 0x14c($s0)
/* AD0344 800591A4 354B0040 */ ori $t3, $t2, 0x40
/* AD0348 800591A8 1000000B */ b .L800591D8
/* AD034C 800591AC A60B014C */ sh $t3, 0x14c($s0)
.L800591B0:
/* AD0350 800591B0 860C014C */ lh $t4, 0x14c($s0)
/* AD0354 800591B4 318D0040 */ andi $t5, $t4, 0x40
/* AD0358 800591B8 51A00008 */ beql $t5, $zero, .L800591DC
/* AD035C 800591BC 8FBF0024 */ lw $ra, 0x24($sp)
/* AD0360 800591C0 8E04008C */ lw $a0, 0x8c($s0)
/* AD0364 800591C4 0C02AA05 */ jal func_800AA814
/* AD0368 800591C8 248400B8 */ addiu $a0, $a0, 0xb8
/* AD036C 800591CC 860F014C */ lh $t7, 0x14c($s0)
/* AD0370 800591D0 31F8FFBF */ andi $t8, $t7, 0xffbf
/* AD0374 800591D4 A618014C */ sh $t8, 0x14c($s0)
.L800591D8:
/* AD0378 800591D8 8FBF0024 */ lw $ra, 0x24($sp)
.L800591DC:
/* AD037C 800591DC D7B40018 */ ldc1 $f20, 0x18($sp)
/* AD0380 800591E0 8FB00020 */ lw $s0, 0x20($sp)
/* AD0384 800591E4 03E00008 */ jr $ra
/* AD0388 800591E8 27BD0068 */ addiu $sp, $sp, 0x68
| {
"language": "Assembly"
} |
.section .opd,"aw",@progbits
.global _start
.type _start,@function
_start:
.quad .L_start, .TOC.@tocbase, 0
.text
.L_start:
lwz 3,x@toc(2)
b _start
.size _start,.-.L_start
.section .toc,"aw",@progbits
.global x
.type x,@object
x: .long 0
.size x,.-x
| {
"language": "Assembly"
} |
; RUN: opt < %s -loop-reduce -S | grep phi | count 2
; PR 2779
; Provide legal integer types.
target datalayout = "n8:16:32:64"
@g_19 = common global i32 0 ; <i32*> [#uses=3]
@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
define i32 @func_8(i8 zeroext %p_9) nounwind {
entry:
ret i32 1
}
define i32 @func_3(i8 signext %p_5) nounwind {
entry:
ret i32 1
}
define void @func_1() nounwind {
entry:
br label %bb
bb: ; preds = %bb, %entry
%indvar = phi i16 [ 0, %entry ], [ %indvar.next, %bb ] ; <i16> [#uses=2]
%tmp = sub i16 0, %indvar ; <i16> [#uses=1]
%tmp27 = trunc i16 %tmp to i8 ; <i8> [#uses=1]
load i32, i32* @g_19, align 4 ; <i32>:0 [#uses=2]
add i32 %0, 1 ; <i32>:1 [#uses=1]
store i32 %1, i32* @g_19, align 4
trunc i32 %0 to i8 ; <i8>:2 [#uses=1]
tail call i32 @func_8( i8 zeroext %2 ) nounwind ; <i32>:3 [#uses=0]
shl i8 %tmp27, 2 ; <i8>:4 [#uses=1]
add i8 %4, -112 ; <i8>:5 [#uses=1]
tail call i32 @func_3( i8 signext %5 ) nounwind ; <i32>:6 [#uses=0]
%indvar.next = add i16 %indvar, 1 ; <i16> [#uses=2]
%exitcond = icmp eq i16 %indvar.next, -28 ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
return: ; preds = %bb
ret void
}
define i32 @main() nounwind {
entry:
tail call void @func_1( ) nounwind
load i32, i32* @g_19, align 4 ; <i32>:0 [#uses=1]
tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), i32 %0 ) nounwind ; <i32>:1 [#uses=0]
ret i32 0
}
declare i32 @printf(i8*, ...) nounwind
| {
"language": "Assembly"
} |
/*
* Copyright 2014, Michael Ellerman, IBM Corp.
* Licensed under GPLv2.
*/
#include <ppc-asm.h>
#include "reg.h"
/* ppc-asm.h defines most of the reg aliases, but not r1/r2. */
#define r1 1
#define r2 2
#define RFEBB .long 0x4c000924
/* Stack layout:
*
* ^
* User stack |
* Back chain ------+ <- r1 <-------+
* ... |
* Red zone / ABI Gap |
* ... |
* vr63 <+ |
* vr0 | |
* VSCR | |
* FSCR | |
* r31 | Save area |
* r0 | |
* XER | |
* CTR | |
* LR | |
* CCR <+ |
* ... <+ |
* LR | Caller frame |
* CCR | |
* Back chain <+ <- updated r1 --------+
*
*/
#if defined(_CALL_ELF) && _CALL_ELF == 2
#define ABIGAP 512
#else
#define ABIGAP 288
#endif
#define NR_GPR 32
#define NR_SPR 6
#define NR_VSR 64
#define SAVE_AREA ((NR_GPR + NR_SPR) * 8 + (NR_VSR * 16))
#define CALLER_FRAME 112
#define STACK_FRAME (ABIGAP + SAVE_AREA + CALLER_FRAME)
#define CCR_SAVE (CALLER_FRAME)
#define LR_SAVE (CCR_SAVE + 8)
#define CTR_SAVE (LR_SAVE + 8)
#define XER_SAVE (CTR_SAVE + 8)
#define GPR_SAVE(n) (XER_SAVE + 8 + (8 * n))
#define FSCR_SAVE (GPR_SAVE(31) + 8)
#define VSCR_SAVE (FSCR_SAVE + 8)
#define VSR_SAVE(n) (VSCR_SAVE + 8 + (16 * n))
#define SAVE_GPR(n) std n,GPR_SAVE(n)(r1)
#define REST_GPR(n) ld n,GPR_SAVE(n)(r1)
#define TRASH_GPR(n) lis n,0xaaaa
#define SAVE_VSR(n, b) li b, VSR_SAVE(n); stxvd2x n,b,r1
#define LOAD_VSR(n, b) li b, VSR_SAVE(n); lxvd2x n,b,r1
#define LOAD_REG_IMMEDIATE(reg,expr) \
lis reg,(expr)@highest; \
ori reg,reg,(expr)@higher; \
rldicr reg,reg,32,31; \
oris reg,reg,(expr)@h; \
ori reg,reg,(expr)@l;
#if defined(_CALL_ELF) && _CALL_ELF == 2
#define ENTRY_POINT(name) \
.type FUNC_NAME(name),@function; \
.globl FUNC_NAME(name); \
FUNC_NAME(name):
#define RESTORE_TOC(name) \
/* Restore our TOC pointer using our entry point */ \
LOAD_REG_IMMEDIATE(r12, name) \
0: addis r2,r12,(.TOC.-0b)@ha; \
addi r2,r2,(.TOC.-0b)@l;
#else
#define ENTRY_POINT(name) FUNC_START(name)
#define RESTORE_TOC(name) \
/* Restore our TOC pointer via our opd entry */ \
LOAD_REG_IMMEDIATE(r2, name) \
ld r2,8(r2);
#endif
.text
ENTRY_POINT(ebb_handler)
stdu r1,-STACK_FRAME(r1)
SAVE_GPR(0)
mflr r0
std r0,LR_SAVE(r1)
mfcr r0
std r0,CCR_SAVE(r1)
mfctr r0
std r0,CTR_SAVE(r1)
mfxer r0
std r0,XER_SAVE(r1)
SAVE_GPR(2)
SAVE_GPR(3)
SAVE_GPR(4)
SAVE_GPR(5)
SAVE_GPR(6)
SAVE_GPR(7)
SAVE_GPR(8)
SAVE_GPR(9)
SAVE_GPR(10)
SAVE_GPR(11)
SAVE_GPR(12)
SAVE_GPR(13)
SAVE_GPR(14)
SAVE_GPR(15)
SAVE_GPR(16)
SAVE_GPR(17)
SAVE_GPR(18)
SAVE_GPR(19)
SAVE_GPR(20)
SAVE_GPR(21)
SAVE_GPR(22)
SAVE_GPR(23)
SAVE_GPR(24)
SAVE_GPR(25)
SAVE_GPR(26)
SAVE_GPR(27)
SAVE_GPR(28)
SAVE_GPR(29)
SAVE_GPR(30)
SAVE_GPR(31)
SAVE_VSR(0, r3)
mffs f0
stfd f0, FSCR_SAVE(r1)
mfvscr f0
stfd f0, VSCR_SAVE(r1)
SAVE_VSR(1, r3)
SAVE_VSR(2, r3)
SAVE_VSR(3, r3)
SAVE_VSR(4, r3)
SAVE_VSR(5, r3)
SAVE_VSR(6, r3)
SAVE_VSR(7, r3)
SAVE_VSR(8, r3)
SAVE_VSR(9, r3)
SAVE_VSR(10, r3)
SAVE_VSR(11, r3)
SAVE_VSR(12, r3)
SAVE_VSR(13, r3)
SAVE_VSR(14, r3)
SAVE_VSR(15, r3)
SAVE_VSR(16, r3)
SAVE_VSR(17, r3)
SAVE_VSR(18, r3)
SAVE_VSR(19, r3)
SAVE_VSR(20, r3)
SAVE_VSR(21, r3)
SAVE_VSR(22, r3)
SAVE_VSR(23, r3)
SAVE_VSR(24, r3)
SAVE_VSR(25, r3)
SAVE_VSR(26, r3)
SAVE_VSR(27, r3)
SAVE_VSR(28, r3)
SAVE_VSR(29, r3)
SAVE_VSR(30, r3)
SAVE_VSR(31, r3)
SAVE_VSR(32, r3)
SAVE_VSR(33, r3)
SAVE_VSR(34, r3)
SAVE_VSR(35, r3)
SAVE_VSR(36, r3)
SAVE_VSR(37, r3)
SAVE_VSR(38, r3)
SAVE_VSR(39, r3)
SAVE_VSR(40, r3)
SAVE_VSR(41, r3)
SAVE_VSR(42, r3)
SAVE_VSR(43, r3)
SAVE_VSR(44, r3)
SAVE_VSR(45, r3)
SAVE_VSR(46, r3)
SAVE_VSR(47, r3)
SAVE_VSR(48, r3)
SAVE_VSR(49, r3)
SAVE_VSR(50, r3)
SAVE_VSR(51, r3)
SAVE_VSR(52, r3)
SAVE_VSR(53, r3)
SAVE_VSR(54, r3)
SAVE_VSR(55, r3)
SAVE_VSR(56, r3)
SAVE_VSR(57, r3)
SAVE_VSR(58, r3)
SAVE_VSR(59, r3)
SAVE_VSR(60, r3)
SAVE_VSR(61, r3)
SAVE_VSR(62, r3)
SAVE_VSR(63, r3)
TRASH_GPR(2)
TRASH_GPR(3)
TRASH_GPR(4)
TRASH_GPR(5)
TRASH_GPR(6)
TRASH_GPR(7)
TRASH_GPR(8)
TRASH_GPR(9)
TRASH_GPR(10)
TRASH_GPR(11)
TRASH_GPR(12)
TRASH_GPR(14)
TRASH_GPR(15)
TRASH_GPR(16)
TRASH_GPR(17)
TRASH_GPR(18)
TRASH_GPR(19)
TRASH_GPR(20)
TRASH_GPR(21)
TRASH_GPR(22)
TRASH_GPR(23)
TRASH_GPR(24)
TRASH_GPR(25)
TRASH_GPR(26)
TRASH_GPR(27)
TRASH_GPR(28)
TRASH_GPR(29)
TRASH_GPR(30)
TRASH_GPR(31)
RESTORE_TOC(ebb_handler)
/*
* r13 is our TLS pointer. We leave whatever value was in there when the
* EBB fired. That seems to be OK because once set the TLS pointer is not
* changed - but presumably that could change in future.
*/
bl ebb_hook
nop
/* r2 may be changed here but we don't care */
lfd f0, FSCR_SAVE(r1)
mtfsf 0xff,f0
lfd f0, VSCR_SAVE(r1)
mtvscr f0
LOAD_VSR(0, r3)
LOAD_VSR(1, r3)
LOAD_VSR(2, r3)
LOAD_VSR(3, r3)
LOAD_VSR(4, r3)
LOAD_VSR(5, r3)
LOAD_VSR(6, r3)
LOAD_VSR(7, r3)
LOAD_VSR(8, r3)
LOAD_VSR(9, r3)
LOAD_VSR(10, r3)
LOAD_VSR(11, r3)
LOAD_VSR(12, r3)
LOAD_VSR(13, r3)
LOAD_VSR(14, r3)
LOAD_VSR(15, r3)
LOAD_VSR(16, r3)
LOAD_VSR(17, r3)
LOAD_VSR(18, r3)
LOAD_VSR(19, r3)
LOAD_VSR(20, r3)
LOAD_VSR(21, r3)
LOAD_VSR(22, r3)
LOAD_VSR(23, r3)
LOAD_VSR(24, r3)
LOAD_VSR(25, r3)
LOAD_VSR(26, r3)
LOAD_VSR(27, r3)
LOAD_VSR(28, r3)
LOAD_VSR(29, r3)
LOAD_VSR(30, r3)
LOAD_VSR(31, r3)
LOAD_VSR(32, r3)
LOAD_VSR(33, r3)
LOAD_VSR(34, r3)
LOAD_VSR(35, r3)
LOAD_VSR(36, r3)
LOAD_VSR(37, r3)
LOAD_VSR(38, r3)
LOAD_VSR(39, r3)
LOAD_VSR(40, r3)
LOAD_VSR(41, r3)
LOAD_VSR(42, r3)
LOAD_VSR(43, r3)
LOAD_VSR(44, r3)
LOAD_VSR(45, r3)
LOAD_VSR(46, r3)
LOAD_VSR(47, r3)
LOAD_VSR(48, r3)
LOAD_VSR(49, r3)
LOAD_VSR(50, r3)
LOAD_VSR(51, r3)
LOAD_VSR(52, r3)
LOAD_VSR(53, r3)
LOAD_VSR(54, r3)
LOAD_VSR(55, r3)
LOAD_VSR(56, r3)
LOAD_VSR(57, r3)
LOAD_VSR(58, r3)
LOAD_VSR(59, r3)
LOAD_VSR(60, r3)
LOAD_VSR(61, r3)
LOAD_VSR(62, r3)
LOAD_VSR(63, r3)
ld r0,XER_SAVE(r1)
mtxer r0
ld r0,CTR_SAVE(r1)
mtctr r0
ld r0,LR_SAVE(r1)
mtlr r0
ld r0,CCR_SAVE(r1)
mtcr r0
REST_GPR(0)
REST_GPR(2)
REST_GPR(3)
REST_GPR(4)
REST_GPR(5)
REST_GPR(6)
REST_GPR(7)
REST_GPR(8)
REST_GPR(9)
REST_GPR(10)
REST_GPR(11)
REST_GPR(12)
REST_GPR(13)
REST_GPR(14)
REST_GPR(15)
REST_GPR(16)
REST_GPR(17)
REST_GPR(18)
REST_GPR(19)
REST_GPR(20)
REST_GPR(21)
REST_GPR(22)
REST_GPR(23)
REST_GPR(24)
REST_GPR(25)
REST_GPR(26)
REST_GPR(27)
REST_GPR(28)
REST_GPR(29)
REST_GPR(30)
REST_GPR(31)
addi r1,r1,STACK_FRAME
RFEBB
FUNC_END(ebb_handler)
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file startup_stm32f303xc.s
* @author MCD Application Team
* @version V1.1.0
* @date 12-Sept-2014
* @brief STM32F303xB/STM32F303xC devices vector table for Atollic
* TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
//bl __libc_init_array
/* Call the application's entry point.*/
//bl main
/**
* Calling the crt0 'cold-start' entry point. There __libc_init_array is called
* and when existing hardware_init_hook() and software_init_hook() before
* starting main(). software_init_hook() is available and has to be called due
* to initializsation when using rtos.
*/
bl _start
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TSC_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN_TX_IRQHandler
.word USB_LP_CAN_RX0_IRQHandler
.word CAN_RX1_IRQHandler
.word CAN_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TSC_IRQHandler
.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN_TX_IRQHandler
.thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN_RX0_IRQHandler
.thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
.weak CAN_RX1_IRQHandler
.thumb_set CAN_RX1_IRQHandler,Default_Handler
.weak CAN_SCE_IRQHandler
.thumb_set CAN_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
0
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0 | {
"language": "Assembly"
} |
/////////////////////////////////////////////////
// 120|-[ModBot]-V0.5 //
/////////////////////////////////////////////////
#include "Inc.h"
#include "Fun.h"
#include "Ext.h"
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
#define _CRC32_(crc, ch) (crc = (crc >> 8) ^ crc32tab[(crc ^ (ch)) & 0xff])
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
static const unsigned long crc32tab[256] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
};
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
unsigned long crc32(char *buf, size_t size)
{
unsigned long crc = (unsigned long)~0;
char *p;
size_t len = 0, nr = size;
for (len += nr, p = buf; nr--; ++p)
_CRC32_(crc, *p);
return ~crc;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
unsigned long crc32f(char *file)
{
long pos=0; unsigned long rval;
char *rbuf=(char *)malloc(0);
FILE *f_crc;
if((f_crc=fopen(file,"rb")) == NULL)
return 0;
while(!feof(f_crc)) {
rbuf=(char*)realloc(rbuf,++pos);
if(rbuf==NULL)
return 0;
fread(&rbuf[pos-1],1,1,f_crc);
}
rval=crc32(rbuf,pos-1);
free(rbuf);
fclose(f_crc);
return rval;
}
/////////////////////////////////////////////////
// 120|-[ModBot]-V0.5 //
///////////////////////////////////////////////// | {
"language": "Assembly"
} |
# arm testcase for cmn $rd,$rs
# mach: unfinished
.include "testutils.inc"
start
.global alu_cmn
alu_cmn:
cmn r0,r0
pass
| {
"language": "Assembly"
} |
/*---------------------------------------------------------------------------------------------------------*/
/* Holtek Semiconductor Inc. */
/* */
/* Copyright (C) Holtek Semiconductor Inc. */
/* All rights reserved. */
/* */
/*-----------------------------------------------------------------------------------------------------------
; File Name : startup_ht32f5xxxx_gcc_03.s
; Version : $Rev:: 4143 $
; Date : $Date:: 2019-07-24 #$
; Description : Startup code.
;-----------------------------------------------------------------------------------------------------------*/
/*
; Supported Device
; ========================================
; HT32F0008
; HT32F52142
; HT32F52344, HT32F52354
; HT32F52357, HT32F52367
*/
;/* <<< Use Configuration Wizard in Context Menu >>> */
/*
;// <o> HT32 Device
;// <0=> By Project Asm Define
;// <6=> HT32F0008
;// <6=> HT32F52142
;// <9=> HT32F52344/54
;// <11=> HT32F52357/67
*/
.equ USE_HT32_CHIP_SET, 0
.equ _HT32FWID, 0xFFFFFFFF
/*
.equ _HT32FWID, 0x00000008
.equ _HT32FWID, 0x00052142
.equ _HT32FWID, 0x00052344
.equ _HT32FWID, 0x00052354
.equ _HT32FWID, 0x00052357
.equ _HT32FWID, 0x00052367
*/
.equ HT32F0008, 6
.equ HT32F52142, 6
.equ HT32F52344_54, 9
.equ HT32F52357_67, 11
.if USE_HT32_CHIP_SET == 0
.else
.equ USE_HT32_CHIP, USE_HT32_CHIP_SET
.endif
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
/* start address for the initialization values of the .data section. defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/*
; Amount of memory (in bytes) allocated for Stack and Heap
; Tailor those values to your application needs
;// <o> Stack Size (in Bytes, must 8 byte aligned) <:8>
*/
.equ Stack_Size, 512
.section ".stack", "w"
.align 3
.globl __StackTop
.globl __StackLimit
.globl __HT_check_sp
__HT_check_sp:
__StackLimit:
.if Stack_Size
.space Stack_Size
.endif
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
;// <o> Heap Size (in Bytes) <:8>
*/
.equ Heap_Size, 0
.section ".heap", "w"
.align 3
.globl __HeapBase
.globl _end
.globl __HeapLimit
.globl __HT_check_heap
__HT_check_heap:
__HeapBase:
_end:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.equ _RESERVED, 0xFFFFFFFF
/*
;*******************************************************************************
; Fill-up the Vector Table entries with the exceptions ISR address
;********************************************************************************/
.section .isr_vector,"a",%progbits
.global __interrupt_vector_cortex_m
.type __interrupt_vector_cortex_m, %object
__interrupt_vector_cortex_m:
.long __StackTop /* ---, 00, 0x000, Top address of Stack */
.long Reset_Handler /* ---, 01, 0x004, Reset Handler */
.long NMI_Handler /* -14, 02, 0x008, NMI Handler */
.long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */
.long _RESERVED /* ---, 04, 0x010, Reserved */
.long _RESERVED /* ---, 05, 0x014, Reserved */
.long _RESERVED /* ---, 06, 0x018, Reserved */
.long _RESERVED /* ---, 07, 0x01C, Reserved */
.long _HT32FWID /* ---, 08, 0x020, Reserved */
.long _RESERVED /* ---, 09, 0x024, Reserved */
.long _RESERVED /* ---, 10, 0x028, Reserved */
.long SVC_Handler /* -05, 11, 0x02C, SVC Handler */
.long _RESERVED /* ---, 12, 0x030, Reserved */
.long _RESERVED /* ---, 13, 0x034, Reserved */
.long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */
.long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */
/* External Interrupt Handler */
.long LVD_BOD_IRQHandler /* 00, 16, 0x040, */
.long RTC_IRQHandler /* 01, 17, 0x044, */
.long FLASH_IRQHandler /* 02, 18, 0x048, */
.long EVWUP_IRQHandler /* 03, 19, 0x04C, */
.long EXTI0_1_IRQHandler /* 04, 20, 0x050, */
.long EXTI2_3_IRQHandler /* 05, 21, 0x054, */
.long EXTI4_15_IRQHandler /* 06, 22, 0x058, */
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 07, 23, 0x05C, */
.endif
.if (USE_HT32_CHIP==HT32F52344_54)
.long COMP_IRQHandler /* 07, 23, 0x05C, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */
.endif
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 08, 24, 0x060, */
.else
.long ADC_IRQHandler /* 08, 24, 0x060, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long AES_IRQHandler /* 09, 25, 0x064, */
.else
.long _RESERVED /* 09, 25, 0x064, */
.endif
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 10, 26, 0x068, */
.else
.long MCTM0_IRQHandler /* 10, 26, 0x068, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long QSPI_IRQHandler /* 11, 27, 0x06C, */
.else
.long _RESERVED /* 11, 27, 0x06C, */
.endif
.long GPTM0_IRQHandler /* 12, 28, 0x070, */
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 13, 29, 0x074, */
.long _RESERVED /* 14, 30, 0x078, */
.else
.long SCTM0_IRQHandler /* 13, 29, 0x074, */
.long SCTM1_IRQHandler /* 14, 30, 0x078, */
.endif
.if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67)
.long PWM0_IRQHandler /* 15, 31, 0x07C, */
.long PWM1_IRQHandler /* 16, 32, 0x080, */
.endif
.if (USE_HT32_CHIP==HT32F52344_54)
.long _RESERVED /* 15, 31, 0x07C, */
.long _RESERVED /* 16, 32, 0x080, */
.endif
.long BFTM0_IRQHandler /* 17, 33, 0x084, */
.long BFTM1_IRQHandler /* 18, 34, 0x088, */
.long I2C0_IRQHandler /* 19, 35, 0x08C, */
.if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54)
.long _RESERVED /* 20, 36, 0x090, */
.else
.long I2C1_IRQHandler /* 20, 36, 0x090, */
.endif
.long SPI0_IRQHandler /* 21, 37, 0x094, */
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 22, 38, 0x098, */
.else
.long SPI1_IRQHandler /* 22, 38, 0x098, */
.endif
.if (USE_HT32_CHIP==HT32F52344_54)
.long _RESERVED /* 23, 39, 0x09C, */
.else
.long USART0_IRQHandler /* 23, 39, 0x09C, */
.endif
.if (USE_HT32_CHIP==HT32F0008)
.long _RESERVED /* 24, 40, 0x0A0, */
.long UART0_IRQHandler /* 25, 41, 0x0A4, */
.long _RESERVED /* 26, 42, 0x0A8, */
.endif
.if (USE_HT32_CHIP==HT32F52344_54)
.long _RESERVED /* 24, 40, 0x0A0, */
.long UART0_IRQHandler /* 25, 41, 0x0A4, */
.long UART1_IRQHandler /* 26, 42, 0x0A8, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long USART1_IRQHandler /* 24, 40, 0x0A0, */
.long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */
.long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long SCI_IRQHandler /* 27, 43, 0x0AC, */
.else
.long _RESERVED /* 27, 43, 0x0AC, */
.endif
.if (USE_HT32_CHIP==HT32F0008)
.long AES_IRQHandler /* 28, 44, 0x0B0, */
.endif
.if (USE_HT32_CHIP==HT32F52344_54)
.long _RESERVED /* 28, 44, 0x0B0, */
.endif
.if (USE_HT32_CHIP==HT32F52357_67)
.long I2S_IRQHandler /* 28, 44, 0x0B0, */
.endif
.long USB_IRQHandler /* 29, 45, 0x0B4, */
.long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */
.long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */
.size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m
.thumb
/* Reset Handler */
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
LDR R0, =__StackTop /* set stack pointer */
MOV SP, R0
LDR R0, =BootProcess
BLX R0
LDR R0, =SystemInit
BLX R0
/* Copy the data segment initializers from flash to SRAM */
MOVS R1, #0
B LoopCopyDataInit
CopyDataInit:
LDR R3, =_sidata
LDR R3, [R3, R1]
STR R3, [R0, R1]
ADDS R1, R1, #4
LoopCopyDataInit:
LDR R0, =_sdata
LDR R3, =_edata
ADDS R2, R0, R1
CMP R2, R3
BCC CopyDataInit
LDR R2, =_sbss
B LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
MOVS R3, #0
STR R3, [R2]
ADDS R2, R2, #4
LoopFillZerobss:
LDR R3, =_ebss
CMP R2, R3
BCC FillZerobss
/* Call static constructors */
BL __libc_init_array
/* Call the application's entry point.*/
BL main
LoopForever:
B LoopForever
.thumb_func
BootProcess:
LDR R0, =0x40080300
LDR R1,[R0, #0x10]
CMP R1, #0
BNE BP1
LDR R1,[R0, #0x14]
CMP R1, #0
BNE BP1
LDR R1,[R0, #0x18]
CMP R1, #0
BNE BP1
LDR R1,[R0, #0x1C]
CMP R1, #0
BEQ BP2
BP1:
LDR R0, =0x40080180
LDR R1,[R0, #0xC]
LSLS R1, R1, #4
LSRS R1, R1, #20
CMP R1, #0
BEQ BP3
CMP R1, #5
BEQ BP3
CMP R1, #6
BEQ BP3
BP2:
DSB
LDR R0, =0x20000000
LDR R1, =0x05fa0004
STR R1, [R0]
LDR R1, =0xe000ed00
LDR R0, =0x05fa0004
STR R0, [R1, #0xC]
DSB
B .
BP3:
LDR R0, =0x20000000
LDR R1, [R0]
LDR R0, =0x05fa0004
CMP R0, R1
BEQ BP4
BX LR
BP4:
LDR R0, =0x40088100
LDR R1, =0x00000001
STR R1, [R0]
LDR R0, =0x20000000
LDR R1, =0x0
STR R1, [R0]
BX LR
.size Reset_Handler, .-Reset_Handler
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ LVD_BOD_IRQHandler
IRQ RTC_IRQHandler
IRQ FLASH_IRQHandler
IRQ EVWUP_IRQHandler
IRQ EXTI0_1_IRQHandler
IRQ EXTI2_3_IRQHandler
IRQ EXTI4_15_IRQHandler
IRQ COMP_IRQHandler
IRQ COMP_DAC_IRQHandler
IRQ ADC_IRQHandler
IRQ MCTM0_IRQHandler
IRQ GPTM0_IRQHandler
IRQ SCTM0_IRQHandler
IRQ SCTM1_IRQHandler
IRQ PWM0_IRQHandler
IRQ PWM1_IRQHandler
IRQ BFTM0_IRQHandler
IRQ BFTM1_IRQHandler
IRQ I2C0_IRQHandler
IRQ I2C1_IRQHandler
IRQ SPI0_IRQHandler
IRQ SPI1_IRQHandler
IRQ QSPI_IRQHandler
IRQ USART0_IRQHandler
IRQ USART1_IRQHandler
IRQ UART0_IRQHandler
IRQ UART1_IRQHandler
IRQ UART0_UART2_IRQHandler
IRQ UART1_UART3_IRQHandler
IRQ SCI_IRQHandler
IRQ I2S_IRQHandler
IRQ AES_IRQHandler
IRQ USB_IRQHandler
IRQ PDMA_CH0_1_IRQHandler
IRQ PDMA_CH2_5_IRQHandler
.end
| {
"language": "Assembly"
} |
use PixelFont.GlyphSource
glyph_source NeoDGM.BitmapFont.PowerlineSymbols do
bmp_glyph unicode: 0xE0A0 do
advance 8
bounds 0..7, -4..12
data """
1100000
1100000
1100000
1100000
1100110
1101111
1100110
1100110
1100110
0000110
1111100
1100000
1100000
1100000
1100000
1100000
"""
end
bmp_glyph unicode: 0xE0A1 do
advance 8
bounds 1..7, -2..10
data """
110000
110000
110000
110000
111110
000000
000000
011110
011011
011011
011011
011011
"""
end
bmp_glyph unicode: 0xE0A2 do
advance 8
bounds 1..7, 0..8
data """
001100
010010
010010
111111
111111
111111
111111
111111
"""
end
bmp_glyph unicode: 0xE0B0 do
advance 8
bounds 0..8, -4..12
data """
10000000
11000000
11100000
11110000
11111000
11111100
11111110
11111111
11111111
11111110
11111100
11111000
11110000
11100000
11000000
10000000
"""
end
bmp_glyph unicode: 0xE0B1 do
advance 8
bounds 0..8, -4..12
data """
10000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
"""
end
bmp_glyph unicode: 0xE0B2 do
advance 8
bounds 0..8, -4..12
data """
00000001
00000011
00000111
00001111
00011111
00111111
01111111
11111111
11111111
01111111
00111111
00011111
00001111
00000111
00000011
00000001
"""
end
bmp_glyph unicode: 0xE0B3 do
advance 8
bounds 0..8, -4..12
data """
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
10000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001
"""
end
end
| {
"language": "Assembly"
} |
What: /config/pcie-gadget
Date: Feb 2011
KernelVersion: 2.6.37
Contact: Pratyush Anand <pratyush.anand@gmail.com>
Description:
Interface is used to configure selected dual mode PCIe controller
as device and then program its various registers to configure it
as a particular device type.
This interfaces can be used to show spear's PCIe device capability.
Nodes are only visible when configfs is mounted. To mount configfs
in /config directory use:
# mount -t configfs none /config/
For nth PCIe Device Controller
/config/pcie-gadget.n/
link ... used to enable ltssm and read its status.
int_type ...used to configure and read type of supported
interrupt
no_of_msi ... used to configure number of MSI vector needed and
to read no of MSI granted.
inta ... write 1 to assert INTA and 0 to de-assert.
send_msi ... write MSI vector to be sent.
vendor_id ... used to write and read vendor id (hex)
device_id ... used to write and read device id (hex)
bar0_size ... used to write and read bar0_size
bar0_address ... used to write and read bar0 mapped area in hex.
bar0_rw_offset ... used to write and read offset of bar0 where
bar0_data will be written or read.
bar0_data ... used to write and read data at bar0_rw_offset.
| {
"language": "Assembly"
} |
; RUN: llc < %s -march=x86 | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
; %0 must not be put in EAX or EDX.
; In the first asm, $0 and $2 must not be put in EAX.
; CHECK: InlineAsm Start
; CHECK-NOT: movl %eax, %eax
; CHECK-NOT: movl (%eax), %eax
; CHECK: InlineAsm End
; In the second asm, $0 and $2 must not be put in EDX.
; CHECK: InlineAsm Start
; CHECK-NOT: movl %edx, %edx
; CHECK-NOT: movl (%edx), %edx
; CHECK: InlineAsm End
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
@x = common global i32 0
define i32 @aci(i32* %pw) nounwind {
entry:
%0 = load i32* @x, align 4
%asmtmp = tail call { i32, i32 } asm "movl $0, %eax\0A\090:\0A\09test %eax, %eax\0A\09je 1f\0A\09movl %eax, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{ax},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind
%asmtmp2 = tail call { i32, i32 } asm "movl $0, %edx\0A\090:\0A\09test %edx, %edx\0A\09je 1f\0A\09movl %edx, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{dx},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind
%asmresult2 = extractvalue { i32, i32 } %asmtmp, 0
%asmresult3 = extractvalue { i32, i32 } %asmtmp2, 0
%1 = add i32 %asmresult2, %asmresult3
%2 = add i32 %0, %1
ret i32 %2
}
| {
"language": "Assembly"
} |
OPTION DOTNAME
.text$ SEGMENT ALIGN(256) 'CODE'
ALIGN 32
__KeccakF1600 PROC PRIVATE
mov rax,QWORD PTR[60+rdi]
mov rbx,QWORD PTR[68+rdi]
mov rcx,QWORD PTR[76+rdi]
mov rdx,QWORD PTR[84+rdi]
mov rbp,QWORD PTR[92+rdi]
jmp $L$oop
ALIGN 32
$L$oop::
mov r8,QWORD PTR[((-100))+rdi]
mov r9,QWORD PTR[((-52))+rdi]
mov r10,QWORD PTR[((-4))+rdi]
mov r11,QWORD PTR[44+rdi]
xor rcx,QWORD PTR[((-84))+rdi]
xor rdx,QWORD PTR[((-76))+rdi]
xor rax,r8
xor rbx,QWORD PTR[((-92))+rdi]
xor rcx,QWORD PTR[((-44))+rdi]
xor rax,QWORD PTR[((-60))+rdi]
mov r12,rbp
xor rbp,QWORD PTR[((-68))+rdi]
xor rcx,r10
xor rax,QWORD PTR[((-20))+rdi]
xor rdx,QWORD PTR[((-36))+rdi]
xor rbx,r9
xor rbp,QWORD PTR[((-28))+rdi]
xor rcx,QWORD PTR[36+rdi]
xor rax,QWORD PTR[20+rdi]
xor rdx,QWORD PTR[4+rdi]
xor rbx,QWORD PTR[((-12))+rdi]
xor rbp,QWORD PTR[12+rdi]
mov r13,rcx
rol rcx,1
xor rcx,rax
xor rdx,r11
rol rax,1
xor rax,rdx
xor rbx,QWORD PTR[28+rdi]
rol rdx,1
xor rdx,rbx
xor rbp,QWORD PTR[52+rdi]
rol rbx,1
xor rbx,rbp
rol rbp,1
xor rbp,r13
xor r9,rcx
xor r10,rdx
rol r9,44
xor r11,rbp
xor r12,rax
rol r10,43
xor r8,rbx
mov r13,r9
rol r11,21
or r9,r10
xor r9,r8
rol r12,14
xor r9,QWORD PTR[r15]
lea r15,QWORD PTR[8+r15]
mov r14,r12
and r12,r11
mov QWORD PTR[((-100))+rsi],r9
xor r12,r10
not r10
mov QWORD PTR[((-84))+rsi],r12
or r10,r11
mov r12,QWORD PTR[76+rdi]
xor r10,r13
mov QWORD PTR[((-92))+rsi],r10
and r13,r8
mov r9,QWORD PTR[((-28))+rdi]
xor r13,r14
mov r10,QWORD PTR[((-20))+rdi]
mov QWORD PTR[((-68))+rsi],r13
or r14,r8
mov r8,QWORD PTR[((-76))+rdi]
xor r14,r11
mov r11,QWORD PTR[28+rdi]
mov QWORD PTR[((-76))+rsi],r14
xor r8,rbp
xor r12,rdx
rol r8,28
xor r11,rcx
xor r9,rax
rol r12,61
rol r11,45
xor r10,rbx
rol r9,20
mov r13,r8
or r8,r12
rol r10,3
xor r8,r11
mov QWORD PTR[((-36))+rsi],r8
mov r14,r9
and r9,r13
mov r8,QWORD PTR[((-92))+rdi]
xor r9,r12
not r12
mov QWORD PTR[((-28))+rsi],r9
or r12,r11
mov r9,QWORD PTR[((-44))+rdi]
xor r12,r10
mov QWORD PTR[((-44))+rsi],r12
and r11,r10
mov r12,QWORD PTR[60+rdi]
xor r11,r14
mov QWORD PTR[((-52))+rsi],r11
or r14,r10
mov r10,QWORD PTR[4+rdi]
xor r14,r13
mov r11,QWORD PTR[52+rdi]
mov QWORD PTR[((-60))+rsi],r14
xor r10,rbp
xor r11,rax
rol r10,25
xor r9,rdx
rol r11,8
xor r12,rbx
rol r9,6
xor r8,rcx
rol r12,18
mov r13,r10
and r10,r11
rol r8,1
not r11
xor r10,r9
mov QWORD PTR[((-12))+rsi],r10
mov r14,r12
and r12,r11
mov r10,QWORD PTR[((-12))+rdi]
xor r12,r13
mov QWORD PTR[((-4))+rsi],r12
or r13,r9
mov r12,QWORD PTR[84+rdi]
xor r13,r8
mov QWORD PTR[((-20))+rsi],r13
and r9,r8
xor r9,r14
mov QWORD PTR[12+rsi],r9
or r14,r8
mov r9,QWORD PTR[((-60))+rdi]
xor r14,r11
mov r11,QWORD PTR[36+rdi]
mov QWORD PTR[4+rsi],r14
mov r8,QWORD PTR[((-68))+rdi]
xor r10,rcx
xor r11,rdx
rol r10,10
xor r9,rbx
rol r11,15
xor r12,rbp
rol r9,36
xor r8,rax
rol r12,56
mov r13,r10
or r10,r11
rol r8,27
not r11
xor r10,r9
mov QWORD PTR[28+rsi],r10
mov r14,r12
or r12,r11
xor r12,r13
mov QWORD PTR[36+rsi],r12
and r13,r9
xor r13,r8
mov QWORD PTR[20+rsi],r13
or r9,r8
xor r9,r14
mov QWORD PTR[52+rsi],r9
and r8,r14
xor r8,r11
mov QWORD PTR[44+rsi],r8
xor rdx,QWORD PTR[((-84))+rdi]
xor rbp,QWORD PTR[((-36))+rdi]
rol rdx,62
xor rcx,QWORD PTR[68+rdi]
rol rbp,55
xor rax,QWORD PTR[12+rdi]
rol rcx,2
xor rbx,QWORD PTR[20+rdi]
xchg rdi,rsi
rol rax,39
rol rbx,41
mov r13,rdx
and rdx,rbp
not rbp
xor rdx,rcx
mov QWORD PTR[92+rdi],rdx
mov r14,rax
and rax,rbp
xor rax,r13
mov QWORD PTR[60+rdi],rax
or r13,rcx
xor r13,rbx
mov QWORD PTR[84+rdi],r13
and rcx,rbx
xor rcx,r14
mov QWORD PTR[76+rdi],rcx
or rbx,r14
xor rbx,rbp
mov QWORD PTR[68+rdi],rbx
mov rbp,rdx
mov rdx,r13
test r15,255
jnz $L$oop
lea r15,QWORD PTR[((-192))+r15]
DB 0F3h,0C3h ;repret
__KeccakF1600 ENDP
ALIGN 32
KeccakF1600 PROC PRIVATE
push rbx
push rbp
push r12
push r13
push r14
push r15
lea rdi,QWORD PTR[100+rdi]
sub rsp,200
not QWORD PTR[((-92))+rdi]
not QWORD PTR[((-84))+rdi]
not QWORD PTR[((-36))+rdi]
not QWORD PTR[((-4))+rdi]
not QWORD PTR[36+rdi]
not QWORD PTR[60+rdi]
lea r15,QWORD PTR[iotas]
lea rsi,QWORD PTR[100+rsp]
call __KeccakF1600
not QWORD PTR[((-92))+rdi]
not QWORD PTR[((-84))+rdi]
not QWORD PTR[((-36))+rdi]
not QWORD PTR[((-4))+rdi]
not QWORD PTR[36+rdi]
not QWORD PTR[60+rdi]
lea rdi,QWORD PTR[((-100))+rdi]
add rsp,200
pop r15
pop r14
pop r13
pop r12
pop rbp
pop rbx
DB 0F3h,0C3h ;repret
KeccakF1600 ENDP
PUBLIC SHA3_absorb
ALIGN 32
SHA3_absorb PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_SHA3_absorb::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
push rbx
push rbp
push r12
push r13
push r14
push r15
lea rdi,QWORD PTR[100+rdi]
sub rsp,232
mov r9,rsi
lea rsi,QWORD PTR[100+rsp]
not QWORD PTR[((-92))+rdi]
not QWORD PTR[((-84))+rdi]
not QWORD PTR[((-36))+rdi]
not QWORD PTR[((-4))+rdi]
not QWORD PTR[36+rdi]
not QWORD PTR[60+rdi]
lea r15,QWORD PTR[iotas]
mov QWORD PTR[((216-100))+rsi],rcx
$L$oop_absorb::
cmp rdx,rcx
jc $L$done_absorb
shr rcx,3
lea r8,QWORD PTR[((-100))+rdi]
$L$block_absorb::
mov rax,QWORD PTR[r9]
lea r9,QWORD PTR[8+r9]
xor rax,QWORD PTR[r8]
lea r8,QWORD PTR[8+r8]
sub rdx,8
mov QWORD PTR[((-8))+r8],rax
sub rcx,1
jnz $L$block_absorb
mov QWORD PTR[((200-100))+rsi],r9
mov QWORD PTR[((208-100))+rsi],rdx
call __KeccakF1600
mov r9,QWORD PTR[((200-100))+rsi]
mov rdx,QWORD PTR[((208-100))+rsi]
mov rcx,QWORD PTR[((216-100))+rsi]
jmp $L$oop_absorb
ALIGN 32
$L$done_absorb::
mov rax,rdx
not QWORD PTR[((-92))+rdi]
not QWORD PTR[((-84))+rdi]
not QWORD PTR[((-36))+rdi]
not QWORD PTR[((-4))+rdi]
not QWORD PTR[36+rdi]
not QWORD PTR[60+rdi]
add rsp,232
pop r15
pop r14
pop r13
pop r12
pop rbp
pop rbx
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_SHA3_absorb::
SHA3_absorb ENDP
PUBLIC SHA3_squeeze
ALIGN 32
SHA3_squeeze PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_SHA3_squeeze::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
push r12
push r13
push r14
shr rcx,3
mov r8,rdi
mov r12,rsi
mov r13,rdx
mov r14,rcx
jmp $L$oop_squeeze
ALIGN 32
$L$oop_squeeze::
cmp r13,8
jb $L$tail_squeeze
mov rax,QWORD PTR[r8]
lea r8,QWORD PTR[8+r8]
mov QWORD PTR[r12],rax
lea r12,QWORD PTR[8+r12]
sub r13,8
jz $L$done_squeeze
sub rcx,1
jnz $L$oop_squeeze
call KeccakF1600
mov r8,rdi
mov rcx,r14
jmp $L$oop_squeeze
$L$tail_squeeze::
mov rsi,r8
mov rdi,r12
mov rcx,r13
DB 0f3h,0a4h
$L$done_squeeze::
pop r14
pop r13
pop r12
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_SHA3_squeeze::
SHA3_squeeze ENDP
ALIGN 256
DQ 0,0,0,0,0,0,0,0
iotas::
DQ 00000000000000001h
DQ 00000000000008082h
DQ 0800000000000808ah
DQ 08000000080008000h
DQ 0000000000000808bh
DQ 00000000080000001h
DQ 08000000080008081h
DQ 08000000000008009h
DQ 0000000000000008ah
DQ 00000000000000088h
DQ 00000000080008009h
DQ 0000000008000000ah
DQ 0000000008000808bh
DQ 0800000000000008bh
DQ 08000000000008089h
DQ 08000000000008003h
DQ 08000000000008002h
DQ 08000000000000080h
DQ 0000000000000800ah
DQ 0800000008000000ah
DQ 08000000080008081h
DQ 08000000000008080h
DQ 00000000080000001h
DQ 08000000080008008h
DB 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111
DB 114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102
DB 111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84
DB 79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64
DB 111,112,101,110,115,115,108,46,111,114,103,62,0
.text$ ENDS
END
| {
"language": "Assembly"
} |
---
layout: page
title: "Q39235: An Example of Declaring a Communal Variable of a Record Type"
permalink: /pubs/pc/reference/microsoft/kb/Q39235/
---
## Q39235: An Example of Declaring a Communal Variable of a Record Type
Article: Q39235
Version(s): 5.00 5.10 | 5.10
Operating System: MS-DOS | OS/2
Flags: ENDUSER |
Last Modified: 12-JAN-1989
Question :
How can I declare a communal variable that has a record type?
Response:
Declare the variable with the size matching the size of the record
type defined in the same source file. There is no need to specify that
the variable has the predefined record type.
The following sample program demonstrates this information:
; module 1
.model small
dosseg
extrn proc2:proc
.stack 100h
.data
color record blink:1, back:3, intense:1, fore:3
comm near pixel:byte ; use "byte" because
; color has size byte.
.code
start: mov ax, @data
mov ds, ax
mov pixel, color <1,2,1,3> ; now the variable pixel
; should have the value "abh",
; which matches the
; pattern 1,010,1,011
call proc2
mov ax, 4c00h
int 21h
end start
******************************
; module 2
.model small
dosseg
.stack 100h
.data
color record blink:1, back:3, intense:1, fore:3
comm near pixel:byte
.code
public proc2
proc2 proc
mov ah, 0
mov ah, pixel ; ah should have the value "abh"
ret
proc2 endp
end
| {
"language": "Assembly"
} |
#if defined(__x86_64__)
.text
.p2align 4
_vpaes_encrypt_core:
movq %rdx,%r9
movq $16,%r11
movl 240(%rdx),%eax
movdqa %xmm9,%xmm1
movdqa L$k_ipt(%rip),%xmm2
pandn %xmm0,%xmm1
movdqu (%r9),%xmm5
psrld $4,%xmm1
pand %xmm9,%xmm0
.byte 102,15,56,0,208
movdqa L$k_ipt+16(%rip),%xmm0
.byte 102,15,56,0,193
pxor %xmm5,%xmm2
addq $16,%r9
pxor %xmm2,%xmm0
leaq L$k_mc_backward(%rip),%r10
jmp L$enc_entry
.p2align 4
L$enc_loop:
movdqa %xmm13,%xmm4
movdqa %xmm12,%xmm0
.byte 102,15,56,0,226
.byte 102,15,56,0,195
pxor %xmm5,%xmm4
movdqa %xmm15,%xmm5
pxor %xmm4,%xmm0
movdqa -64(%r11,%r10,1),%xmm1
.byte 102,15,56,0,234
movdqa (%r11,%r10,1),%xmm4
movdqa %xmm14,%xmm2
.byte 102,15,56,0,211
movdqa %xmm0,%xmm3
pxor %xmm5,%xmm2
.byte 102,15,56,0,193
addq $16,%r9
pxor %xmm2,%xmm0
.byte 102,15,56,0,220
addq $16,%r11
pxor %xmm0,%xmm3
.byte 102,15,56,0,193
andq $0x30,%r11
subq $1,%rax
pxor %xmm3,%xmm0
L$enc_entry:
movdqa %xmm9,%xmm1
movdqa %xmm11,%xmm5
pandn %xmm0,%xmm1
psrld $4,%xmm1
pand %xmm9,%xmm0
.byte 102,15,56,0,232
movdqa %xmm10,%xmm3
pxor %xmm1,%xmm0
.byte 102,15,56,0,217
movdqa %xmm10,%xmm4
pxor %xmm5,%xmm3
.byte 102,15,56,0,224
movdqa %xmm10,%xmm2
pxor %xmm5,%xmm4
.byte 102,15,56,0,211
movdqa %xmm10,%xmm3
pxor %xmm0,%xmm2
.byte 102,15,56,0,220
movdqu (%r9),%xmm5
pxor %xmm1,%xmm3
jnz L$enc_loop
movdqa -96(%r10),%xmm4
movdqa -80(%r10),%xmm0
.byte 102,15,56,0,226
pxor %xmm5,%xmm4
.byte 102,15,56,0,195
movdqa 64(%r11,%r10,1),%xmm1
pxor %xmm4,%xmm0
.byte 102,15,56,0,193
.byte 0xf3,0xc3
.p2align 4
_vpaes_decrypt_core:
movq %rdx,%r9
movl 240(%rdx),%eax
movdqa %xmm9,%xmm1
movdqa L$k_dipt(%rip),%xmm2
pandn %xmm0,%xmm1
movq %rax,%r11
psrld $4,%xmm1
movdqu (%r9),%xmm5
shlq $4,%r11
pand %xmm9,%xmm0
.byte 102,15,56,0,208
movdqa L$k_dipt+16(%rip),%xmm0
xorq $0x30,%r11
leaq L$k_dsbd(%rip),%r10
.byte 102,15,56,0,193
andq $0x30,%r11
pxor %xmm5,%xmm2
movdqa L$k_mc_forward+48(%rip),%xmm5
pxor %xmm2,%xmm0
addq $16,%r9
addq %r10,%r11
jmp L$dec_entry
.p2align 4
L$dec_loop:
movdqa -32(%r10),%xmm4
movdqa -16(%r10),%xmm1
.byte 102,15,56,0,226
.byte 102,15,56,0,203
pxor %xmm4,%xmm0
movdqa 0(%r10),%xmm4
pxor %xmm1,%xmm0
movdqa 16(%r10),%xmm1
.byte 102,15,56,0,226
.byte 102,15,56,0,197
.byte 102,15,56,0,203
pxor %xmm4,%xmm0
movdqa 32(%r10),%xmm4
pxor %xmm1,%xmm0
movdqa 48(%r10),%xmm1
.byte 102,15,56,0,226
.byte 102,15,56,0,197
.byte 102,15,56,0,203
pxor %xmm4,%xmm0
movdqa 64(%r10),%xmm4
pxor %xmm1,%xmm0
movdqa 80(%r10),%xmm1
.byte 102,15,56,0,226
.byte 102,15,56,0,197
.byte 102,15,56,0,203
pxor %xmm4,%xmm0
addq $16,%r9
.byte 102,15,58,15,237,12
pxor %xmm1,%xmm0
subq $1,%rax
L$dec_entry:
movdqa %xmm9,%xmm1
pandn %xmm0,%xmm1
movdqa %xmm11,%xmm2
psrld $4,%xmm1
pand %xmm9,%xmm0
.byte 102,15,56,0,208
movdqa %xmm10,%xmm3
pxor %xmm1,%xmm0
.byte 102,15,56,0,217
movdqa %xmm10,%xmm4
pxor %xmm2,%xmm3
.byte 102,15,56,0,224
pxor %xmm2,%xmm4
movdqa %xmm10,%xmm2
.byte 102,15,56,0,211
movdqa %xmm10,%xmm3
pxor %xmm0,%xmm2
.byte 102,15,56,0,220
movdqu (%r9),%xmm0
pxor %xmm1,%xmm3
jnz L$dec_loop
movdqa 96(%r10),%xmm4
.byte 102,15,56,0,226
pxor %xmm0,%xmm4
movdqa 112(%r10),%xmm0
movdqa -352(%r11),%xmm2
.byte 102,15,56,0,195
pxor %xmm4,%xmm0
.byte 102,15,56,0,194
.byte 0xf3,0xc3
.p2align 4
_vpaes_schedule_core:
call _vpaes_preheat
movdqa L$k_rcon(%rip),%xmm8
movdqu (%rdi),%xmm0
movdqa %xmm0,%xmm3
leaq L$k_ipt(%rip),%r11
call _vpaes_schedule_transform
movdqa %xmm0,%xmm7
leaq L$k_sr(%rip),%r10
testq %rcx,%rcx
jnz L$schedule_am_decrypting
movdqu %xmm0,(%rdx)
jmp L$schedule_go
L$schedule_am_decrypting:
movdqa (%r8,%r10,1),%xmm1
.byte 102,15,56,0,217
movdqu %xmm3,(%rdx)
xorq $0x30,%r8
L$schedule_go:
cmpl $192,%esi
ja L$schedule_256
je L$schedule_192
L$schedule_128:
movl $10,%esi
L$oop_schedule_128:
call _vpaes_schedule_round
decq %rsi
jz L$schedule_mangle_last
call _vpaes_schedule_mangle
jmp L$oop_schedule_128
.p2align 4
L$schedule_192:
movdqu 8(%rdi),%xmm0
call _vpaes_schedule_transform
movdqa %xmm0,%xmm6
pxor %xmm4,%xmm4
movhlps %xmm4,%xmm6
movl $4,%esi
L$oop_schedule_192:
call _vpaes_schedule_round
.byte 102,15,58,15,198,8
call _vpaes_schedule_mangle
call _vpaes_schedule_192_smear
call _vpaes_schedule_mangle
call _vpaes_schedule_round
decq %rsi
jz L$schedule_mangle_last
call _vpaes_schedule_mangle
call _vpaes_schedule_192_smear
jmp L$oop_schedule_192
.p2align 4
L$schedule_256:
movdqu 16(%rdi),%xmm0
call _vpaes_schedule_transform
movl $7,%esi
L$oop_schedule_256:
call _vpaes_schedule_mangle
movdqa %xmm0,%xmm6
call _vpaes_schedule_round
decq %rsi
jz L$schedule_mangle_last
call _vpaes_schedule_mangle
pshufd $0xFF,%xmm0,%xmm0
movdqa %xmm7,%xmm5
movdqa %xmm6,%xmm7
call _vpaes_schedule_low_round
movdqa %xmm5,%xmm7
jmp L$oop_schedule_256
.p2align 4
L$schedule_mangle_last:
leaq L$k_deskew(%rip),%r11
testq %rcx,%rcx
jnz L$schedule_mangle_last_dec
movdqa (%r8,%r10,1),%xmm1
.byte 102,15,56,0,193
leaq L$k_opt(%rip),%r11
addq $32,%rdx
L$schedule_mangle_last_dec:
addq $-16,%rdx
pxor L$k_s63(%rip),%xmm0
call _vpaes_schedule_transform
movdqu %xmm0,(%rdx)
pxor %xmm0,%xmm0
pxor %xmm1,%xmm1
pxor %xmm2,%xmm2
pxor %xmm3,%xmm3
pxor %xmm4,%xmm4
pxor %xmm5,%xmm5
pxor %xmm6,%xmm6
pxor %xmm7,%xmm7
.byte 0xf3,0xc3
.p2align 4
_vpaes_schedule_192_smear:
pshufd $0x80,%xmm6,%xmm1
pshufd $0xFE,%xmm7,%xmm0
pxor %xmm1,%xmm6
pxor %xmm1,%xmm1
pxor %xmm0,%xmm6
movdqa %xmm6,%xmm0
movhlps %xmm1,%xmm6
.byte 0xf3,0xc3
.p2align 4
_vpaes_schedule_round:
pxor %xmm1,%xmm1
.byte 102,65,15,58,15,200,15
.byte 102,69,15,58,15,192,15
pxor %xmm1,%xmm7
pshufd $0xFF,%xmm0,%xmm0
.byte 102,15,58,15,192,1
_vpaes_schedule_low_round:
movdqa %xmm7,%xmm1
pslldq $4,%xmm7
pxor %xmm1,%xmm7
movdqa %xmm7,%xmm1
pslldq $8,%xmm7
pxor %xmm1,%xmm7
pxor L$k_s63(%rip),%xmm7
movdqa %xmm9,%xmm1
pandn %xmm0,%xmm1
psrld $4,%xmm1
pand %xmm9,%xmm0
movdqa %xmm11,%xmm2
.byte 102,15,56,0,208
pxor %xmm1,%xmm0
movdqa %xmm10,%xmm3
.byte 102,15,56,0,217
pxor %xmm2,%xmm3
movdqa %xmm10,%xmm4
.byte 102,15,56,0,224
pxor %xmm2,%xmm4
movdqa %xmm10,%xmm2
.byte 102,15,56,0,211
pxor %xmm0,%xmm2
movdqa %xmm10,%xmm3
.byte 102,15,56,0,220
pxor %xmm1,%xmm3
movdqa %xmm13,%xmm4
.byte 102,15,56,0,226
movdqa %xmm12,%xmm0
.byte 102,15,56,0,195
pxor %xmm4,%xmm0
pxor %xmm7,%xmm0
movdqa %xmm0,%xmm7
.byte 0xf3,0xc3
.p2align 4
_vpaes_schedule_transform:
movdqa %xmm9,%xmm1
pandn %xmm0,%xmm1
psrld $4,%xmm1
pand %xmm9,%xmm0
movdqa (%r11),%xmm2
.byte 102,15,56,0,208
movdqa 16(%r11),%xmm0
.byte 102,15,56,0,193
pxor %xmm2,%xmm0
.byte 0xf3,0xc3
.p2align 4
_vpaes_schedule_mangle:
movdqa %xmm0,%xmm4
movdqa L$k_mc_forward(%rip),%xmm5
testq %rcx,%rcx
jnz L$schedule_mangle_dec
addq $16,%rdx
pxor L$k_s63(%rip),%xmm4
.byte 102,15,56,0,229
movdqa %xmm4,%xmm3
.byte 102,15,56,0,229
pxor %xmm4,%xmm3
.byte 102,15,56,0,229
pxor %xmm4,%xmm3
jmp L$schedule_mangle_both
.p2align 4
L$schedule_mangle_dec:
leaq L$k_dksd(%rip),%r11
movdqa %xmm9,%xmm1
pandn %xmm4,%xmm1
psrld $4,%xmm1
pand %xmm9,%xmm4
movdqa 0(%r11),%xmm2
.byte 102,15,56,0,212
movdqa 16(%r11),%xmm3
.byte 102,15,56,0,217
pxor %xmm2,%xmm3
.byte 102,15,56,0,221
movdqa 32(%r11),%xmm2
.byte 102,15,56,0,212
pxor %xmm3,%xmm2
movdqa 48(%r11),%xmm3
.byte 102,15,56,0,217
pxor %xmm2,%xmm3
.byte 102,15,56,0,221
movdqa 64(%r11),%xmm2
.byte 102,15,56,0,212
pxor %xmm3,%xmm2
movdqa 80(%r11),%xmm3
.byte 102,15,56,0,217
pxor %xmm2,%xmm3
.byte 102,15,56,0,221
movdqa 96(%r11),%xmm2
.byte 102,15,56,0,212
pxor %xmm3,%xmm2
movdqa 112(%r11),%xmm3
.byte 102,15,56,0,217
pxor %xmm2,%xmm3
addq $-16,%rdx
L$schedule_mangle_both:
movdqa (%r8,%r10,1),%xmm1
.byte 102,15,56,0,217
addq $-16,%r8
andq $0x30,%r8
movdqu %xmm3,(%rdx)
.byte 0xf3,0xc3
.globl _vpaes_set_encrypt_key
.private_extern _vpaes_set_encrypt_key
.p2align 4
_vpaes_set_encrypt_key:
movl %esi,%eax
shrl $5,%eax
addl $5,%eax
movl %eax,240(%rdx)
movl $0,%ecx
movl $0x30,%r8d
call _vpaes_schedule_core
xorl %eax,%eax
.byte 0xf3,0xc3
.globl _vpaes_set_decrypt_key
.private_extern _vpaes_set_decrypt_key
.p2align 4
_vpaes_set_decrypt_key:
movl %esi,%eax
shrl $5,%eax
addl $5,%eax
movl %eax,240(%rdx)
shll $4,%eax
leaq 16(%rdx,%rax,1),%rdx
movl $1,%ecx
movl %esi,%r8d
shrl $1,%r8d
andl $32,%r8d
xorl $32,%r8d
call _vpaes_schedule_core
xorl %eax,%eax
.byte 0xf3,0xc3
.globl _vpaes_encrypt
.private_extern _vpaes_encrypt
.p2align 4
_vpaes_encrypt:
movdqu (%rdi),%xmm0
call _vpaes_preheat
call _vpaes_encrypt_core
movdqu %xmm0,(%rsi)
.byte 0xf3,0xc3
.globl _vpaes_decrypt
.private_extern _vpaes_decrypt
.p2align 4
_vpaes_decrypt:
movdqu (%rdi),%xmm0
call _vpaes_preheat
call _vpaes_decrypt_core
movdqu %xmm0,(%rsi)
.byte 0xf3,0xc3
.globl _vpaes_cbc_encrypt
.private_extern _vpaes_cbc_encrypt
.p2align 4
_vpaes_cbc_encrypt:
xchgq %rcx,%rdx
subq $16,%rcx
jc L$cbc_abort
movdqu (%r8),%xmm6
subq %rdi,%rsi
call _vpaes_preheat
cmpl $0,%r9d
je L$cbc_dec_loop
jmp L$cbc_enc_loop
.p2align 4
L$cbc_enc_loop:
movdqu (%rdi),%xmm0
pxor %xmm6,%xmm0
call _vpaes_encrypt_core
movdqa %xmm0,%xmm6
movdqu %xmm0,(%rsi,%rdi,1)
leaq 16(%rdi),%rdi
subq $16,%rcx
jnc L$cbc_enc_loop
jmp L$cbc_done
.p2align 4
L$cbc_dec_loop:
movdqu (%rdi),%xmm0
movdqa %xmm0,%xmm7
call _vpaes_decrypt_core
pxor %xmm6,%xmm0
movdqa %xmm7,%xmm6
movdqu %xmm0,(%rsi,%rdi,1)
leaq 16(%rdi),%rdi
subq $16,%rcx
jnc L$cbc_dec_loop
L$cbc_done:
movdqu %xmm6,(%r8)
L$cbc_abort:
.byte 0xf3,0xc3
.p2align 4
_vpaes_preheat:
leaq L$k_s0F(%rip),%r10
movdqa -32(%r10),%xmm10
movdqa -16(%r10),%xmm11
movdqa 0(%r10),%xmm9
movdqa 48(%r10),%xmm13
movdqa 64(%r10),%xmm12
movdqa 80(%r10),%xmm15
movdqa 96(%r10),%xmm14
.byte 0xf3,0xc3
.p2align 6
_vpaes_consts:
L$k_inv:
.quad 0x0E05060F0D080180, 0x040703090A0B0C02
.quad 0x01040A060F0B0780, 0x030D0E0C02050809
L$k_s0F:
.quad 0x0F0F0F0F0F0F0F0F, 0x0F0F0F0F0F0F0F0F
L$k_ipt:
.quad 0xC2B2E8985A2A7000, 0xCABAE09052227808
.quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81
L$k_sb1:
.quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544
.quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF
L$k_sb2:
.quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD
.quad 0x69EB88400AE12900, 0xC2A163C8AB82234A
L$k_sbo:
.quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878
.quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA
L$k_mc_forward:
.quad 0x0407060500030201, 0x0C0F0E0D080B0A09
.quad 0x080B0A0904070605, 0x000302010C0F0E0D
.quad 0x0C0F0E0D080B0A09, 0x0407060500030201
.quad 0x000302010C0F0E0D, 0x080B0A0904070605
L$k_mc_backward:
.quad 0x0605040702010003, 0x0E0D0C0F0A09080B
.quad 0x020100030E0D0C0F, 0x0A09080B06050407
.quad 0x0E0D0C0F0A09080B, 0x0605040702010003
.quad 0x0A09080B06050407, 0x020100030E0D0C0F
L$k_sr:
.quad 0x0706050403020100, 0x0F0E0D0C0B0A0908
.quad 0x030E09040F0A0500, 0x0B06010C07020D08
.quad 0x0F060D040B020900, 0x070E050C030A0108
.quad 0x0B0E0104070A0D00, 0x0306090C0F020508
L$k_rcon:
.quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81
L$k_s63:
.quad 0x5B5B5B5B5B5B5B5B, 0x5B5B5B5B5B5B5B5B
L$k_opt:
.quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808
.quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0
L$k_deskew:
.quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A
.quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77
L$k_dksd:
.quad 0xFEB91A5DA3E44700, 0x0740E3A45A1DBEF9
.quad 0x41C277F4B5368300, 0x5FDC69EAAB289D1E
L$k_dksb:
.quad 0x9A4FCA1F8550D500, 0x03D653861CC94C99
.quad 0x115BEDA7B6FC4A00, 0xD993256F7E3482C8
L$k_dkse:
.quad 0xD5031CCA1FC9D600, 0x53859A4C994F5086
.quad 0xA23196054FDC7BE8, 0xCD5EF96A20B31487
L$k_dks9:
.quad 0xB6116FC87ED9A700, 0x4AED933482255BFC
.quad 0x4576516227143300, 0x8BB89FACE9DAFDCE
L$k_dipt:
.quad 0x0F505B040B545F00, 0x154A411E114E451A
.quad 0x86E383E660056500, 0x12771772F491F194
L$k_dsb9:
.quad 0x851C03539A86D600, 0xCAD51F504F994CC9
.quad 0xC03B1789ECD74900, 0x725E2C9EB2FBA565
L$k_dsbd:
.quad 0x7D57CCDFE6B1A200, 0xF56E9B13882A4439
.quad 0x3CE2FAF724C6CB00, 0x2931180D15DEEFD3
L$k_dsbb:
.quad 0xD022649296B44200, 0x602646F6B0F2D404
.quad 0xC19498A6CD596700, 0xF3FF0C3E3255AA6B
L$k_dsbe:
.quad 0x46F2929626D4D000, 0x2242600464B4F6B0
.quad 0x0C55A6CDFFAAC100, 0x9467F36B98593E32
L$k_dsbo:
.quad 0x1387EA537EF94000, 0xC7AA6DB9D4943E2D
.quad 0x12D7560F93441D00, 0xCA4B8159D8C58E9C
.byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,120,56,54,95,54,52,47,83,83,83,69,51,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0
.p2align 6
#endif
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file stm32l4xx_ll_fmc.c
* @author MCD Application Team
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
* + Initialization/de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### FMC peripheral features #####
==============================================================================
[..] The Flexible memory controller (FMC) includes following memory controllers:
(+) The NOR/PSRAM memory controller
(+) The NAND memory controller
[..] The FMC functional block makes the interface with synchronous and asynchronous static
memories. Its main purposes are:
(+) to translate AHB transactions into the appropriate external device protocol
(+) to meet the access time requirements of the external memory devices
[..] All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique Chip Select. The FMC performs
only one access at a time to an external device.
The main features of the FMC controller are the following:
(+) Interface with static-memory mapped devices including:
(++) Static random access memory (SRAM)
(++) Read-only memory (ROM)
(++) NOR Flash memory/OneNAND Flash memory
(++) PSRAM (4 memory banks)
(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
data
(+) Independent Chip Select control for each memory bank
(+) Independent configuration for each memory bank
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
* @{
*/
/* ----------------------- FMC registers bit mask --------------------------- */
#if defined(FMC_BANK1)
/* --- BCR Register ---*/
/* BCR register clear mask */
#if defined(FMC_BCRx_NBLSET)
#if defined(FMC_BCR1_WFDIS)
#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
FMC_BCRx_MTYP | FMC_BCRx_MWID |\
FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\
FMC_BCRx_NBLSET))
#else
#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
FMC_BCRx_MTYP | FMC_BCRx_MWID |\
FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
FMC_BCR1_CCLKEN | FMC_BCRx_NBLSET))
#endif /* FMC_BCR1_WFDIS */
#else
#if defined(FMC_BCR1_WFDIS)
#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
FMC_BCRx_MTYP | FMC_BCRx_MWID |\
FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS))
#else
#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
FMC_BCRx_MTYP | FMC_BCRx_MWID |\
FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
FMC_BCR1_CCLKEN))
#endif /* FMC_BCR1_WFDIS */
#endif /* FMC_BCRx_NBLSET */
/* --- BTR Register ---*/
/* BTR register clear mask */
#if defined(FMC_BTRx_DATAHLD)
#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
#else
#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
FMC_BTRx_ACCMOD))
#endif /* FMC_BTRx_DATAHLD */
/* --- BWTR Register ---*/
/* BWTR register clear mask */
#if defined(FMC_BWTRx_DATAHLD)
#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
#else
#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
FMC_BWTRx_ACCMOD))
#endif /* FMC_BWTRx_DATAHLD */
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/* --- PCR Register ---*/
/* PCR register clear mask */
#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
FMC_PCR_PTYP | FMC_PCR_PWID | \
FMC_PCR_ECCEN | FMC_PCR_TCLR | \
FMC_PCR_TAR | FMC_PCR_ECCPS))
/* --- PMEM Register ---*/
/* PMEM register clear mask */
#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
/* --- PATT Register ---*/
/* PATT register clear mask */
#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
#endif /* FMC_BANK3 */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
* @brief NORSRAM Controller functions
*
@verbatim
==============================================================================
##### How to use NORSRAM device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
to run the NORSRAM external devices.
(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
(+) FMC NORSRAM bank extended timing configuration using the function
FMC_NORSRAM_Extended_Timing_Init()
(+) FMC NORSRAM bank enable/disable write operation using the functions
FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
@endverbatim
* @{
*/
/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the FMC NORSRAM interface
(+) De-initialize the FMC NORSRAM interface
(+) Configure the FMC clock and associated GPIOs
@endverbatim
* @{
*/
/**
* @brief Initialize the FMC_NORSRAM device according to the specified
* control parameters in the FMC_NORSRAM_InitTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
assert_param(IS_FMC_MUX(Init->DataAddressMux));
assert_param(IS_FMC_MEMORY(Init->MemoryType));
assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
#if defined(FMC_BCR1_WFDIS)
assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
#endif /* FMC_BCR1_WFDIS */
assert_param(IS_FMC_PAGESIZE(Init->PageSize));
#if defined(FMC_BCRx_NBLSET)
assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
#endif /* FMC_BCRx_NBLSET */
/* Disable NORSRAM Device */
__FMC_NORSRAM_DISABLE(Device, Init->NSBank);
/* Set NORSRAM device control parameters */
if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
}
else
{
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess |
Init->DataAddressMux |
Init->MemoryType |
Init->MemoryDataWidth |
Init->BurstAccessMode |
Init->WaitSignalPolarity |
Init->WaitSignalActive |
Init->WriteOperation |
Init->WaitSignal |
Init->ExtendedMode |
Init->AsynchronousWait |
Init->WriteBurst |
Init->ContinuousClock |
#if defined(FMC_BCR1_WFDIS)
Init->WriteFifo |
#endif /* FMC_BCR1_WFDIS */
#if defined(FMC_BCRx_NBLSET)
Init->NBLSetupTime |
#endif /* FMC_BCRx_NBLSET */
Init->PageSize));
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
{
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
}
#if defined(FMC_BCR1_WFDIS)
if (Init->NSBank != FMC_NORSRAM_BANK1)
{
/* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
}
#endif /* FMC_BCR1_WFDIS */
return HAL_OK;
}
/**
* @brief DeInitialize the FMC_NORSRAM peripheral
* @param Device Pointer to NORSRAM device instance
* @param ExDevice Pointer to NORSRAM extended mode device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Disable the FMC_NORSRAM device */
__FMC_NORSRAM_DISABLE(Device, Bank);
/* De-initialize the FMC_NORSRAM device */
/* FMC_NORSRAM_BANK1 */
if (Bank == FMC_NORSRAM_BANK1)
{
Device->BTCR[Bank] = 0x000030DBU;
}
/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
else
{
Device->BTCR[Bank] = 0x000030D2U;
}
Device->BTCR[Bank + 1] = 0x0FFFFFFFU;
ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
return HAL_OK;
}
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Timing Pointer to NORSRAM Timing structure
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
#if defined(FMC_BTRx_DATAHLD)
assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
#endif /* FMC_BTRx_DATAHLD */
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set FMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
#if defined(FMC_BTRx_DATAHLD)
((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
#endif /* FMC_BTRx_DATAHLD */
((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2) << FMC_BTRx_DATLAT_Pos) |
(Timing->AccessMode)));
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos);
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
}
return HAL_OK;
}
/**
* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Timing Pointer to NORSRAM Timing structure
* @param Bank NORSRAM bank number
* @param ExtendedMode FMC Extended Mode
* This parameter can be one of the following values:
* @arg FMC_EXTENDED_MODE_DISABLE
* @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
#if defined(FMC_BTRx_DATAHLD)
assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
#endif /* FMC_BTRx_DATAHLD */
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
#if defined(FMC_BTRx_DATAHLD)
((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
#endif /* FMC_BTRx_DATAHLD */
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
}
else
{
Device->BWTR[Bank] = 0x0FFFFFFFU;
}
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
* @brief management functions
*
@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FMC NORSRAM interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically FMC_NORSRAM write operation.
* @param Device Pointer to NORSRAM device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Enable write operation */
SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NORSRAM write operation.
* @param Device Pointer to NORSRAM device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Disable write operation */
CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
* @brief NAND Controller functions
*
@verbatim
==============================================================================
##### How to use NAND device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FMC NAND banks in order
to run the NAND external devices.
(+) FMC NAND bank reset using the function FMC_NAND_DeInit()
(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
(+) FMC NAND bank common space timing configuration using the function
FMC_NAND_CommonSpace_Timing_Init()
(+) FMC NAND bank attribute space timing configuration using the function
FMC_NAND_AttributeSpace_Timing_Init()
(+) FMC NAND bank enable/disable ECC correction feature using the functions
FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
@endverbatim
* @{
*/
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the FMC NAND interface
(+) De-initialize the FMC NAND interface
(+) Configure the FMC clock and associated GPIOs
@endverbatim
* @{
*/
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
* @param Device Pointer to NAND device instance
* @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Init->NandBank));
assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
FMC_PCR_MEMORY_TYPE_NAND |
Init->MemoryDataWidth |
Init->EccComputation |
Init->ECCPageSize |
((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
return HAL_OK;
}
/**
* @brief Initializes the FMC_NAND Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to NAND device instance
* @param Timing Pointer to NAND timing structure
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
return HAL_OK;
}
/**
* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to NAND device instance
* @param Timing Pointer to NAND timing structure
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
return HAL_OK;
}
/**
* @brief DeInitializes the FMC_NAND device
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Disable the NAND Bank */
__FMC_NAND_DISABLE(Device);
/* De-initialize the NAND Bank */
/* Set the FMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR, 0x00000018);
WRITE_REG(Device->SR, 0x00000040);
WRITE_REG(Device->PMEM, 0xFCFCFCFC);
WRITE_REG(Device->PATT, 0xFCFCFCFC);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### FMC_NAND Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FMC NAND interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically FMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Enable ECC feature */
SET_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Disable ECC feature */
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param ECCval Pointer to ECC value
* @param Bank NAND bank number
* @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Bank);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until FIFO is empty */
while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
/* Get the ECCR register value */
*ECCval = (uint32_t)Device->ECCR;
return HAL_OK;
}
/**
* @}
*/
#endif /* FMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
#include <asm.h>
.include "constants.inc"
SOStartup:
lis 0, SOStartupAddr@h
ori 0, 0, SOStartupAddr@l
mtctr 0
bctr
| {
"language": "Assembly"
} |
; Test to ensure the pgo memop optimization pass doesn't try to scale
; up a value profile with a 0 count, which would lead to divide by 0.
; RUN: opt < %s -passes=pgo-memop-opt -pgo-memop-count-threshold=1 -S | FileCheck %s --check-prefix=MEMOP_OPT
; RUN: opt < %s -pgo-memop-opt -pgo-memop-count-threshold=1 -S | FileCheck %s --check-prefix=MEMOP_OPT
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @foo(i8* %dst, i8* %src, i64 %conv) !prof !0 {
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %conv, i32 1, i1 false), !prof !1
ret void
}
; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %conv, i32 1, i1 false), !prof !1
!0 = !{!"function_entry_count", i64 1}
!1 = !{!"VP", i32 1, i64 0, i64 1, i64 0, i64 2, i64 0, i64 3, i64 0, i64 9, i64 0, i64 4, i64 0, i64 5, i64 0, i64 6, i64 0, i64 7, i64 0, i64 8, i64 0}
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1)
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBVDPAU
bool "libvdpau"
depends on BR2_TOOLCHAIN_HAS_THREADS
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_PACKAGE_XORG7
select BR2_PACKAGE_XLIB_LIBX11
select BR2_PACKAGE_XLIB_LIBXEXT
help
VDPAU is the Video Decode and Presentation API for UNIX.
It provides an interface to video decode acceleration and
presentation hardware present in modern GPUs.
http://freedesktop.org/wiki/Software/VDPAU
comment "libvdpau needs a toolchain w/ threads, C++"
depends on BR2_PACKAGE_XORG7
depends on !BR2_TOOLCHAIN_HAS_THREADS || !BR2_INSTALL_LIBSTDCPP
| {
"language": "Assembly"
} |
// go run mkasm_darwin.go arm64
// Code generated by the command above; DO NOT EDIT.
// +build go1.13
#include "textflag.h"
TEXT ·libc_fdopendir_trampoline(SB),NOSPLIT,$0-0
JMP libc_fdopendir(SB)
TEXT ·libc_closedir_trampoline(SB),NOSPLIT,$0-0
JMP libc_closedir(SB)
TEXT ·libc_readdir_r_trampoline(SB),NOSPLIT,$0-0
JMP libc_readdir_r(SB)
| {
"language": "Assembly"
} |
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V1.07
; * @date 30. January 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER(1)
WDT_IRQHandler
B WDT_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK TIM0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM0_IRQHandler
B TIM0_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK MCIA_IRQHandler
SECTION .text:CODE:REORDER(1)
MCIA_IRQHandler
B MCIA_IRQHandler
PUBWEAK MCIB_IRQHandler
SECTION .text:CODE:REORDER(1)
MCIB_IRQHandler
B MCIB_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK AACI_IRQHandler
SECTION .text:CODE:REORDER(1)
AACI_IRQHandler
B AACI_IRQHandler
PUBWEAK CLCD_IRQHandler
SECTION .text:CODE:REORDER(1)
CLCD_IRQHandler
B CLCD_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK USBDC_IRQHandler
SECTION .text:CODE:REORDER(1)
USBDC_IRQHandler
B USBDC_IRQHandler
PUBWEAK USBHC_IRQHandler
SECTION .text:CODE:REORDER(1)
USBHC_IRQHandler
B USBHC_IRQHandler
PUBWEAK CHLCD_IRQHandler
SECTION .text:CODE:REORDER(1)
CHLCD_IRQHandler
B CHLCD_IRQHandler
PUBWEAK FLEXRAY_IRQHandler
SECTION .text:CODE:REORDER(1)
FLEXRAY_IRQHandler
B FLEXRAY_IRQHandler
PUBWEAK CAN_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN_IRQHandler
B CAN_IRQHandler
PUBWEAK LIN_IRQHandler
SECTION .text:CODE:REORDER(1)
LIN_IRQHandler
B LIN_IRQHandler
PUBWEAK I2C_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C_IRQHandler
B I2C_IRQHandler
PUBWEAK CPU_CLCD_IRQHandler
SECTION .text:CODE:REORDER(1)
CPU_CLCD_IRQHandler
B CPU_CLCD_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK SPI_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI_IRQHandler
B SPI_IRQHandler
END
| {
"language": "Assembly"
} |
.include "validation.a"
.include "ppu_sync.a"
.default palette = default_palette
.default tiles = default_tiles
.code
begin_ppu_test:
lda #40
jsr delay_msec
jsr wait_vbl
jsr disable_ppu
jsr clear_vram
jsr clear_sprites
rts
.code
default_palette:
.db $0f,$01,$02,$39
.db $0f,$03,$04,$38
.db $0f,$05,$06,$38
.db $0f,$11,$12,$38
.db $0f,$32,$32,$21
.db $0f,$32,$32,$32
.db $0f,$32,$32,$32
.db $0f,$32,$32,$32
.code
default_tiles:
.db $00,$00,$00,$00,$00,$00,$00,$00
.db $00,$00,$00,$00,$00,$00,$00,$00
.db $ff,$ff,$ff,$ff,$ff,$ff,$ff,$ff
.db $ff,$ff,$ff,$ff,$ff,$ff,$ff,$ff
.db $f0,$0f,$f0,$0f,$f0,$0f,$f0,$0f
.db $f0,$0f,$f0,$0f,$f0,$0f,$f0,$0f
.db $80,$00,$00,$00,$00,$00,$00,$00
.db $80,$00,$00,$00,$00,$00,$00,$00
.db $81,$00,$00,$00,$00,$00,$00,$81
.db $81,$00,$00,$00,$00,$00,$00,$81
.code
clear_palette:
jsr wait_vbl
lda #$3f
jsr set_vpage
lda #$0f
ldx #$20
: sta $2007
dex
bne -
rts
.code
; A = # of tiles
load_tiles:
asl a
asl a
asl a
asl a
tax
jsr wait_vbl
lda #0
jsr set_vpage
ldy #0
: lda tiles,y
sta $2007
iny
dex
bne -
rts
.code
load_test_chr:
jsr wait_vbl
lda #0
jsr set_vpage
ldy #0
: lda tiles,y
sta $2007
iny
cpy #$40
bne -
rts
.code
load_palette:
lda #$3f
jsr set_vpage
ldy #0
: lda palette,y
sta $2007
iny
cpy #$20
bne -
rts
.code
load_graphics:
jsr wait_vbl
jsr load_palette
jsr load_test_chr
jsr clear_nametable
rts
.code
; Find first byte in VRAM which doesn't match A.
; Address is Y * $100 + X
find_changed_vram:
pha
lda #0
jsr set_vpage
bit $2007
pla
ldx #0
ldy #0
: cmp $2007
bne found
inx
bne -
iny
cpy #$24
bne -
found:
rts
| {
"language": "Assembly"
} |
/***********************************************************************
Copyright (c) 2006-2012, Skype Limited. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, (subject to the limitations in the disclaimer below)
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of Skype Limited, nor the names of specific
contributors, may be used to endorse or promote products derived from
this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED
BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
***********************************************************************/
#if defined(__arm__)
#include "SKP_Silk_AsmPreproc.h"
#if EMBEDDED_ARM >= 5
VARDEF A, r2
VARDEF len, r4
VARDEF S00, r5
VARDEF ink1, r6
VARDEF ink2, r8
VARDEF Y2, sb
VARDEF outk1, sl
VARDEF outk2, ip
.globl SYM(SKP_Silk_allpass_int)
SYM(SKP_Silk_allpass_int):
stmdb sp!, {r4-r10, fp, ip, lr}
add fp, sp, #36
.set len_offset, 40
ldr len, [sp, #len_offset]
ldr S00, [r1]
movs A, A, lsl #17
sub len, len, #1
ldmia r0!, {ink1,ink2}
bge LR(1, f)/*AgeZero*/
L(0)
sub Y2, ink1, S00
smlawt outk1, Y2, A, ink1
add S00, Y2, outk1
subs len, len, #2
sub Y2, ink2, S00
smlawt outk2, Y2, A, ink2
#ifdef _WINRT
ble LR(3, f)
ldmia r0!, {ink1,ink2}
L(3)
#else
ldmgtia r0!, {ink1,ink2}
#endif
add S00, Y2, outk2
stmia r3!, {outk1, outk2}
bgt LR(0, b)
#ifdef _WINRT
bne LR(2, f)
ldr ink1, [r0], #4
sub Y2, ink1, S00
smlawt outk1, Y2, A, ink1
add S00, Y2, outk1
str outk1, [r3]
L(2)
#else
ldreq ink1, [r0], #4
subeq Y2, ink1, S00
smlawteq outk1, Y2, A, ink1
addeq S00, Y2, outk1
streq outk1, [r3]
#endif
str S00, [r1]
ldmia sp!, {r4-r10, fp, ip, pc}
L(1)/*AgeZero:*/
sub Y2, ink1, S00
smlawt outk1, Y2, A, S00
add S00, Y2, outk1
subs len, len, #2
sub Y2, ink2, S00
smlawt outk2, Y2, A, S00
#ifdef _WINRT
ble LR(3, f)
ldmia r0!, {ink1,ink2}
L(3)
#else
ldmgtia r0!, {ink1,ink2}
#endif
add S00, Y2, outk2
stmia r3!, {outk1, outk2}
bgt LR(1, b)
#ifdef _WINRT
bne LR(2, f)
ldr ink1, [r0], #4
sub Y2, ink1, S00
smlawt outk1, Y2, A, S00
add S00, Y2, outk1
str outk1, [r3]
L(2)
#else
ldreq ink1, [r0], #4
subeq Y2, ink1, S00
smlawteq outk1, Y2, A, S00
addeq S00, Y2, outk1
streq outk1, [r3]
#endif
str S00, [r1]
ldmia sp!, {r4-r10, fp, ip, pc}
END
#endif
#endif
| {
"language": "Assembly"
} |
/* Copyright (C) 1991-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#include <errno.h>
#include <sys/socket.h>
/* Send N bytes of BUF on socket FD to peer at address ADDR (which is
ADDR_LEN bytes long). Returns the number sent, or -1 for errors. */
ssize_t
__sendto (int fd, const void *buf, size_t n, int flags,
__CONST_SOCKADDR_ARG addr, socklen_t addr_len)
{
__set_errno (ENOSYS);
return -1;
}
weak_alias (__sendto, sendto)
stub_warning (sendto)
| {
"language": "Assembly"
} |
// Modified by Princeton University on June 9th, 2015
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: iob_int_disp_vec.s
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/***********************************************************************
* Name: iob_int_disp_vec.s
* Date:
*
* Description: Generate interrupt, idle, resume and reset requests to
* to all 32 threads.
*
**********************************************************************/
#define MAIN_PAGE_HV_ALSO
#include "iob_defines.h"
#define H_HT0_Interrupt_0x60 trap_interrupt_iob
#include "boot.s"
.text
.align 64
.global main
main:
th_fork(th_main,%l0) ! start up to four threads.
! All threads do the same thing. No need to run more than one core,
! and no need to differentiate the threads because nobody stores
! anything.
th_main_31:
th_main_30:
th_main_29:
th_main_28:
th_main_27:
th_main_26:
th_main_25:
th_main_24:
th_main_23:
th_main_22:
th_main_21:
th_main_20:
th_main_19:
th_main_18:
th_main_17:
th_main_16:
th_main_15:
th_main_14:
th_main_13:
th_main_12:
th_main_11:
th_main_10:
th_main_9:
th_main_8:
th_main_7:
th_main_6:
th_main_5:
th_main_4:
th_main_3:
th_main_2:
th_main_1:
ta T_CHANGE_HPRIV ! Operations can only be done in hyper visor priv mode.
nop
set 0x0, %l7
set 0x40, %g7
! Wait forever.
wait_loop:
ba wait_loop
nop
th_main_0:
ta T_CHANGE_HPRIV ! Operations can only be done in hyper visor priv mode.
nop
setx 0x0000009800000800, %l0, %g1 ! Register address.
set THREAD_COUNT, %g2 ! Number of threads.
set THREAD_STRIDE, %g6 ! Thread stride.
set 0x1, %g3 ! Current thread to receive requests.
set 0x0, %g7 ! Thread to generate requests.
set 0x0, %l7
set 0x40, %g7
gen_int_loop:
! Clear semaphore.
clr_sema_int:
setx semaphore, %l0, %l1
set 0x0, %l2
sll %g3, 0x3, %l2
add %l1, %l2, %l3
set 0x0, %l4
stx %l4, [%l3]
! Issue interrupt request.
issue_int:
mov %l7, %l1
set 0x0, %l2
sll %g3, 0x8, %l2
set 0x0, %g4
set 0x0, %l3
sll %g4, 0x10, %l3
or %l2, %l3, %l4
or %l1, %l4, %l5
stx %l5, [%g1]
! Wait for the thread to be interrupted.
wait_int_req_loop:
nop
nop
nop
nop
setx semaphore, %l0, %l1
set 0x0, %l2
sll %g3, 0x3, %l2
add %l1, %l2, %l3
ldx [%l3], %l4
setx 0x0123456789abcdef, %l0, %l5
cmp %l4, %l5
bne wait_int_req_loop
nop
add %l7, 0x1, %l7
cmp %l7, %g7
bne gen_int_loop
nop
diag_pass:
ta T_GOOD_TRAP
nop
diag_fail:
ta T_BAD_TRAP
nop
! Include subroutines and data.
#include "iob_subs.s"
#include "iob_data.s"
! Trap handlers.
SECTION .HTRAPS
.text
.align 64
! Interrupt iob trap handler.
! No need to clear the mask for interrupt generated by iob since
! the interrupt is not maskable.
.global trap_interrupt_iob
trap_interrupt_iob:
! Check the correct bit is set in the ASI interrupt registers.
ldxa [%g0] 0x72, %g1
set 0x1, %g2
sllx %g2, %l7, %g3
cmp %g1, %g3
bne trap_diag_fail
nop
! Check the correct vector is logged in the ASI interrupt registers.
ldxa [%g0] 0x74, %g1
mov %l7, %g3
cmp %g1, %g3
bne trap_diag_fail
nop
! Write to semaphore to indicate interrupt completion.
setx semaphore, %g0, %g1
rdth_id
set 0x0, %g2
sll %o1, 0x3, %g2
add %g1, %g2, %g3
setx 0x0123456789abcdef, %g0, %g4
stx %g4, [%g3]
! Clear iob interrupt mask.
setx 0x0000009800000408, %l0, %l1 ! Set interrupt control register address.
set 0x0, %l2 ! Write to interrupt control register.
stx %l2, [%l1]
add %l7, 0x1, %l7
retry
trap_diag_fail:
ta T_BAD_TRAP
nop
| {
"language": "Assembly"
} |
$ if f$search("ioapi.h_orig") .eqs. "" then copy ioapi.h ioapi.h_orig
$ open/write zdef vmsdefs.h
$ copy sys$input: zdef
$ deck
#define unix
#define fill_zlib_filefunc64_32_def_from_filefunc32 fillzffunc64from
#define Write_Zip64EndOfCentralDirectoryLocator Write_Zip64EoDLocator
#define Write_Zip64EndOfCentralDirectoryRecord Write_Zip64EoDRecord
#define Write_EndOfCentralDirectoryRecord Write_EoDRecord
$ eod
$ close zdef
$ copy vmsdefs.h,ioapi.h_orig ioapi.h
$ cc/include=[--]/prefix=all ioapi.c
$ cc/include=[--]/prefix=all miniunz.c
$ cc/include=[--]/prefix=all unzip.c
$ cc/include=[--]/prefix=all minizip.c
$ cc/include=[--]/prefix=all zip.c
$ link miniunz,unzip,ioapi,[--]libz.olb/lib
$ link minizip,zip,ioapi,[--]libz.olb/lib
$ mcr []minizip test minizip_info.txt
$ mcr []miniunz -l test.zip
$ rename minizip_info.txt; minizip_info.txt_old
$ mcr []miniunz test.zip
$ delete test.zip;*
$exit
| {
"language": "Assembly"
} |
// RUN: %target-sil-opt -assume-parsing-unqualified-ownership-sil -module-name Swift %s -aa-kind=basic-aa -aa-dump -o /dev/null | %FileCheck %s
// REQUIRES: asserts
import Builtin
struct Int {
var _value: Builtin.Int64
}
struct Int32 {
var _value: Builtin.Int32
}
enum Optional<T> {
case none
case some(T)
}
// CHECK-LABEL: @index_addr_inst_with_unknown_index
// CHECK: PAIR #16.
// CHECK-NEXT: %3 = index_addr %2 : $*Int, %1 : $Builtin.Word
// CHECK-NEXT: %4 = index_addr %2 : $*Int, %1 : $Builtin.Word
// CHECK-NEXT: MayAlias
sil @index_addr_inst_with_unknown_index : $@convention(thin) (Builtin.RawPointer, Builtin.Word) -> () {
bb0(%0 : $Builtin.RawPointer, %1 : $Builtin.Word):
%212 = pointer_to_address %0 : $Builtin.RawPointer to [strict] $*Int
%214 = index_addr %212 : $*Int, %1 : $Builtin.Word
%2114 = index_addr %212 : $*Int, %1 : $Builtin.Word
br bb1
bb1:
%3 = tuple()
return %3 : $()
}
// CHECK-LABEL: @index_addr_inst_with_same_constant_index
// CHECK: PAIR #16.
// CHECK-NEXT: %3 = index_addr %2 : $*Int, %1 : $Builtin.Word
// CHECK-NEXT: %4 = index_addr %2 : $*Int, %1 : $Builtin.Word
// CHECK-NEXT: MustAlias
sil @index_addr_inst_with_same_constant_index : $@convention(thin) (Builtin.RawPointer) -> () {
bb0(%0 : $Builtin.RawPointer):
%6 = integer_literal $Builtin.Word, 2
%212 = pointer_to_address %0 : $Builtin.RawPointer to [strict] $*Int
%214 = index_addr %212 : $*Int, %6 : $Builtin.Word
%2114 = index_addr %212 : $*Int, %6 : $Builtin.Word
br bb1
bb1:
%3 = tuple()
return %3 : $()
}
// CHECK-LABEL: @index_addr_inst_with_different_constant_index
// CHECK: PAIR #23.
// CHECK-NEXT: %4 = index_addr %3 : $*Int, %1 : $Builtin.Word
// CHECK-NEXT: %5 = index_addr %3 : $*Int, %2 : $Builtin.Word
// CHECK-NEXT: NoAlias
sil @index_addr_inst_with_different_constant_index : $@convention(thin) (Builtin.RawPointer) -> () {
bb0(%0 : $Builtin.RawPointer):
%6 = integer_literal $Builtin.Word, 2
%7 = integer_literal $Builtin.Word, 3
%212 = pointer_to_address %0 : $Builtin.RawPointer to [strict] $*Int
%214 = index_addr %212 : $*Int, %6 : $Builtin.Word
%2114 = index_addr %212 : $*Int, %7 : $Builtin.Word
br bb1
bb1:
%3 = tuple()
return %3 : $()
}
// Address Arguments don't alias if they are arguments to the first BB.
//
// CHECK-LABEL: @address_args_dont_alias_in_first_bb
// CHECK: PAIR #0.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: MustAlias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = argument of bb0
// CHECK-NEXT: %1 = argument of bb0
// CHECK-NEXT: NoAlias
sil @address_args_dont_alias_in_first_bb : $@convention(thin) (@in Builtin.NativeObject, @in Builtin.NativeObject) -> () {
bb0(%0 : $*Builtin.NativeObject, %1 : $*Builtin.NativeObject):
%2 = tuple()
return %2 : $()
}
// Address Arguments may alias if they are arguments to a BB besides the first.
//
// FIXME: Once we support looking through PHIs, we will allow for must alias here.
//
// CHECK-LABEL: @address_args_may_alias_in_non_first_bb
// CHECK-NOT: NoAlias
sil @address_args_may_alias_in_non_first_bb : $@convention(thin) (@inout Builtin.NativeObject) -> () {
bb0(%0 : $*Builtin.NativeObject):
br bb1(%0 : $*Builtin.NativeObject, %0 : $*Builtin.NativeObject)
bb1(%1 : $*Builtin.NativeObject, %2 : $*Builtin.NativeObject):
%3 = tuple()
return %3 : $()
}
// Assume that inout arguments alias to preserve memory safety.
//
// CHECK-LABEL: @inout_args_may_alias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = argument of bb0
// CHECK-NEXT: %1 = argument of bb0
// CHECK-NEXT: MayAlias
sil @inout_args_may_alias: $@convention(thin) (@inout Builtin.NativeObject, @inout Builtin.NativeObject) -> () {
bb0(%0 : $*Builtin.NativeObject, %1 : $*Builtin.NativeObject):
%2 = tuple()
return %2 : $()
}
struct StructLvl2 {
var tup : (Builtin.Int64, Builtin.Int32)
}
struct StructLvl1 {
var sub : StructLvl2
var x : Builtin.Int64
}
// Two values with different underlying alloc_stack cannot alias.
//
// CHECK-LABEL: @different_alloc_stack_dont_alias
// cannot alias non types.
// CHECK: PAIR #0.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: MustAlias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %1 = alloc_stack $StructLvl1
// CHECK-NEXT: NoAlias
// CHECK: PAIR #2.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #3.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %3 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.x
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #4.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %4 = struct_element_addr %2 : $*StructLvl2, #StructLvl2.tup
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #12.
// CHECK-NEXT: %0 = alloc_stack $StructLvl1
// CHECK-NEXT: %14 = tuple ()
// CHECK-NEXT: MayAlias
// CHECK: PAIR #21.
// CHECK-NEXT: %1 = alloc_stack $StructLvl1
// CHECK-NEXT: %9 = struct_element_addr %7 : $*StructLvl2, #StructLvl2.tup
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #22.
// CHECK-NEXT: %1 = alloc_stack $StructLvl1
// CHECK-NEXT: %10 = tuple_element_addr %9 : $*(Builtin.Int64, Builtin.Int32), 0
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #23.
// CHECK-NEXT: %1 = alloc_stack $StructLvl1
// CHECK-NEXT: %11 = tuple_element_addr %9 : $*(Builtin.Int64, Builtin.Int32), 1
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #26.
// CHECK-NEXT: %2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
// CHECK-NEXT: %3 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.x
// CHECK-NEXT: NoAlias
// CHECK: PAIR #27.
// CHECK-NEXT: %2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
// CHECK-NEXT: %4 = struct_element_addr %2 : $*StructLvl2, #StructLvl2.tup
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #28.
// CHECK-NEXT: %2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
// CHECK-NEXT: %5 = tuple_element_addr %4 : $*(Builtin.Int64, Builtin.Int32), 0
// CHECK-NEXT: PartialAlias
// CHECK: PAIR #29.
// CHECK-NEXT: %2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
// CHECK-NEXT: %6 = tuple_element_addr %4 : $*(Builtin.Int64, Builtin.Int32), 1
// CHECK-NEXT: PartialAlias
sil @different_alloc_stack_dont_alias : $@convention(thin) () -> () {
%0 = alloc_stack $StructLvl1
%1 = alloc_stack $StructLvl1
%2 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
%3 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.x
%4 = struct_element_addr %2 : $*StructLvl2, #StructLvl2.tup
%5 = tuple_element_addr %4 : $*(Builtin.Int64, Builtin.Int32), 0
%6 = tuple_element_addr %4 : $*(Builtin.Int64, Builtin.Int32), 1
%7 = struct_element_addr %1 : $*StructLvl1, #StructLvl1.sub
%8 = struct_element_addr %1 : $*StructLvl1, #StructLvl1.x
%9 = struct_element_addr %7 : $*StructLvl2, #StructLvl2.tup
%10 = tuple_element_addr %9 : $*(Builtin.Int64, Builtin.Int32), 0
%11 = tuple_element_addr %9 : $*(Builtin.Int64, Builtin.Int32), 1
dealloc_stack %1 : $*StructLvl1
dealloc_stack %0 : $*StructLvl1
%12 = tuple()
return %12 : $()
}
// Function Arguments cannot alias with no alias arguments or with identified
// function locals.
//
// CHECK-LABEL: @args_dont_alias_with_identified_function_locals
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #2.
// CHECK-NEXT: %0 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %2 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #3.
// CHECK-NEXT: %0 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #4.
// CHECK-NEXT: %0 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %5 = tuple ()
// CHECK-NEXT: MayAlias
// CHECK: PAIR #6.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %2 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #7.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #10.
// CHECK-NEXT: %2 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
sil @args_dont_alias_with_identified_function_locals : $@convention(thin) (Builtin.NativeObject, Builtin.NativeObject, @in Builtin.NativeObject) -> () {
bb0(%0 : $Builtin.NativeObject, %1 : $Builtin.NativeObject, %2 : $*Builtin.NativeObject):
%3 = alloc_stack $Builtin.NativeObject
dealloc_stack %3 : $*Builtin.NativeObject
%4 = tuple()
return %4 : $()
}
sil @create_native_object : $@convention(thin) () -> (Builtin.NativeObject)
sil @use_native_object : $@convention(thin) (Builtin.NativeObject) -> ()
// For this test, we care about the following results:
// %1, %3, %5, %7, %8, %9
// Check every alias query involving those.
// CHECK-LABEL: @escapesource_functionlocal_test_escapesource_nonescapinglocal
// Test %0
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #2.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #3.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #5.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #8.
// CHECK-NEXT: %0 = argument of bb0 : $*Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// Test %1 (the aliasing argument)
// CHECK: PAIR #11.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: MustAlias
// CHECK: PAIR #12.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #13.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #15.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #16.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %6 = load %0 : $*Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #18.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #19.
// CHECK-NEXT: %1 = argument of bb0 : $Builtin.NativeObject
// CHECK-NEXT: %9 = apply %7(%8) : $@convention(thin) (Builtin.NativeObject) -> ()
// CHECK-NEXT: MayAlias
// Test %2
// CHECK: PAIR #22.
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #24.
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #25.
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %6 = load %0 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #27.
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #28.
// CHECK-NEXT: %2 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %9 = apply %7(%8) : $@convention(thin) (Builtin.NativeObject) -> ()
// CHECK-NEXT: MayAlias
// Test %3 (the escaping alloca).
// CHECK: PAIR #32.
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #33.
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %6 = load %0 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// CHECK: PAIR #35.
// CHECK-NEXT: %3 = alloc_stack $Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: NoAlias
// Test %5 (the read write apply inst).
// CHECK: PAIR #45.
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: MustAlias
// CHECK: PAIR #46.
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: %6 = load %0 : $*Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #47.
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: function_ref use_native_object
// CHECK-NEXT: %7 = function_ref @use_native_object : $@convention(thin) (Builtin.NativeObject) -> ()
// CHECK-NEXT: MayAlias
// CHECK: PAIR #48.
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: MayAlias
// CHECK: PAIR #49.
// CHECK-NEXT: %5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
// CHECK-NEXT: %9 = apply %7(%8) : $@convention(thin) (Builtin.NativeObject) -> ()
// CHECK-NEXT: MayAlias
// Test %8 (the escaping load)
// CHECK: PAIR #60.
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: MustAlias
// CHECK: PAIR #61.
// CHECK-NEXT: %8 = load %3 : $*Builtin.NativeObject
// CHECK-NEXT: %9 = apply %7(%8) : $@convention(thin) (Builtin.NativeObject) -> ()
// CHECK-NEXT: MayAlias
sil @escapesource_functionlocal_test_escapesource_nonescapinglocal : $@convention(thin) (@in Builtin.NativeObject, Builtin.NativeObject) -> () {
bb0(%0 : $*Builtin.NativeObject, %1 : $Builtin.NativeObject):
%2 = alloc_stack $Builtin.NativeObject
%3 = alloc_stack $Builtin.NativeObject
%4 = function_ref @create_native_object : $@convention(thin) () -> Builtin.NativeObject
%5 = apply %4() : $@convention(thin) () -> Builtin.NativeObject
%6 = load %0 : $*Builtin.NativeObject
%7 = function_ref @use_native_object : $@convention(thin) (Builtin.NativeObject) -> ()
%8 = load %3 : $*Builtin.NativeObject
%9 = apply %7(%8) : $@convention(thin) (Builtin.NativeObject) -> ()
dealloc_stack %3 : $*Builtin.NativeObject
dealloc_stack %2 : $*Builtin.NativeObject
%12 = tuple ()
return %12 : $()
}
// CHECK-LABEL: @projections_from_the_same_source_with_the_same_projection_path_mustalias
// CHECK: PAIR #24.
// CHECK-NEXT: %3 = tuple_element_addr %2 : $*(Builtin.Int64, Builtin.Int32), 1
// CHECK-NEXT: %6 = tuple_element_addr %5 : $*(Builtin.Int64, Builtin.Int32), 1
// CHECK-NEXT: MustAlias
sil @projections_from_the_same_source_with_the_same_projection_path_mustalias : $@convention(thin) () -> () {
%0 = alloc_stack $StructLvl1
%1 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
%2 = struct_element_addr %1 : $*StructLvl2, #StructLvl2.tup
%3 = tuple_element_addr %2 : $*(Builtin.Int64, Builtin.Int32), 1
%4 = struct_element_addr %0 : $*StructLvl1, #StructLvl1.sub
%5 = struct_element_addr %4 : $*StructLvl2, #StructLvl2.tup
%6 = tuple_element_addr %5 : $*(Builtin.Int64, Builtin.Int32), 1
dealloc_stack %0 : $*StructLvl1
%7 = tuple()
return %7 : $()
}
sil_global public @sil_global1 : $Builtin.Int32
sil_global public @sil_global2 : $Builtin.Int32
class X { }
// CHECK-LABEL: @globals_dont_alias
// CHECK: PAIR #0.
// CHECK-NEXT: %0 = global_addr @sil_global1 : $*Builtin.Int32
// CHECK-NEXT: %0 = global_addr @sil_global1 : $*Builtin.Int32
// CHECK-NEXT: MustAlias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = global_addr @sil_global1 : $*Builtin.Int32
// CHECK-NEXT: %1 = global_addr @sil_global2 : $*Builtin.Int32
// CHECK-NEXT: NoAlias
sil @globals_dont_alias : $@convention(thin) () -> () {
%0 = global_addr @sil_global1 : $*Builtin.Int32
%1 = global_addr @sil_global2 : $*Builtin.Int32
%4 = tuple()
return %4 : $()
}
// CHECK-LABEL: @globals_and_allocs_dont_alias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = global_addr @sil_global1 : $*Builtin.Int32
// CHECK-NEXT: %1 = alloc_ref $X
// CHECK-NEXT: NoAlias
sil @globals_and_allocs_dont_alias : $@convention(thin) () -> () {
%0 = global_addr @sil_global1 : $*Builtin.Int32
%1 = alloc_ref $X
%4 = tuple()
return %4 : $()
}
sil_global @sil_global3 : $Int32
// CHECK-LABEL: @globals_alias
// CHECK: PAIR #0.
// CHECK-NEXT: %0 = global_addr @sil_global3 : $*Int32
// CHECK-NEXT: %0 = global_addr @sil_global3 : $*Int32
// CHECK-NEXT: MustAlias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = global_addr @sil_global3 : $*Int32
// CHECK-NEXT: %1 = global_addr @sil_global3 : $*Int32
// CHECK-NEXT: MustAlias
// CHECK: PAIR #2.
// CHECK-NEXT: %0 = global_addr @sil_global3 : $*Int32
// CHECK-NEXT: %2 = struct_element_addr %1 : $*Int32, #Int32._value
// CHECK-NEXT: PartialAlias
sil @globals_alias : $@convention(thin) () -> () {
%0 = global_addr @sil_global3 : $*Int32
%1 = global_addr @sil_global3 : $*Int32
%2 = struct_element_addr %1 : $*Int32, #Int32._value
%4 = tuple()
return %4 : $()
}
class HalfOpenRange {
final var current: Int32
final let end: Int32
init(start: Int32, end: Int32)
}
// CHECK-LABEL: @different_fields
// CHECK: PAIR #51.
// CHECK-NEXT: %5 = ref_element_addr %4 : $HalfOpenRange, #HalfOpenRange.current
// CHECK-NEXT: %7 = ref_element_addr %4 : $HalfOpenRange, #HalfOpenRange.end
// CHECK-NEXT: NoAlias
// CHECK: PAIR #64.
// CHECK-NEXT: %9 = struct_element_addr %5 : $*Int32, #Int32._value
// CHECK-NEXT: %10 = struct_element_addr %7 : $*Int32, #Int32._value
// CHECK-NEXT: NoAlias
sil @different_fields : $@convention(thin) () -> () {
%0 = integer_literal $Builtin.Int32, 0
%1 = struct $Int32 (%0 : $Builtin.Int32)
%2 = integer_literal $Builtin.Int32, 10
%3 = struct $Int32 (%2 : $Builtin.Int32)
%4 = alloc_ref $HalfOpenRange
%5 = ref_element_addr %4 : $HalfOpenRange, #HalfOpenRange.current
store %1 to %5 : $*Int32
%7 = ref_element_addr %4 : $HalfOpenRange, #HalfOpenRange.end
store %3 to %7 : $*Int32
%9 = struct_element_addr %5 : $*Int32, #Int32._value
%10 = struct_element_addr %7 : $*Int32, #Int32._value
%11 = load %9 : $*Builtin.Int32
%12 = load %10 : $*Builtin.Int32
%13 = tuple()
return %13 : $()
}
public final class C {
@sil_stored final var a: Int { get set }
@sil_stored final var b: Int { get set }
deinit
init()
}
// CHECK-LABEL: @ref_element_addr_and_object_itself
// CHECK: PAIR #0.
// CHECK-NEXT: %0 = alloc_ref $C{{.*}} // user: %1
// CHECK-NEXT: %0 = alloc_ref $C{{.*}} // user: %1
// CHECK-NEXT: MustAlias
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = alloc_ref $C{{.*}} // user: %1
// CHECK-NEXT: %1 = ref_element_addr %0 : $C, #C.a
// CHECK-NEXT: PartialAlias
sil @ref_element_addr_and_object_itself : $@convention(thin) () -> () {
bb0:
%0 = alloc_ref $C
%1 = ref_element_addr %0 : $C, #C.a
%2 = tuple()
return %2 : $()
}
// CHECK-LABEL: @different_fields_of_different_refs
// CHECK: PAIR #13.
// CHECK-NEXT: %3 = ref_element_addr %0 : $C, #C.a
// CHECK-NEXT: %4 = ref_element_addr %1 : $C, #C.b
// CHECK-NEXT: NoAlias
sil @different_fields_of_different_refs : $@convention(thin) (@owned C, @owned C, Int) -> Int {
bb0(%0 : $C, %1 : $C, %2 : $Int):
%6 = ref_element_addr %0 : $C, #C.a
%8 = ref_element_addr %1 : $C, #C.b
return %2 : $Int
}
// CHECK-LABEL: @non_escaping_local_object_does_not_alias_with_unknown
// CHECK: PAIR #7.
// CHECK-NEXT: %1 = alloc_ref $X{{.*}} // user: %3
// CHECK-NEXT: %3 = apply %2(%1) : $@convention(thin) (X) -> X
// CHECK-NEXT: NoAlias
sil @non_escaping_local_object_does_not_alias_with_unknown : $@convention(thin) (X) -> () {
bb0(%0 : $X):
%1 = alloc_ref $X
%f = function_ref @not_escaping : $@convention(thin) (X) -> X
%2 = apply %f(%1) : $@convention(thin) (X) -> X
%12 = tuple()
return %12 : $()
}
sil @not_escaping: $@convention(thin) (X) -> X {
bb0(%0 : $X):
%1 = alloc_ref $X
return %1 : $X
}
// CHECK-LABEL: @alloc_stack_and_addr_cast
// CHECK: PAIR #1.
// CHECK-NEXT: %0 = alloc_stack $C{{.*}} // users: %2, %1
// CHECK-NEXT: %1 = unchecked_addr_cast %0 : $*C to $*Optional<C>
// CHECK-NEXT: MayAlias
sil @alloc_stack_and_addr_cast : $@convention(thin) () -> () {
bb0:
%0 = alloc_stack $C
%1 = unchecked_addr_cast %0 : $*C to $*Optional<C>
dealloc_stack %0 : $*C
%2 = tuple()
return %2 : $()
}
| {
"language": "Assembly"
} |
#!/usr/bin/env perl
#
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
# ====================================================================
#
# March, June 2010
#
# The module implements "4-bit" GCM GHASH function and underlying
# single multiplication operation in GF(2^128). "4-bit" means that
# it uses 256 bytes per-key table [+128 bytes shared table]. GHASH
# function features so called "528B" variant utilizing additional
# 256+16 bytes of per-key storage [+512 bytes shared table].
# Performance results are for this streamed GHASH subroutine and are
# expressed in cycles per processed byte, less is better:
#
# gcc 3.4.x(*) assembler
#
# P4 28.6 14.0 +100%
# Opteron 19.3 7.7 +150%
# Core2 17.8 8.1(**) +120%
# Atom 31.6 16.8 +88%
# VIA Nano 21.8 10.1 +115%
#
# (*) comparison is not completely fair, because C results are
# for vanilla "256B" implementation, while assembler results
# are for "528B";-)
# (**) it's mystery [to me] why Core2 result is not same as for
# Opteron;
# May 2010
#
# Add PCLMULQDQ version performing at 2.02 cycles per processed byte.
# See ghash-x86.pl for background information and details about coding
# techniques.
#
# Special thanks to David Woodhouse <dwmw2@infradead.org> for
# providing access to a Westmere-based system on behalf of Intel
# Open Source Technology Centre.
# December 2012
#
# Overhaul: aggregate Karatsuba post-processing, improve ILP in
# reduction_alg9, increase reduction aggregate factor to 4x. As for
# the latter. ghash-x86.pl discusses that it makes lesser sense to
# increase aggregate factor. Then why increase here? Critical path
# consists of 3 independent pclmulqdq instructions, Karatsuba post-
# processing and reduction. "On top" of this we lay down aggregated
# multiplication operations, triplets of independent pclmulqdq's. As
# issue rate for pclmulqdq is limited, it makes lesser sense to
# aggregate more multiplications than it takes to perform remaining
# non-multiplication operations. 2x is near-optimal coefficient for
# contemporary Intel CPUs (therefore modest improvement coefficient),
# but not for Bulldozer. Latter is because logical SIMD operations
# are twice as slow in comparison to Intel, so that critical path is
# longer. A CPU with higher pclmulqdq issue rate would also benefit
# from higher aggregate factor...
#
# Westmere 1.78(+13%)
# Sandy Bridge 1.80(+8%)
# Ivy Bridge 1.80(+7%)
# Haswell 0.55(+93%) (if system doesn't support AVX)
# Broadwell 0.45(+110%)(if system doesn't support AVX)
# Bulldozer 1.49(+27%)
# Silvermont 2.88(+13%)
# March 2013
#
# ... 8x aggregate factor AVX code path is using reduction algorithm
# suggested by Shay Gueron[1]. Even though contemporary AVX-capable
# CPUs such as Sandy and Ivy Bridge can execute it, the code performs
# sub-optimally in comparison to above mentioned version. But thanks
# to Ilya Albrekht and Max Locktyukhin of Intel Corp. we knew that
# it performs in 0.41 cycles per byte on Haswell processor, and in
# 0.29 on Broadwell.
#
# [1] http://rt.openssl.org/Ticket/Display.html?id=2900&user=guest&pass=guest
$flavour = shift;
$output = shift;
if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
die "can't locate x86_64-xlate.pl";
if (`$ENV{CC} -Wa,-v -c -o /dev/null -x assembler /dev/null 2>&1`
=~ /GNU assembler version ([2-9]\.[0-9]+)/) {
$avx = ($1>=2.20) + ($1>=2.22);
}
if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
`nasm -v 2>&1` =~ /NASM version ([2-9]\.[0-9]+)/) {
$avx = ($1>=2.09) + ($1>=2.10);
}
if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
`ml64 2>&1` =~ /Version ([0-9]+)\./) {
$avx = ($1>=10) + ($1>=11);
}
if (!$avx && `$ENV{CC} -v 2>&1` =~ /((?:^clang|LLVM) version|.*based on LLVM) ([3-9]\.[0-9]+)/) {
$avx = ($2>=3.0) + ($2>3.0);
}
open OUT,"| \"$^X\" $xlate $flavour $output";
*STDOUT=*OUT;
$do4xaggr=1;
# common register layout
$nlo="%rax";
$nhi="%rbx";
$Zlo="%r8";
$Zhi="%r9";
$tmp="%r10";
$rem_4bit = "%r11";
$Xi="%rdi";
$Htbl="%rsi";
# per-function register layout
$cnt="%rcx";
$rem="%rdx";
sub LB() { my $r=shift; $r =~ s/%[er]([a-d])x/%\1l/ or
$r =~ s/%[er]([sd]i)/%\1l/ or
$r =~ s/%[er](bp)/%\1l/ or
$r =~ s/%(r[0-9]+)[d]?/%\1b/; $r; }
sub AUTOLOAD() # thunk [simplified] 32-bit style perlasm
{ my $opcode = $AUTOLOAD; $opcode =~ s/.*:://;
my $arg = pop;
$arg = "\$$arg" if ($arg*1 eq $arg);
$code .= "\t$opcode\t".join(',',$arg,reverse @_)."\n";
}
{ my $N;
sub loop() {
my $inp = shift;
$N++;
$code.=<<___;
xor $nlo,$nlo
xor $nhi,$nhi
mov `&LB("$Zlo")`,`&LB("$nlo")`
mov `&LB("$Zlo")`,`&LB("$nhi")`
shl \$4,`&LB("$nlo")`
mov \$14,$cnt
mov 8($Htbl,$nlo),$Zlo
mov ($Htbl,$nlo),$Zhi
and \$0xf0,`&LB("$nhi")`
mov $Zlo,$rem
jmp .Loop$N
.align 16
.Loop$N:
shr \$4,$Zlo
and \$0xf,$rem
mov $Zhi,$tmp
mov ($inp,$cnt),`&LB("$nlo")`
shr \$4,$Zhi
xor 8($Htbl,$nhi),$Zlo
shl \$60,$tmp
xor ($Htbl,$nhi),$Zhi
mov `&LB("$nlo")`,`&LB("$nhi")`
xor ($rem_4bit,$rem,8),$Zhi
mov $Zlo,$rem
shl \$4,`&LB("$nlo")`
xor $tmp,$Zlo
dec $cnt
js .Lbreak$N
shr \$4,$Zlo
and \$0xf,$rem
mov $Zhi,$tmp
shr \$4,$Zhi
xor 8($Htbl,$nlo),$Zlo
shl \$60,$tmp
xor ($Htbl,$nlo),$Zhi
and \$0xf0,`&LB("$nhi")`
xor ($rem_4bit,$rem,8),$Zhi
mov $Zlo,$rem
xor $tmp,$Zlo
jmp .Loop$N
.align 16
.Lbreak$N:
shr \$4,$Zlo
and \$0xf,$rem
mov $Zhi,$tmp
shr \$4,$Zhi
xor 8($Htbl,$nlo),$Zlo
shl \$60,$tmp
xor ($Htbl,$nlo),$Zhi
and \$0xf0,`&LB("$nhi")`
xor ($rem_4bit,$rem,8),$Zhi
mov $Zlo,$rem
xor $tmp,$Zlo
shr \$4,$Zlo
and \$0xf,$rem
mov $Zhi,$tmp
shr \$4,$Zhi
xor 8($Htbl,$nhi),$Zlo
shl \$60,$tmp
xor ($Htbl,$nhi),$Zhi
xor $tmp,$Zlo
xor ($rem_4bit,$rem,8),$Zhi
bswap $Zlo
bswap $Zhi
___
}}
$code=<<___;
.text
.extern OPENSSL_ia32cap_P
.globl gcm_gmult_4bit
.type gcm_gmult_4bit,\@function,2
.align 16
gcm_gmult_4bit:
push %rbx
push %rbp # %rbp and %r12 are pushed exclusively in
push %r12 # order to reuse Win64 exception handler...
.Lgmult_prologue:
movzb 15($Xi),$Zlo
lea .Lrem_4bit(%rip),$rem_4bit
___
&loop ($Xi);
$code.=<<___;
mov $Zlo,8($Xi)
mov $Zhi,($Xi)
mov 16(%rsp),%rbx
lea 24(%rsp),%rsp
.Lgmult_epilogue:
ret
.size gcm_gmult_4bit,.-gcm_gmult_4bit
___
# per-function register layout
$inp="%rdx";
$len="%rcx";
$rem_8bit=$rem_4bit;
$code.=<<___;
.globl gcm_ghash_4bit
.type gcm_ghash_4bit,\@function,4
.align 16
gcm_ghash_4bit:
push %rbx
push %rbp
push %r12
push %r13
push %r14
push %r15
sub \$280,%rsp
.Lghash_prologue:
mov $inp,%r14 # reassign couple of args
mov $len,%r15
___
{ my $inp="%r14";
my $dat="%edx";
my $len="%r15";
my @nhi=("%ebx","%ecx");
my @rem=("%r12","%r13");
my $Hshr4="%rbp";
&sub ($Htbl,-128); # size optimization
&lea ($Hshr4,"16+128(%rsp)");
{ my @lo =($nlo,$nhi);
my @hi =($Zlo,$Zhi);
&xor ($dat,$dat);
for ($i=0,$j=-2;$i<18;$i++,$j++) {
&mov ("$j(%rsp)",&LB($dat)) if ($i>1);
&or ($lo[0],$tmp) if ($i>1);
&mov (&LB($dat),&LB($lo[1])) if ($i>0 && $i<17);
&shr ($lo[1],4) if ($i>0 && $i<17);
&mov ($tmp,$hi[1]) if ($i>0 && $i<17);
&shr ($hi[1],4) if ($i>0 && $i<17);
&mov ("8*$j($Hshr4)",$hi[0]) if ($i>1);
&mov ($hi[0],"16*$i+0-128($Htbl)") if ($i<16);
&shl (&LB($dat),4) if ($i>0 && $i<17);
&mov ("8*$j-128($Hshr4)",$lo[0]) if ($i>1);
&mov ($lo[0],"16*$i+8-128($Htbl)") if ($i<16);
&shl ($tmp,60) if ($i>0 && $i<17);
push (@lo,shift(@lo));
push (@hi,shift(@hi));
}
}
&add ($Htbl,-128);
&mov ($Zlo,"8($Xi)");
&mov ($Zhi,"0($Xi)");
&add ($len,$inp); # pointer to the end of data
&lea ($rem_8bit,".Lrem_8bit(%rip)");
&jmp (".Louter_loop");
$code.=".align 16\n.Louter_loop:\n";
&xor ($Zhi,"($inp)");
&mov ("%rdx","8($inp)");
&lea ($inp,"16($inp)");
&xor ("%rdx",$Zlo);
&mov ("($Xi)",$Zhi);
&mov ("8($Xi)","%rdx");
&shr ("%rdx",32);
&xor ($nlo,$nlo);
&rol ($dat,8);
&mov (&LB($nlo),&LB($dat));
&movz ($nhi[0],&LB($dat));
&shl (&LB($nlo),4);
&shr ($nhi[0],4);
for ($j=11,$i=0;$i<15;$i++) {
&rol ($dat,8);
&xor ($Zlo,"8($Htbl,$nlo)") if ($i>0);
&xor ($Zhi,"($Htbl,$nlo)") if ($i>0);
&mov ($Zlo,"8($Htbl,$nlo)") if ($i==0);
&mov ($Zhi,"($Htbl,$nlo)") if ($i==0);
&mov (&LB($nlo),&LB($dat));
&xor ($Zlo,$tmp) if ($i>0);
&movzw ($rem[1],"($rem_8bit,$rem[1],2)") if ($i>0);
&movz ($nhi[1],&LB($dat));
&shl (&LB($nlo),4);
&movzb ($rem[0],"(%rsp,$nhi[0])");
&shr ($nhi[1],4) if ($i<14);
&and ($nhi[1],0xf0) if ($i==14);
&shl ($rem[1],48) if ($i>0);
&xor ($rem[0],$Zlo);
&mov ($tmp,$Zhi);
&xor ($Zhi,$rem[1]) if ($i>0);
&shr ($Zlo,8);
&movz ($rem[0],&LB($rem[0]));
&mov ($dat,"$j($Xi)") if (--$j%4==0);
&shr ($Zhi,8);
&xor ($Zlo,"-128($Hshr4,$nhi[0],8)");
&shl ($tmp,56);
&xor ($Zhi,"($Hshr4,$nhi[0],8)");
unshift (@nhi,pop(@nhi)); # "rotate" registers
unshift (@rem,pop(@rem));
}
&movzw ($rem[1],"($rem_8bit,$rem[1],2)");
&xor ($Zlo,"8($Htbl,$nlo)");
&xor ($Zhi,"($Htbl,$nlo)");
&shl ($rem[1],48);
&xor ($Zlo,$tmp);
&xor ($Zhi,$rem[1]);
&movz ($rem[0],&LB($Zlo));
&shr ($Zlo,4);
&mov ($tmp,$Zhi);
&shl (&LB($rem[0]),4);
&shr ($Zhi,4);
&xor ($Zlo,"8($Htbl,$nhi[0])");
&movzw ($rem[0],"($rem_8bit,$rem[0],2)");
&shl ($tmp,60);
&xor ($Zhi,"($Htbl,$nhi[0])");
&xor ($Zlo,$tmp);
&shl ($rem[0],48);
&bswap ($Zlo);
&xor ($Zhi,$rem[0]);
&bswap ($Zhi);
&cmp ($inp,$len);
&jb (".Louter_loop");
}
$code.=<<___;
mov $Zlo,8($Xi)
mov $Zhi,($Xi)
lea 280(%rsp),%rsi
mov 0(%rsi),%r15
mov 8(%rsi),%r14
mov 16(%rsi),%r13
mov 24(%rsi),%r12
mov 32(%rsi),%rbp
mov 40(%rsi),%rbx
lea 48(%rsi),%rsp
.Lghash_epilogue:
ret
.size gcm_ghash_4bit,.-gcm_ghash_4bit
___
######################################################################
# PCLMULQDQ version.
@_4args=$win64? ("%rcx","%rdx","%r8", "%r9") : # Win64 order
("%rdi","%rsi","%rdx","%rcx"); # Unix order
($Xi,$Xhi)=("%xmm0","%xmm1"); $Hkey="%xmm2";
($T1,$T2,$T3)=("%xmm3","%xmm4","%xmm5");
sub clmul64x64_T2 { # minimal register pressure
my ($Xhi,$Xi,$Hkey,$HK)=@_;
if (!defined($HK)) { $HK = $T2;
$code.=<<___;
movdqa $Xi,$Xhi #
pshufd \$0b01001110,$Xi,$T1
pshufd \$0b01001110,$Hkey,$T2
pxor $Xi,$T1 #
pxor $Hkey,$T2
___
} else {
$code.=<<___;
movdqa $Xi,$Xhi #
pshufd \$0b01001110,$Xi,$T1
pxor $Xi,$T1 #
___
}
$code.=<<___;
pclmulqdq \$0x00,$Hkey,$Xi #######
pclmulqdq \$0x11,$Hkey,$Xhi #######
pclmulqdq \$0x00,$HK,$T1 #######
pxor $Xi,$T1 #
pxor $Xhi,$T1 #
movdqa $T1,$T2 #
psrldq \$8,$T1
pslldq \$8,$T2 #
pxor $T1,$Xhi
pxor $T2,$Xi #
___
}
sub reduction_alg9 { # 17/11 times faster than Intel version
my ($Xhi,$Xi) = @_;
$code.=<<___;
# 1st phase
movdqa $Xi,$T2 #
movdqa $Xi,$T1
psllq \$5,$Xi
pxor $Xi,$T1 #
psllq \$1,$Xi
pxor $T1,$Xi #
psllq \$57,$Xi #
movdqa $Xi,$T1 #
pslldq \$8,$Xi
psrldq \$8,$T1 #
pxor $T2,$Xi
pxor $T1,$Xhi #
# 2nd phase
movdqa $Xi,$T2
psrlq \$1,$Xi
pxor $T2,$Xhi #
pxor $Xi,$T2
psrlq \$5,$Xi
pxor $T2,$Xi #
psrlq \$1,$Xi #
pxor $Xhi,$Xi #
___
}
{ my ($Htbl,$Xip)=@_4args;
my $HK="%xmm6";
$code.=<<___;
.globl gcm_init_clmul
.type gcm_init_clmul,\@abi-omnipotent
.align 16
gcm_init_clmul:
.L_init_clmul:
___
$code.=<<___ if ($win64);
.LSEH_begin_gcm_init_clmul:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x83,0xec,0x18 #sub $0x18,%rsp
.byte 0x0f,0x29,0x34,0x24 #movaps %xmm6,(%rsp)
___
$code.=<<___;
movdqu ($Xip),$Hkey
pshufd \$0b01001110,$Hkey,$Hkey # dword swap
# <<1 twist
pshufd \$0b11111111,$Hkey,$T2 # broadcast uppermost dword
movdqa $Hkey,$T1
psllq \$1,$Hkey
pxor $T3,$T3 #
psrlq \$63,$T1
pcmpgtd $T2,$T3 # broadcast carry bit
pslldq \$8,$T1
por $T1,$Hkey # H<<=1
# magic reduction
pand .L0x1c2_polynomial(%rip),$T3
pxor $T3,$Hkey # if(carry) H^=0x1c2_polynomial
# calculate H^2
pshufd \$0b01001110,$Hkey,$HK
movdqa $Hkey,$Xi
pxor $Hkey,$HK
___
&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$HK);
&reduction_alg9 ($Xhi,$Xi);
$code.=<<___;
pshufd \$0b01001110,$Hkey,$T1
pshufd \$0b01001110,$Xi,$T2
pxor $Hkey,$T1 # Karatsuba pre-processing
movdqu $Hkey,0x00($Htbl) # save H
pxor $Xi,$T2 # Karatsuba pre-processing
movdqu $Xi,0x10($Htbl) # save H^2
palignr \$8,$T1,$T2 # low part is H.lo^H.hi...
movdqu $T2,0x20($Htbl) # save Karatsuba "salt"
___
if ($do4xaggr) {
&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$HK); # H^3
&reduction_alg9 ($Xhi,$Xi);
$code.=<<___;
movdqa $Xi,$T3
___
&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$HK); # H^4
&reduction_alg9 ($Xhi,$Xi);
$code.=<<___;
pshufd \$0b01001110,$T3,$T1
pshufd \$0b01001110,$Xi,$T2
pxor $T3,$T1 # Karatsuba pre-processing
movdqu $T3,0x30($Htbl) # save H^3
pxor $Xi,$T2 # Karatsuba pre-processing
movdqu $Xi,0x40($Htbl) # save H^4
palignr \$8,$T1,$T2 # low part is H^3.lo^H^3.hi...
movdqu $T2,0x50($Htbl) # save Karatsuba "salt"
___
}
$code.=<<___ if ($win64);
movaps (%rsp),%xmm6
lea 0x18(%rsp),%rsp
.LSEH_end_gcm_init_clmul:
___
$code.=<<___;
ret
.size gcm_init_clmul,.-gcm_init_clmul
___
}
{ my ($Xip,$Htbl)=@_4args;
$code.=<<___;
.globl gcm_gmult_clmul
.type gcm_gmult_clmul,\@abi-omnipotent
.align 16
gcm_gmult_clmul:
.L_gmult_clmul:
movdqu ($Xip),$Xi
movdqa .Lbswap_mask(%rip),$T3
movdqu ($Htbl),$Hkey
movdqu 0x20($Htbl),$T2
pshufb $T3,$Xi
___
&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$T2);
$code.=<<___ if (0 || (&reduction_alg9($Xhi,$Xi)&&0));
# experimental alternative. special thing about is that there
# no dependency between the two multiplications...
mov \$`0xE1<<1`,%eax
mov \$0xA040608020C0E000,%r10 # ((7..0)·0xE0)&0xff
mov \$0x07,%r11d
movq %rax,$T1
movq %r10,$T2
movq %r11,$T3 # borrow $T3
pand $Xi,$T3
pshufb $T3,$T2 # ($Xi&7)·0xE0
movq %rax,$T3
pclmulqdq \$0x00,$Xi,$T1 # ·(0xE1<<1)
pxor $Xi,$T2
pslldq \$15,$T2
paddd $T2,$T2 # <<(64+56+1)
pxor $T2,$Xi
pclmulqdq \$0x01,$T3,$Xi
movdqa .Lbswap_mask(%rip),$T3 # reload $T3
psrldq \$1,$T1
pxor $T1,$Xhi
pslldq \$7,$Xi
pxor $Xhi,$Xi
___
$code.=<<___;
pshufb $T3,$Xi
movdqu $Xi,($Xip)
ret
.size gcm_gmult_clmul,.-gcm_gmult_clmul
___
}
{ my ($Xip,$Htbl,$inp,$len)=@_4args;
my ($Xln,$Xmn,$Xhn,$Hkey2,$HK) = map("%xmm$_",(3..7));
my ($T1,$T2,$T3)=map("%xmm$_",(8..10));
$code.=<<___;
.globl gcm_ghash_clmul
.type gcm_ghash_clmul,\@abi-omnipotent
.align 32
gcm_ghash_clmul:
.L_ghash_clmul:
___
$code.=<<___ if ($win64);
lea -0x88(%rsp),%rax
.LSEH_begin_gcm_ghash_clmul:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x8d,0x60,0xe0 #lea -0x20(%rax),%rsp
.byte 0x0f,0x29,0x70,0xe0 #movaps %xmm6,-0x20(%rax)
.byte 0x0f,0x29,0x78,0xf0 #movaps %xmm7,-0x10(%rax)
.byte 0x44,0x0f,0x29,0x00 #movaps %xmm8,0(%rax)
.byte 0x44,0x0f,0x29,0x48,0x10 #movaps %xmm9,0x10(%rax)
.byte 0x44,0x0f,0x29,0x50,0x20 #movaps %xmm10,0x20(%rax)
.byte 0x44,0x0f,0x29,0x58,0x30 #movaps %xmm11,0x30(%rax)
.byte 0x44,0x0f,0x29,0x60,0x40 #movaps %xmm12,0x40(%rax)
.byte 0x44,0x0f,0x29,0x68,0x50 #movaps %xmm13,0x50(%rax)
.byte 0x44,0x0f,0x29,0x70,0x60 #movaps %xmm14,0x60(%rax)
.byte 0x44,0x0f,0x29,0x78,0x70 #movaps %xmm15,0x70(%rax)
___
$code.=<<___;
movdqa .Lbswap_mask(%rip),$T3
movdqu ($Xip),$Xi
movdqu ($Htbl),$Hkey
movdqu 0x20($Htbl),$HK
pshufb $T3,$Xi
sub \$0x10,$len
jz .Lodd_tail
movdqu 0x10($Htbl),$Hkey2
___
if ($do4xaggr) {
my ($Xl,$Xm,$Xh,$Hkey3,$Hkey4)=map("%xmm$_",(11..15));
$code.=<<___;
mov OPENSSL_ia32cap_P+4(%rip),%eax
cmp \$0x30,$len
jb .Lskip4x
and \$`1<<26|1<<22`,%eax # isolate MOVBE+XSAVE
cmp \$`1<<22`,%eax # check for MOVBE without XSAVE
je .Lskip4x
sub \$0x30,$len
mov \$0xA040608020C0E000,%rax # ((7..0)·0xE0)&0xff
movdqu 0x30($Htbl),$Hkey3
movdqu 0x40($Htbl),$Hkey4
#######
# Xi+4 =[(H*Ii+3) + (H^2*Ii+2) + (H^3*Ii+1) + H^4*(Ii+Xi)] mod P
#
movdqu 0x30($inp),$Xln
movdqu 0x20($inp),$Xl
pshufb $T3,$Xln
pshufb $T3,$Xl
movdqa $Xln,$Xhn
pshufd \$0b01001110,$Xln,$Xmn
pxor $Xln,$Xmn
pclmulqdq \$0x00,$Hkey,$Xln
pclmulqdq \$0x11,$Hkey,$Xhn
pclmulqdq \$0x00,$HK,$Xmn
movdqa $Xl,$Xh
pshufd \$0b01001110,$Xl,$Xm
pxor $Xl,$Xm
pclmulqdq \$0x00,$Hkey2,$Xl
pclmulqdq \$0x11,$Hkey2,$Xh
pclmulqdq \$0x10,$HK,$Xm
xorps $Xl,$Xln
xorps $Xh,$Xhn
movups 0x50($Htbl),$HK
xorps $Xm,$Xmn
movdqu 0x10($inp),$Xl
movdqu 0($inp),$T1
pshufb $T3,$Xl
pshufb $T3,$T1
movdqa $Xl,$Xh
pshufd \$0b01001110,$Xl,$Xm
pxor $T1,$Xi
pxor $Xl,$Xm
pclmulqdq \$0x00,$Hkey3,$Xl
movdqa $Xi,$Xhi
pshufd \$0b01001110,$Xi,$T1
pxor $Xi,$T1
pclmulqdq \$0x11,$Hkey3,$Xh
pclmulqdq \$0x00,$HK,$Xm
xorps $Xl,$Xln
xorps $Xh,$Xhn
lea 0x40($inp),$inp
sub \$0x40,$len
jc .Ltail4x
jmp .Lmod4_loop
.align 32
.Lmod4_loop:
pclmulqdq \$0x00,$Hkey4,$Xi
xorps $Xm,$Xmn
movdqu 0x30($inp),$Xl
pshufb $T3,$Xl
pclmulqdq \$0x11,$Hkey4,$Xhi
xorps $Xln,$Xi
movdqu 0x20($inp),$Xln
movdqa $Xl,$Xh
pclmulqdq \$0x10,$HK,$T1
pshufd \$0b01001110,$Xl,$Xm
xorps $Xhn,$Xhi
pxor $Xl,$Xm
pshufb $T3,$Xln
movups 0x20($Htbl),$HK
xorps $Xmn,$T1
pclmulqdq \$0x00,$Hkey,$Xl
pshufd \$0b01001110,$Xln,$Xmn
pxor $Xi,$T1 # aggregated Karatsuba post-processing
movdqa $Xln,$Xhn
pxor $Xhi,$T1 #
pxor $Xln,$Xmn
movdqa $T1,$T2 #
pclmulqdq \$0x11,$Hkey,$Xh
pslldq \$8,$T1
psrldq \$8,$T2 #
pxor $T1,$Xi
movdqa .L7_mask(%rip),$T1
pxor $T2,$Xhi #
movq %rax,$T2
pand $Xi,$T1 # 1st phase
pshufb $T1,$T2 #
pxor $Xi,$T2 #
pclmulqdq \$0x00,$HK,$Xm
psllq \$57,$T2 #
movdqa $T2,$T1 #
pslldq \$8,$T2
pclmulqdq \$0x00,$Hkey2,$Xln
psrldq \$8,$T1 #
pxor $T2,$Xi
pxor $T1,$Xhi #
movdqu 0($inp),$T1
movdqa $Xi,$T2 # 2nd phase
psrlq \$1,$Xi
pclmulqdq \$0x11,$Hkey2,$Xhn
xorps $Xl,$Xln
movdqu 0x10($inp),$Xl
pshufb $T3,$Xl
pclmulqdq \$0x10,$HK,$Xmn
xorps $Xh,$Xhn
movups 0x50($Htbl),$HK
pshufb $T3,$T1
pxor $T2,$Xhi #
pxor $Xi,$T2
psrlq \$5,$Xi
movdqa $Xl,$Xh
pxor $Xm,$Xmn
pshufd \$0b01001110,$Xl,$Xm
pxor $T2,$Xi #
pxor $T1,$Xhi
pxor $Xl,$Xm
pclmulqdq \$0x00,$Hkey3,$Xl
psrlq \$1,$Xi #
pxor $Xhi,$Xi #
movdqa $Xi,$Xhi
pclmulqdq \$0x11,$Hkey3,$Xh
xorps $Xl,$Xln
pshufd \$0b01001110,$Xi,$T1
pxor $Xi,$T1
pclmulqdq \$0x00,$HK,$Xm
xorps $Xh,$Xhn
lea 0x40($inp),$inp
sub \$0x40,$len
jnc .Lmod4_loop
.Ltail4x:
pclmulqdq \$0x00,$Hkey4,$Xi
pclmulqdq \$0x11,$Hkey4,$Xhi
pclmulqdq \$0x10,$HK,$T1
xorps $Xm,$Xmn
xorps $Xln,$Xi
xorps $Xhn,$Xhi
pxor $Xi,$Xhi # aggregated Karatsuba post-processing
pxor $Xmn,$T1
pxor $Xhi,$T1 #
pxor $Xi,$Xhi
movdqa $T1,$T2 #
psrldq \$8,$T1
pslldq \$8,$T2 #
pxor $T1,$Xhi
pxor $T2,$Xi #
___
&reduction_alg9($Xhi,$Xi);
$code.=<<___;
add \$0x40,$len
jz .Ldone
movdqu 0x20($Htbl),$HK
sub \$0x10,$len
jz .Lodd_tail
.Lskip4x:
___
}
$code.=<<___;
#######
# Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
# [(H*Ii+1) + (H*Xi+1)] mod P =
# [(H*Ii+1) + H^2*(Ii+Xi)] mod P
#
movdqu ($inp),$T1 # Ii
movdqu 16($inp),$Xln # Ii+1
pshufb $T3,$T1
pshufb $T3,$Xln
pxor $T1,$Xi # Ii+Xi
movdqa $Xln,$Xhn
pshufd \$0b01001110,$Xln,$Xmn
pxor $Xln,$Xmn
pclmulqdq \$0x00,$Hkey,$Xln
pclmulqdq \$0x11,$Hkey,$Xhn
pclmulqdq \$0x00,$HK,$Xmn
lea 32($inp),$inp # i+=2
nop
sub \$0x20,$len
jbe .Leven_tail
nop
jmp .Lmod_loop
.align 32
.Lmod_loop:
movdqa $Xi,$Xhi
movdqa $Xmn,$T1
pshufd \$0b01001110,$Xi,$Xmn #
pxor $Xi,$Xmn #
pclmulqdq \$0x00,$Hkey2,$Xi
pclmulqdq \$0x11,$Hkey2,$Xhi
pclmulqdq \$0x10,$HK,$Xmn
pxor $Xln,$Xi # (H*Ii+1) + H^2*(Ii+Xi)
pxor $Xhn,$Xhi
movdqu ($inp),$T2 # Ii
pxor $Xi,$T1 # aggregated Karatsuba post-processing
pshufb $T3,$T2
movdqu 16($inp),$Xln # Ii+1
pxor $Xhi,$T1
pxor $T2,$Xhi # "Ii+Xi", consume early
pxor $T1,$Xmn
pshufb $T3,$Xln
movdqa $Xmn,$T1 #
psrldq \$8,$T1
pslldq \$8,$Xmn #
pxor $T1,$Xhi
pxor $Xmn,$Xi #
movdqa $Xln,$Xhn #
movdqa $Xi,$T2 # 1st phase
movdqa $Xi,$T1
psllq \$5,$Xi
pxor $Xi,$T1 #
pclmulqdq \$0x00,$Hkey,$Xln #######
psllq \$1,$Xi
pxor $T1,$Xi #
psllq \$57,$Xi #
movdqa $Xi,$T1 #
pslldq \$8,$Xi
psrldq \$8,$T1 #
pxor $T2,$Xi
pshufd \$0b01001110,$Xhn,$Xmn
pxor $T1,$Xhi #
pxor $Xhn,$Xmn #
movdqa $Xi,$T2 # 2nd phase
psrlq \$1,$Xi
pclmulqdq \$0x11,$Hkey,$Xhn #######
pxor $T2,$Xhi #
pxor $Xi,$T2
psrlq \$5,$Xi
pxor $T2,$Xi #
lea 32($inp),$inp
psrlq \$1,$Xi #
pclmulqdq \$0x00,$HK,$Xmn #######
pxor $Xhi,$Xi #
sub \$0x20,$len
ja .Lmod_loop
.Leven_tail:
movdqa $Xi,$Xhi
movdqa $Xmn,$T1
pshufd \$0b01001110,$Xi,$Xmn #
pxor $Xi,$Xmn #
pclmulqdq \$0x00,$Hkey2,$Xi
pclmulqdq \$0x11,$Hkey2,$Xhi
pclmulqdq \$0x10,$HK,$Xmn
pxor $Xln,$Xi # (H*Ii+1) + H^2*(Ii+Xi)
pxor $Xhn,$Xhi
pxor $Xi,$T1
pxor $Xhi,$T1
pxor $T1,$Xmn
movdqa $Xmn,$T1 #
psrldq \$8,$T1
pslldq \$8,$Xmn #
pxor $T1,$Xhi
pxor $Xmn,$Xi #
___
&reduction_alg9 ($Xhi,$Xi);
$code.=<<___;
test $len,$len
jnz .Ldone
.Lodd_tail:
movdqu ($inp),$T1 # Ii
pshufb $T3,$T1
pxor $T1,$Xi # Ii+Xi
___
&clmul64x64_T2 ($Xhi,$Xi,$Hkey,$HK); # H*(Ii+Xi)
&reduction_alg9 ($Xhi,$Xi);
$code.=<<___;
.Ldone:
pshufb $T3,$Xi
movdqu $Xi,($Xip)
___
$code.=<<___ if ($win64);
movaps (%rsp),%xmm6
movaps 0x10(%rsp),%xmm7
movaps 0x20(%rsp),%xmm8
movaps 0x30(%rsp),%xmm9
movaps 0x40(%rsp),%xmm10
movaps 0x50(%rsp),%xmm11
movaps 0x60(%rsp),%xmm12
movaps 0x70(%rsp),%xmm13
movaps 0x80(%rsp),%xmm14
movaps 0x90(%rsp),%xmm15
lea 0xa8(%rsp),%rsp
.LSEH_end_gcm_ghash_clmul:
___
$code.=<<___;
ret
.size gcm_ghash_clmul,.-gcm_ghash_clmul
___
}
$code.=<<___;
.globl gcm_init_avx
.type gcm_init_avx,\@abi-omnipotent
.align 32
gcm_init_avx:
___
if ($avx) {
my ($Htbl,$Xip)=@_4args;
my $HK="%xmm6";
$code.=<<___ if ($win64);
.LSEH_begin_gcm_init_avx:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x83,0xec,0x18 #sub $0x18,%rsp
.byte 0x0f,0x29,0x34,0x24 #movaps %xmm6,(%rsp)
___
$code.=<<___;
vzeroupper
vmovdqu ($Xip),$Hkey
vpshufd \$0b01001110,$Hkey,$Hkey # dword swap
# <<1 twist
vpshufd \$0b11111111,$Hkey,$T2 # broadcast uppermost dword
vpsrlq \$63,$Hkey,$T1
vpsllq \$1,$Hkey,$Hkey
vpxor $T3,$T3,$T3 #
vpcmpgtd $T2,$T3,$T3 # broadcast carry bit
vpslldq \$8,$T1,$T1
vpor $T1,$Hkey,$Hkey # H<<=1
# magic reduction
vpand .L0x1c2_polynomial(%rip),$T3,$T3
vpxor $T3,$Hkey,$Hkey # if(carry) H^=0x1c2_polynomial
vpunpckhqdq $Hkey,$Hkey,$HK
vmovdqa $Hkey,$Xi
vpxor $Hkey,$HK,$HK
mov \$4,%r10 # up to H^8
jmp .Linit_start_avx
___
sub clmul64x64_avx {
my ($Xhi,$Xi,$Hkey,$HK)=@_;
if (!defined($HK)) { $HK = $T2;
$code.=<<___;
vpunpckhqdq $Xi,$Xi,$T1
vpunpckhqdq $Hkey,$Hkey,$T2
vpxor $Xi,$T1,$T1 #
vpxor $Hkey,$T2,$T2
___
} else {
$code.=<<___;
vpunpckhqdq $Xi,$Xi,$T1
vpxor $Xi,$T1,$T1 #
___
}
$code.=<<___;
vpclmulqdq \$0x11,$Hkey,$Xi,$Xhi #######
vpclmulqdq \$0x00,$Hkey,$Xi,$Xi #######
vpclmulqdq \$0x00,$HK,$T1,$T1 #######
vpxor $Xi,$Xhi,$T2 #
vpxor $T2,$T1,$T1 #
vpslldq \$8,$T1,$T2 #
vpsrldq \$8,$T1,$T1
vpxor $T2,$Xi,$Xi #
vpxor $T1,$Xhi,$Xhi
___
}
sub reduction_avx {
my ($Xhi,$Xi) = @_;
$code.=<<___;
vpsllq \$57,$Xi,$T1 # 1st phase
vpsllq \$62,$Xi,$T2
vpxor $T1,$T2,$T2 #
vpsllq \$63,$Xi,$T1
vpxor $T1,$T2,$T2 #
vpslldq \$8,$T2,$T1 #
vpsrldq \$8,$T2,$T2
vpxor $T1,$Xi,$Xi #
vpxor $T2,$Xhi,$Xhi
vpsrlq \$1,$Xi,$T2 # 2nd phase
vpxor $Xi,$Xhi,$Xhi
vpxor $T2,$Xi,$Xi #
vpsrlq \$5,$T2,$T2
vpxor $T2,$Xi,$Xi #
vpsrlq \$1,$Xi,$Xi #
vpxor $Xhi,$Xi,$Xi #
___
}
$code.=<<___;
.align 32
.Linit_loop_avx:
vpalignr \$8,$T1,$T2,$T3 # low part is H.lo^H.hi...
vmovdqu $T3,-0x10($Htbl) # save Karatsuba "salt"
___
&clmul64x64_avx ($Xhi,$Xi,$Hkey,$HK); # calculate H^3,5,7
&reduction_avx ($Xhi,$Xi);
$code.=<<___;
.Linit_start_avx:
vmovdqa $Xi,$T3
___
&clmul64x64_avx ($Xhi,$Xi,$Hkey,$HK); # calculate H^2,4,6,8
&reduction_avx ($Xhi,$Xi);
$code.=<<___;
vpshufd \$0b01001110,$T3,$T1
vpshufd \$0b01001110,$Xi,$T2
vpxor $T3,$T1,$T1 # Karatsuba pre-processing
vmovdqu $T3,0x00($Htbl) # save H^1,3,5,7
vpxor $Xi,$T2,$T2 # Karatsuba pre-processing
vmovdqu $Xi,0x10($Htbl) # save H^2,4,6,8
lea 0x30($Htbl),$Htbl
sub \$1,%r10
jnz .Linit_loop_avx
vpalignr \$8,$T2,$T1,$T3 # last "salt" is flipped
vmovdqu $T3,-0x10($Htbl)
vzeroupper
___
$code.=<<___ if ($win64);
movaps (%rsp),%xmm6
lea 0x18(%rsp),%rsp
.LSEH_end_gcm_init_avx:
___
$code.=<<___;
ret
.size gcm_init_avx,.-gcm_init_avx
___
} else {
$code.=<<___;
jmp .L_init_clmul
.size gcm_init_avx,.-gcm_init_avx
___
}
$code.=<<___;
.globl gcm_gmult_avx
.type gcm_gmult_avx,\@abi-omnipotent
.align 32
gcm_gmult_avx:
jmp .L_gmult_clmul
.size gcm_gmult_avx,.-gcm_gmult_avx
___
$code.=<<___;
.globl gcm_ghash_avx
.type gcm_ghash_avx,\@abi-omnipotent
.align 32
gcm_ghash_avx:
___
if ($avx) {
my ($Xip,$Htbl,$inp,$len)=@_4args;
my ($Xlo,$Xhi,$Xmi,
$Zlo,$Zhi,$Zmi,
$Hkey,$HK,$T1,$T2,
$Xi,$Xo,$Tred,$bswap,$Ii,$Ij) = map("%xmm$_",(0..15));
$code.=<<___ if ($win64);
lea -0x88(%rsp),%rax
.LSEH_begin_gcm_ghash_avx:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x8d,0x60,0xe0 #lea -0x20(%rax),%rsp
.byte 0x0f,0x29,0x70,0xe0 #movaps %xmm6,-0x20(%rax)
.byte 0x0f,0x29,0x78,0xf0 #movaps %xmm7,-0x10(%rax)
.byte 0x44,0x0f,0x29,0x00 #movaps %xmm8,0(%rax)
.byte 0x44,0x0f,0x29,0x48,0x10 #movaps %xmm9,0x10(%rax)
.byte 0x44,0x0f,0x29,0x50,0x20 #movaps %xmm10,0x20(%rax)
.byte 0x44,0x0f,0x29,0x58,0x30 #movaps %xmm11,0x30(%rax)
.byte 0x44,0x0f,0x29,0x60,0x40 #movaps %xmm12,0x40(%rax)
.byte 0x44,0x0f,0x29,0x68,0x50 #movaps %xmm13,0x50(%rax)
.byte 0x44,0x0f,0x29,0x70,0x60 #movaps %xmm14,0x60(%rax)
.byte 0x44,0x0f,0x29,0x78,0x70 #movaps %xmm15,0x70(%rax)
___
$code.=<<___;
vzeroupper
vmovdqu ($Xip),$Xi # load $Xi
lea .L0x1c2_polynomial(%rip),%r10
lea 0x40($Htbl),$Htbl # size optimization
vmovdqu .Lbswap_mask(%rip),$bswap
vpshufb $bswap,$Xi,$Xi
cmp \$0x80,$len
jb .Lshort_avx
sub \$0x80,$len
vmovdqu 0x70($inp),$Ii # I[7]
vmovdqu 0x00-0x40($Htbl),$Hkey # $Hkey^1
vpshufb $bswap,$Ii,$Ii
vmovdqu 0x20-0x40($Htbl),$HK
vpunpckhqdq $Ii,$Ii,$T2
vmovdqu 0x60($inp),$Ij # I[6]
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpxor $Ii,$T2,$T2
vpshufb $bswap,$Ij,$Ij
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0x10-0x40($Htbl),$Hkey # $Hkey^2
vpunpckhqdq $Ij,$Ij,$T1
vmovdqu 0x50($inp),$Ii # I[5]
vpclmulqdq \$0x00,$HK,$T2,$Xmi
vpxor $Ij,$T1,$T1
vpshufb $bswap,$Ii,$Ii
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpunpckhqdq $Ii,$Ii,$T2
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vmovdqu 0x30-0x40($Htbl),$Hkey # $Hkey^3
vpxor $Ii,$T2,$T2
vmovdqu 0x40($inp),$Ij # I[4]
vpclmulqdq \$0x10,$HK,$T1,$Zmi
vmovdqu 0x50-0x40($Htbl),$HK
vpshufb $bswap,$Ij,$Ij
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpxor $Xhi,$Zhi,$Zhi
vpunpckhqdq $Ij,$Ij,$T1
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0x40-0x40($Htbl),$Hkey # $Hkey^4
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T2,$Xmi
vpxor $Ij,$T1,$T1
vmovdqu 0x30($inp),$Ii # I[3]
vpxor $Zlo,$Xlo,$Xlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpxor $Zhi,$Xhi,$Xhi
vpshufb $bswap,$Ii,$Ii
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vmovdqu 0x60-0x40($Htbl),$Hkey # $Hkey^5
vpxor $Zmi,$Xmi,$Xmi
vpunpckhqdq $Ii,$Ii,$T2
vpclmulqdq \$0x10,$HK,$T1,$Zmi
vmovdqu 0x80-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vmovdqu 0x20($inp),$Ij # I[2]
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpxor $Xhi,$Zhi,$Zhi
vpshufb $bswap,$Ij,$Ij
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0x70-0x40($Htbl),$Hkey # $Hkey^6
vpxor $Xmi,$Zmi,$Zmi
vpunpckhqdq $Ij,$Ij,$T1
vpclmulqdq \$0x00,$HK,$T2,$Xmi
vpxor $Ij,$T1,$T1
vmovdqu 0x10($inp),$Ii # I[1]
vpxor $Zlo,$Xlo,$Xlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpxor $Zhi,$Xhi,$Xhi
vpshufb $bswap,$Ii,$Ii
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vmovdqu 0x90-0x40($Htbl),$Hkey # $Hkey^7
vpxor $Zmi,$Xmi,$Xmi
vpunpckhqdq $Ii,$Ii,$T2
vpclmulqdq \$0x10,$HK,$T1,$Zmi
vmovdqu 0xb0-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vmovdqu ($inp),$Ij # I[0]
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpxor $Xhi,$Zhi,$Zhi
vpshufb $bswap,$Ij,$Ij
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0xa0-0x40($Htbl),$Hkey # $Hkey^8
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x10,$HK,$T2,$Xmi
lea 0x80($inp),$inp
cmp \$0x80,$len
jb .Ltail_avx
vpxor $Xi,$Ij,$Ij # accumulate $Xi
sub \$0x80,$len
jmp .Loop8x_avx
.align 32
.Loop8x_avx:
vpunpckhqdq $Ij,$Ij,$T1
vmovdqu 0x70($inp),$Ii # I[7]
vpxor $Xlo,$Zlo,$Zlo
vpxor $Ij,$T1,$T1
vpclmulqdq \$0x00,$Hkey,$Ij,$Xi
vpshufb $bswap,$Ii,$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xo
vmovdqu 0x00-0x40($Htbl),$Hkey # $Hkey^1
vpunpckhqdq $Ii,$Ii,$T2
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Tred
vmovdqu 0x20-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vmovdqu 0x60($inp),$Ij # I[6]
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpxor $Zlo,$Xi,$Xi # collect result
vpshufb $bswap,$Ij,$Ij
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vxorps $Zhi,$Xo,$Xo
vmovdqu 0x10-0x40($Htbl),$Hkey # $Hkey^2
vpunpckhqdq $Ij,$Ij,$T1
vpclmulqdq \$0x00,$HK, $T2,$Xmi
vpxor $Zmi,$Tred,$Tred
vxorps $Ij,$T1,$T1
vmovdqu 0x50($inp),$Ii # I[5]
vpxor $Xi,$Tred,$Tred # aggregated Karatsuba post-processing
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpxor $Xo,$Tred,$Tred
vpslldq \$8,$Tred,$T2
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vpsrldq \$8,$Tred,$Tred
vpxor $T2, $Xi, $Xi
vmovdqu 0x30-0x40($Htbl),$Hkey # $Hkey^3
vpshufb $bswap,$Ii,$Ii
vxorps $Tred,$Xo, $Xo
vpxor $Xhi,$Zhi,$Zhi
vpunpckhqdq $Ii,$Ii,$T2
vpclmulqdq \$0x10,$HK, $T1,$Zmi
vmovdqu 0x50-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vpxor $Xmi,$Zmi,$Zmi
vmovdqu 0x40($inp),$Ij # I[4]
vpalignr \$8,$Xi,$Xi,$Tred # 1st phase
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpshufb $bswap,$Ij,$Ij
vpxor $Zlo,$Xlo,$Xlo
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0x40-0x40($Htbl),$Hkey # $Hkey^4
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Zhi,$Xhi,$Xhi
vpclmulqdq \$0x00,$HK, $T2,$Xmi
vxorps $Ij,$T1,$T1
vpxor $Zmi,$Xmi,$Xmi
vmovdqu 0x30($inp),$Ii # I[3]
vpclmulqdq \$0x10,(%r10),$Xi,$Xi
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpshufb $bswap,$Ii,$Ii
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vmovdqu 0x60-0x40($Htbl),$Hkey # $Hkey^5
vpunpckhqdq $Ii,$Ii,$T2
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x10,$HK, $T1,$Zmi
vmovdqu 0x80-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vpxor $Xmi,$Zmi,$Zmi
vmovdqu 0x20($inp),$Ij # I[2]
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpshufb $bswap,$Ij,$Ij
vpxor $Zlo,$Xlo,$Xlo
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0x70-0x40($Htbl),$Hkey # $Hkey^6
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Zhi,$Xhi,$Xhi
vpclmulqdq \$0x00,$HK, $T2,$Xmi
vpxor $Ij,$T1,$T1
vpxor $Zmi,$Xmi,$Xmi
vxorps $Tred,$Xi,$Xi
vmovdqu 0x10($inp),$Ii # I[1]
vpalignr \$8,$Xi,$Xi,$Tred # 2nd phase
vpclmulqdq \$0x00,$Hkey,$Ij,$Zlo
vpshufb $bswap,$Ii,$Ii
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x11,$Hkey,$Ij,$Zhi
vmovdqu 0x90-0x40($Htbl),$Hkey # $Hkey^7
vpclmulqdq \$0x10,(%r10),$Xi,$Xi
vxorps $Xo,$Tred,$Tred
vpunpckhqdq $Ii,$Ii,$T2
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x10,$HK, $T1,$Zmi
vmovdqu 0xb0-0x40($Htbl),$HK
vpxor $Ii,$T2,$T2
vpxor $Xmi,$Zmi,$Zmi
vmovdqu ($inp),$Ij # I[0]
vpclmulqdq \$0x00,$Hkey,$Ii,$Xlo
vpshufb $bswap,$Ij,$Ij
vpclmulqdq \$0x11,$Hkey,$Ii,$Xhi
vmovdqu 0xa0-0x40($Htbl),$Hkey # $Hkey^8
vpxor $Tred,$Ij,$Ij
vpclmulqdq \$0x10,$HK, $T2,$Xmi
vpxor $Xi,$Ij,$Ij # accumulate $Xi
lea 0x80($inp),$inp
sub \$0x80,$len
jnc .Loop8x_avx
add \$0x80,$len
jmp .Ltail_no_xor_avx
.align 32
.Lshort_avx:
vmovdqu -0x10($inp,$len),$Ii # very last word
lea ($inp,$len),$inp
vmovdqu 0x00-0x40($Htbl),$Hkey # $Hkey^1
vmovdqu 0x20-0x40($Htbl),$HK
vpshufb $bswap,$Ii,$Ij
vmovdqa $Xlo,$Zlo # subtle way to zero $Zlo,
vmovdqa $Xhi,$Zhi # $Zhi and
vmovdqa $Xmi,$Zmi # $Zmi
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x20($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x10-0x40($Htbl),$Hkey # $Hkey^2
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vpsrldq \$8,$HK,$HK
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x30($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x30-0x40($Htbl),$Hkey # $Hkey^3
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vmovdqu 0x50-0x40($Htbl),$HK
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x40($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x40-0x40($Htbl),$Hkey # $Hkey^4
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vpsrldq \$8,$HK,$HK
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x50($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x60-0x40($Htbl),$Hkey # $Hkey^5
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vmovdqu 0x80-0x40($Htbl),$HK
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x60($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x70-0x40($Htbl),$Hkey # $Hkey^6
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vpsrldq \$8,$HK,$HK
sub \$0x10,$len
jz .Ltail_avx
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vmovdqu -0x70($inp),$Ii
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vmovdqu 0x90-0x40($Htbl),$Hkey # $Hkey^7
vpshufb $bswap,$Ii,$Ij
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vmovq 0xb8-0x40($Htbl),$HK
sub \$0x10,$len
jmp .Ltail_avx
.align 32
.Ltail_avx:
vpxor $Xi,$Ij,$Ij # accumulate $Xi
.Ltail_no_xor_avx:
vpunpckhqdq $Ij,$Ij,$T1
vpxor $Xlo,$Zlo,$Zlo
vpclmulqdq \$0x00,$Hkey,$Ij,$Xlo
vpxor $Ij,$T1,$T1
vpxor $Xhi,$Zhi,$Zhi
vpclmulqdq \$0x11,$Hkey,$Ij,$Xhi
vpxor $Xmi,$Zmi,$Zmi
vpclmulqdq \$0x00,$HK,$T1,$Xmi
vmovdqu (%r10),$Tred
vpxor $Xlo,$Zlo,$Xi
vpxor $Xhi,$Zhi,$Xo
vpxor $Xmi,$Zmi,$Zmi
vpxor $Xi, $Zmi,$Zmi # aggregated Karatsuba post-processing
vpxor $Xo, $Zmi,$Zmi
vpslldq \$8, $Zmi,$T2
vpsrldq \$8, $Zmi,$Zmi
vpxor $T2, $Xi, $Xi
vpxor $Zmi,$Xo, $Xo
vpclmulqdq \$0x10,$Tred,$Xi,$T2 # 1st phase
vpalignr \$8,$Xi,$Xi,$Xi
vpxor $T2,$Xi,$Xi
vpclmulqdq \$0x10,$Tred,$Xi,$T2 # 2nd phase
vpalignr \$8,$Xi,$Xi,$Xi
vpxor $Xo,$Xi,$Xi
vpxor $T2,$Xi,$Xi
cmp \$0,$len
jne .Lshort_avx
vpshufb $bswap,$Xi,$Xi
vmovdqu $Xi,($Xip)
vzeroupper
___
$code.=<<___ if ($win64);
movaps (%rsp),%xmm6
movaps 0x10(%rsp),%xmm7
movaps 0x20(%rsp),%xmm8
movaps 0x30(%rsp),%xmm9
movaps 0x40(%rsp),%xmm10
movaps 0x50(%rsp),%xmm11
movaps 0x60(%rsp),%xmm12
movaps 0x70(%rsp),%xmm13
movaps 0x80(%rsp),%xmm14
movaps 0x90(%rsp),%xmm15
lea 0xa8(%rsp),%rsp
.LSEH_end_gcm_ghash_avx:
___
$code.=<<___;
ret
.size gcm_ghash_avx,.-gcm_ghash_avx
___
} else {
$code.=<<___;
jmp .L_ghash_clmul
.size gcm_ghash_avx,.-gcm_ghash_avx
___
}
$code.=<<___;
.align 64
.Lbswap_mask:
.byte 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
.L0x1c2_polynomial:
.byte 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0xc2
.L7_mask:
.long 7,0,7,0
.L7_mask_poly:
.long 7,0,`0xE1<<1`,0
.align 64
.type .Lrem_4bit,\@object
.Lrem_4bit:
.long 0,`0x0000<<16`,0,`0x1C20<<16`,0,`0x3840<<16`,0,`0x2460<<16`
.long 0,`0x7080<<16`,0,`0x6CA0<<16`,0,`0x48C0<<16`,0,`0x54E0<<16`
.long 0,`0xE100<<16`,0,`0xFD20<<16`,0,`0xD940<<16`,0,`0xC560<<16`
.long 0,`0x9180<<16`,0,`0x8DA0<<16`,0,`0xA9C0<<16`,0,`0xB5E0<<16`
.type .Lrem_8bit,\@object
.Lrem_8bit:
.value 0x0000,0x01C2,0x0384,0x0246,0x0708,0x06CA,0x048C,0x054E
.value 0x0E10,0x0FD2,0x0D94,0x0C56,0x0918,0x08DA,0x0A9C,0x0B5E
.value 0x1C20,0x1DE2,0x1FA4,0x1E66,0x1B28,0x1AEA,0x18AC,0x196E
.value 0x1230,0x13F2,0x11B4,0x1076,0x1538,0x14FA,0x16BC,0x177E
.value 0x3840,0x3982,0x3BC4,0x3A06,0x3F48,0x3E8A,0x3CCC,0x3D0E
.value 0x3650,0x3792,0x35D4,0x3416,0x3158,0x309A,0x32DC,0x331E
.value 0x2460,0x25A2,0x27E4,0x2626,0x2368,0x22AA,0x20EC,0x212E
.value 0x2A70,0x2BB2,0x29F4,0x2836,0x2D78,0x2CBA,0x2EFC,0x2F3E
.value 0x7080,0x7142,0x7304,0x72C6,0x7788,0x764A,0x740C,0x75CE
.value 0x7E90,0x7F52,0x7D14,0x7CD6,0x7998,0x785A,0x7A1C,0x7BDE
.value 0x6CA0,0x6D62,0x6F24,0x6EE6,0x6BA8,0x6A6A,0x682C,0x69EE
.value 0x62B0,0x6372,0x6134,0x60F6,0x65B8,0x647A,0x663C,0x67FE
.value 0x48C0,0x4902,0x4B44,0x4A86,0x4FC8,0x4E0A,0x4C4C,0x4D8E
.value 0x46D0,0x4712,0x4554,0x4496,0x41D8,0x401A,0x425C,0x439E
.value 0x54E0,0x5522,0x5764,0x56A6,0x53E8,0x522A,0x506C,0x51AE
.value 0x5AF0,0x5B32,0x5974,0x58B6,0x5DF8,0x5C3A,0x5E7C,0x5FBE
.value 0xE100,0xE0C2,0xE284,0xE346,0xE608,0xE7CA,0xE58C,0xE44E
.value 0xEF10,0xEED2,0xEC94,0xED56,0xE818,0xE9DA,0xEB9C,0xEA5E
.value 0xFD20,0xFCE2,0xFEA4,0xFF66,0xFA28,0xFBEA,0xF9AC,0xF86E
.value 0xF330,0xF2F2,0xF0B4,0xF176,0xF438,0xF5FA,0xF7BC,0xF67E
.value 0xD940,0xD882,0xDAC4,0xDB06,0xDE48,0xDF8A,0xDDCC,0xDC0E
.value 0xD750,0xD692,0xD4D4,0xD516,0xD058,0xD19A,0xD3DC,0xD21E
.value 0xC560,0xC4A2,0xC6E4,0xC726,0xC268,0xC3AA,0xC1EC,0xC02E
.value 0xCB70,0xCAB2,0xC8F4,0xC936,0xCC78,0xCDBA,0xCFFC,0xCE3E
.value 0x9180,0x9042,0x9204,0x93C6,0x9688,0x974A,0x950C,0x94CE
.value 0x9F90,0x9E52,0x9C14,0x9DD6,0x9898,0x995A,0x9B1C,0x9ADE
.value 0x8DA0,0x8C62,0x8E24,0x8FE6,0x8AA8,0x8B6A,0x892C,0x88EE
.value 0x83B0,0x8272,0x8034,0x81F6,0x84B8,0x857A,0x873C,0x86FE
.value 0xA9C0,0xA802,0xAA44,0xAB86,0xAEC8,0xAF0A,0xAD4C,0xAC8E
.value 0xA7D0,0xA612,0xA454,0xA596,0xA0D8,0xA11A,0xA35C,0xA29E
.value 0xB5E0,0xB422,0xB664,0xB7A6,0xB2E8,0xB32A,0xB16C,0xB0AE
.value 0xBBF0,0xBA32,0xB874,0xB9B6,0xBCF8,0xBD3A,0xBF7C,0xBEBE
.asciz "GHASH for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
.align 64
___
# EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
# CONTEXT *context,DISPATCHER_CONTEXT *disp)
if ($win64) {
$rec="%rcx";
$frame="%rdx";
$context="%r8";
$disp="%r9";
$code.=<<___;
.extern __imp_RtlVirtualUnwind
.type se_handler,\@abi-omnipotent
.align 16
se_handler:
push %rsi
push %rdi
push %rbx
push %rbp
push %r12
push %r13
push %r14
push %r15
pushfq
sub \$64,%rsp
mov 120($context),%rax # pull context->Rax
mov 248($context),%rbx # pull context->Rip
mov 8($disp),%rsi # disp->ImageBase
mov 56($disp),%r11 # disp->HandlerData
mov 0(%r11),%r10d # HandlerData[0]
lea (%rsi,%r10),%r10 # prologue label
cmp %r10,%rbx # context->Rip<prologue label
jb .Lin_prologue
mov 152($context),%rax # pull context->Rsp
mov 4(%r11),%r10d # HandlerData[1]
lea (%rsi,%r10),%r10 # epilogue label
cmp %r10,%rbx # context->Rip>=epilogue label
jae .Lin_prologue
lea 24(%rax),%rax # adjust "rsp"
mov -8(%rax),%rbx
mov -16(%rax),%rbp
mov -24(%rax),%r12
mov %rbx,144($context) # restore context->Rbx
mov %rbp,160($context) # restore context->Rbp
mov %r12,216($context) # restore context->R12
.Lin_prologue:
mov 8(%rax),%rdi
mov 16(%rax),%rsi
mov %rax,152($context) # restore context->Rsp
mov %rsi,168($context) # restore context->Rsi
mov %rdi,176($context) # restore context->Rdi
mov 40($disp),%rdi # disp->ContextRecord
mov $context,%rsi # context
mov \$`1232/8`,%ecx # sizeof(CONTEXT)
.long 0xa548f3fc # cld; rep movsq
mov $disp,%rsi
xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
mov 8(%rsi),%rdx # arg2, disp->ImageBase
mov 0(%rsi),%r8 # arg3, disp->ControlPc
mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
mov 40(%rsi),%r10 # disp->ContextRecord
lea 56(%rsi),%r11 # &disp->HandlerData
lea 24(%rsi),%r12 # &disp->EstablisherFrame
mov %r10,32(%rsp) # arg5
mov %r11,40(%rsp) # arg6
mov %r12,48(%rsp) # arg7
mov %rcx,56(%rsp) # arg8, (NULL)
call *__imp_RtlVirtualUnwind(%rip)
mov \$1,%eax # ExceptionContinueSearch
add \$64,%rsp
popfq
pop %r15
pop %r14
pop %r13
pop %r12
pop %rbp
pop %rbx
pop %rdi
pop %rsi
ret
.size se_handler,.-se_handler
.section .pdata
.align 4
.rva .LSEH_begin_gcm_gmult_4bit
.rva .LSEH_end_gcm_gmult_4bit
.rva .LSEH_info_gcm_gmult_4bit
.rva .LSEH_begin_gcm_ghash_4bit
.rva .LSEH_end_gcm_ghash_4bit
.rva .LSEH_info_gcm_ghash_4bit
.rva .LSEH_begin_gcm_init_clmul
.rva .LSEH_end_gcm_init_clmul
.rva .LSEH_info_gcm_init_clmul
.rva .LSEH_begin_gcm_ghash_clmul
.rva .LSEH_end_gcm_ghash_clmul
.rva .LSEH_info_gcm_ghash_clmul
___
$code.=<<___ if ($avx);
.rva .LSEH_begin_gcm_init_avx
.rva .LSEH_end_gcm_init_avx
.rva .LSEH_info_gcm_init_clmul
.rva .LSEH_begin_gcm_ghash_avx
.rva .LSEH_end_gcm_ghash_avx
.rva .LSEH_info_gcm_ghash_clmul
___
$code.=<<___;
.section .xdata
.align 8
.LSEH_info_gcm_gmult_4bit:
.byte 9,0,0,0
.rva se_handler
.rva .Lgmult_prologue,.Lgmult_epilogue # HandlerData
.LSEH_info_gcm_ghash_4bit:
.byte 9,0,0,0
.rva se_handler
.rva .Lghash_prologue,.Lghash_epilogue # HandlerData
.LSEH_info_gcm_init_clmul:
.byte 0x01,0x08,0x03,0x00
.byte 0x08,0x68,0x00,0x00 #movaps 0x00(rsp),xmm6
.byte 0x04,0x22,0x00,0x00 #sub rsp,0x18
.LSEH_info_gcm_ghash_clmul:
.byte 0x01,0x33,0x16,0x00
.byte 0x33,0xf8,0x09,0x00 #movaps 0x90(rsp),xmm15
.byte 0x2e,0xe8,0x08,0x00 #movaps 0x80(rsp),xmm14
.byte 0x29,0xd8,0x07,0x00 #movaps 0x70(rsp),xmm13
.byte 0x24,0xc8,0x06,0x00 #movaps 0x60(rsp),xmm12
.byte 0x1f,0xb8,0x05,0x00 #movaps 0x50(rsp),xmm11
.byte 0x1a,0xa8,0x04,0x00 #movaps 0x40(rsp),xmm10
.byte 0x15,0x98,0x03,0x00 #movaps 0x30(rsp),xmm9
.byte 0x10,0x88,0x02,0x00 #movaps 0x20(rsp),xmm8
.byte 0x0c,0x78,0x01,0x00 #movaps 0x10(rsp),xmm7
.byte 0x08,0x68,0x00,0x00 #movaps 0x00(rsp),xmm6
.byte 0x04,0x01,0x15,0x00 #sub rsp,0xa8
___
}
$code =~ s/\`([^\`]*)\`/eval($1)/gem;
print $code;
close STDOUT;
| {
"language": "Assembly"
} |
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 25-June-2015
;* Description : STM32F746xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M7 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
; 2017-01-04 William R Sowerbutts
.module devrd_hw
.z180
; exported symbols
.globl _rd_platform_copy
.globl _rd_cpy_count
.globl _rd_reverse
.globl _rd_dst_userspace
.globl _rd_dst_address
.globl _rd_src_address
.globl _devmem_read
.globl _devmem_write
.include "kernel.def"
.include "../kernel-z80.def"
.include "../cpu-z180/z180.def"
.area _CODE
_devmem_write:
ld a, #1
ld (_rd_reverse), a ; 1 = write
jr _devmem_go
_devmem_read:
xor a
ld (_rd_reverse), a ; 0 = read
inc a
_devmem_go:
ld (_rd_dst_userspace), a ; 1 = userspace
; load the other parameters
ld hl, (_udata + U_DATA__U_BASE)
ld (_rd_dst_address), hl
ld hl, (_udata + U_DATA__U_COUNT)
ld (_rd_cpy_count), hl
ld hl, (_udata + U_DATA__U_OFFSET)
ld (_rd_src_address), hl
ld hl, (_udata + U_DATA__U_OFFSET+2)
ld (_rd_src_address+2), hl
; FALL THROUGH INTO _rd_platform_copy
;=========================================================================
; _rd_page_copy - Copy data from one physical page to another
; See notes in devrd.h for input parameters
; This code is Z180 specific so can safely use ld a,i
;=========================================================================
_rd_platform_copy:
; save interrupt flag on stack then disable interrupts
ld a, i
push af
di
; load source page number
ld de, (_rd_src_address+1) ; and +2
ld a, (_rd_src_address+0)
ld b, a
; compute destination
ld a,(_rd_dst_userspace) ; are we loading into userspace memory?
or a
jr nz, rd_translate_userspace
ld hl, #(OS_BANK + FIRST_RAM_BANK) << 4
jr rd_done_translate
rd_translate_userspace:
ld hl,(_udata + U_DATA__U_PAGE) ; load page number
add hl, hl ; shift left 4 bits
add hl, hl
add hl, hl
add hl, hl
rd_done_translate:
; add in page offset
ld a,(_rd_dst_address+1) ; top 8 bits of address
add a, l
ld l, a
adc a, h
sub l
ld h, a ; result in hl
ld a,(_rd_dst_address+0)
ld c, a
ld a,(_rd_reverse)
or a
jr z,not_reversed
ex de, hl
out0 (DMA_SAR0L),c
out0 (DMA_DAR0L),b
jr topbits
not_reversed:
out0 (DMA_SAR0L),b
out0 (DMA_DAR0L),c
topbits:
out0 (DMA_SAR0B),d
out0 (DMA_SAR0H),e
out0 (DMA_DAR0B),h
out0 (DMA_DAR0H),l
ld hl,(_rd_cpy_count)
out0 (DMA_BCR0L),l
out0 (DMA_BCR0H),h
; make dma go
ld bc, #0x0240
out0 (DMA_DMODE), b ; 0x02 - memory to memory, burst mode
out0 (DMA_DSTAT), c ; 0x40 - enable DMA channel 0
; CPU stalls until DMA burst completes
; recover interrupt flag from stack and restore ints if required
pop af
ret po
ei
ret ; return with HL=_rd_cpy_count, as required by char device drivers
; variables
_rd_cpy_count:
.dw 0 ; uint16_t
_rd_reverse:
.db 0 ; bool
_rd_dst_userspace:
.db 0 ; bool
_rd_dst_address:
.dw 0 ; uint16_t
_rd_src_address:
.db 0 ; uint32_t
.db 0
.db 0
.db 0
;=========================================================================
| {
"language": "Assembly"
} |
/*
synth_stereo_neon_accurate: ARM NEON optimized synth (stereo specific, MPEG compliant 16-bit output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0L r1
#define B0R r2
#define SAMPLES r3
/*
int synth_1to1_s_neon_accurate_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples
*/
.code 32
#ifndef __APPLE__
.fpu neon
#endif
.text
.globl ASM_NAME(synth_1to1_s_neon_accurate_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s_neon_accurate_asm), %function
#endif
ASM_NAME(synth_1to1_s_neon_accurate_asm):
push {r4-r7, lr}
vpush {q4-q7}
ldr r4, [sp, #84]
mov r7, sp
sub sp, sp, #16
bic sp, #0xff
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r4, lsl #2
mov r4, #4
mov r5, #128
mov r6, #64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r4, #4
mov r6, #-64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
subs r4, r4, #1
bne 1b
vld1.32 {q0}, [sp, :128]
vpadd.i32 d0, d0, d1
vpadd.i32 d0, d0, d0
vmov.32 r0, d0[0]
mov sp, r7
vpop {q4-q7}
pop {r4-r7, pc}
NONEXEC_STACK
| {
"language": "Assembly"
} |
#if 0
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// fxc /Zpc /Tps_4_0 /Emain /D __INST__=40 /D __EFFEKSEER_BUILD_VERSION16__=1
// /Fh ShaderHeader/EffekseerRenderer.ModelRenderer.ShaderTexture_PS.h
// Shader/model_renderer_texture_PS.fx
//
//
// Buffer Definitions:
//
// cbuffer PS_ConstanBuffer
// {
//
// float4 fLightDirection; // Offset: 0 Size: 16 [unused]
// float4 fLightColor; // Offset: 16 Size: 16 [unused]
// float4 fLightAmbient; // Offset: 32 Size: 16 [unused]
// float4 fFlipbookParameter; // Offset: 48 Size: 16
// float4 fUVDistortionParameter; // Offset: 64 Size: 16
// float4 fBlendTextureParameter; // Offset: 80 Size: 16
// float4 fCameraFrontDirection; // Offset: 96 Size: 16
//
// struct
// {
//
// float4 Param; // Offset: 112
// float4 BeginColor; // Offset: 128
// float4 EndColor; // Offset: 144
//
// } fFalloffParam; // Offset: 112 Size: 48
// float4 fEmissiveScaling; // Offset: 160 Size: 16
// float4 fEdgeColor; // Offset: 176 Size: 16
// float4 fEdgeParameter; // Offset: 192 Size: 16
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// g_colorSampler sampler NA NA 0 1
// g_alphaSampler sampler NA NA 2 1
// g_uvDistortionSampler sampler NA NA 3 1
// g_blendSampler sampler NA NA 4 1
// g_blendAlphaSampler sampler NA NA 5 1
// g_blendUVDistortionSampler sampler NA NA 6 1
// g_colorTexture texture float4 2d 0 1
// g_alphaTexture texture float4 2d 2 1
// g_uvDistortionTexture texture float4 2d 3 1
// g_blendTexture texture float4 2d 4 1
// g_blendAlphaTexture texture float4 2d 5 1
// g_blendUVDistortionTexture texture float4 2d 6 1
// PS_ConstanBuffer cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_POSITION 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 7 zw 1 NONE float zw
// TEXCOORD 1 xyz 2 NONE float xyz
// TEXCOORD 2 xyz 3 NONE float
// TEXCOORD 3 xyz 4 NONE float
// COLOR 0 xyzw 5 NONE float xyzw
// TEXCOORD 4 xyzw 6 NONE float xyzw
// TEXCOORD 5 xyzw 7 NONE float xyzw
// TEXCOORD 6 xyzw 8 NONE float xyzw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
ps_4_0
dcl_constantbuffer cb0[13], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s2, mode_default
dcl_sampler s3, mode_default
dcl_sampler s4, mode_default
dcl_sampler s5, mode_default
dcl_sampler s6, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t2
dcl_resource_texture2d (float,float,float,float) t3
dcl_resource_texture2d (float,float,float,float) t4
dcl_resource_texture2d (float,float,float,float) t5
dcl_resource_texture2d (float,float,float,float) t6
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_input_ps linear v2.xyz
dcl_input_ps linear v5.xyzw
dcl_input_ps linear v6.xyzw
dcl_input_ps linear v7.xyzw
dcl_input_ps linear v8.xyzw
dcl_output o0.xyzw
dcl_temps 7
sample r0.xyzw, v6.zwzz, t3.xyzw, s3
mad r0.xy, r0.xyxx, l(2.000000, 2.000000, 0.000000, 0.000000), l(-1.000000, -1.000000, 0.000000, 0.000000)
mad r0.z, -r0.y, cb0[4].w, cb0[4].z
mad r0.yw, r0.xxxz, cb0[4].xxxx, v1.xxxy
sample r1.xyzw, r0.ywyy, t0.xyzw, s0
mul r1.xyzw, r1.xyzw, v5.xyzw
lt r0.y, l(0.000000), cb0[3].x
if_nz r0.y
mad r0.yw, r0.xxxz, cb0[4].xxxx, v8.zzzw
sample r2.xyzw, r0.ywyy, t0.xyzw, s0
eq r0.y, cb0[3].y, l(1.000000)
mad r2.xyzw, r2.xyzw, v5.xyzw, -r1.xyzw
mad r2.xyzw, v1.zzzz, r2.xyzw, r1.xyzw
movc r1.xyzw, r0.yyyy, r2.xyzw, r1.xyzw
endif
mad r0.xy, r0.xzxx, cb0[4].xxxx, v6.xyxx
sample r0.xyzw, r0.xyxx, t2.xyzw, s2
mul r0.x, r0.w, r0.x
mul r0.w, r0.x, r1.w
sample r2.xyzw, v7.zwzz, t6.xyzw, s6
mad r2.xy, r2.xyxx, l(2.000000, 2.000000, 0.000000, 0.000000), l(-1.000000, -1.000000, 0.000000, 0.000000)
mad r2.z, -r2.y, cb0[4].w, cb0[4].z
mad r2.yw, r2.xxxz, cb0[4].yyyy, v8.xxxy
sample r3.xyzw, r2.ywyy, t4.xyzw, s4
mad r2.xy, r2.xzxx, cb0[4].yyyy, v7.xyxx
sample r2.xyzw, r2.xyxx, t5.xyzw, s5
mul r1.w, r2.w, r2.x
mul r2.x, r1.w, r3.w
mul r2.yzw, r3.xxyz, r2.xxxx
mad r1.w, -r3.w, r1.w, l(1.000000)
mad r4.xyz, r1.wwww, r1.xyzx, r2.yzwy
mad r5.xyz, r2.xxxx, r3.xyzx, r1.xyzx
mad r3.xyz, -r2.xxxx, r3.xyzx, r1.xyzx
eq r6.xyzw, cb0[5].xxxx, l(0.000000, 1.000000, 2.000000, 3.000000)
mul r2.xyz, r1.xyzx, r2.yzwy
movc r1.xyz, r6.wwww, r2.xyzx, r1.xyzx
movc r1.xyz, r6.zzzz, r3.xyzx, r1.xyzx
movc r1.xyz, r6.yyyy, r5.xyzx, r1.xyzx
movc r0.xyz, r6.xxxx, r4.xyzx, r1.xyzx
dp3 r1.x, -cb0[6].xyzx, -cb0[6].xyzx
rsq r1.x, r1.x
mul r1.xyz, r1.xxxx, -cb0[6].xyzx
dp3 r1.w, v2.xyzx, v2.xyzx
rsq r1.w, r1.w
mul r2.xyz, r1.wwww, v2.xyzx
dp3_sat r1.x, r1.xyzx, r2.xyzx
log r1.x, r1.x
mul r1.x, r1.x, cb0[7].z
exp r1.x, r1.x
add r2.xyzw, cb0[8].xyzw, -cb0[9].xyzw
mad r1.xyzw, r1.xxxx, r2.xyzw, cb0[9].xyzw
add r2.xyz, r0.xyzx, r1.xyzx
add r3.xyz, r0.xyzx, -r1.xyzx
eq r4.xyzw, cb0[7].xyyy, l(1.000000, 0.000000, 1.000000, 2.000000)
mul r1.xyz, r0.xyzx, r1.xyzx
movc r1.xyz, r4.wwww, r1.xyzx, r0.xyzx
movc r1.xyz, r4.zzzz, r3.xyzx, r1.xyzx
movc r2.xyz, r4.yyyy, r2.xyzx, r1.xyzx
mul r2.w, r0.w, r1.w
movc r0.xyzw, r4.xxxx, r2.xyzw, r0.xyzw
max r1.x, v1.w, l(0.000000)
ge r1.x, r1.x, r0.w
discard r1.x
mul r1.xyz, cb0[11].xyzx, cb0[12].yyyy
add r1.w, r0.w, -v1.w
add r1.w, r1.w, -cb0[12].x
round_pi r1.w, r1.w
mad r0.xyz, r0.xyzx, cb0[10].xxxx, -r1.xyzx
mad o0.xyz, r1.wwww, r0.xyzx, r1.xyzx
mov o0.w, r0.w
ret
// Approximately 71 instruction slots used
#endif
const BYTE g_main[] =
{
68, 88, 66, 67, 187, 178,
65, 192, 151, 112, 130, 101,
179, 171, 106, 151, 83, 205,
215, 244, 1, 0, 0, 0,
152, 17, 0, 0, 5, 0,
0, 0, 52, 0, 0, 0,
108, 5, 0, 0, 136, 6,
0, 0, 188, 6, 0, 0,
28, 17, 0, 0, 82, 68,
69, 70, 48, 5, 0, 0,
1, 0, 0, 0, 180, 2,
0, 0, 13, 0, 0, 0,
28, 0, 0, 0, 0, 4,
255, 255, 16, 1, 0, 0,
255, 4, 0, 0, 188, 1,
0, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0,
203, 1, 0, 0, 3, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 2, 0, 0, 0,
1, 0, 0, 0, 1, 0,
0, 0, 218, 1, 0, 0,
3, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 3, 0,
0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 240, 1,
0, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0,
255, 1, 0, 0, 3, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 5, 0, 0, 0,
1, 0, 0, 0, 1, 0,
0, 0, 19, 2, 0, 0,
3, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 6, 0,
0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 46, 2,
0, 0, 2, 0, 0, 0,
5, 0, 0, 0, 4, 0,
0, 0, 255, 255, 255, 255,
0, 0, 0, 0, 1, 0,
0, 0, 13, 0, 0, 0,
61, 2, 0, 0, 2, 0,
0, 0, 5, 0, 0, 0,
4, 0, 0, 0, 255, 255,
255, 255, 2, 0, 0, 0,
1, 0, 0, 0, 13, 0,
0, 0, 76, 2, 0, 0,
2, 0, 0, 0, 5, 0,
0, 0, 4, 0, 0, 0,
255, 255, 255, 255, 3, 0,
0, 0, 1, 0, 0, 0,
13, 0, 0, 0, 98, 2,
0, 0, 2, 0, 0, 0,
5, 0, 0, 0, 4, 0,
0, 0, 255, 255, 255, 255,
4, 0, 0, 0, 1, 0,
0, 0, 13, 0, 0, 0,
113, 2, 0, 0, 2, 0,
0, 0, 5, 0, 0, 0,
4, 0, 0, 0, 255, 255,
255, 255, 5, 0, 0, 0,
1, 0, 0, 0, 13, 0,
0, 0, 133, 2, 0, 0,
2, 0, 0, 0, 5, 0,
0, 0, 4, 0, 0, 0,
255, 255, 255, 255, 6, 0,
0, 0, 1, 0, 0, 0,
13, 0, 0, 0, 160, 2,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0,
103, 95, 99, 111, 108, 111,
114, 83, 97, 109, 112, 108,
101, 114, 0, 103, 95, 97,
108, 112, 104, 97, 83, 97,
109, 112, 108, 101, 114, 0,
103, 95, 117, 118, 68, 105,
115, 116, 111, 114, 116, 105,
111, 110, 83, 97, 109, 112,
108, 101, 114, 0, 103, 95,
98, 108, 101, 110, 100, 83,
97, 109, 112, 108, 101, 114,
0, 103, 95, 98, 108, 101,
110, 100, 65, 108, 112, 104,
97, 83, 97, 109, 112, 108,
101, 114, 0, 103, 95, 98,
108, 101, 110, 100, 85, 86,
68, 105, 115, 116, 111, 114,
116, 105, 111, 110, 83, 97,
109, 112, 108, 101, 114, 0,
103, 95, 99, 111, 108, 111,
114, 84, 101, 120, 116, 117,
114, 101, 0, 103, 95, 97,
108, 112, 104, 97, 84, 101,
120, 116, 117, 114, 101, 0,
103, 95, 117, 118, 68, 105,
115, 116, 111, 114, 116, 105,
111, 110, 84, 101, 120, 116,
117, 114, 101, 0, 103, 95,
98, 108, 101, 110, 100, 84,
101, 120, 116, 117, 114, 101,
0, 103, 95, 98, 108, 101,
110, 100, 65, 108, 112, 104,
97, 84, 101, 120, 116, 117,
114, 101, 0, 103, 95, 98,
108, 101, 110, 100, 85, 86,
68, 105, 115, 116, 111, 114,
116, 105, 111, 110, 84, 101,
120, 116, 117, 114, 101, 0,
80, 83, 95, 67, 111, 110,
115, 116, 97, 110, 66, 117,
102, 102, 101, 114, 0, 171,
171, 171, 160, 2, 0, 0,
11, 0, 0, 0, 204, 2,
0, 0, 208, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 212, 3, 0, 0,
0, 0, 0, 0, 16, 0,
0, 0, 0, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 244, 3, 0, 0,
16, 0, 0, 0, 16, 0,
0, 0, 0, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 0, 4, 0, 0,
32, 0, 0, 0, 16, 0,
0, 0, 0, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 14, 4, 0, 0,
48, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 33, 4, 0, 0,
64, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 56, 4, 0, 0,
80, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 79, 4, 0, 0,
96, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 101, 4, 0, 0,
112, 0, 0, 0, 48, 0,
0, 0, 2, 0, 0, 0,
196, 4, 0, 0, 0, 0,
0, 0, 212, 4, 0, 0,
160, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 229, 4, 0, 0,
176, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 240, 4, 0, 0,
192, 0, 0, 0, 16, 0,
0, 0, 2, 0, 0, 0,
228, 3, 0, 0, 0, 0,
0, 0, 102, 76, 105, 103,
104, 116, 68, 105, 114, 101,
99, 116, 105, 111, 110, 0,
1, 0, 3, 0, 1, 0,
4, 0, 0, 0, 0, 0,
0, 0, 0, 0, 102, 76,
105, 103, 104, 116, 67, 111,
108, 111, 114, 0, 102, 76,
105, 103, 104, 116, 65, 109,
98, 105, 101, 110, 116, 0,
102, 70, 108, 105, 112, 98,
111, 111, 107, 80, 97, 114,
97, 109, 101, 116, 101, 114,
0, 102, 85, 86, 68, 105,
115, 116, 111, 114, 116, 105,
111, 110, 80, 97, 114, 97,
109, 101, 116, 101, 114, 0,
102, 66, 108, 101, 110, 100,
84, 101, 120, 116, 117, 114,
101, 80, 97, 114, 97, 109,
101, 116, 101, 114, 0, 102,
67, 97, 109, 101, 114, 97,
70, 114, 111, 110, 116, 68,
105, 114, 101, 99, 116, 105,
111, 110, 0, 102, 70, 97,
108, 108, 111, 102, 102, 80,
97, 114, 97, 109, 0, 80,
97, 114, 97, 109, 0, 171,
171, 171, 1, 0, 3, 0,
1, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0, 0,
66, 101, 103, 105, 110, 67,
111, 108, 111, 114, 0, 69,
110, 100, 67, 111, 108, 111,
114, 0, 115, 4, 0, 0,
124, 4, 0, 0, 0, 0,
0, 0, 140, 4, 0, 0,
124, 4, 0, 0, 16, 0,
0, 0, 151, 4, 0, 0,
124, 4, 0, 0, 32, 0,
0, 0, 5, 0, 0, 0,
1, 0, 12, 0, 0, 0,
3, 0, 160, 4, 0, 0,
102, 69, 109, 105, 115, 115,
105, 118, 101, 83, 99, 97,
108, 105, 110, 103, 0, 102,
69, 100, 103, 101, 67, 111,
108, 111, 114, 0, 102, 69,
100, 103, 101, 80, 97, 114,
97, 109, 101, 116, 101, 114,
0, 77, 105, 99, 114, 111,
115, 111, 102, 116, 32, 40,
82, 41, 32, 72, 76, 83,
76, 32, 83, 104, 97, 100,
101, 114, 32, 67, 111, 109,
112, 105, 108, 101, 114, 32,
57, 46, 50, 57, 46, 57,
53, 50, 46, 51, 49, 49,
49, 0, 73, 83, 71, 78,
20, 1, 0, 0, 10, 0,
0, 0, 8, 0, 0, 0,
248, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0,
3, 0, 0, 0, 0, 0,
0, 0, 15, 0, 0, 0,
4, 1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 1, 0,
0, 0, 3, 3, 0, 0,
4, 1, 0, 0, 7, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 1, 0,
0, 0, 12, 12, 0, 0,
4, 1, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 2, 0,
0, 0, 7, 7, 0, 0,
4, 1, 0, 0, 2, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 3, 0,
0, 0, 7, 0, 0, 0,
4, 1, 0, 0, 3, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 4, 0,
0, 0, 7, 0, 0, 0,
13, 1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 5, 0,
0, 0, 15, 15, 0, 0,
4, 1, 0, 0, 4, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 6, 0,
0, 0, 15, 15, 0, 0,
4, 1, 0, 0, 5, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 7, 0,
0, 0, 15, 15, 0, 0,
4, 1, 0, 0, 6, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 8, 0,
0, 0, 15, 15, 0, 0,
83, 86, 95, 80, 79, 83,
73, 84, 73, 79, 78, 0,
84, 69, 88, 67, 79, 79,
82, 68, 0, 67, 79, 76,
79, 82, 0, 171, 79, 83,
71, 78, 44, 0, 0, 0,
1, 0, 0, 0, 8, 0,
0, 0, 32, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 3, 0, 0, 0,
0, 0, 0, 0, 15, 0,
0, 0, 83, 86, 95, 84,
97, 114, 103, 101, 116, 0,
171, 171, 83, 72, 68, 82,
88, 10, 0, 0, 64, 0,
0, 0, 150, 2, 0, 0,
89, 0, 0, 4, 70, 142,
32, 0, 0, 0, 0, 0,
13, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
0, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
2, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
3, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
4, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
5, 0, 0, 0, 90, 0,
0, 3, 0, 96, 16, 0,
6, 0, 0, 0, 88, 24,
0, 4, 0, 112, 16, 0,
0, 0, 0, 0, 85, 85,
0, 0, 88, 24, 0, 4,
0, 112, 16, 0, 2, 0,
0, 0, 85, 85, 0, 0,
88, 24, 0, 4, 0, 112,
16, 0, 3, 0, 0, 0,
85, 85, 0, 0, 88, 24,
0, 4, 0, 112, 16, 0,
4, 0, 0, 0, 85, 85,
0, 0, 88, 24, 0, 4,
0, 112, 16, 0, 5, 0,
0, 0, 85, 85, 0, 0,
88, 24, 0, 4, 0, 112,
16, 0, 6, 0, 0, 0,
85, 85, 0, 0, 98, 16,
0, 3, 50, 16, 16, 0,
1, 0, 0, 0, 98, 16,
0, 3, 194, 16, 16, 0,
1, 0, 0, 0, 98, 16,
0, 3, 114, 16, 16, 0,
2, 0, 0, 0, 98, 16,
0, 3, 242, 16, 16, 0,
5, 0, 0, 0, 98, 16,
0, 3, 242, 16, 16, 0,
6, 0, 0, 0, 98, 16,
0, 3, 242, 16, 16, 0,
7, 0, 0, 0, 98, 16,
0, 3, 242, 16, 16, 0,
8, 0, 0, 0, 101, 0,
0, 3, 242, 32, 16, 0,
0, 0, 0, 0, 104, 0,
0, 2, 7, 0, 0, 0,
69, 0, 0, 9, 242, 0,
16, 0, 0, 0, 0, 0,
230, 26, 16, 0, 6, 0,
0, 0, 70, 126, 16, 0,
3, 0, 0, 0, 0, 96,
16, 0, 3, 0, 0, 0,
50, 0, 0, 15, 50, 0,
16, 0, 0, 0, 0, 0,
70, 0, 16, 0, 0, 0,
0, 0, 2, 64, 0, 0,
0, 0, 0, 64, 0, 0,
0, 64, 0, 0, 0, 0,
0, 0, 0, 0, 2, 64,
0, 0, 0, 0, 128, 191,
0, 0, 128, 191, 0, 0,
0, 0, 0, 0, 0, 0,
50, 0, 0, 12, 66, 0,
16, 0, 0, 0, 0, 0,
26, 0, 16, 128, 65, 0,
0, 0, 0, 0, 0, 0,
58, 128, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
42, 128, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
50, 0, 0, 10, 162, 0,
16, 0, 0, 0, 0, 0,
6, 8, 16, 0, 0, 0,
0, 0, 6, 128, 32, 0,
0, 0, 0, 0, 4, 0,
0, 0, 6, 20, 16, 0,
1, 0, 0, 0, 69, 0,
0, 9, 242, 0, 16, 0,
1, 0, 0, 0, 214, 5,
16, 0, 0, 0, 0, 0,
70, 126, 16, 0, 0, 0,
0, 0, 0, 96, 16, 0,
0, 0, 0, 0, 56, 0,
0, 7, 242, 0, 16, 0,
1, 0, 0, 0, 70, 14,
16, 0, 1, 0, 0, 0,
70, 30, 16, 0, 5, 0,
0, 0, 49, 0, 0, 8,
34, 0, 16, 0, 0, 0,
0, 0, 1, 64, 0, 0,
0, 0, 0, 0, 10, 128,
32, 0, 0, 0, 0, 0,
3, 0, 0, 0, 31, 0,
4, 3, 26, 0, 16, 0,
0, 0, 0, 0, 50, 0,
0, 10, 162, 0, 16, 0,
0, 0, 0, 0, 6, 8,
16, 0, 0, 0, 0, 0,
6, 128, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
166, 30, 16, 0, 8, 0,
0, 0, 69, 0, 0, 9,
242, 0, 16, 0, 2, 0,
0, 0, 214, 5, 16, 0,
0, 0, 0, 0, 70, 126,
16, 0, 0, 0, 0, 0,
0, 96, 16, 0, 0, 0,
0, 0, 24, 0, 0, 8,
34, 0, 16, 0, 0, 0,
0, 0, 26, 128, 32, 0,
0, 0, 0, 0, 3, 0,
0, 0, 1, 64, 0, 0,
0, 0, 128, 63, 50, 0,
0, 10, 242, 0, 16, 0,
2, 0, 0, 0, 70, 14,
16, 0, 2, 0, 0, 0,
70, 30, 16, 0, 5, 0,
0, 0, 70, 14, 16, 128,
65, 0, 0, 0, 1, 0,
0, 0, 50, 0, 0, 9,
242, 0, 16, 0, 2, 0,
0, 0, 166, 26, 16, 0,
1, 0, 0, 0, 70, 14,
16, 0, 2, 0, 0, 0,
70, 14, 16, 0, 1, 0,
0, 0, 55, 0, 0, 9,
242, 0, 16, 0, 1, 0,
0, 0, 86, 5, 16, 0,
0, 0, 0, 0, 70, 14,
16, 0, 2, 0, 0, 0,
70, 14, 16, 0, 1, 0,
0, 0, 21, 0, 0, 1,
50, 0, 0, 10, 50, 0,
16, 0, 0, 0, 0, 0,
134, 0, 16, 0, 0, 0,
0, 0, 6, 128, 32, 0,
0, 0, 0, 0, 4, 0,
0, 0, 70, 16, 16, 0,
6, 0, 0, 0, 69, 0,
0, 9, 242, 0, 16, 0,
0, 0, 0, 0, 70, 0,
16, 0, 0, 0, 0, 0,
70, 126, 16, 0, 2, 0,
0, 0, 0, 96, 16, 0,
2, 0, 0, 0, 56, 0,
0, 7, 18, 0, 16, 0,
0, 0, 0, 0, 58, 0,
16, 0, 0, 0, 0, 0,
10, 0, 16, 0, 0, 0,
0, 0, 56, 0, 0, 7,
130, 0, 16, 0, 0, 0,
0, 0, 10, 0, 16, 0,
0, 0, 0, 0, 58, 0,
16, 0, 1, 0, 0, 0,
69, 0, 0, 9, 242, 0,
16, 0, 2, 0, 0, 0,
230, 26, 16, 0, 7, 0,
0, 0, 70, 126, 16, 0,
6, 0, 0, 0, 0, 96,
16, 0, 6, 0, 0, 0,
50, 0, 0, 15, 50, 0,
16, 0, 2, 0, 0, 0,
70, 0, 16, 0, 2, 0,
0, 0, 2, 64, 0, 0,
0, 0, 0, 64, 0, 0,
0, 64, 0, 0, 0, 0,
0, 0, 0, 0, 2, 64,
0, 0, 0, 0, 128, 191,
0, 0, 128, 191, 0, 0,
0, 0, 0, 0, 0, 0,
50, 0, 0, 12, 66, 0,
16, 0, 2, 0, 0, 0,
26, 0, 16, 128, 65, 0,
0, 0, 2, 0, 0, 0,
58, 128, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
42, 128, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
50, 0, 0, 10, 162, 0,
16, 0, 2, 0, 0, 0,
6, 8, 16, 0, 2, 0,
0, 0, 86, 133, 32, 0,
0, 0, 0, 0, 4, 0,
0, 0, 6, 20, 16, 0,
8, 0, 0, 0, 69, 0,
0, 9, 242, 0, 16, 0,
3, 0, 0, 0, 214, 5,
16, 0, 2, 0, 0, 0,
70, 126, 16, 0, 4, 0,
0, 0, 0, 96, 16, 0,
4, 0, 0, 0, 50, 0,
0, 10, 50, 0, 16, 0,
2, 0, 0, 0, 134, 0,
16, 0, 2, 0, 0, 0,
86, 133, 32, 0, 0, 0,
0, 0, 4, 0, 0, 0,
70, 16, 16, 0, 7, 0,
0, 0, 69, 0, 0, 9,
242, 0, 16, 0, 2, 0,
0, 0, 70, 0, 16, 0,
2, 0, 0, 0, 70, 126,
16, 0, 5, 0, 0, 0,
0, 96, 16, 0, 5, 0,
0, 0, 56, 0, 0, 7,
130, 0, 16, 0, 1, 0,
0, 0, 58, 0, 16, 0,
2, 0, 0, 0, 10, 0,
16, 0, 2, 0, 0, 0,
56, 0, 0, 7, 18, 0,
16, 0, 2, 0, 0, 0,
58, 0, 16, 0, 1, 0,
0, 0, 58, 0, 16, 0,
3, 0, 0, 0, 56, 0,
0, 7, 226, 0, 16, 0,
2, 0, 0, 0, 6, 9,
16, 0, 3, 0, 0, 0,
6, 0, 16, 0, 2, 0,
0, 0, 50, 0, 0, 10,
130, 0, 16, 0, 1, 0,
0, 0, 58, 0, 16, 128,
65, 0, 0, 0, 3, 0,
0, 0, 58, 0, 16, 0,
1, 0, 0, 0, 1, 64,
0, 0, 0, 0, 128, 63,
50, 0, 0, 9, 114, 0,
16, 0, 4, 0, 0, 0,
246, 15, 16, 0, 1, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 150, 7,
16, 0, 2, 0, 0, 0,
50, 0, 0, 9, 114, 0,
16, 0, 5, 0, 0, 0,
6, 0, 16, 0, 2, 0,
0, 0, 70, 2, 16, 0,
3, 0, 0, 0, 70, 2,
16, 0, 1, 0, 0, 0,
50, 0, 0, 10, 114, 0,
16, 0, 3, 0, 0, 0,
6, 0, 16, 128, 65, 0,
0, 0, 2, 0, 0, 0,
70, 2, 16, 0, 3, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 24, 0,
0, 11, 242, 0, 16, 0,
6, 0, 0, 0, 6, 128,
32, 0, 0, 0, 0, 0,
5, 0, 0, 0, 2, 64,
0, 0, 0, 0, 0, 0,
0, 0, 128, 63, 0, 0,
0, 64, 0, 0, 64, 64,
56, 0, 0, 7, 114, 0,
16, 0, 2, 0, 0, 0,
70, 2, 16, 0, 1, 0,
0, 0, 150, 7, 16, 0,
2, 0, 0, 0, 55, 0,
0, 9, 114, 0, 16, 0,
1, 0, 0, 0, 246, 15,
16, 0, 6, 0, 0, 0,
70, 2, 16, 0, 2, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 55, 0,
0, 9, 114, 0, 16, 0,
1, 0, 0, 0, 166, 10,
16, 0, 6, 0, 0, 0,
70, 2, 16, 0, 3, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 55, 0,
0, 9, 114, 0, 16, 0,
1, 0, 0, 0, 86, 5,
16, 0, 6, 0, 0, 0,
70, 2, 16, 0, 5, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 55, 0,
0, 9, 114, 0, 16, 0,
0, 0, 0, 0, 6, 0,
16, 0, 6, 0, 0, 0,
70, 2, 16, 0, 4, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 16, 0,
0, 11, 18, 0, 16, 0,
1, 0, 0, 0, 70, 130,
32, 128, 65, 0, 0, 0,
0, 0, 0, 0, 6, 0,
0, 0, 70, 130, 32, 128,
65, 0, 0, 0, 0, 0,
0, 0, 6, 0, 0, 0,
68, 0, 0, 5, 18, 0,
16, 0, 1, 0, 0, 0,
10, 0, 16, 0, 1, 0,
0, 0, 56, 0, 0, 9,
114, 0, 16, 0, 1, 0,
0, 0, 6, 0, 16, 0,
1, 0, 0, 0, 70, 130,
32, 128, 65, 0, 0, 0,
0, 0, 0, 0, 6, 0,
0, 0, 16, 0, 0, 7,
130, 0, 16, 0, 1, 0,
0, 0, 70, 18, 16, 0,
2, 0, 0, 0, 70, 18,
16, 0, 2, 0, 0, 0,
68, 0, 0, 5, 130, 0,
16, 0, 1, 0, 0, 0,
58, 0, 16, 0, 1, 0,
0, 0, 56, 0, 0, 7,
114, 0, 16, 0, 2, 0,
0, 0, 246, 15, 16, 0,
1, 0, 0, 0, 70, 18,
16, 0, 2, 0, 0, 0,
16, 32, 0, 7, 18, 0,
16, 0, 1, 0, 0, 0,
70, 2, 16, 0, 1, 0,
0, 0, 70, 2, 16, 0,
2, 0, 0, 0, 47, 0,
0, 5, 18, 0, 16, 0,
1, 0, 0, 0, 10, 0,
16, 0, 1, 0, 0, 0,
56, 0, 0, 8, 18, 0,
16, 0, 1, 0, 0, 0,
10, 0, 16, 0, 1, 0,
0, 0, 42, 128, 32, 0,
0, 0, 0, 0, 7, 0,
0, 0, 25, 0, 0, 5,
18, 0, 16, 0, 1, 0,
0, 0, 10, 0, 16, 0,
1, 0, 0, 0, 0, 0,
0, 10, 242, 0, 16, 0,
2, 0, 0, 0, 70, 142,
32, 0, 0, 0, 0, 0,
8, 0, 0, 0, 70, 142,
32, 128, 65, 0, 0, 0,
0, 0, 0, 0, 9, 0,
0, 0, 50, 0, 0, 10,
242, 0, 16, 0, 1, 0,
0, 0, 6, 0, 16, 0,
1, 0, 0, 0, 70, 14,
16, 0, 2, 0, 0, 0,
70, 142, 32, 0, 0, 0,
0, 0, 9, 0, 0, 0,
0, 0, 0, 7, 114, 0,
16, 0, 2, 0, 0, 0,
70, 2, 16, 0, 0, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 0, 0,
0, 8, 114, 0, 16, 0,
3, 0, 0, 0, 70, 2,
16, 0, 0, 0, 0, 0,
70, 2, 16, 128, 65, 0,
0, 0, 1, 0, 0, 0,
24, 0, 0, 11, 242, 0,
16, 0, 4, 0, 0, 0,
70, 133, 32, 0, 0, 0,
0, 0, 7, 0, 0, 0,
2, 64, 0, 0, 0, 0,
128, 63, 0, 0, 0, 0,
0, 0, 128, 63, 0, 0,
0, 64, 56, 0, 0, 7,
114, 0, 16, 0, 1, 0,
0, 0, 70, 2, 16, 0,
0, 0, 0, 0, 70, 2,
16, 0, 1, 0, 0, 0,
55, 0, 0, 9, 114, 0,
16, 0, 1, 0, 0, 0,
246, 15, 16, 0, 4, 0,
0, 0, 70, 2, 16, 0,
1, 0, 0, 0, 70, 2,
16, 0, 0, 0, 0, 0,
55, 0, 0, 9, 114, 0,
16, 0, 1, 0, 0, 0,
166, 10, 16, 0, 4, 0,
0, 0, 70, 2, 16, 0,
3, 0, 0, 0, 70, 2,
16, 0, 1, 0, 0, 0,
55, 0, 0, 9, 114, 0,
16, 0, 2, 0, 0, 0,
86, 5, 16, 0, 4, 0,
0, 0, 70, 2, 16, 0,
2, 0, 0, 0, 70, 2,
16, 0, 1, 0, 0, 0,
56, 0, 0, 7, 130, 0,
16, 0, 2, 0, 0, 0,
58, 0, 16, 0, 0, 0,
0, 0, 58, 0, 16, 0,
1, 0, 0, 0, 55, 0,
0, 9, 242, 0, 16, 0,
0, 0, 0, 0, 6, 0,
16, 0, 4, 0, 0, 0,
70, 14, 16, 0, 2, 0,
0, 0, 70, 14, 16, 0,
0, 0, 0, 0, 52, 0,
0, 7, 18, 0, 16, 0,
1, 0, 0, 0, 58, 16,
16, 0, 1, 0, 0, 0,
1, 64, 0, 0, 0, 0,
0, 0, 29, 0, 0, 7,
18, 0, 16, 0, 1, 0,
0, 0, 10, 0, 16, 0,
1, 0, 0, 0, 58, 0,
16, 0, 0, 0, 0, 0,
13, 0, 4, 3, 10, 0,
16, 0, 1, 0, 0, 0,
56, 0, 0, 9, 114, 0,
16, 0, 1, 0, 0, 0,
70, 130, 32, 0, 0, 0,
0, 0, 11, 0, 0, 0,
86, 133, 32, 0, 0, 0,
0, 0, 12, 0, 0, 0,
0, 0, 0, 8, 130, 0,
16, 0, 1, 0, 0, 0,
58, 0, 16, 0, 0, 0,
0, 0, 58, 16, 16, 128,
65, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 9,
130, 0, 16, 0, 1, 0,
0, 0, 58, 0, 16, 0,
1, 0, 0, 0, 10, 128,
32, 128, 65, 0, 0, 0,
0, 0, 0, 0, 12, 0,
0, 0, 66, 0, 0, 5,
130, 0, 16, 0, 1, 0,
0, 0, 58, 0, 16, 0,
1, 0, 0, 0, 50, 0,
0, 11, 114, 0, 16, 0,
0, 0, 0, 0, 70, 2,
16, 0, 0, 0, 0, 0,
6, 128, 32, 0, 0, 0,
0, 0, 10, 0, 0, 0,
70, 2, 16, 128, 65, 0,
0, 0, 1, 0, 0, 0,
50, 0, 0, 9, 114, 32,
16, 0, 0, 0, 0, 0,
246, 15, 16, 0, 1, 0,
0, 0, 70, 2, 16, 0,
0, 0, 0, 0, 70, 2,
16, 0, 1, 0, 0, 0,
54, 0, 0, 5, 130, 32,
16, 0, 0, 0, 0, 0,
58, 0, 16, 0, 0, 0,
0, 0, 62, 0, 0, 1,
83, 84, 65, 84, 116, 0,
0, 0, 71, 0, 0, 0,
7, 0, 0, 0, 0, 0,
0, 0, 8, 0, 0, 0,
32, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 7, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 9, 0,
0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0
};
| {
"language": "Assembly"
} |
comment "apitrace needs a glibc toolchain w/ C++, gcc >= 4.9"
depends on BR2_PACKAGE_XORG7
depends on !BR2_INSTALL_LIBSTDCPP || !BR2_TOOLCHAIN_USES_GLIBC \
|| !BR2_TOOLCHAIN_GCC_AT_LEAST_4_9
config BR2_PACKAGE_APITRACE
bool "apitrace"
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_TOOLCHAIN_USES_GLIBC # uses glibc specific __libc_dlsym
depends on BR2_TOOLCHAIN_GCC_AT_LEAST_4_9
depends on BR2_PACKAGE_XORG7
select BR2_PACKAGE_XLIB_LIBX11
select BR2_PACKAGE_LIBPNG
help
Trace and replay OpenGL and OpenGL ES APIs calls to/from a
file. You may install apitrace GUI from your distribution to
inspect generated traces.
http://apitrace.github.io/
| {
"language": "Assembly"
} |
; RUN: opt -basicaa -loop-distribute -scoped-noalias -loop-versioning -S < %s | FileCheck %s
; Test the metadata generated when versioning an already versioned loop. Here
; we invoke loop distribution to perform the first round of versioning. It
; adds memchecks for accesses that can alias across the distribution boundary.
; Then we further version the distributed loops to fully disambiguate accesses
; within each.
;
; So as an example, we add noalias between C and A during the versioning
; within loop distribution and then add noalias between C and D during the
; second explicit versioning step:
;
; for (i = 0; i < n; i++) {
; A[i + 1] = A[i] * B[i];
; -------------------------------
; C[i] = D[i] * E[i];
; }
; To see it easier what's going on, I expanded every noalias/scope metadata
; reference below in a comment. For a scope I use the format scope(domain),
; e.g. scope 17 in domain 15 is written as 17(15).
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@B = common global i32* null, align 8
@A = common global i32* null, align 8
@C = common global i32* null, align 8
@D = common global i32* null, align 8
@E = common global i32* null, align 8
define void @f() {
entry:
%a = load i32*, i32** @A, align 8
%b = load i32*, i32** @B, align 8
%c = load i32*, i32** @C, align 8
%d = load i32*, i32** @D, align 8
%e = load i32*, i32** @E, align 8
br label %for.body
for.body: ; preds = %for.body, %entry
%ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
%arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
; CHECK: %loadA.ldist1 = {{.*}} !noalias !25
; A noalias C: !25 -> { 17(15), 18(15), 19(15), 26(24) }
; ^^^^^^
%loadA = load i32, i32* %arrayidxA, align 4
%arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
%loadB = load i32, i32* %arrayidxB, align 4
%mulA = mul i32 %loadB, %loadA
%add = add nuw nsw i64 %ind, 1
%arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
store i32 %mulA, i32* %arrayidxA_plus_4, align 4
; CHECK: for.body:
%arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
; CHECK: %loadD = {{.*}} !alias.scope !31
; D's scope: !31 -> { 18(15), 32(33) }
; ^^^^^^
%loadD = load i32, i32* %arrayidxD, align 4
%arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
; CHECK: %loadE = {{.*}} !alias.scope !34
; E's scope: !34 -> { 19(15), 35(33) }
; ^^^^^^
%loadE = load i32, i32* %arrayidxE, align 4
%mulC = mul i32 %loadD, %loadE
%arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
; CHECK: store i32 %mulC, {{.*}} !alias.scope !36, !noalias !38
; C's scope: !36 -> { 17(15), 37(33) }
; ^^^^^^
; C noalias D and E: !38 -> { 21(15), 32(33), 35(33) }
; ^^^^^^ ^^^^^^
store i32 %mulC, i32* %arrayidxC, align 4
%exitcond = icmp eq i64 %add, 20
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
}
; Domain for the second loop versioning for the top loop after
; distribution.
; CHECK: !15 = distinct !{!15, !"LVerDomain"}
; CHECK: !17 = distinct !{!17, !15}
; CHECK: !25 = !{!17, !18, !19, !26}
; CHECK: !31 = !{!18, !32}
; CHECK: !32 = distinct !{!32, !33}
; Domain for the second loop versioning for the bottom loop after
; distribution.
; CHECK: !33 = distinct !{!33, !"LVerDomain"}
; CHECK: !34 = !{!19, !35}
; CHECK: !35 = distinct !{!35, !33}
; CHECK: !36 = !{!17, !37}
; CHECK: !38 = !{!21, !32, !35}
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for arm, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
TEXT ·seek(SB),NOSPLIT,$0-32
B syscall·seek(SB)
| {
"language": "Assembly"
} |
.i86
;;; termination.asm
;;; Used to test termination scenarios. For instance, a terminating function has no live-out registers!
main proc
mov cx,123
mov ax,32
mov bx,0x3212
call maybeterminate
mov [0x230],ax
mov [0x234],cx
ret
endp
maybeterminate proc
cmp ax,[bx]
jc die
cmp ax,[bx+2]
jae die
add bx,ax
mov ax,[bx]
ret
die:
xor cx,cx
mov [0x0232],cx
mov ax,0x4C00
int 0x21
endp
| {
"language": "Assembly"
} |
// RUN: %target-swift-frontend %s -emit-ir -g -o - | %FileCheck %s
// RUN: %target-swift-frontend %s -S -g -o - | %FileCheck %s --check-prefix ASM-CHECK
// REQUIRES: CPU=i386 || CPU=x86_64
import Swift
func markUsed<T>(_ t: T) {}
class MyClass
{
var x : Int64
init(input: Int64) { x = input }
func do_something(_ input: Int64) -> Int64
{
return x * input
}
}
func call_me(_ code: @escaping () -> Void)
{
code ()
}
func main(_ x: Int64) -> Void
// CHECK-LABEL: define hidden {{.*}} void @"$s9linetable4main{{[_0-9a-zA-Z]*}}F"
{
var my_class = MyClass(input: 10)
// Linetable continuity. Don't go into the closure expression.
// ASM-CHECK: .loc [[FILEID:[0-9]]] [[@LINE+1]] 5
call_me (
// ASM-CHECK-NOT: .loc [[FILEID]] [[@LINE+1]] 5
// CHECK-LABEL: define {{.*}} @"$s9linetable4mainyys5Int64VFyycfU_Tf2in_n"({{.*}})
{
var result = my_class.do_something(x)
markUsed(result)
// CHECK: call {{.*}} @swift_release {{.*}}
// CHECK: bitcast
// CHECK: llvm.lifetime.end
// CHECK: call {{.*}}llvm.lifetime.end{{.*}}, !dbg ![[CLOSURE_END:.*]]
// CHECK-NEXT: ret void, !dbg ![[CLOSURE_END]]
// CHECK: ![[CLOSURE_END]] = !DILocation(line: [[@LINE+1]],
}
)
// The swift_releases at the end should not jump to the point where
// that memory was retained/allocated and also not to line 0.
// ASM-CHECK-NOT: .loc [[FILEID]] 0 0
// ASM-CHECK: .loc [[FILEID]] [[@LINE+2]] 1
// ASM-CHECK: ret
}
// ASM-CHECK: {{^_?\$s9linetable4mainyys5Int64VFyycfU_Tf2in_n:}}
// ASM-CHECK-NOT: retq
// The end-of-prologue should have a valid location (0 is ok, too).
// ASM-CHECK: .loc [[FILEID]] {{0|34}} {{[0-9]+}} prologue_end
main(30)
| {
"language": "Assembly"
} |
; RUN: llc < %s -mtriple=armv7-apple-ios6 -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT
; RUN: llc < %s -mtriple=armv7-apple-ios7 -mcpu=cortex-a8 | FileCheck %s --check-prefix=SINCOS
; Combine sin / cos into a single call.
; rdar://12856873
define float @test1(float %x) nounwind {
entry:
; SINCOS-LABEL: test1:
; SINCOS: bl ___sincosf_stret
; NOOPT-LABEL: test1:
; NOOPT: bl _sinf
; NOOPT: bl _cosf
%call = tail call float @sinf(float %x) nounwind readnone
%call1 = tail call float @cosf(float %x) nounwind readnone
%add = fadd float %call, %call1
ret float %add
}
define double @test2(double %x) nounwind {
entry:
; SINCOS-LABEL: test2:
; SINCOS: bl ___sincos_stret
; NOOPT-LABEL: test2:
; NOOPT: bl _sin
; NOOPT: bl _cos
%call = tail call double @sin(double %x) nounwind readnone
%call1 = tail call double @cos(double %x) nounwind readnone
%add = fadd double %call, %call1
ret double %add
}
declare float @sinf(float) readonly
declare double @sin(double) readonly
declare float @cosf(float) readonly
declare double @cos(double) readonly
| {
"language": "Assembly"
} |
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include <core/clc_core.h>
#include <spirv/spirv.h>
#define __CLC_BODY <mad_sat.inc>
#include <clc/integer/gentype.inc>
| {
"language": "Assembly"
} |
; REQUIRES: object-emission
; RUN: llc -mtriple=x86_64-linux -O0 -filetype=obj -generate-arange-section < %s | llvm-dwarfdump -debug-dump=aranges - | FileCheck %s
; RUN: llc -mtriple=x86_64-linux -O0 -filetype=obj -generate-arange-section < %s | llvm-readobj --relocations - | FileCheck --check-prefix=OBJ %s
; extern int i;
; template<int *x>
; struct foo {
; };
;
; foo<&i> f;
; Check that we only have one arange in this compilation unit (it will be for 'f'), and not an extra one (for 'i' - since it isn't actually defined in this CU)
; CHECK: Address Range Header
; CHECK-NEXT: [0x
; CHECK-NOT: [0x
; Check that we have a relocation back to the debug_info section from the debug_aranges section
; OBJ: debug_aranges
; OBJ-NEXT: R_X86_64_32 .debug_info 0x0
%struct.foo = type { i8 }
@f = global %struct.foo zeroinitializer, align 1
@i = external global i32
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!12, !13}
!llvm.ident = !{!14}
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !3, globals: !9, imports: !2)
!1 = !DIFile(filename: "simple.cpp", directory: "/tmp/dbginfo")
!2 = !{}
!3 = !{!4}
!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo<&i>", line: 3, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS3fooIXadL_Z1iEEE")
!5 = !{!6}
!6 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "x", type: !7, value: i32* @i)
!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!9 = !{!10}
!10 = !DIGlobalVariable(name: "f", line: 6, isLocal: false, isDefinition: true, scope: null, file: !11, type: !4, variable: %struct.foo* @f)
!11 = !DIFile(filename: "simple.cpp", directory: "/tmp/dbginfo")
!12 = !{i32 2, !"Dwarf Version", i32 4}
!13 = !{i32 1, !"Debug Info Version", i32 3}
!14 = !{!"clang version 3.5 "}
| {
"language": "Assembly"
} |
// Copyright (c) Microsoft Corporation.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#include <eh.h>
#include <exception>
_STD_BEGIN
_CRTIMP2_PURE int __CLRCALL_PURE_OR_CDECL uncaught_exceptions() noexcept { // report number of throws being handled
return __uncaught_exceptions();
}
_STD_END
| {
"language": "Assembly"
} |
SECTION code_graphics
PUBLIC commoncircle
EXTERN _circledraw
; Common line drawing entry point
;
;void *(int x, int y, int radius, int skip) __smallc
;Note ints are actually uint8_t
;Entry: hl = draw function
commoncircle:
push hl ;Function pointer
ld hl,sp+4 ; &skip
ld e,(hl)
inc hl
ld d,(hl)
inc hl
push de
ld e,(hl) ;radius
inc hl
ld d,(hl)
inc hl
push de
ld e,(hl) ;y
inc hl
ld d,(hl)
inc hl
push de
ld e,(hl) ;x
inc hl
ld d,(hl)
push de
call _circledraw
IF __CPU_GBZ80__
add sp,10
ELSE
ld hl,10
add hl,sp
ld sp,hl
ENDIF
ret
| {
"language": "Assembly"
} |
; RUN: opt -newgvn -disable-output < %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
@nuls = external global [10 x i8]
define fastcc void @p_ere() nounwind {
entry:
br label %"<bb 5>"
"<L18>.i":
br i1 undef, label %"<bb 3>.i30.i", label %doemit.exit51.i
"<bb 3>.i30.i":
unreachable
doemit.exit51.i:
br label %"<bb 53>.i"
"<L19>.i":
br i1 undef, label %"<bb 3>.i55.i", label %doemit.exit76.i
"<bb 3>.i55.i":
unreachable
doemit.exit76.i:
br label %"<bb 53>.i"
"<L98>.i":
store i8* getelementptr inbounds ([10 x i8], [10 x i8]* @nuls, i64 0, i64 0), i8** undef, align 8
br label %"<bb 53>.i"
"<L99>.i":
br label %"<bb 53>.i"
"<L24>.i":
br i1 undef, label %"<bb 53>.i", label %"<bb 35>.i"
"<bb 35>.i":
br label %"<bb 53>.i"
"<L28>.i":
br label %"<bb 53>.i"
"<L29>.i":
br label %"<bb 53>.i"
"<L39>.i":
br label %"<bb 53>.i"
"<bb 53>.i":
%wascaret_2.i = phi i32 [ 0, %"<L39>.i" ], [ 0, %"<L29>.i" ], [ 0, %"<L28>.i" ], [ 0, %"<bb 35>.i" ], [ 0, %"<L99>.i" ], [ 0, %"<L98>.i" ], [ 0, %doemit.exit76.i ], [ 1, %doemit.exit51.i ], [ 0, %"<L24>.i" ]
%D.5496_84.i = load i8*, i8** undef, align 8
br i1 undef, label %"<bb 54>.i", label %"<bb 5>"
"<bb 54>.i":
br i1 undef, label %"<bb 5>", label %"<bb 58>.i"
"<bb 58>.i":
br i1 undef, label %"<bb 64>.i", label %"<bb 59>.i"
"<bb 59>.i":
br label %"<bb 64>.i"
"<bb 64>.i":
switch i32 undef, label %"<bb 5>" [
i32 42, label %"<L54>.i"
i32 43, label %"<L55>.i"
i32 63, label %"<L56>.i"
i32 123, label %"<bb 5>.i258.i"
]
"<L54>.i":
br i1 undef, label %"<bb 3>.i105.i", label %doemit.exit127.i
"<bb 3>.i105.i":
unreachable
doemit.exit127.i:
unreachable
"<L55>.i":
br i1 undef, label %"<bb 3>.i157.i", label %"<bb 5>"
"<bb 3>.i157.i":
unreachable
"<L56>.i":
br label %"<bb 5>"
"<bb 5>.i258.i":
unreachable
"<bb 5>":
switch i32 undef, label %"<L39>.i" [
i32 36, label %"<L19>.i"
i32 94, label %"<L18>.i"
i32 124, label %"<L98>.i"
i32 42, label %"<L99>.i"
i32 43, label %"<L99>.i"
i32 46, label %"<L24>.i"
i32 63, label %"<L99>.i"
i32 91, label %"<L28>.i"
i32 92, label %"<L29>.i"
]
}
| {
"language": "Assembly"
} |
/* $NetBSD: memset.S,v 1.2 2008/02/16 17:37:13 apb Exp $ */
/*-
* Copyright (c) 2002 SHIMIZU Ryo. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#if defined(LIBC_SCCS) && !defined(lint)
RCSID("$NetBSD: memset.S,v 1.2 2008/02/16 17:37:13 apb Exp $")
#endif
#define REG_PTR r0
#define REG_TMP1 r1
#ifdef BZERO
# define REG_C r2
# define REG_DST r4
# define REG_LEN r5
#else
# define REG_DST0 r3
# define REG_DST r4
# define REG_C r5
# define REG_LEN r6
#endif
#ifdef BZERO
ENTRY(bzero)
#else
ENTRY(memset)
mov REG_DST,REG_DST0 /* for return value */
#endif
/* small amount to fill ? */
mov #28,REG_TMP1
cmp/hs REG_TMP1,REG_LEN /* if (len >= 28) goto large; */
bt/s large
mov #12,REG_TMP1 /* if (len >= 12) goto small; */
cmp/hs REG_TMP1,REG_LEN
bt/s small
#ifdef BZERO
mov #0,REG_C
#endif
/* very little fill (0 ~ 11 bytes) */
tst REG_LEN,REG_LEN
add REG_DST,REG_LEN
bt/s done
add #1,REG_DST
/* unroll 4 loops */
cmp/eq REG_DST,REG_LEN
1: mov.b REG_C,@-REG_LEN
bt/s done
cmp/eq REG_DST,REG_LEN
mov.b REG_C,@-REG_LEN
bt/s done
cmp/eq REG_DST,REG_LEN
mov.b REG_C,@-REG_LEN
bt/s done
cmp/eq REG_DST,REG_LEN
mov.b REG_C,@-REG_LEN
bf/s 1b
cmp/eq REG_DST,REG_LEN
done:
#ifdef BZERO
rts
nop
#else
rts
mov REG_DST0,r0
#endif
small:
mov REG_DST,r0
tst #1,r0
bt/s small_aligned
mov REG_DST,REG_TMP1
shll REG_LEN
mova 1f,r0 /* 1f must be 4bytes aligned! */
add #16,REG_TMP1 /* REG_TMP1 = dst+16; */
sub REG_LEN,r0
jmp @r0
mov REG_C,r0
.align 2
mov.b r0,@(15,REG_TMP1)
mov.b r0,@(14,REG_TMP1)
mov.b r0,@(13,REG_TMP1)
mov.b r0,@(12,REG_TMP1)
mov.b r0,@(11,REG_TMP1)
mov.b r0,@(10,REG_TMP1)
mov.b r0,@(9,REG_TMP1)
mov.b r0,@(8,REG_TMP1)
mov.b r0,@(7,REG_TMP1)
mov.b r0,@(6,REG_TMP1)
mov.b r0,@(5,REG_TMP1)
mov.b r0,@(4,REG_TMP1)
mov.b r0,@(3,REG_TMP1)
mov.b r0,@(2,REG_TMP1)
mov.b r0,@(1,REG_TMP1)
mov.b r0,@REG_TMP1
mov.b r0,@(15,REG_DST)
mov.b r0,@(14,REG_DST)
mov.b r0,@(13,REG_DST)
mov.b r0,@(12,REG_DST)
mov.b r0,@(11,REG_DST)
mov.b r0,@(10,REG_DST)
mov.b r0,@(9,REG_DST)
mov.b r0,@(8,REG_DST)
mov.b r0,@(7,REG_DST)
mov.b r0,@(6,REG_DST)
mov.b r0,@(5,REG_DST)
mov.b r0,@(4,REG_DST)
mov.b r0,@(3,REG_DST)
mov.b r0,@(2,REG_DST)
mov.b r0,@(1,REG_DST)
#ifdef BZERO
rts
1: mov.b r0,@REG_DST
#else
mov.b r0,@REG_DST
1: rts
mov REG_DST0,r0
#endif
/* 2 bytes aligned small fill */
small_aligned:
#ifndef BZERO
extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
or REG_TMP1,REG_C /* REG_C = ????xxxx */
#endif
mov REG_LEN,r0
tst #1,r0 /* len is aligned? */
bt/s 1f
add #-1,r0
mov.b REG_C,@(r0,REG_DST) /* fill last a byte */
mov r0,REG_LEN
1:
mova 1f,r0 /* 1f must be 4bytes aligned! */
sub REG_LEN,r0
jmp @r0
mov REG_C,r0
.align 2
mov.w r0,@(30,REG_DST)
mov.w r0,@(28,REG_DST)
mov.w r0,@(26,REG_DST)
mov.w r0,@(24,REG_DST)
mov.w r0,@(22,REG_DST)
mov.w r0,@(20,REG_DST)
mov.w r0,@(18,REG_DST)
mov.w r0,@(16,REG_DST)
mov.w r0,@(14,REG_DST)
mov.w r0,@(12,REG_DST)
mov.w r0,@(10,REG_DST)
mov.w r0,@(8,REG_DST)
mov.w r0,@(6,REG_DST)
mov.w r0,@(4,REG_DST)
mov.w r0,@(2,REG_DST)
#ifdef BZERO
rts
1: mov.w r0,@REG_DST
#else
mov.w r0,@REG_DST
1: rts
mov REG_DST0,r0
#endif
.align 2
large:
#ifdef BZERO
mov #0,REG_C
#else
extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
or REG_C,REG_TMP1 /* REG_C = ????xx00, REG_TMP1 = ????xxxx */
swap.w REG_TMP1,REG_C /* REG_C = xxxx????, REG_TMP1 = ????xxxx */
xtrct REG_TMP1,REG_C /* REG_C = xxxxxxxx */
#endif
mov #3,REG_TMP1
tst REG_TMP1,REG_DST
mov REG_DST,REG_PTR
bf/s unaligned_dst
add REG_LEN,REG_PTR /* REG_PTR = dst + len; */
tst REG_TMP1,REG_LEN
bf/s unaligned_len
aligned:
/* fill 32*n bytes */
mov #32,REG_TMP1
cmp/hi REG_LEN,REG_TMP1
bt 9f
.align 2
1: sub REG_TMP1,REG_PTR
mov.l REG_C,@REG_PTR
sub REG_TMP1,REG_LEN
mov.l REG_C,@(4,REG_PTR)
cmp/hi REG_LEN,REG_TMP1
mov.l REG_C,@(8,REG_PTR)
mov.l REG_C,@(12,REG_PTR)
mov.l REG_C,@(16,REG_PTR)
mov.l REG_C,@(20,REG_PTR)
mov.l REG_C,@(24,REG_PTR)
bf/s 1b
mov.l REG_C,@(28,REG_PTR)
9:
/* fill left 4*n bytes */
cmp/eq REG_DST,REG_PTR
bt 9f
add #4,REG_DST
cmp/eq REG_DST,REG_PTR
1: mov.l REG_C,@-REG_PTR
bt/s 9f
cmp/eq REG_DST,REG_PTR
mov.l REG_C,@-REG_PTR
bt/s 9f
cmp/eq REG_DST,REG_PTR
mov.l REG_C,@-REG_PTR
bt/s 9f
cmp/eq REG_DST,REG_PTR
mov.l REG_C,@-REG_PTR
bf/s 1b
cmp/eq REG_DST,REG_PTR
9:
#ifdef BZERO
rts
nop
#else
rts
mov REG_DST0,r0
#endif
unaligned_dst:
mov #1,REG_TMP1
tst REG_TMP1,REG_DST /* if (dst & 1) { */
add #1,REG_TMP1
bt/s 2f
tst REG_TMP1,REG_DST
mov.b REG_C,@REG_DST /* *dst++ = c; */
add #1,REG_DST
tst REG_TMP1,REG_DST
2: /* } */
/* if (dst & 2) { */
bt 4f
mov.w REG_C,@REG_DST /* *(uint16_t*)dst++ = c; */
add #2,REG_DST
4: /* } */
tst #3,REG_PTR /* if (ptr & 3) { */
bt/s 4f /* */
unaligned_len:
tst #1,REG_PTR /* if (ptr & 1) { */
bt/s 2f
tst #2,REG_PTR
mov.b REG_C,@-REG_PTR /* --ptr = c; */
2: /* } */
/* if (ptr & 2) { */
bt 4f
mov.w REG_C,@-REG_PTR /* *--(uint16_t*)ptr = c; */
4: /* } */
/* } */
mov REG_PTR,REG_LEN
bra aligned
sub REG_DST,REG_LEN
| {
"language": "Assembly"
} |
/* Force .data aligned to 4K, so .got very likely gets at 0x13190
(0x60 bytes .tdata and 0x130 bytes .dynamic) */
.data
.balign 4096
.section ".tdata", "awT", @progbits
.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
sg1: .long 17
sg2: .long 18
sg3: .long 19
sg4: .long 20
sg5: .long 21
sg6: .long 22
sg7: .long 23
sg8: .long 24
sl1: .long 65
sl2: .long 66
sl3: .long 67
sl4: .long 68
sl5: .long 69
sl6: .long 70
sl7: .long 71
sl8: .long 72
sh1: .long 257
sh2: .long 258
sh3: .long 259
sh4: .long 260
sh5: .long 261
sh6: .long 262
sh7: .long 263
sh8: .long 264
.explicit
.pred.safe_across_calls p1-p5,p16-p63
/* Force .text aligned to 4K, so it very likely gets at 0x1000. */
.text
.balign 4096
.globl fn1#
.proc fn1#
fn1:
.prologue 12, 33
.mib
.save ar.pfs, r34
alloc r34 = ar.pfs, 0, 3, 2, 0
.save rp, r33
mov r33 = b0
/* GD */
addl r14 = @ltoff(@dtpmod(sg1#)), gp
addl r15 = @ltoff(@dtprel(sg1#)), gp
;;
ld8 out0 = [r14]
ld8 out1 = [r15]
br.call.sptk.many b0 = __tls_get_addr#
;;
/* GD against hidden symbol */
addl r14 = @ltoff(@dtpmod(sh2#)), gp
addl r15 = @ltoff(@dtprel(sh2#)), gp
;;
ld8 out0 = [r14]
ld8 out1 = [r15]
br.call.sptk.many b0 = __tls_get_addr#
;;
/* LD */
addl r14 = @ltoff(@dtpmod(sl1#)), gp
addl out1 = @dtprel(sl1#) + 1, r0
;;
ld8 out0 = [r14]
br.call.sptk.many b0 = __tls_get_addr#
;;
/* LD with 4 variables variables */
addl r14 = @ltoff(@dtpmod(sh1#)), gp
mov out1 = r0
;;
ld8 out0 = [r14]
br.call.sptk.many b0 = __tls_get_addr#
;;
mov r2 = r8
;;
addl r14 = @dtprel(sh1#), r2
addl r15 = @dtprel(sH1#) + 2, r2
;;
adds r14 = @dtprel(sh5#) + 3, r8
movl r15 = @dtprel(sH5#) + 1
;;
add r15 = r15, r8
;;
/* IE against global */
addl r14 = @ltoff(@tprel(sg2#)), gp
;;
ld8 r15 = [r14]
;;
add r14 = r15, r13
;;
/* IE against local and hidden */
addl r14 = @ltoff(@tprel(sl2#)), gp
addl r15 = @ltoff(@tprel(sh2#)), gp
;;
ld8 r14 = [r14]
ld8 r15 = [r15]
;;
add r14 = r14, r13
add r15 = r15, r13
;;
mov ar.pfs = r34
mov b0 = r33
br.ret.sptk.many b0
.endp fn1#
| {
"language": "Assembly"
} |
/*
* CDDL HEADER START
*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
* http://www.illumos.org/license/CDDL.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 David MacKay. All rights reserved.
* Use is subject to license terms.
*/
%{
#include "svccfg.h"
#include "svccfg.tab.h"
%}
%option reentrant
%option noyywrap
%option stack
%option yylineno
%option extra-type = "char **"
%%
"import" { return TK_IMPORT; }
"quit" { return TK_QUIT; }
"\n" { return TK_NL; }
[^ \t\n"]+ { *yyextra = strdup(yytext); return TK_TEXT; }
" "
| {
"language": "Assembly"
} |
; RUN: opt < %s -loop-simplify -disable-output
define void @test() {
loopentry.0:
br label %loopentry.1
loopentry.1: ; preds = %then.6, %then.6, %loopentry.1, %loopentry.0
%pixel.4 = phi i32 [ 0, %loopentry.0 ], [ %pixel.4, %loopentry.1 ], [ %tmp.370, %then.6 ], [ %tmp.370, %then.6 ] ; <i32> [#uses=1]
br i1 false, label %then.6, label %loopentry.1
then.6: ; preds = %loopentry.1
%tmp.370 = add i32 0, 0 ; <i32> [#uses=2]
switch i32 0, label %label.7 [
i32 6408, label %loopentry.1
i32 32841, label %loopentry.1
]
label.7: ; preds = %then.6
ret void
}
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 %s
// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits -std=c++11 %s 2>&1 | FileCheck %s
[[noreturn()]] void f(); // expected-error {{attribute 'noreturn' cannot have an argument list}} \
// CHECK: fix-it:"{{.*}}":{4:11-4:13}:""
| {
"language": "Assembly"
} |
;---------------------------------------
;
; animation cel data
;
sign3_data::
byte out + 3
byte 0b00000100
byte sign3_start_end - sign3_data
byte no_cont
byte 208+right,12+left,255
byte 0b11111110
byte 0b00011110
byte 0b00000110
byte 0b11111000
word sign3_data_a - sign3_data
word sign3_data_b - sign3_data
word sign3_data_c - sign3_data
word sign3_data_d - sign3_data
word sign3_data_e - sign3_data
word sign3_data_f - sign3_data
word sign3_data_g - sign3_data
sign3_start_end:
byte 0,0,1,1,2,2,3,3
sign3_data_a:
byte cel_box + 0x01, 0x5f, 0x05, 0x4d, 0x00, 0x00
byte 0xaa
sign3_data_b:
byte cel_box + 0x08, 0x05, 0xfd, 0x4d, 0x00, 0x00
byte 0xaa
sign3_data_c:
byte 0x02, 0x08, 0x03, 0x48, 0x00, 0x00
byte run,0x80+4
byte 2
byte 8
byte 32
byte 128
byte 2
byte 8
byte 32
byte 128
byte run,0x80+4
sign3_data_d:
byte cel_box + 0x01, 0x06, 0x02, 0x48, 0x00, 0x00
byte 0x20
sign3_data_e:
byte cel_box + 0x01, 0x06, 0xfd, 0x48, 0x00, 0x00
byte 0x02
sign3_data_f:
byte cel_box + both_bord + 0x08, 0x20, 0xfc, 0x42, 0x00, 0x00
byte 0q1111
sign3_data_g:
byte cel_text + 0x01, 0x01, 0xfc, 0x3e, 0x00, 0x00
byte pat_black
byte 1
| {
"language": "Assembly"
} |
/* arch/arm/mach-tegra/include/mach/entry-macro.S
*
* Copyright (C) 2009 Palm, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/iomap.h>
#include <mach/io.h>
#if defined(CONFIG_ARM_GIC)
#include <asm/hardware/gic.h>
/* Uses the GIC interrupt controller built into the cpu */
#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
movw \base, #(ICTRL_BASE & 0x0000ffff)
movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an interrupt
* if it's between 30 and 1020. The test_for_ipi routine below will
* pick up on IPIs.
*
* A simple read from the controller will tell us the number of the
* highest priority enabled interrupt. We then just need to check
* whether it is in the valid range for an IRQ (30-1020 inclusive).
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* bits 12-10 = src CPU, 9-0 = int # */
ldr \irqstat, [\base, #GIC_CPU_INTACK]
ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt on the
* controller, since this requires the original irqstat value which
* we won't easily be able to recreate later.
*/
.macro test_for_ipi, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #16
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
#else
/* legacy interrupt controller for AP16 */
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
@ enable imprecise aborts
cpsie a
@ EVP base at 0xf010f000
mov \base, #0xf0000000
orr \base, #0x00100000
orr \base, #0x0000f000
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS
cmp \irqnr, #0x80
.endm
#endif
| {
"language": "Assembly"
} |
/*************************************************************
*
* MathJax/jax/output/HTML-CSS/fonts/STIX/General/Bold/LetterlikeSymbols.js
*
* Copyright (c) 2009-2018 The MathJax Consortium
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
MathJax.Hub.Insert(
MathJax.OutputJax['HTML-CSS'].FONTDATA.FONTS['STIXGeneral-bold'],
{
0x2102: [691,19,727,45,672], // stix-mathematical bold oblique double-struck capital C
0x2105: [688,12,873,38,835], // CARE OF
0x2107: [691,19,699,65,662], // EULER CONSTANT
0x210C: [701,205,843,42,795], // BLACK-LETTER CAPITAL H
0x210D: [676,0,768,75,693], // stix-mathematical bold oblique double-struck capital H
0x210E: [685,10,576,50,543], // PLANCK CONSTANT
0x210F: [685,10,576,50,543], // stix-/hbar - Planck's over 2pi
0x2111: [701,25,790,54,735], // BLACK-LETTER CAPITAL I
0x2113: [699,14,500,43,632], // SCRIPT SMALL L
0x2115: [676,0,738,75,663], // stix-mathematical bold oblique double-struck capital N
0x2116: [691,18,1093,10,1042], // NUMERO SIGN
0x2117: [691,19,747,26,721], // SOUND RECORDING COPYRIGHT
0x2118: [541,219,850,55,822], // SCRIPT CAPITAL P
0x2119: [676,0,700,75,670], // stix-mathematical bold oblique double-struck capital P
0x211A: [691,64,797,45,747], // stix-mathematical bold oblique double-struck capital Q
0x211C: [701,25,884,50,841], // BLACK-LETTER CAPITAL R
0x211D: [676,0,783,75,758], // stix-mathematical bold oblique double-struck capital R
0x211E: [676,101,722,26,726], // PRESCRIPTION TAKE
0x2122: [676,-271,1000,24,977], // TRADE MARK SIGN
0x2124: [691,0,777,52,727], // stix-mathematical bold oblique double-struck capital Z
0x2125: [676,205,448,21,424], // OUNCE SIGN
0x2126: [692,0,758,35,723], // OHM SIGN
0x2127: [674,18,758,35,723], // INVERTED OHM SIGN
0x2128: [701,195,755,44,703], // BLACK-LETTER CAPITAL Z
0x2129: [475,0,312,9,244], // TURNED GREEK SMALL LETTER IOTA
0x212B: [920,0,722,9,689], // ANGSTROM SIGN
0x212D: [701,19,773,54,731], // BLACK-LETTER CAPITAL C
0x2132: [676,0,616,48,546], // TURNED CAPITAL F
0x2135: [694,34,766,76,690], // ALEF SYMBOL
0x2136: [694,34,703,60,659], // BET SYMBOL
0x2137: [694,34,562,71,493], // GIMEL SYMBOL
0x2138: [694,34,599,40,559], // DALET SYMBOL
0x213C: [461,11,804,55,759], // DOUBLE-STRUCK SMALL PI
0x213D: [486,203,646,23,624], // DOUBLE-STRUCK SMALL GAMMA
0x213E: [676,0,497,75,643], // DOUBLE-STRUCK CAPITAL GAMMA
0x213F: [676,0,768,75,693], // DOUBLE-STRUCK CAPITAL PI
0x2140: [773,269,976,36,952], // DOUBLE-STRUCK N-ARY SUMMATION
0x214B: [690,17,833,61,788] // TURNED AMPERSAND
}
);
MathJax.Ajax.loadComplete(MathJax.OutputJax["HTML-CSS"].fontDir + "/General/Bold/LetterlikeSymbols.js");
| {
"language": "Assembly"
} |
; Test that the strcpy library call simplifier works correctly.
; RUN: opt < %s -instcombine -S | FileCheck %s
;
; This transformation requires the pointer size, as it assumes that size_t is
; the size of a pointer.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
@hello = constant [6 x i8] c"hello\00"
@a = common global [32 x i8] zeroinitializer, align 1
declare i16* @strcpy(i8*, i8*)
define void @test_no_simplify1() {
; CHECK-LABEL: @test_no_simplify1(
%dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
%src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
call i16* @strcpy(i8* %dst, i8* %src)
; CHECK: call i16* @strcpy
ret void
}
| {
"language": "Assembly"
} |
; RUN: %souper-check -print-counterexample=false -reinfer-rhs %s > %t 2>&1
; RUN: %FileCheck %s < %t
; CHECK: no cost regression
; CHECK: no cost regression
; CHECK: no cost regression
; CHECK: no cost regression
; CHECK: no cost regression
%0:i8 = var (knownBits=xxxx0000)
%1:i8 = var (knownBits=0000xxxx)
%2:i8 = and %0, %1
%3:i1 = eq %2, 0:i8
cand %3 1:i1
%0:i16 = var (knownBits=1x1x1x1x1x1x1x1x)
%1:i16 = var (knownBits=x1x1x1x1x1x1x1x1)
%2:i16 = or %0, %1
%3:i1 = eq %2, 65535:i16
cand %3 1:i1
%0:i64 = var (knownBits=1111111111111111111111111111111111111111111111111111111111111111)
%1:i64 = var (knownBits=0000000000000000000000000000000000000000000000000000000000000000)
%2:i64 = and %0, %1
%3:i1 = eq %2, 0:i64
cand %3 1:i1
%0:i32 = var (knownBits=10000000000000000000000000000000)
%1:i1 = eq 0:i32, %0
cand %1 0:i1
%0:i128 = var (knownBits=11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111)
%1:i128 = var (knownBits=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)
%2:i128 = and %0, %1
%3:i1 = eq %2, 0:i128
cand %3 1:i1
| {
"language": "Assembly"
} |
--- a/lib/iconv.c 2015-06-06 12:37:05.267944000 -0400
+++ b/lib/iconv.c 2015-06-06 12:37:27.311277142 -0400
@@ -176,9 +176,6 @@
#include "aliases2.h"
#undef S
};
-#ifdef __GNUC__
-__inline
-#endif
const struct alias *
aliases2_lookup (register const char *str)
{
| {
"language": "Assembly"
} |
/*
* Copyright © 2016 Broadcom
* Copyright © 2020 Google LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
/* Unit test for disassembly of instructions.
*
* The goal is to take instructions we've seen the blob produce, and test that
* we can disassemble them correctly. For the next person investigating the
* behavior of this instruction, please include the testcase it was generated
* from, and the qcom disassembly as a comment if it differs from what we
* produce.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "util/macros.h"
#include "disasm.h"
#define INSTR_5XX(i, d) { .gpu_id = 540, .instr = #i, .expected = d }
#define INSTR_6XX(i, d) { .gpu_id = 630, .instr = #i, .expected = d }
static const struct test {
int gpu_id;
const char *instr;
const char *expected;
} tests[] = {
/* cat0 */
INSTR_6XX(00000000_00000000, "nop"),
INSTR_6XX(00000200_00000000, "(rpt2)nop"),
INSTR_6XX(03000000_00000000, "end"),
INSTR_6XX(00800000_00000004, "br p0.x, #4"),
INSTR_6XX(00900000_00000003, "br !p0.x, #3"),
INSTR_6XX(03820000_00000015, "shps #21"), /* emit */
INSTR_6XX(04021000_00000000, "(ss)shpe"), /* cut */
INSTR_6XX(02820000_00000014, "getone #20"), /* kill p0.x */
/* cat1 */
INSTR_6XX(20244000_00000020, "mov.f32f32 r0.x, c8.x"),
INSTR_6XX(20200000_00000020, "mov.f16f16 hr0.x, hc8.x"),
INSTR_6XX(20150000_00000000, "cov.s32s16 hr0.x, r0.x"),
INSTR_6XX(20156004_00000c11, "(ul)mov.s32s32 r1.x, c<a0.x + 17>"),
INSTR_6XX(201100f4_00000000, "mova a0.x, hr0.x"),
INSTR_6XX(20244905_00000410, "(rpt1)mov.f32f32 r1.y, (r)c260.x"),
/* cat2 */
INSTR_6XX(40104002_0c210001, "add.f hr0.z, r0.y, c<a0.x + 33>"),
INSTR_6XX(40b80804_10408004, "(nop3) cmps.f.lt r1.x, (abs)r1.x, c16.x"),
INSTR_6XX(47308a02_00002000, "(rpt2)bary.f (ei)r0.z, (r)0, r0.x"),
INSTR_6XX(43480801_00008001, "(nop3) absneg.s hr0.y, (abs)hr0.y"),
/* cat3 */
INSTR_6XX(66000000_10421041, "sel.f16 hr0.x, hc16.y, hr0.x, hc16.z"),
INSTR_6XX(64848109_109a9099, "(rpt1)sel.b32 r2.y, c38.y, (r)r2.y, c38.z"),
INSTR_6XX(64810904_30521036, "(rpt1)sel.b32 r1.x, (r)c13.z, r0.z, (r)c20.z"),
INSTR_6XX(64818902_20041032, "(rpt1)sel.b32 r0.z, (r)c12.z, r0.w, (r)r1.x"),
INSTR_6XX(63820005_10315030, "mad.f32 r1.y, (neg)c12.x, r1.x, c12.y"),
INSTR_6XX(62050009_00091000, "mad.u24 r2.y, c0.x, r2.z, r2.y"),
/* cat4 */
INSTR_6XX(8010000a_00000003, "rcp r2.z, r0.w"),
/* cat5 */
/* dEQP-VK.glsl.derivate.dfdx.uniform_if.float_mediump */
INSTR_6XX(a3801102_00000001, "dsx (f32)(x)r0.z, r0.x"), /* dsx (f32)(xOOO)r0.z, r0.x */
/* dEQP-VK.glsl.derivate.dfdy.uniform_if.float_mediump */
INSTR_6XX(a3c01102_00000001, "dsy (f32)(x)r0.z, r0.x"), /* dsy (f32)(xOOO)r0.z, r0.x */
/* dEQP-VK.glsl.derivate.dfdxfine.uniform_loop.float_highp */
INSTR_6XX(a6001105_00000001, "dsxpp.1 (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
INSTR_6XX(a6201105_00000001, "dsxpp.1.p (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
INSTR_6XX(a2802f00_00000001, "getsize (u16)(xyzw)hr0.x, r0.x, t#0"),
/* cat6 */
INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x"),
/* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
INSTR_6XX(c0d20906_02800004, "stg.f32 g[r1.x+r1.z], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */
/* TODO: We don't support disasm of stc yet and produce a stgb instead
* (same as their disasm does for other families. They're used as part
* uniforms setup, followed by a shpe and then a load of the constant that
* was stored in the dynamic part of the shader.
*/
/* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
/* INSTR_6XX(c7020020_01800000, "stc c[32], r0.x, 1"), */
/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
/* INSTR_6XX(c7060020_03800000, "stc c[32], r0.x, 3"), */
/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
INSTR_6XX(c0260200_03676100, "stib.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
/* dEQP-VK.texture.filtering.cube.formats.a8b8g8r8_srgb_nearest_mipmap_nearest.txt */
INSTR_6XX(c0220200_0361b801, "ldib.typed.1d.f32.4.imm r0.x, r0.w, 1"), /* ldib.f32.1d.4.mode0.base0 r0.x, r0.w, 1 */
/* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
INSTR_6XX(c2c21100_04800006, "stlw.f32 l[r2.x], r0.w, 4"),
INSTR_6XX(c2c20f00_01800004, "stlw.f32 l[r1.w], r0.z, 1"),
INSTR_6XX(c2860003_02808011, "ldlw.u32 r0.w, l[r0.z+8], 2"),
/* dEQP-VK.compute.basic.shared_var_single_group */
INSTR_6XX(c1060500_01800008, "stl.u32 l[r0.z], r1.x, 1"),
INSTR_6XX(c0460001_01804001, "ldl.u32 r0.y, l[r0.y], 1"),
/* resinfo */
INSTR_6XX(c0260000_0063c200, "resinfo.untyped.2d.u32.1.imm r0.x, 0"), /* resinfo.u32.2d.mode0.base0 r0.x, 0 */
/* dEQP-GLES31.functional.image_load_store.buffer.image_size.writeonly_7.txt */
INSTR_6XX(c0260000_0063c000, "resinfo.untyped.1d.u32.1.imm r0.x, 0"), /* resinfo.u32.1d.mode0.base0 r0.x, 0 */
/* dEQP-VK.image.image_size.2d.readonly_12x34.txt */
INSTR_6XX(c0260000_0063c300, "resinfo.untyped.2d.u32.1.imm.base0 r0.x, 0"), /* resinfo.u32.2d.mode4.base0 r0.x, 0 */
/* dEQP-GLES31.functional.image_load_store.buffer.image_size.readonly_writeonly_7 */
INSTR_5XX(c3e60000_00000e00, "resinfo.4d r0.x, g[0]"), /* resinfo.u32.1dtype r0.x, 0 */
/* dEQP-GLES31.functional.image_load_store.2d.image_size.readonly_writeonly_32x32.txt */
INSTR_5XX(c3e60000_00000200, "resinfo.2d r0.x, g[0]"), /* resinfo.u32.2d r0.x, 0 */
/* dEQP-GLES31.functional.image_load_store.3d.image_size.readonly_writeonly_12x34x56 */
INSTR_5XX(c3e60000_00000c00, "resinfo.3d r0.x, g[0]"), /* resinfo.u32.3d r0.x, 0 */
/* ldgb */
/* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_vec4 */
INSTR_5XX(c6e20000_06003600, "ldgb.untyped.4d.f32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.f32.4 r0.x, g[r0.x], r1.z, 0 */
/* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_ivec4 */
INSTR_5XX(c6ea0000_06003600, "ldgb.untyped.4d.s32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.s32.4 r0.x, g[r0.x], r1.z, 0 */
/* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_float */
INSTR_5XX(c6e20000_02000600, "ldgb.untyped.4d.f32.1 r0.x, g[0], r0.x, r0.z"), /* ldgb.a.untyped.1dtype.f32.1 r0.x, g[r0.x], r0.z, 0 */
/* dEQP-GLES31.functional.ssbo.layout.random.vector_types.0 */
INSTR_5XX(c6ea0008_14002600, "ldgb.untyped.4d.s32.3 r2.x, g[0], r0.x, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r2.x, g[r0.x], r5.x, 0 */
INSTR_5XX(c6ea0204_1401a600, "ldgb.untyped.4d.s32.3 r1.x, g[1], r1.z, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r1.x, g[r1.z], r5.x, 1 */
/* discard stuff */
INSTR_6XX(42b400f8_20010004, "cmps.s.eq p0.x, r1.x, 1"),
INSTR_6XX(02800000_00000000, "kill p0.x"),
/* Immediates */
INSTR_6XX(40100007_68000008, "add.f r1.w, r2.x, (neg)(0.0)"),
INSTR_6XX(40100007_68010008, "add.f r1.w, r2.x, (neg)(0.5)"),
INSTR_6XX(40100007_68020008, "add.f r1.w, r2.x, (neg)(1.0)"),
INSTR_6XX(40100007_68030008, "add.f r1.w, r2.x, (neg)(2.0)"),
INSTR_6XX(40100007_68040008, "add.f r1.w, r2.x, (neg)(e)"),
INSTR_6XX(40100007_68050008, "add.f r1.w, r2.x, (neg)(pi)"),
INSTR_6XX(40100007_68060008, "add.f r1.w, r2.x, (neg)(1/pi)"),
INSTR_6XX(40100007_68070008, "add.f r1.w, r2.x, (neg)(1/log2(e))"),
INSTR_6XX(40100007_68080008, "add.f r1.w, r2.x, (neg)(log2(e))"),
INSTR_6XX(40100007_68090008, "add.f r1.w, r2.x, (neg)(1/log2(10))"),
INSTR_6XX(40100007_680a0008, "add.f r1.w, r2.x, (neg)(log2(10))"),
INSTR_6XX(40100007_680b0008, "add.f r1.w, r2.x, (neg)(4.0)"),
/* LDC. Our disasm differs greatly from qcom here, and we've got some
* important info they lack(?!), but same goes the other way.
*/
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment */
INSTR_6XX(c0260000_00c78040, "ldc.offset0.1.uniform r0.x, r0.x, r0.x"), /* ldc.1.mode1.base0 r0.x, 0, r0.x */
INSTR_6XX(c0260201_00c78040, "ldc.offset0.1.uniform r0.y, r0.x, r0.y"), /* ldc.1.mode1.base0 r0.y, 0, r0.y */
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_fragment */
INSTR_6XX(c0260000_00c78080, "ldc.offset0.1.nonuniform r0.x, r0.x, r0.x"), /* ldc.1.mode2.base0 r0.x, 0, r0.x */
INSTR_6XX(c0260201_00c78080, "ldc.offset0.1.nonuniform r0.y, r0.x, r0.y"), /* ldc.1.mode2.base0 r0.y, 0, r0.y */
/* custom shaders, loading .x, .y, .z, .w from an array of vec4 in block 0 */
INSTR_6XX(c0260000_00478000, "ldc.offset0.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_6XX(c0260000_00478200, "ldc.offset1.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_6XX(c0260000_00478400, "ldc.offset2.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_6XX(c0260000_00478600, "ldc.offset3.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
/* dEQP-VK.glsl.struct.local.nested_struct_array_dynamic_index_fragment */
INSTR_6XX(c1425b50_01803e02, "stp.f32 p[r11.y-176], r0.y, 1"),
INSTR_6XX(c1425b98_02803e14, "stp.f32 p[r11.y-104], r2.z, 2"),
INSTR_6XX(c1465ba0_01803e2a, "stp.u32 p[r11.y-96], r5.y, 1"),
INSTR_6XX(c0860008_01860001, "ldp.u32 r2.x, p[r6.x], 1"),
/* Custom stp based on above to catch a disasm bug. */
INSTR_6XX(c1465b00_0180022a, "stp.u32 p[r11.y+256], r5.y, 1"),
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.fragment.sampler2d (looks like maybe the compiler didn't figure out */
INSTR_6XX(a0c81f07_0100000b, "sam.s2en (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode0 (f32)(xyzw)r1.w, r1.y, hr2.x */
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.dynamically_uniform.fragment.sampler2d */
INSTR_6XX(a0c81f07_8100000b, "sam.s2en.uniform (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode4 (f32)(xyzw)r1.w, r1.y, hr2.x */
};
static void
trim(char *string)
{
for (int len = strlen(string); len > 0 && string[len - 1] == '\n'; len--)
string[len - 1] = 0;
}
int
main(int argc, char **argv)
{
int retval = 0;
const int output_size = 4096;
char *disasm_output = malloc(output_size);
FILE *fdisasm = fmemopen(disasm_output, output_size, "w+");
if (!fdisasm) {
fprintf(stderr, "failed to fmemopen\n");
return 1;
}
for (int i = 0; i < ARRAY_SIZE(tests); i++) {
const struct test *test = &tests[i];
printf("Testing a%d %s: \"%s\"...\n",
test->gpu_id, test->instr, test->expected);
rewind(fdisasm);
memset(disasm_output, 0, output_size);
uint32_t code[2] = {
strtoll(&test->instr[9], NULL, 16),
strtoll(&test->instr[0], NULL, 16),
};
disasm_a3xx(code, ARRAY_SIZE(code), 0, fdisasm, test->gpu_id);
fflush(fdisasm);
trim(disasm_output);
if (strcmp(disasm_output, test->expected) != 0) {
printf("FAIL\n");
printf(" Expected: \"%s\"\n", test->expected);
printf(" Got: \"%s\"\n", disasm_output);
retval = 1;
continue;
}
}
fclose(fdisasm);
free(disasm_output);
return retval;
}
| {
"language": "Assembly"
} |
; RUN: opt -S -unroll-runtime -loop-unroll < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
;; Check that we don't emit expensive instructions to compute trip
;; counts when unrolling loops.
define i32 @test(i64 %v12, i8* %array, i64* %loc) {
; CHECK-LABEL: @test(
; CHECK-NOT: udiv
entry:
%step = load i64, i64* %loc, !range !0
br label %loop
loop: ; preds = %entry, %loop
%k.015 = phi i64 [ %v15, %loop ], [ %v12, %entry ]
%v14 = getelementptr inbounds i8, i8* %array, i64 %k.015
store i8 0, i8* %v14
%v15 = add nuw nsw i64 %k.015, %step
%v16 = icmp slt i64 %v15, 8193
br i1 %v16, label %loop, label %loopexit
loopexit: ; preds = %loop
ret i32 0
}
;; Though SCEV for loop tripcount contains division,
;; it shouldn't be considered expensive, since the division already
;; exists in the code and we don't need to expand it once more.
;; Thus, it shouldn't prevent us from unrolling the loop.
define i32 @test2(i64* %loc, i64 %conv7) {
; CHECK-LABEL: @test2(
; CHECK: udiv
; CHECK: udiv
; CHECK-NOT: udiv
; CHECK-LABEL: for.body
entry:
%rem0 = load i64, i64* %loc, align 8
%ExpensiveComputation = udiv i64 %rem0, 42 ; <<< Extra computations are added to the trip-count expression
br label %bb1
bb1:
%div11 = udiv i64 %ExpensiveComputation, %conv7
%cmp.i38 = icmp ugt i64 %div11, 1
%div12 = select i1 %cmp.i38, i64 %div11, i64 1
br label %for.body
for.body:
%rem1 = phi i64 [ %rem0, %bb1 ], [ %rem2, %for.body ]
%k1 = phi i64 [ %div12, %bb1 ], [ %dec, %for.body ]
%mul1 = mul i64 %rem1, 48271
%rem2 = urem i64 %mul1, 2147483647
%dec = add i64 %k1, -1
%cmp = icmp eq i64 %dec, 0
br i1 %cmp, label %exit, label %for.body
exit:
%rem3 = phi i64 [ %rem2, %for.body ]
store i64 %rem3, i64* %loc, align 8
ret i32 0
}
!0 = !{i64 1, i64 100}
| {
"language": "Assembly"
} |
// RUN: not %clang -std=c++98 %s -Wno-c++0x-compat -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX98 %s
// RUN: not %clang -std=gnu++98 %s -Wno-c++0x-compat -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX98 %s
// RUN: not %clang -std=c++03 %s -Wno-c++0x-compat -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX98 %s
// RUN: not %clang -std=c++0x %s -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX11 %s
// RUN: not %clang -std=gnu++0x %s -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX11 %s
// RUN: not %clang -std=c++11 %s -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX11 %s
// RUN: not %clang -std=gnu++11 %s -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX11 %s
// RUN: not %clang -std=c++1y %s -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX1Y %s
// RUN: not %clang -std=gnu++1y %s -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX1Y %s
// RUN: not %clang -std=c++1z %s -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX1Z %s
// RUN: not %clang -std=gnu++1z %s -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX1Z %s
// RUN: not %clang -std=c++2a %s -fsyntax-only 2>&1 | FileCheck -check-prefix=CXX2A %s
// RUN: not %clang -std=gnu++2a %s -fsyntax-only 2>&1 | FileCheck -check-prefix=GNUXX2A %s
void f(int n) {
typeof(n)();
decltype(n)();
}
// CXX98: undeclared identifier 'typeof'
// CXX98: undeclared identifier 'decltype'
// GNUXX98-NOT: undeclared identifier 'typeof'
// GNUXX98: undeclared identifier 'decltype'
// CXX11: undeclared identifier 'typeof'
// CXX11-NOT: undeclared identifier 'decltype'
// GNUXX11-NOT: undeclared identifier 'typeof'
// GNUXX11-NOT: undeclared identifier 'decltype'
// CXX1Y: undeclared identifier 'typeof'
// CXX1Y-NOT: undeclared identifier 'decltype'
// GNUXX1Y-NOT: undeclared identifier 'typeof'
// GNUXX1Y-NOT: undeclared identifier 'decltype'
// CXX1Z: undeclared identifier 'typeof'
// CXX1Z-NOT: undeclared identifier 'decltype'
// GNUXX1Z-NOT: undeclared identifier 'typeof'
// GNUXX1Z-NOT: undeclared identifier 'decltype'
// CXX2A: undeclared identifier 'typeof'
// CXX2A-NOT: undeclared identifier 'decltype'
// GNUXX2A-NOT: undeclared identifier 'typeof'
// GNUXX2A-NOT: undeclared identifier 'decltype'
| {
"language": "Assembly"
} |
; Test that the inliner doesn't leave around dead allocas, and that it folds
; uncond branches away after it is done specializing.
; RUN: opt < %s -inline -S | FileCheck %s
; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s
@A = weak global i32 0 ; <i32*> [#uses=1]
@B = weak global i32 0 ; <i32*> [#uses=1]
@C = weak global i32 0 ; <i32*> [#uses=1]
define internal fastcc void @foo(i32 %X) {
entry:
%ALL = alloca i32, align 4 ; <i32*> [#uses=1]
%tmp1 = and i32 %X, 1 ; <i32> [#uses=1]
%tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
br i1 %tmp1.upgrd.1, label %cond_next, label %cond_true
cond_true: ; preds = %entry
store i32 1, i32* @A
br label %cond_next
cond_next: ; preds = %cond_true, %entry
%tmp4 = and i32 %X, 2 ; <i32> [#uses=1]
%tmp4.upgrd.2 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]
br i1 %tmp4.upgrd.2, label %cond_next7, label %cond_true5
cond_true5: ; preds = %cond_next
store i32 1, i32* @B
br label %cond_next7
cond_next7: ; preds = %cond_true5, %cond_next
%tmp10 = and i32 %X, 4 ; <i32> [#uses=1]
%tmp10.upgrd.3 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1]
br i1 %tmp10.upgrd.3, label %cond_next13, label %cond_true11
cond_true11: ; preds = %cond_next7
store i32 1, i32* @C
br label %cond_next13
cond_next13: ; preds = %cond_true11, %cond_next7
%tmp16 = and i32 %X, 8 ; <i32> [#uses=1]
%tmp16.upgrd.4 = icmp eq i32 %tmp16, 0 ; <i1> [#uses=1]
br i1 %tmp16.upgrd.4, label %UnifiedReturnBlock, label %cond_true17
cond_true17: ; preds = %cond_next13
call void @ext( i32* %ALL )
ret void
UnifiedReturnBlock: ; preds = %cond_next13
ret void
}
declare void @ext(i32*)
define void @test() {
; CHECK-LABEL: @test(
; CHECK-NOT: ret
;
; FIXME: This should be a CHECK-NOT, but currently we have a bug that causes us
; to not nuke unused allocas.
; CHECK: alloca
; CHECK-NOT: ret
;
; No branches should survive the inliner's cleanup.
; CHECK-NOT: br
; CHECK: ret void
entry:
tail call fastcc void @foo( i32 1 )
tail call fastcc void @foo( i32 2 )
tail call fastcc void @foo( i32 3 )
tail call fastcc void @foo( i32 8 )
ret void
}
declare void @f(i32 %x)
define void @inner2(i32 %x, i32 %y, i32 %z, i1 %b) {
entry:
%cmp1 = icmp ne i32 %x, 0
br i1 %cmp1, label %then1, label %end1
then1:
call void @f(i32 %x)
br label %end1
end1:
%x2 = and i32 %x, %z
%cmp2 = icmp sgt i32 %x2, 1
br i1 %cmp2, label %then2, label %end2
then2:
call void @f(i32 %x2)
br label %end2
end2:
%y2 = or i32 %y, %z
%cmp3 = icmp sgt i32 %y2, 0
br i1 %cmp3, label %then3, label %end3
then3:
call void @f(i32 %y2)
br label %end3
end3:
br i1 %b, label %end3.1, label %end3.2
end3.1:
%x3.1 = or i32 %x, 10
br label %end3.3
end3.2:
%x3.2 = or i32 %x, 10
br label %end3.3
end3.3:
%x3.3 = phi i32 [ %x3.1, %end3.1 ], [ %x3.2, %end3.2 ]
%cmp4 = icmp slt i32 %x3.3, 1
br i1 %cmp4, label %then4, label %end4
then4:
call void @f(i32 %x3.3)
br label %end4
end4:
ret void
}
define void @outer2(i32 %z, i1 %b) {
; Ensure that after inlining, none of the blocks with a call to @f actually
; make it through inlining.
; CHECK-LABEL: define void @outer2(
; CHECK-NOT: call
; CHECK: ret void
entry:
call void @inner2(i32 0, i32 -1, i32 %z, i1 %b)
ret void
}
define void @PR12470_inner(i16 signext %p1) nounwind uwtable {
entry:
br i1 undef, label %cond.true, label %cond.false
cond.true:
br label %cond.end
cond.false:
%conv = sext i16 %p1 to i32
br label %cond.end
cond.end:
%cond = phi i32 [ undef, %cond.true ], [ 0, %cond.false ]
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.end5, label %if.then
if.then:
ret void
if.end5:
ret void
}
define void @PR12470_outer() {
; This previously crashed during inliner cleanup and folding inner return
; instructions. Check that we don't crash and we produce a function with a single
; return instruction due to merging the returns of the inlined function.
; CHECK-LABEL: define void @PR12470_outer(
; CHECK-NOT: call
; CHECK: ret void
; CHECK-NOT: ret void
; CHECK: }
entry:
call void @PR12470_inner(i16 signext 1)
ret void
}
define void @crasher_inner() nounwind uwtable {
entry:
br i1 false, label %for.end28, label %for.body6
for.body6:
br i1 undef, label %for.body6, label %for.cond12.for.inc26_crit_edge
for.cond12.for.inc26_crit_edge:
br label %for.body6.1
for.end28:
ret void
for.body6.1:
br i1 undef, label %for.body6.1, label %for.cond12.for.inc26_crit_edge.1
for.cond12.for.inc26_crit_edge.1:
br label %for.body6.2
for.body6.2:
br i1 undef, label %for.body6.2, label %for.cond12.for.inc26_crit_edge.2
for.cond12.for.inc26_crit_edge.2:
br label %for.end28
}
define void @crasher_outer() {
; CHECK-LABEL: @crasher_outer(
; CHECK-NOT: call
; CHECK: ret void
; CHECK-NOT: ret
; CHECK: }
entry:
tail call void @crasher_inner()
ret void
}
| {
"language": "Assembly"
} |
// RUN: mlir-opt -allow-unregistered-dialect %s | FileCheck %s
// Verify the printed output can be parsed.
// RUN: mlir-opt -allow-unregistered-dialect %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
// Verify the generic form can be parsed.
// RUN: mlir-opt -allow-unregistered-dialect -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
// CHECK: #map0 = affine_map<(d0) -> (d0 + 1)>
// CHECK: #map1 = affine_map<()[s0] -> (s0 + 1)>
// CHECK-DAG: #[[$BASE_MAP0:map[0-9]+]] = affine_map<(d0, d1, d2) -> (d0 * 64 + d1 * 4 + d2)>
// CHECK-DAG: #[[$BASE_MAP3:map[0-9]+]] = affine_map<(d0, d1, d2)[s0, s1, s2, s3] -> (d0 * s1 + s0 + d1 * s2 + d2 * s3)>
// CHECK-DAG: #[[$BASE_MAP1:map[0-9]+]] = affine_map<(d0)[s0] -> (d0 + s0)>
// CHECK-DAG: #[[$SUBVIEW_MAP1:map[0-9]+]] = affine_map<(d0)[s0, s1] -> (d0 * s1 + s0)>
// CHECK-DAG: #[[$BASE_MAP2:map[0-9]+]] = affine_map<(d0, d1) -> (d0 * 22 + d1)>
// CHECK-DAG: #[[$SUBVIEW_MAP2:map[0-9]+]] = affine_map<(d0, d1)[s0, s1, s2] -> (d0 * s1 + s0 + d1 * s2)>
// CHECK-DAG: #[[$SUBVIEW_MAP3:map[0-9]+]] = affine_map<(d0, d1, d2) -> (d0 * 64 + d1 * 4 + d2 + 8)>
// CHECK-DAG: #[[$SUBVIEW_MAP4:map[0-9]+]] = affine_map<(d0, d1)[s0, s1] -> (d0 * s1 + s0 + d1)>
// CHECK-DAG: #[[$SUBVIEW_MAP5:map[0-9]+]] = affine_map<(d0, d1)[s0] -> (d0 * 8 + s0 + d1 * 2)>
// CHECK-LABEL: func @func_with_ops
// CHECK-SAME: %[[ARG:.*]]: f32
func @func_with_ops(f32) {
^bb0(%a : f32):
// CHECK: %[[T:.*]] = "getTensor"() : () -> tensor<4x4x?xf32>
%t = "getTensor"() : () -> tensor<4x4x?xf32>
// CHECK: %[[C2:.*]] = constant 2 : index
// CHECK-NEXT: %{{.*}} = dim %[[T]], %[[C2]] : tensor<4x4x?xf32>
%c2 = constant 2 : index
%t2 = "std.dim"(%t, %c2) : (tensor<4x4x?xf32>, index) -> index
// CHECK: %{{.*}} = addf %[[ARG]], %[[ARG]] : f32
%x = "std.addf"(%a, %a) : (f32,f32) -> (f32)
// CHECK: return
return
}
// CHECK-LABEL: func @standard_instrs(%arg0: tensor<4x4x?xf32>, %arg1: f32, %arg2: i32, %arg3: index, %arg4: i64, %arg5: f16) {
func @standard_instrs(tensor<4x4x?xf32>, f32, i32, index, i64, f16) {
^bb42(%t: tensor<4x4x?xf32>, %f: f32, %i: i32, %idx : index, %j: i64, %half: f16):
// CHECK: %[[C2:.*]] = constant 2 : index
// CHECK: %[[A2:.*]] = dim %arg0, %[[C2]] : tensor<4x4x?xf32>
%c2 = constant 2 : index
%a2 = dim %t, %c2 : tensor<4x4x?xf32>
// CHECK: %[[F2:.*]] = addf %arg1, %arg1 : f32
%f2 = "std.addf"(%f, %f) : (f32,f32) -> f32
// CHECK: %[[F3:.*]] = addf %[[F2]], %[[F2]] : f32
%f3 = addf %f2, %f2 : f32
// CHECK: %[[I2:.*]] = addi %arg2, %arg2 : i32
%i2 = "std.addi"(%i, %i) : (i32,i32) -> i32
// CHECK: %[[I3:.*]] = addi %[[I2]], %[[I2]] : i32
%i3 = addi %i2, %i2 : i32
// CHECK: %[[IDX1:.*]] = addi %arg3, %arg3 : index
%idx1 = addi %idx, %idx : index
// CHECK: %[[IDX2:.*]] = addi %arg3, %[[IDX1]] : index
%idx2 = "std.addi"(%idx, %idx1) : (index, index) -> index
// CHECK: %[[F4:.*]] = subf %arg1, %arg1 : f32
%f4 = "std.subf"(%f, %f) : (f32,f32) -> f32
// CHECK: %[[F5:.*]] = subf %[[F4]], %[[F4]] : f32
%f5 = subf %f4, %f4 : f32
// CHECK: %[[I4:.*]] = subi %arg2, %arg2 : i32
%i4 = "std.subi"(%i, %i) : (i32,i32) -> i32
// CHECK: %[[I5:.*]] = subi %[[I4]], %[[I4]] : i32
%i5 = subi %i4, %i4 : i32
// CHECK: %[[F6:.*]] = mulf %[[F2]], %[[F2]] : f32
%f6 = mulf %f2, %f2 : f32
// CHECK: %[[I6:.*]] = muli %[[I2]], %[[I2]] : i32
%i6 = muli %i2, %i2 : i32
// CHECK: %[[C0:.*]] = create_complex %[[F2]], %[[F2]] : complex<f32>
%c0 = "std.create_complex"(%f2, %f2) : (f32, f32) -> complex<f32>
// CHECK: %[[C1:.*]] = create_complex %[[F2]], %[[F2]] : complex<f32>
%c1 = create_complex %f2, %f2 : complex<f32>
// CHECK: %[[REAL0:.*]] = re %[[CPLX0:.*]] : complex<f32>
%real0 = "std.re"(%c0) : (complex<f32>) -> f32
// CHECK: %[[REAL1:.*]] = re %[[CPLX0]] : complex<f32>
%real1 = re %c0 : complex<f32>
// CHECK: %[[IMAG0:.*]] = im %[[CPLX0]] : complex<f32>
%imag0 = "std.im"(%c0) : (complex<f32>) -> f32
// CHECK: %[[IMAG1:.*]] = im %[[CPLX0]] : complex<f32>
%imag1 = im %c0 : complex<f32>
// CHECK: %c42_i32 = constant 42 : i32
%x = "std.constant"(){value = 42 : i32} : () -> i32
// CHECK: %c42_i32_0 = constant 42 : i32
%7 = constant 42 : i32
// CHECK: %c43 = constant {crazy = "std.foo"} 43 : index
%8 = constant {crazy = "std.foo"} 43: index
// CHECK: %cst = constant 4.300000e+01 : bf16
%9 = constant 43.0 : bf16
// CHECK: %f = constant @func_with_ops : (f32) -> ()
%10 = constant @func_with_ops : (f32) -> ()
// CHECK: %f_1 = constant @affine_apply : () -> ()
%11 = constant @affine_apply : () -> ()
// CHECK: %f_2 = constant @affine_apply : () -> ()
%12 = constant @affine_apply : () -> ()
// CHECK: %cst_3 = constant dense<0> : vector<4xi32>
%13 = constant dense<0> : vector<4 x i32>
// CHECK: %cst_4 = constant dense<0> : tensor<42xi32>
%tci32 = constant dense<0> : tensor<42 x i32>
// CHECK: %cst_5 = constant dense<0> : vector<42xi32>
%vci32 = constant dense<0> : vector<42 x i32>
// CHECK: %{{[0-9]+}} = cmpi "eq", %{{[0-9]+}}, %{{[0-9]+}} : i32
%14 = cmpi "eq", %i3, %i4 : i32
// Predicate 1 means inequality comparison.
// CHECK: %{{[0-9]+}} = cmpi "ne", %{{[0-9]+}}, %{{[0-9]+}} : i32
%15 = "std.cmpi"(%i3, %i4) {predicate = 1} : (i32, i32) -> i1
// CHECK: %{{[0-9]+}} = cmpi "slt", %cst_3, %cst_3 : vector<4xi32>
%16 = cmpi "slt", %13, %13 : vector<4 x i32>
// CHECK: %{{[0-9]+}} = cmpi "ne", %cst_3, %cst_3 : vector<4xi32>
%17 = "std.cmpi"(%13, %13) {predicate = 1} : (vector<4 x i32>, vector<4 x i32>) -> vector<4 x i1>
// CHECK: %{{[0-9]+}} = cmpi "slt", %arg3, %arg3 : index
%18 = cmpi "slt", %idx, %idx : index
// CHECK: %{{[0-9]+}} = cmpi "eq", %cst_4, %cst_4 : tensor<42xi32>
%19 = cmpi "eq", %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = cmpi "eq", %cst_5, %cst_5 : vector<42xi32>
%20 = cmpi "eq", %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = select %{{[0-9]+}}, %arg3, %arg3 : index
%21 = select %18, %idx, %idx : index
// CHECK: %{{[0-9]+}} = select %{{[0-9]+}}, %cst_4, %cst_4 : tensor<42xi1>, tensor<42xi32>
%22 = select %19, %tci32, %tci32 : tensor<42 x i1>, tensor<42 x i32>
// CHECK: %{{[0-9]+}} = select %{{[0-9]+}}, %cst_5, %cst_5 : vector<42xi1>, vector<42xi32>
%23 = select %20, %vci32, %vci32 : vector<42 x i1>, vector<42 x i32>
// CHECK: %{{[0-9]+}} = select %{{[0-9]+}}, %arg3, %arg3 : index
%24 = "std.select"(%18, %idx, %idx) : (i1, index, index) -> index
// CHECK: %{{[0-9]+}} = select %{{[0-9]+}}, %cst_4, %cst_4 : tensor<42xi32>
%25 = std.select %18, %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = divi_signed %arg2, %arg2 : i32
%26 = divi_signed %i, %i : i32
// CHECK: %{{[0-9]+}} = divi_signed %arg3, %arg3 : index
%27 = divi_signed %idx, %idx : index
// CHECK: %{{[0-9]+}} = divi_signed %cst_5, %cst_5 : vector<42xi32>
%28 = divi_signed %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = divi_signed %cst_4, %cst_4 : tensor<42xi32>
%29 = divi_signed %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = divi_signed %arg2, %arg2 : i32
%30 = "std.divi_signed"(%i, %i) : (i32, i32) -> i32
// CHECK: %{{[0-9]+}} = divi_unsigned %arg2, %arg2 : i32
%31 = divi_unsigned %i, %i : i32
// CHECK: %{{[0-9]+}} = divi_unsigned %arg3, %arg3 : index
%32 = divi_unsigned %idx, %idx : index
// CHECK: %{{[0-9]+}} = divi_unsigned %cst_5, %cst_5 : vector<42xi32>
%33 = divi_unsigned %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = divi_unsigned %cst_4, %cst_4 : tensor<42xi32>
%34 = divi_unsigned %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = divi_unsigned %arg2, %arg2 : i32
%35 = "std.divi_unsigned"(%i, %i) : (i32, i32) -> i32
// CHECK: %{{[0-9]+}} = remi_signed %arg2, %arg2 : i32
%36 = remi_signed %i, %i : i32
// CHECK: %{{[0-9]+}} = remi_signed %arg3, %arg3 : index
%37 = remi_signed %idx, %idx : index
// CHECK: %{{[0-9]+}} = remi_signed %cst_5, %cst_5 : vector<42xi32>
%38 = remi_signed %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = remi_signed %cst_4, %cst_4 : tensor<42xi32>
%39 = remi_signed %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = remi_signed %arg2, %arg2 : i32
%40 = "std.remi_signed"(%i, %i) : (i32, i32) -> i32
// CHECK: %{{[0-9]+}} = remi_unsigned %arg2, %arg2 : i32
%41 = remi_unsigned %i, %i : i32
// CHECK: %{{[0-9]+}} = remi_unsigned %arg3, %arg3 : index
%42 = remi_unsigned %idx, %idx : index
// CHECK: %{{[0-9]+}} = remi_unsigned %cst_5, %cst_5 : vector<42xi32>
%43 = remi_unsigned %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = remi_unsigned %cst_4, %cst_4 : tensor<42xi32>
%44 = remi_unsigned %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = remi_unsigned %arg2, %arg2 : i32
%45 = "std.remi_unsigned"(%i, %i) : (i32, i32) -> i32
// CHECK: %{{[0-9]+}} = divf %arg1, %arg1 : f32
%46 = "std.divf"(%f, %f) : (f32,f32) -> f32
// CHECK: %{{[0-9]+}} = divf %arg1, %arg1 : f32
%47 = divf %f, %f : f32
// CHECK: %{{[0-9]+}} = divf %arg0, %arg0 : tensor<4x4x?xf32>
%48 = divf %t, %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = remf %arg1, %arg1 : f32
%49 = "std.remf"(%f, %f) : (f32,f32) -> f32
// CHECK: %{{[0-9]+}} = remf %arg1, %arg1 : f32
%50 = remf %f, %f : f32
// CHECK: %{{[0-9]+}} = remf %arg0, %arg0 : tensor<4x4x?xf32>
%51 = remf %t, %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = and %arg2, %arg2 : i32
%52 = "std.and"(%i, %i) : (i32,i32) -> i32
// CHECK: %{{[0-9]+}} = and %arg2, %arg2 : i32
%53 = and %i, %i : i32
// CHECK: %{{[0-9]+}} = and %cst_5, %cst_5 : vector<42xi32>
%54 = std.and %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = and %cst_4, %cst_4 : tensor<42xi32>
%55 = and %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = or %arg2, %arg2 : i32
%56 = "std.or"(%i, %i) : (i32,i32) -> i32
// CHECK: %{{[0-9]+}} = or %arg2, %arg2 : i32
%57 = or %i, %i : i32
// CHECK: %{{[0-9]+}} = or %cst_5, %cst_5 : vector<42xi32>
%58 = std.or %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = or %cst_4, %cst_4 : tensor<42xi32>
%59 = or %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = xor %arg2, %arg2 : i32
%60 = "std.xor"(%i, %i) : (i32,i32) -> i32
// CHECK: %{{[0-9]+}} = xor %arg2, %arg2 : i32
%61 = xor %i, %i : i32
// CHECK: %{{[0-9]+}} = xor %cst_5, %cst_5 : vector<42xi32>
%62 = std.xor %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = xor %cst_4, %cst_4 : tensor<42xi32>
%63 = xor %tci32, %tci32 : tensor<42 x i32>
%64 = constant dense<0.> : vector<4 x f32>
%tcf32 = constant dense<0.> : tensor<42 x f32>
%vcf32 = constant dense<0.> : vector<4 x f32>
// CHECK: %{{[0-9]+}} = cmpf "ogt", %{{[0-9]+}}, %{{[0-9]+}} : f32
%65 = cmpf "ogt", %f3, %f4 : f32
// Predicate 0 means ordered equality comparison.
// CHECK: %{{[0-9]+}} = cmpf "oeq", %{{[0-9]+}}, %{{[0-9]+}} : f32
%66 = "std.cmpf"(%f3, %f4) {predicate = 1} : (f32, f32) -> i1
// CHECK: %{{[0-9]+}} = cmpf "olt", %cst_8, %cst_8 : vector<4xf32>
%67 = cmpf "olt", %vcf32, %vcf32 : vector<4 x f32>
// CHECK: %{{[0-9]+}} = cmpf "oeq", %cst_8, %cst_8 : vector<4xf32>
%68 = "std.cmpf"(%vcf32, %vcf32) {predicate = 1} : (vector<4 x f32>, vector<4 x f32>) -> vector<4 x i1>
// CHECK: %{{[0-9]+}} = cmpf "oeq", %cst_7, %cst_7 : tensor<42xf32>
%69 = cmpf "oeq", %tcf32, %tcf32 : tensor<42 x f32>
// CHECK: %{{[0-9]+}} = cmpf "oeq", %cst_8, %cst_8 : vector<4xf32>
%70 = cmpf "oeq", %vcf32, %vcf32 : vector<4 x f32>
// CHECK: %{{[0-9]+}} = rank %arg0 : tensor<4x4x?xf32>
%71 = "std.rank"(%t) : (tensor<4x4x?xf32>) -> index
// CHECK: %{{[0-9]+}} = rank %arg0 : tensor<4x4x?xf32>
%72 = rank %t : tensor<4x4x?xf32>
// CHECK: = constant unit
%73 = constant unit
// CHECK: constant true
%74 = constant true
// CHECK: constant false
%75 = constant false
// CHECK: = index_cast {{.*}} : index to i64
%76 = index_cast %idx : index to i64
// CHECK: = index_cast {{.*}} : i32 to index
%77 = index_cast %i : i32 to index
// CHECK: = sitofp {{.*}} : i32 to f32
%78 = sitofp %i : i32 to f32
// CHECK: = sitofp {{.*}} : i32 to f64
%79 = sitofp %i : i32 to f64
// CHECK: = sitofp {{.*}} : i64 to f32
%80 = sitofp %j : i64 to f32
// CHECK: = sitofp {{.*}} : i64 to f64
%81 = sitofp %j : i64 to f64
// CHECK: = sexti %arg2 : i32 to i64
%82 = "std.sexti"(%i) : (i32) -> i64
// CHECK: = sexti %arg2 : i32 to i64
%83 = sexti %i : i32 to i64
// CHECK: %{{[0-9]+}} = sexti %cst_5 : vector<42xi32>
%84 = sexti %vci32 : vector<42 x i32> to vector<42 x i64>
// CHECK: %{{[0-9]+}} = sexti %cst_4 : tensor<42xi32>
%85 = sexti %tci32 : tensor<42 x i32> to tensor<42 x i64>
// CHECK: = zexti %arg2 : i32 to i64
%86 = "std.zexti"(%i) : (i32) -> i64
// CHECK: = zexti %arg2 : i32 to i64
%87 = zexti %i : i32 to i64
// CHECK: %{{[0-9]+}} = zexti %cst_5 : vector<42xi32>
%88 = zexti %vci32 : vector<42 x i32> to vector<42 x i64>
// CHECK: %{{[0-9]+}} = zexti %cst_4 : tensor<42xi32>
%89 = zexti %tci32 : tensor<42 x i32> to tensor<42 x i64>
// CHECK: = trunci %arg2 : i32 to i16
%90 = "std.trunci"(%i) : (i32) -> i16
// CHECK: = trunci %arg2 : i32 to i16
%91 = trunci %i : i32 to i16
// CHECK: %{{[0-9]+}} = trunci %cst_5 : vector<42xi32>
%92 = trunci %vci32 : vector<42 x i32> to vector<42 x i16>
// CHECK: %{{[0-9]+}} = trunci %cst_4 : tensor<42xi32>
%93 = trunci %tci32 : tensor<42 x i32> to tensor<42 x i16>
// CHECK: = fpext {{.*}} : f16 to f32
%94 = fpext %half : f16 to f32
// CHECK: = fptrunc {{.*}} : f32 to f16
%95 = fptrunc %f : f32 to f16
// CHECK: %{{[0-9]+}} = exp %arg1 : f32
%96 = "std.exp"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = exp %arg1 : f32
%97 = exp %f : f32
// CHECK: %{{[0-9]+}} = exp %cst_8 : vector<4xf32>
%98 = exp %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = exp %arg0 : tensor<4x4x?xf32>
%99 = exp %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = absf %arg1 : f32
%100 = "std.absf"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = absf %arg1 : f32
%101 = absf %f : f32
// CHECK: %{{[0-9]+}} = absf %cst_8 : vector<4xf32>
%102 = absf %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = absf %arg0 : tensor<4x4x?xf32>
%103 = absf %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = ceilf %arg1 : f32
%104 = "std.ceilf"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = ceilf %arg1 : f32
%105 = ceilf %f : f32
// CHECK: %{{[0-9]+}} = ceilf %cst_8 : vector<4xf32>
%106 = ceilf %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = ceilf %arg0 : tensor<4x4x?xf32>
%107 = ceilf %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = cos %arg1 : f32
%108 = "std.cos"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = cos %arg1 : f32
%109 = cos %f : f32
// CHECK: %{{[0-9]+}} = cos %cst_8 : vector<4xf32>
%110 = cos %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = cos %arg0 : tensor<4x4x?xf32>
%111 = cos %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = negf %arg1 : f32
%112 = "std.negf"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = negf %arg1 : f32
%113 = negf %f : f32
// CHECK: %{{[0-9]+}} = negf %cst_8 : vector<4xf32>
%114 = negf %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = negf %arg0 : tensor<4x4x?xf32>
%115 = negf %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = copysign %arg1, %arg1 : f32
%116 = "std.copysign"(%f, %f) : (f32, f32) -> f32
// CHECK: %{{[0-9]+}} = copysign %arg1, %arg1 : f32
%117 = copysign %f, %f : f32
// CHECK: %{{[0-9]+}} = copysign %cst_8, %cst_8 : vector<4xf32>
%118 = copysign %vcf32, %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = copysign %arg0, %arg0 : tensor<4x4x?xf32>
%119 = copysign %t, %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = tanh %arg1 : f32
%120 = "std.tanh"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = tanh %arg1 : f32
%121 = tanh %f : f32
// CHECK: %{{[0-9]+}} = tanh %cst_8 : vector<4xf32>
%122 = tanh %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = tanh %arg0 : tensor<4x4x?xf32>
%123 = tanh %t : tensor<4x4x?xf32>
// CHECK: %{{[0-9]+}} = shift_left %arg2, %arg2 : i32
%124 = "std.shift_left"(%i, %i) : (i32, i32) -> i32
// CHECK:%{{[0-9]+}} = shift_left %[[I2]], %[[I2]] : i32
%125 = shift_left %i2, %i2 : i32
// CHECK: %{{[0-9]+}} = shift_left %arg3, %arg3 : index
%126 = shift_left %idx, %idx : index
// CHECK: %{{[0-9]+}} = shift_left %cst_5, %cst_5 : vector<42xi32>
%127 = shift_left %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = shift_left %cst_4, %cst_4 : tensor<42xi32>
%128 = shift_left %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = shift_right_signed %arg2, %arg2 : i32
%129 = "std.shift_right_signed"(%i, %i) : (i32, i32) -> i32
// CHECK:%{{[0-9]+}} = shift_right_signed %[[I2]], %[[I2]] : i32
%130 = shift_right_signed %i2, %i2 : i32
// CHECK: %{{[0-9]+}} = shift_right_signed %arg3, %arg3 : index
%131 = shift_right_signed %idx, %idx : index
// CHECK: %{{[0-9]+}} = shift_right_signed %cst_5, %cst_5 : vector<42xi32>
%132 = shift_right_signed %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = shift_right_signed %cst_4, %cst_4 : tensor<42xi32>
%133 = shift_right_signed %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = shift_right_unsigned %arg2, %arg2 : i32
%134 = "std.shift_right_unsigned"(%i, %i) : (i32, i32) -> i32
// CHECK:%{{[0-9]+}} = shift_right_unsigned %[[I2]], %[[I2]] : i32
%135 = shift_right_unsigned %i2, %i2 : i32
// CHECK: %{{[0-9]+}} = shift_right_unsigned %arg3, %arg3 : index
%136 = shift_right_unsigned %idx, %idx : index
// CHECK: %{{[0-9]+}} = shift_right_unsigned %cst_5, %cst_5 : vector<42xi32>
%137 = shift_right_unsigned %vci32, %vci32 : vector<42 x i32>
// CHECK: %{{[0-9]+}} = shift_right_unsigned %cst_4, %cst_4 : tensor<42xi32>
%138 = shift_right_unsigned %tci32, %tci32 : tensor<42 x i32>
// CHECK: %{{[0-9]+}} = sqrt %arg1 : f32
%139 = "std.sqrt"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = sqrt %arg1 : f32
%140 = sqrt %f : f32
// CHECK: %{{[0-9]+}} = sqrt %cst_8 : vector<4xf32>
%141 = sqrt %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = sqrt %arg0 : tensor<4x4x?xf32>
%142 = sqrt %t : tensor<4x4x?xf32>
// CHECK: = fpext {{.*}} : vector<4xf32> to vector<4xf64>
%143 = fpext %vcf32 : vector<4xf32> to vector<4xf64>
// CHECK: = fptrunc {{.*}} : vector<4xf32> to vector<4xf16>
%144 = fptrunc %vcf32 : vector<4xf32> to vector<4xf16>
// CHECK: %{{[0-9]+}} = rsqrt %arg1 : f32
%145 = rsqrt %f : f32
// CHECK: %{{[0-9]+}} = sin %arg1 : f32
%146 = "std.sin"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = sin %arg1 : f32
%147 = sin %f : f32
// CHECK: %{{[0-9]+}} = sin %cst_8 : vector<4xf32>
%148 = sin %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = sin %arg0 : tensor<4x4x?xf32>
%149 = sin %t : tensor<4x4x?xf32>
// CHECK: = fptosi {{.*}} : f32 to i32
%159 = fptosi %f : f32 to i32
// CHECK: = fptosi {{.*}} : f32 to i64
%160 = fptosi %f : f32 to i64
// CHECK: = fptosi {{.*}} : f16 to i32
%161 = fptosi %half : f16 to i32
// CHECK: = fptosi {{.*}} : f16 to i64
%162 = fptosi %half : f16 to i64
// CHECK: floorf %arg1 : f32
%163 = "std.floorf"(%f) : (f32) -> f32
// CHECK: %{{[0-9]+}} = floorf %arg1 : f32
%164 = floorf %f : f32
// CHECK: %{{[0-9]+}} = floorf %cst_8 : vector<4xf32>
%165 = floorf %vcf32 : vector<4xf32>
// CHECK: %{{[0-9]+}} = floorf %arg0 : tensor<4x4x?xf32>
%166 = floorf %t : tensor<4x4x?xf32>
return
}
// CHECK-LABEL: func @affine_apply() {
func @affine_apply() {
%i = "std.constant"() {value = 0: index} : () -> index
%j = "std.constant"() {value = 1: index} : () -> index
// CHECK: affine.apply #map0(%c0)
%a = "affine.apply" (%i) { map = affine_map<(d0) -> (d0 + 1)> } :
(index) -> (index)
// CHECK: affine.apply #map1()[%c0]
%b = affine.apply affine_map<()[x] -> (x+1)>()[%i]
return
}
// CHECK-LABEL: func @load_store_prefetch
func @load_store_prefetch(memref<4x4xi32>, index) {
^bb0(%0: memref<4x4xi32>, %1: index):
// CHECK: %0 = load %arg0[%arg1, %arg1] : memref<4x4xi32>
%2 = "std.load"(%0, %1, %1) : (memref<4x4xi32>, index, index)->i32
// CHECK: %{{.*}} = load %arg0[%arg1, %arg1] : memref<4x4xi32>
%3 = load %0[%1, %1] : memref<4x4xi32>
// CHECK: prefetch %arg0[%arg1, %arg1], write, locality<1>, data : memref<4x4xi32>
prefetch %0[%1, %1], write, locality<1>, data : memref<4x4xi32>
// CHECK: prefetch %arg0[%arg1, %arg1], read, locality<3>, instr : memref<4x4xi32>
prefetch %0[%1, %1], read, locality<3>, instr : memref<4x4xi32>
return
}
// Test with zero-dimensional operands using no index in load/store.
// CHECK-LABEL: func @zero_dim_no_idx
func @zero_dim_no_idx(%arg0 : memref<i32>, %arg1 : memref<i32>, %arg2 : memref<i32>) {
%0 = std.load %arg0[] : memref<i32>
std.store %0, %arg1[] : memref<i32>
return
// CHECK: %0 = load %{{.*}}[] : memref<i32>
// CHECK: store %{{.*}}, %{{.*}}[] : memref<i32>
}
// CHECK-LABEL: func @return_op(%arg0: i32) -> i32 {
func @return_op(%a : i32) -> i32 {
// CHECK: return %arg0 : i32
"std.return" (%a) : (i32)->()
}
// CHECK-LABEL: func @calls(%arg0: i32) {
func @calls(%arg0: i32) {
// CHECK: %0 = call @return_op(%arg0) : (i32) -> i32
%x = call @return_op(%arg0) : (i32) -> i32
// CHECK: %1 = call @return_op(%0) : (i32) -> i32
%y = call @return_op(%x) : (i32) -> i32
// CHECK: %2 = call @return_op(%0) : (i32) -> i32
%z = "std.call"(%x) {callee = @return_op} : (i32) -> i32
// CHECK: %f = constant @affine_apply : () -> ()
%f = constant @affine_apply : () -> ()
// CHECK: call_indirect %f() : () -> ()
call_indirect %f() : () -> ()
// CHECK: %f_0 = constant @return_op : (i32) -> i32
%f_0 = constant @return_op : (i32) -> i32
// CHECK: %3 = call_indirect %f_0(%arg0) : (i32) -> i32
%2 = call_indirect %f_0(%arg0) : (i32) -> i32
// CHECK: %4 = call_indirect %f_0(%arg0) : (i32) -> i32
%3 = "std.call_indirect"(%f_0, %arg0) : ((i32) -> i32, i32) -> i32
return
}
// CHECK-LABEL: func @extract_element(%arg0: tensor<*xi32>, %arg1: tensor<4x4xf32>) -> i32 {
func @extract_element(%arg0: tensor<*xi32>, %arg1 : tensor<4x4xf32>) -> i32 {
%c0 = "std.constant"() {value = 0: index} : () -> index
// CHECK: %0 = extract_element %arg0[%c0, %c0, %c0, %c0] : tensor<*xi32>
%0 = extract_element %arg0[%c0, %c0, %c0, %c0] : tensor<*xi32>
// CHECK: %1 = extract_element %arg1[%c0, %c0] : tensor<4x4xf32>
%1 = extract_element %arg1[%c0, %c0] : tensor<4x4xf32>
return %0 : i32
}
// CHECK-LABEL: func @tensor_from_elements() {
func @tensor_from_elements() {
%c0 = "std.constant"() {value = 0: index} : () -> index
// CHECK: %0 = tensor_from_elements %c0 : tensor<1xindex>
%0 = tensor_from_elements %c0 : tensor<1xindex>
%c1 = "std.constant"() {value = 1: index} : () -> index
// CHECK: %1 = tensor_from_elements %c0, %c1 : tensor<2xindex>
%1 = tensor_from_elements %c0, %c1 : tensor<2xindex>
%c0_f32 = "std.constant"() {value = 0.0: f32} : () -> f32
// CHECK: [[C0_F32:%.*]] = constant
// CHECK: %2 = tensor_from_elements [[C0_F32]] : tensor<1xf32>
%2 = tensor_from_elements %c0_f32 : tensor<1xf32>
// CHECK: tensor_from_elements : tensor<0xindex>
%3 = tensor_from_elements : tensor<0xindex>
return
}
// CHECK-LABEL: func @tensor_cast(%arg0
func @tensor_cast(%arg0: tensor<*xf32>, %arg1 : tensor<4x4xf32>, %arg2: tensor<?x?xf32>) {
// CHECK: %0 = tensor_cast %arg0 : tensor<*xf32> to tensor<?x?xf32>
%0 = tensor_cast %arg0 : tensor<*xf32> to tensor<?x?xf32>
// CHECK: %1 = tensor_cast %arg1 : tensor<4x4xf32> to tensor<*xf32>
%1 = tensor_cast %arg1 : tensor<4x4xf32> to tensor<*xf32>
// CHECK: %2 = tensor_cast %arg2 : tensor<?x?xf32> to tensor<4x?xf32>
%2 = tensor_cast %arg2 : tensor<?x?xf32> to tensor<4x?xf32>
// CHECK: %3 = tensor_cast %2 : tensor<4x?xf32> to tensor<?x?xf32>
%3 = tensor_cast %2 : tensor<4x?xf32> to tensor<?x?xf32>
return
}
// CHECK-LABEL: func @memref_cast(%arg0
func @memref_cast(%arg0: memref<4xf32>, %arg1 : memref<?xf32>, %arg2 : memref<64x16x4xf32, offset: 0, strides: [64, 4, 1]>) {
// CHECK: %0 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
%0 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
// CHECK: %1 = memref_cast %arg1 : memref<?xf32> to memref<4xf32>
%1 = memref_cast %arg1 : memref<?xf32> to memref<4xf32>
// CHECK: {{%.*}} = memref_cast %arg2 : memref<64x16x4xf32, #[[$BASE_MAP0]]> to memref<64x16x4xf32, #[[$BASE_MAP3]]>
%2 = memref_cast %arg2 : memref<64x16x4xf32, offset: 0, strides: [64, 4, 1]> to memref<64x16x4xf32, offset: ?, strides: [?, ?, ?]>
// CHECK: {{%.*}} = memref_cast {{%.*}} : memref<64x16x4xf32, #[[$BASE_MAP3]]> to memref<64x16x4xf32, #[[$BASE_MAP0]]>
%3 = memref_cast %2 : memref<64x16x4xf32, offset: ?, strides: [?, ?, ?]> to memref<64x16x4xf32, offset: 0, strides: [64, 4, 1]>
// CHECK: memref_cast %{{.*}} : memref<4xf32> to memref<*xf32>
%4 = memref_cast %1 : memref<4xf32> to memref<*xf32>
// CHECK: memref_cast %{{.*}} : memref<*xf32> to memref<4xf32>
%5 = memref_cast %4 : memref<*xf32> to memref<4xf32>
return
}
// Check that unranked memrefs with non-default memory space roundtrip
// properly.
// CHECK-LABEL: @unranked_memref_roundtrip(memref<*xf32, 4>)
func @unranked_memref_roundtrip(memref<*xf32, 4>)
// CHECK-LABEL: func @memref_view(%arg0
func @memref_view(%arg0 : index, %arg1 : index, %arg2 : index) {
%0 = alloc() : memref<2048xi8>
// Test two dynamic sizes and dynamic offset.
// CHECK: %{{.*}} = std.view %0[%arg2][%arg0, %arg1] : memref<2048xi8> to memref<?x?xf32>
%1 = view %0[%arg2][%arg0, %arg1] : memref<2048xi8> to memref<?x?xf32>
// Test one dynamic size and dynamic offset.
// CHECK: %{{.*}} = std.view %0[%arg2][%arg1] : memref<2048xi8> to memref<4x?xf32>
%3 = view %0[%arg2][%arg1] : memref<2048xi8> to memref<4x?xf32>
// Test static sizes and static offset.
// CHECK: %{{.*}} = std.view %0[{{.*}}][] : memref<2048xi8> to memref<64x4xf32>
%c0 = constant 0: index
%5 = view %0[%c0][] : memref<2048xi8> to memref<64x4xf32>
return
}
// CHECK-LABEL: func @memref_subview(%arg0
func @memref_subview(%arg0 : index, %arg1 : index, %arg2 : index) {
%c0 = constant 0 : index
%c1 = constant 1 : index
%0 = alloc() : memref<8x16x4xf32, affine_map<(d0, d1, d2) -> (d0 * 64 + d1 * 4 + d2)>>
// CHECK: subview %0[%c0, %c0, %c0] [%arg0, %arg1, %arg2] [%c1, %c1, %c1] :
// CHECK-SAME: memref<8x16x4xf32, #[[$BASE_MAP0]]>
// CHECK-SAME: to memref<?x?x?xf32, #[[$BASE_MAP3]]>
%1 = subview %0[%c0, %c0, %c0][%arg0, %arg1, %arg2][%c1, %c1, %c1]
: memref<8x16x4xf32, offset:0, strides: [64, 4, 1]> to
memref<?x?x?xf32, offset: ?, strides: [?, ?, ?]>
%2 = alloc()[%arg2] : memref<64xf32, affine_map<(d0)[s0] -> (d0 + s0)>>
// CHECK: subview %2[%c1] [%arg0] [%c1] :
// CHECK-SAME: memref<64xf32, #[[$BASE_MAP1]]>
// CHECK-SAME: to memref<?xf32, #[[$SUBVIEW_MAP1]]>
%3 = subview %2[%c1][%arg0][%c1]
: memref<64xf32, affine_map<(d0)[s0] -> (d0 + s0)>> to
memref<?xf32, affine_map<(d0)[s0, s1] -> (d0 * s1 + s0)>>
%4 = alloc() : memref<64x22xf32, affine_map<(d0, d1) -> (d0 * 22 + d1)>>
// CHECK: subview %4[%c0, %c1] [%arg0, %arg1] [%c1, %c0] :
// CHECK-SAME: memref<64x22xf32, #[[$BASE_MAP2]]>
// CHECK-SAME: to memref<?x?xf32, #[[$SUBVIEW_MAP2]]>
%5 = subview %4[%c0, %c1][%arg0, %arg1][%c1, %c0]
: memref<64x22xf32, offset:0, strides: [22, 1]> to
memref<?x?xf32, offset:?, strides: [?, ?]>
// CHECK: subview %0[0, 2, 0] [4, 4, 4] [1, 1, 1] :
// CHECK-SAME: memref<8x16x4xf32, #[[$BASE_MAP0]]>
// CHECK-SAME: to memref<4x4x4xf32, #[[$SUBVIEW_MAP3]]>
%6 = subview %0[0, 2, 0][4, 4, 4][1, 1, 1]
: memref<8x16x4xf32, offset:0, strides: [64, 4, 1]> to
memref<4x4x4xf32, offset:8, strides: [64, 4, 1]>
%7 = alloc(%arg1, %arg2) : memref<?x?xf32>
// CHECK: subview {{%.*}}[0, 0] [4, 4] [1, 1] :
// CHECK-SAME: memref<?x?xf32>
// CHECK-SAME: to memref<4x4xf32, #[[$SUBVIEW_MAP4]]>
%8 = subview %7[0, 0][4, 4][1, 1]
: memref<?x?xf32> to memref<4x4xf32, offset: ?, strides:[?, 1]>
%9 = alloc() : memref<16x4xf32>
// CHECK: subview {{%.*}}[{{%.*}}, {{%.*}}] [4, 4] [{{%.*}}, {{%.*}}] :
// CHECK-SAME: memref<16x4xf32>
// CHECK-SAME: to memref<4x4xf32, #[[$SUBVIEW_MAP2]]
%10 = subview %9[%arg1, %arg1][4, 4][%arg2, %arg2]
: memref<16x4xf32> to memref<4x4xf32, offset: ?, strides:[?, ?]>
// CHECK: subview {{%.*}}[{{%.*}}, {{%.*}}] [4, 4] [2, 2] :
// CHECK-SAME: memref<16x4xf32>
// CHECK-SAME: to memref<4x4xf32, #[[$SUBVIEW_MAP5]]
%11 = subview %9[%arg1, %arg2][4, 4][2, 2]
: memref<16x4xf32> to memref<4x4xf32, offset: ?, strides:[8, 2]>
return
}
// CHECK-LABEL: func @test_dimop
// CHECK-SAME: %[[ARG:.*]]: tensor<4x4x?xf32>
func @test_dimop(%arg0: tensor<4x4x?xf32>) {
// CHECK: %[[C2:.*]] = constant 2 : index
// CHECK: %{{.*}} = dim %[[ARG]], %[[C2]] : tensor<4x4x?xf32>
%c2 = constant 2 : index
%0 = dim %arg0, %c2 : tensor<4x4x?xf32>
// use dim as an index to ensure type correctness
%1 = affine.apply affine_map<(d0) -> (d0)>(%0)
return
}
// CHECK-LABEL: func @test_splat_op
// CHECK-SAME: [[S:%arg[0-9]+]]: f32
func @test_splat_op(%s : f32) {
%v = splat %s : vector<8xf32>
// CHECK: splat [[S]] : vector<8xf32>
%t = splat %s : tensor<8xf32>
// CHECK: splat [[S]] : tensor<8xf32>
%u = "std.splat"(%s) : (f32) -> vector<4xf32>
// CHECK: splat [[S]] : vector<4xf32>
return
}
// CHECK-LABEL: func @tensor_load_store
func @tensor_load_store(%0 : memref<4x4xi32>) {
// CHECK: %[[TENSOR:.*]] = tensor_load %[[MEMREF:.*]] : memref<4x4xi32>
%1 = tensor_load %0 : memref<4x4xi32>
// CHECK: tensor_store %[[TENSOR]], %[[MEMREF]] : memref<4x4xi32>
tensor_store %1, %0 : memref<4x4xi32>
return
}
// CHECK-LABEL: func @unranked_tensor_load_store
func @unranked_tensor_load_store(%0 : memref<*xi32>) {
// CHECK: %[[TENSOR:.*]] = tensor_load %[[MEMREF:.*]] : memref<*xi32>
%1 = tensor_load %0 : memref<*xi32>
// CHECK: tensor_store %[[TENSOR]], %[[MEMREF]] : memref<*xi32>
tensor_store %1, %0 : memref<*xi32>
return
}
// CHECK-LABEL: func @atomic_rmw
// CHECK-SAME: ([[BUF:%.*]]: memref<10xf32>, [[VAL:%.*]]: f32, [[I:%.*]]: index)
func @atomic_rmw(%I: memref<10xf32>, %val: f32, %i : index) {
%x = atomic_rmw "addf" %val, %I[%i] : (f32, memref<10xf32>) -> f32
// CHECK: atomic_rmw "addf" [[VAL]], [[BUF]]{{\[}}[[I]]]
return
}
// CHECK-LABEL: func @generic_atomic_rmw
// CHECK-SAME: ([[BUF:%.*]]: memref<1x2xf32>, [[I:%.*]]: index, [[J:%.*]]: index)
func @generic_atomic_rmw(%I: memref<1x2xf32>, %i : index, %j : index) {
%x = generic_atomic_rmw %I[%i, %j] : memref<1x2xf32> {
// CHECK-NEXT: generic_atomic_rmw [[BUF]]{{\[}}[[I]], [[J]]] : memref
^bb0(%old_value : f32):
%c1 = constant 1.0 : f32
%out = addf %c1, %old_value : f32
atomic_yield %out : f32
// CHECK: index_attr = 8 : index
} { index_attr = 8 : index }
return
}
// CHECK-LABEL: func @assume_alignment
// CHECK-SAME: %[[MEMREF:.*]]: memref<4x4xf16>
func @assume_alignment(%0: memref<4x4xf16>) {
// CHECK: assume_alignment %[[MEMREF]], 16 : memref<4x4xf16>
assume_alignment %0, 16 : memref<4x4xf16>
return
}
| {
"language": "Assembly"
} |
/****************************************************************************/
/* */
/* */
/* These files contain the attributes and methods needed to manage a */
/* ring buffer. It turns out that we do this so much, that it may be a */
/* good idea to just make a library that does this. */
/* */
/* BY: Ken Wada */
/* Aurium Technologies Inc. */
/* 15-July-2013 */
/* */
/****************************************************************************/
/****************************************************************************/
/* THE COMPANY: Aurium Technologies Inc. */
/* */
/* THIS FIRMWARE IS FREE TO USE AND TO MODIFY. IT IS PRESENTED HERE FOR */
/* DEMONSTRATION PURPOSES AS AN EXAMPLE ON HOW TO CODE FOR ANY DEEPLY */
/* EMBEDDED SYSTEM. */
/* */
/* AS A RESULT, THE COMPANY SHALL NOT BE HELD LIABLE FOR ANY DIRECT, */
/* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING */
/* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY USERS OF */
/* THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR */
/* PRODUCTS. */
/****************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RINGBUFFER_H
#define __RINGBUFFER_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "config.h"
#define RINGBUFFER_SIZE 128
typedef struct RingBuffer
{
uint8_t head;
uint8_t tail;
uint8_t count;
uint8_t buf[RINGBUFFER_SIZE];
} RingBuffer;
void RingBuffer_init(RingBuffer *_this);
uint8_t RingBuffer_empty(RingBuffer *_this);
uint8_t RingBuffer_full(RingBuffer *_this);
uint8_t RingBuffer_pop(RingBuffer *_this);
void RingBuffer_push(RingBuffer *_this, uint8_t value);
void RingBuffer_flush(RingBuffer *_this, uint8_t clearBuffer);
bool RingBuffer_erase(RingBuffer *_this, uint8_t range);
uint8_t RingBuffer_get(RingBuffer *_this, uint8_t index);
#ifdef __cplusplus
}
#endif
#endif /* __UTILITIES_H */ | {
"language": "Assembly"
} |
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build arm64
// +build !gccgo
#include "textflag.h"
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
B syscall·Syscall6(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
; RUN: opt < %s -licm -S | FileCheck %s
; Promote value if at least one use is safe
define i32 @f2(i32* %p, i8* %q) {
entry:
br label %loop.head
loop.head: ; preds = %cond.true, %entry
store i32 20, i32* %p
%tmp3.i = icmp eq i8* null, %q ; <i1> [#uses=1]
br i1 %tmp3.i, label %exit, label %cond.true
cond.true: ; preds = %loop.head
store i32 40, i32* %p
br label %loop.head
; CHECK: exit:
; CHECK: store i32 20, i32* %p
exit: ; preds = %loop.head
ret i32 0
}
| {
"language": "Assembly"
} |
//============
// N64 Header
//============
// PI_BSB_DOM1
db $80 // Initial PI_BSB_DOM1_LAT_REG Value
db $37 // Initial PI_BSB_DOM1_PGS_REG Value
db $12 // Initial PI_BSB_DOM1_PWD_REG Value
db $40 // Initial PI_BSB_DOM1_PGS_REG Value
// CLOCK RATE
dw $000F // Initial Clock Rate
// VECTOR
dw Start // Boot Address Offset
dw $1444 // Release Offset
// COMPLEMENT CHECK & CHECKSUM
db "CRC1" // CRC1: COMPLEMENT CHECK
db "CRC2" // CRC2: CHECKSUM
dd 0 // UNUSED
// PROGRAM TITLE (27 Byte ASCII String, Use Spaces For Unused Bytes)
db "RSP TEST CP2 VRCP VRSQ "
// "123456789012345678901234567"
// DEVELOPER ID CODE
db $00 // "N" = Nintendo
// CARTRIDGE ID CODE
db $00
db 0 // UNUSED
// COUNTRY CODE
db $00 // "D" = Germany, "E" = USA, "J" = Japan, "P" = Europe, "U" = Australia
db 0 // UNUSED | {
"language": "Assembly"
} |
// RUN: llvm-mc -triple i686-apple-darwin10 %s | FileCheck %s
.data
// CHECK: a:
a:
.long 0
// CHECK: b:
"b":
.long 0
// CHECK: a$b:
"a$b":
.long 0
.text
foo:
// CHECK: addl $24, a$b(%eax)
addl $24, "a$b"(%eax)
// CHECK: addl $24, a$b+10(%eax)
addl $24, ("a$b" + 10)(%eax)
// CHECK: b$c = 10
"b$c" = 10
// CHECK: addl $10, %eax
addl $"b$c", %eax
// CHECK: "a 0" = 11
.set "a 0", 11
// CHECK: .long 11
.long "a 0"
// XXCHCK: .section "a 1,a 2"
//.section "a 1", "a 2"
// CHECK: .globl "a 3"
.globl "a 3"
// CHECK: .desc "a 5",1
.desc "a 5", 1
// CHECK: .comm "a 6",1
.comm "a 6", 1
// CHECK: .lcomm "a 7",1
.lcomm "a 7", 1
// FIXME: We don't bother to support .lsym.
// CHECX: .lsym "a 8",1
// .lsym "a 8", 1
// CHECK: "a 9" = a-b
.set "a 9", a - b
// CHECK: .long "a 9"
.long "a 9"
| {
"language": "Assembly"
} |
; Processor-independent options for LynxOS.
; Copyright (C) 2005 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 2, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING. If not, write to the Free
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
; 02110-1301, USA.
mlegacy-threads
Target RejectNegative
Support legacy multi-threading
mshared
Target RejectNegative
Use shared libraries
mthreads
Target RejectNegative
Support multi-threading
| {
"language": "Assembly"
} |
rv64ui-v-srai: file format elf64-littleriscv
Disassembly of section .text.init:
0000000080000000 <_start>:
80000000: 00c0006f j 8000000c <handle_reset>
0000000080000004 <nmi_vector>:
80000004: 2600206f j 80002264 <wtf>
0000000080000008 <trap_vector>:
80000008: 25c0206f j 80002264 <wtf>
000000008000000c <handle_reset>:
8000000c: 00000093 li ra,0
80000010: 00000113 li sp,0
80000014: 00000193 li gp,0
80000018: 00000213 li tp,0
8000001c: 00000293 li t0,0
80000020: 00000313 li t1,0
80000024: 00000393 li t2,0
80000028: 00000413 li s0,0
8000002c: 00000493 li s1,0
80000030: 00000513 li a0,0
80000034: 00000593 li a1,0
80000038: 00000613 li a2,0
8000003c: 00000693 li a3,0
80000040: 00000713 li a4,0
80000044: 00000793 li a5,0
80000048: 00000813 li a6,0
8000004c: 00000893 li a7,0
80000050: 00000913 li s2,0
80000054: 00000993 li s3,0
80000058: 00000a13 li s4,0
8000005c: 00000a93 li s5,0
80000060: 00000b13 li s6,0
80000064: 00000b93 li s7,0
80000068: 00000c13 li s8,0
8000006c: 00000c93 li s9,0
80000070: 00000d13 li s10,0
80000074: 00000d93 li s11,0
80000078: 00000e13 li t3,0
8000007c: 00000e93 li t4,0
80000080: 00000f13 li t5,0
80000084: 00000f93 li t6,0
80000088: 00000297 auipc t0,0x0
8000008c: f8028293 addi t0,t0,-128 # 80000008 <trap_vector>
80000090: 30529073 csrw mtvec,t0
80000094: 00008117 auipc sp,0x8
80000098: 63c10113 addi sp,sp,1596 # 800086d0 <_end+0xee0>
8000009c: f14022f3 csrr t0,mhartid
800000a0: 00c29293 slli t0,t0,0xc
800000a4: 00510133 add sp,sp,t0
800000a8: 34011073 csrw mscratch,sp
800000ac: 231020ef jal ra,80002adc <extra_boot>
800000b0: 00003517 auipc a0,0x3
800000b4: a3050513 addi a0,a0,-1488 # 80002ae0 <userstart>
800000b8: 7f80206f j 800028b0 <vm_boot>
00000000800000bc <pop_tf>:
800000bc: 10853283 ld t0,264(a0)
800000c0: 14129073 csrw sepc,t0
800000c4: 00853083 ld ra,8(a0)
800000c8: 01053103 ld sp,16(a0)
800000cc: 01853183 ld gp,24(a0)
800000d0: 02053203 ld tp,32(a0)
800000d4: 02853283 ld t0,40(a0)
800000d8: 03053303 ld t1,48(a0)
800000dc: 03853383 ld t2,56(a0)
800000e0: 04053403 ld s0,64(a0)
800000e4: 04853483 ld s1,72(a0)
800000e8: 05853583 ld a1,88(a0)
800000ec: 06053603 ld a2,96(a0)
800000f0: 06853683 ld a3,104(a0)
800000f4: 07053703 ld a4,112(a0)
800000f8: 07853783 ld a5,120(a0)
800000fc: 08053803 ld a6,128(a0)
80000100: 08853883 ld a7,136(a0)
80000104: 09053903 ld s2,144(a0)
80000108: 09853983 ld s3,152(a0)
8000010c: 0a053a03 ld s4,160(a0)
80000110: 0a853a83 ld s5,168(a0)
80000114: 0b053b03 ld s6,176(a0)
80000118: 0b853b83 ld s7,184(a0)
8000011c: 0c053c03 ld s8,192(a0)
80000120: 0c853c83 ld s9,200(a0)
80000124: 0d053d03 ld s10,208(a0)
80000128: 0d853d83 ld s11,216(a0)
8000012c: 0e053e03 ld t3,224(a0)
80000130: 0e853e83 ld t4,232(a0)
80000134: 0f053f03 ld t5,240(a0)
80000138: 0f853f83 ld t6,248(a0)
8000013c: 05053503 ld a0,80(a0)
80000140: 10200073 sret
0000000080000144 <trap_entry>:
80000144: 14011173 csrrw sp,sscratch,sp
80000148: 00113423 sd ra,8(sp)
8000014c: 00313c23 sd gp,24(sp)
80000150: 02413023 sd tp,32(sp)
80000154: 02513423 sd t0,40(sp)
80000158: 02613823 sd t1,48(sp)
8000015c: 02713c23 sd t2,56(sp)
80000160: 04813023 sd s0,64(sp)
80000164: 04913423 sd s1,72(sp)
80000168: 04a13823 sd a0,80(sp)
8000016c: 04b13c23 sd a1,88(sp)
80000170: 06c13023 sd a2,96(sp)
80000174: 06d13423 sd a3,104(sp)
80000178: 06e13823 sd a4,112(sp)
8000017c: 06f13c23 sd a5,120(sp)
80000180: 09013023 sd a6,128(sp)
80000184: 09113423 sd a7,136(sp)
80000188: 09213823 sd s2,144(sp)
8000018c: 09313c23 sd s3,152(sp)
80000190: 0b413023 sd s4,160(sp)
80000194: 0b513423 sd s5,168(sp)
80000198: 0b613823 sd s6,176(sp)
8000019c: 0b713c23 sd s7,184(sp)
800001a0: 0d813023 sd s8,192(sp)
800001a4: 0d913423 sd s9,200(sp)
800001a8: 0da13823 sd s10,208(sp)
800001ac: 0db13c23 sd s11,216(sp)
800001b0: 0fc13023 sd t3,224(sp)
800001b4: 0fd13423 sd t4,232(sp)
800001b8: 0fe13823 sd t5,240(sp)
800001bc: 0ff13c23 sd t6,248(sp)
800001c0: 140112f3 csrrw t0,sscratch,sp
800001c4: 00513823 sd t0,16(sp)
800001c8: 100022f3 csrr t0,sstatus
800001cc: 10513023 sd t0,256(sp)
800001d0: 141022f3 csrr t0,sepc
800001d4: 10513423 sd t0,264(sp)
800001d8: 143022f3 csrr t0,stval
800001dc: 10513823 sd t0,272(sp)
800001e0: 142022f3 csrr t0,scause
800001e4: 10513c23 sd t0,280(sp)
800001e8: 00010513 mv a0,sp
800001ec: 3a40206f j 80002590 <handle_trap>
Disassembly of section .text:
0000000080002000 <memcpy>:
80002000: 00c5e7b3 or a5,a1,a2
80002004: 00f567b3 or a5,a0,a5
80002008: 0077f793 andi a5,a5,7
8000200c: 00c506b3 add a3,a0,a2
80002010: 02078463 beqz a5,80002038 <memcpy+0x38>
80002014: 00c58633 add a2,a1,a2
80002018: 00050793 mv a5,a0
8000201c: 02d57e63 bgeu a0,a3,80002058 <memcpy+0x58>
80002020: 0005c703 lbu a4,0(a1)
80002024: 00158593 addi a1,a1,1
80002028: 00178793 addi a5,a5,1
8000202c: fee78fa3 sb a4,-1(a5)
80002030: fec598e3 bne a1,a2,80002020 <memcpy+0x20>
80002034: 00008067 ret
80002038: fed57ee3 bgeu a0,a3,80002034 <memcpy+0x34>
8000203c: 00050793 mv a5,a0
80002040: 0005b703 ld a4,0(a1)
80002044: 00878793 addi a5,a5,8
80002048: 00858593 addi a1,a1,8
8000204c: fee7bc23 sd a4,-8(a5)
80002050: fed7e8e3 bltu a5,a3,80002040 <memcpy+0x40>
80002054: 00008067 ret
80002058: 00008067 ret
000000008000205c <memset>:
8000205c: 00c567b3 or a5,a0,a2
80002060: 0077f793 andi a5,a5,7
80002064: 00c50633 add a2,a0,a2
80002068: 0ff5f593 andi a1,a1,255
8000206c: 00078e63 beqz a5,80002088 <memset+0x2c>
80002070: 00050793 mv a5,a0
80002074: 04c57263 bgeu a0,a2,800020b8 <memset+0x5c>
80002078: 00178793 addi a5,a5,1
8000207c: feb78fa3 sb a1,-1(a5)
80002080: fef61ce3 bne a2,a5,80002078 <memset+0x1c>
80002084: 00008067 ret
80002088: 00859793 slli a5,a1,0x8
8000208c: 00b7e5b3 or a1,a5,a1
80002090: 01059793 slli a5,a1,0x10
80002094: 00b7e7b3 or a5,a5,a1
80002098: 02079593 slli a1,a5,0x20
8000209c: 00f5e5b3 or a1,a1,a5
800020a0: fec572e3 bgeu a0,a2,80002084 <memset+0x28>
800020a4: 00050793 mv a5,a0
800020a8: 00878793 addi a5,a5,8
800020ac: feb7bc23 sd a1,-8(a5)
800020b0: fec7ece3 bltu a5,a2,800020a8 <memset+0x4c>
800020b4: 00008067 ret
800020b8: 00008067 ret
00000000800020bc <strlen>:
800020bc: 00054783 lbu a5,0(a0)
800020c0: 00078e63 beqz a5,800020dc <strlen+0x20>
800020c4: 00050793 mv a5,a0
800020c8: 0017c703 lbu a4,1(a5)
800020cc: 00178793 addi a5,a5,1
800020d0: fe071ce3 bnez a4,800020c8 <strlen+0xc>
800020d4: 40a78533 sub a0,a5,a0
800020d8: 00008067 ret
800020dc: 00000513 li a0,0
800020e0: 00008067 ret
00000000800020e4 <strcmp>:
800020e4: 00054783 lbu a5,0(a0)
800020e8: 00158593 addi a1,a1,1
800020ec: 00150513 addi a0,a0,1
800020f0: fff5c703 lbu a4,-1(a1)
800020f4: 00078a63 beqz a5,80002108 <strcmp+0x24>
800020f8: fee786e3 beq a5,a4,800020e4 <strcmp>
800020fc: 0007851b sext.w a0,a5
80002100: 40e5053b subw a0,a0,a4
80002104: 00008067 ret
80002108: 00000513 li a0,0
8000210c: ff5ff06f j 80002100 <strcmp+0x1c>
0000000080002110 <memcmp>:
80002110: 00b567b3 or a5,a0,a1
80002114: 0077f793 andi a5,a5,7
80002118: 02079e63 bnez a5,80002154 <memcmp+0x44>
8000211c: ff867813 andi a6,a2,-8
80002120: 01050833 add a6,a0,a6
80002124: 03057863 bgeu a0,a6,80002154 <memcmp+0x44>
80002128: 00050793 mv a5,a0
8000212c: 0100006f j 8000213c <memcmp+0x2c>
80002130: 00878793 addi a5,a5,8
80002134: 00858593 addi a1,a1,8
80002138: 0107f863 bgeu a5,a6,80002148 <memcmp+0x38>
8000213c: 0007b683 ld a3,0(a5)
80002140: 0005b703 ld a4,0(a1)
80002144: fee686e3 beq a3,a4,80002130 <memcmp+0x20>
80002148: 40a78533 sub a0,a5,a0
8000214c: 40a60633 sub a2,a2,a0
80002150: 00078513 mv a0,a5
80002154: 00c58633 add a2,a1,a2
80002158: 0140006f j 8000216c <memcmp+0x5c>
8000215c: 0005c703 lbu a4,0(a1)
80002160: fff54783 lbu a5,-1(a0)
80002164: 00158593 addi a1,a1,1
80002168: 00e79a63 bne a5,a4,8000217c <memcmp+0x6c>
8000216c: 00150513 addi a0,a0,1
80002170: fec596e3 bne a1,a2,8000215c <memcmp+0x4c>
80002174: 00000513 li a0,0
80002178: 00008067 ret
8000217c: 40e7853b subw a0,a5,a4
80002180: 00008067 ret
0000000080002184 <strcpy>:
80002184: 00050793 mv a5,a0
80002188: 0005c703 lbu a4,0(a1)
8000218c: 00178793 addi a5,a5,1
80002190: 00158593 addi a1,a1,1
80002194: fee78fa3 sb a4,-1(a5)
80002198: fe0718e3 bnez a4,80002188 <strcpy+0x4>
8000219c: 00008067 ret
00000000800021a0 <atol>:
800021a0: 00054703 lbu a4,0(a0)
800021a4: 02000693 li a3,32
800021a8: 00050793 mv a5,a0
800021ac: 00d71863 bne a4,a3,800021bc <atol+0x1c>
800021b0: 0017c703 lbu a4,1(a5)
800021b4: 00178793 addi a5,a5,1
800021b8: fed70ce3 beq a4,a3,800021b0 <atol+0x10>
800021bc: 02d00693 li a3,45
800021c0: 06d70063 beq a4,a3,80002220 <atol+0x80>
800021c4: 02b00693 li a3,43
800021c8: 04d70063 beq a4,a3,80002208 <atol+0x68>
800021cc: 0007c683 lbu a3,0(a5)
800021d0: 00000593 li a1,0
800021d4: 04068263 beqz a3,80002218 <atol+0x78>
800021d8: 00000513 li a0,0
800021dc: 00178793 addi a5,a5,1
800021e0: fd06861b addiw a2,a3,-48
800021e4: 00251713 slli a4,a0,0x2
800021e8: 0007c683 lbu a3,0(a5)
800021ec: 00a70533 add a0,a4,a0
800021f0: 00151513 slli a0,a0,0x1
800021f4: 00a60533 add a0,a2,a0
800021f8: fe0692e3 bnez a3,800021dc <atol+0x3c>
800021fc: 02058063 beqz a1,8000221c <atol+0x7c>
80002200: 40a00533 neg a0,a0
80002204: 00008067 ret
80002208: 0017c683 lbu a3,1(a5)
8000220c: 00000593 li a1,0
80002210: 00178793 addi a5,a5,1
80002214: fc0692e3 bnez a3,800021d8 <atol+0x38>
80002218: 00000513 li a0,0
8000221c: 00008067 ret
80002220: 0017c683 lbu a3,1(a5)
80002224: 00100593 li a1,1
80002228: 00178793 addi a5,a5,1
8000222c: fa0696e3 bnez a3,800021d8 <atol+0x38>
80002230: 00000513 li a0,0
80002234: fe9ff06f j 8000221c <atol+0x7c>
0000000080002238 <terminate>:
80002238: fffff797 auipc a5,0xfffff
8000223c: dc878793 addi a5,a5,-568 # 80001000 <tohost>
80002240: 0007b683 ld a3,0(a5)
80002244: 00050713 mv a4,a0
80002248: 00068a63 beqz a3,8000225c <terminate+0x24>
8000224c: fffff697 auipc a3,0xfffff
80002250: de06ba23 sd zero,-524(a3) # 80001040 <fromhost>
80002254: 0007b683 ld a3,0(a5)
80002258: fe069ae3 bnez a3,8000224c <terminate+0x14>
8000225c: 00e7b023 sd a4,0(a5)
80002260: 0000006f j 80002260 <terminate+0x28>
0000000080002264 <wtf>:
80002264: ff010113 addi sp,sp,-16
80002268: 34900513 li a0,841
8000226c: 00113423 sd ra,8(sp)
80002270: fc9ff0ef jal ra,80002238 <terminate>
0000000080002274 <printhex>:
80002274: fe010113 addi sp,sp,-32
80002278: 00810613 addi a2,sp,8
8000227c: 01710793 addi a5,sp,23
80002280: 00900813 li a6,9
80002284: 0080006f j 8000228c <printhex+0x18>
80002288: 00070793 mv a5,a4
8000228c: 00f57693 andi a3,a0,15
80002290: 00068713 mv a4,a3
80002294: 03000593 li a1,48
80002298: 00d87463 bgeu a6,a3,800022a0 <printhex+0x2c>
8000229c: 05700593 li a1,87
800022a0: 00b7073b addw a4,a4,a1
800022a4: 00e78023 sb a4,0(a5)
800022a8: 00455513 srli a0,a0,0x4
800022ac: fff78713 addi a4,a5,-1
800022b0: fcf61ce3 bne a2,a5,80002288 <printhex+0x14>
800022b4: 00814783 lbu a5,8(sp)
800022b8: 00010c23 sb zero,24(sp)
800022bc: 04078263 beqz a5,80002300 <printhex+0x8c>
800022c0: 10100513 li a0,257
800022c4: 00060693 mv a3,a2
800022c8: fffff717 auipc a4,0xfffff
800022cc: d3870713 addi a4,a4,-712 # 80001000 <tohost>
800022d0: 03051513 slli a0,a0,0x30
800022d4: 00073583 ld a1,0(a4)
800022d8: 00168693 addi a3,a3,1
800022dc: 00a7e633 or a2,a5,a0
800022e0: 00058a63 beqz a1,800022f4 <printhex+0x80>
800022e4: fffff797 auipc a5,0xfffff
800022e8: d407be23 sd zero,-676(a5) # 80001040 <fromhost>
800022ec: 00073783 ld a5,0(a4)
800022f0: fe079ae3 bnez a5,800022e4 <printhex+0x70>
800022f4: 0006c783 lbu a5,0(a3)
800022f8: 00c73023 sd a2,0(a4)
800022fc: fc079ce3 bnez a5,800022d4 <printhex+0x60>
80002300: 02010113 addi sp,sp,32
80002304: 00008067 ret
0000000080002308 <handle_fault>:
80002308: fffff6b7 lui a3,0xfffff
8000230c: 00d50733 add a4,a0,a3
80002310: 0003e7b7 lui a5,0x3e
80002314: 14f77063 bgeu a4,a5,80002454 <handle_fault+0x14c>
80002318: 00c55893 srli a7,a0,0xc
8000231c: 60088813 addi a6,a7,1536
80002320: 00001617 auipc a2,0x1
80002324: ce060613 addi a2,a2,-800 # 80003000 <begin_signature>
80002328: 00381793 slli a5,a6,0x3
8000232c: 00f607b3 add a5,a2,a5
80002330: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000>
80002334: 00d57533 and a0,a0,a3
80002338: 02070663 beqz a4,80002364 <handle_fault+0x5c>
8000233c: 04077693 andi a3,a4,64
80002340: 0e068c63 beqz a3,80002438 <handle_fault+0x130>
80002344: 08077693 andi a3,a4,128
80002348: 16069263 bnez a3,800024ac <handle_fault+0x1a4>
8000234c: 00f00693 li a3,15
80002350: 14d59e63 bne a1,a3,800024ac <handle_fault+0x1a4>
80002354: 08076713 ori a4,a4,128
80002358: 00e7b023 sd a4,0(a5)
8000235c: 12050073 sfence.vma a0
80002360: 00008067 ret
80002364: 00005697 auipc a3,0x5
80002368: 48468693 addi a3,a3,1156 # 800077e8 <freelist_head>
8000236c: 0006b703 ld a4,0(a3)
80002370: 18070463 beqz a4,800024f8 <handle_fault+0x1f0>
80002374: 00873783 ld a5,8(a4)
80002378: 00005597 auipc a1,0x5
8000237c: 4685b583 ld a1,1128(a1) # 800077e0 <freelist_tail>
80002380: 00f6b023 sd a5,0(a3)
80002384: 0cb78263 beq a5,a1,80002448 <handle_fault+0x140>
80002388: 00073783 ld a5,0(a4)
8000238c: 00381593 slli a1,a6,0x3
80002390: 00b605b3 add a1,a2,a1
80002394: 00c7d793 srli a5,a5,0xc
80002398: 00a79793 slli a5,a5,0xa
8000239c: 0df7e313 ori t1,a5,223
800023a0: 01f7e693 ori a3,a5,31
800023a4: 0065b023 sd t1,0(a1)
800023a8: 12050073 sfence.vma a0
800023ac: 00005797 auipc a5,0x5
800023b0: 04478793 addi a5,a5,68 # 800073f0 <user_mapping>
800023b4: 00489893 slli a7,a7,0x4
800023b8: 011788b3 add a7,a5,a7
800023bc: 0008b783 ld a5,0(a7)
800023c0: 18079263 bnez a5,80002544 <handle_fault+0x23c>
800023c4: 00073783 ld a5,0(a4)
800023c8: 00f8b023 sd a5,0(a7)
800023cc: 00873783 ld a5,8(a4)
800023d0: 00f8b423 sd a5,8(a7)
800023d4: 000408b7 lui a7,0x40
800023d8: 1008a8f3 csrrs a7,sstatus,a7
800023dc: ffe007b7 lui a5,0xffe00
800023e0: 00f507b3 add a5,a0,a5
800023e4: 000015b7 lui a1,0x1
800023e8: 00050713 mv a4,a0
800023ec: 00b785b3 add a1,a5,a1
800023f0: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810>
800023f4: 0087be83 ld t4,8(a5)
800023f8: 0107be03 ld t3,16(a5)
800023fc: 0187b303 ld t1,24(a5)
80002400: 01e73023 sd t5,0(a4)
80002404: 01d73423 sd t4,8(a4)
80002408: 01c73823 sd t3,16(a4)
8000240c: 00673c23 sd t1,24(a4)
80002410: 02078793 addi a5,a5,32
80002414: 02070713 addi a4,a4,32
80002418: fcb79ce3 bne a5,a1,800023f0 <handle_fault+0xe8>
8000241c: 10089073 csrw sstatus,a7
80002420: 00381813 slli a6,a6,0x3
80002424: 01060633 add a2,a2,a6
80002428: 00d63023 sd a3,0(a2)
8000242c: 12050073 sfence.vma a0
80002430: 0000100f fence.i
80002434: 00008067 ret
80002438: 04076713 ori a4,a4,64
8000243c: 00e7b023 sd a4,0(a5)
80002440: 12050073 sfence.vma a0
80002444: 00008067 ret
80002448: 00005797 auipc a5,0x5
8000244c: 3807bc23 sd zero,920(a5) # 800077e0 <freelist_tail>
80002450: f39ff06f j 80002388 <handle_fault+0x80>
80002454: 10100613 li a2,257
80002458: 04100713 li a4,65
8000245c: 00001697 auipc a3,0x1
80002460: 96468693 addi a3,a3,-1692 # 80002dc0 <pass+0x10>
80002464: fffff797 auipc a5,0xfffff
80002468: b9c78793 addi a5,a5,-1124 # 80001000 <tohost>
8000246c: 03061613 slli a2,a2,0x30
80002470: 0007b503 ld a0,0(a5)
80002474: 00168693 addi a3,a3,1
80002478: 00c765b3 or a1,a4,a2
8000247c: 00050a63 beqz a0,80002490 <handle_fault+0x188>
80002480: fffff717 auipc a4,0xfffff
80002484: bc073023 sd zero,-1088(a4) # 80001040 <fromhost>
80002488: 0007b703 ld a4,0(a5)
8000248c: fe071ae3 bnez a4,80002480 <handle_fault+0x178>
80002490: 0006c703 lbu a4,0(a3)
80002494: 00b7b023 sd a1,0(a5)
80002498: fc071ce3 bnez a4,80002470 <handle_fault+0x168>
8000249c: ff010113 addi sp,sp,-16
800024a0: 00300513 li a0,3
800024a4: 00113423 sd ra,8(sp)
800024a8: d91ff0ef jal ra,80002238 <terminate>
800024ac: 10100613 li a2,257
800024b0: 04100713 li a4,65
800024b4: 00001697 auipc a3,0x1
800024b8: 95468693 addi a3,a3,-1708 # 80002e08 <pass+0x58>
800024bc: fffff797 auipc a5,0xfffff
800024c0: b4478793 addi a5,a5,-1212 # 80001000 <tohost>
800024c4: 03061613 slli a2,a2,0x30
800024c8: 0007b503 ld a0,0(a5)
800024cc: 00168693 addi a3,a3,1
800024d0: 00c765b3 or a1,a4,a2
800024d4: 00050a63 beqz a0,800024e8 <handle_fault+0x1e0>
800024d8: fffff717 auipc a4,0xfffff
800024dc: b6073423 sd zero,-1176(a4) # 80001040 <fromhost>
800024e0: 0007b703 ld a4,0(a5)
800024e4: fe071ae3 bnez a4,800024d8 <handle_fault+0x1d0>
800024e8: 0006c703 lbu a4,0(a3)
800024ec: 00b7b023 sd a1,0(a5)
800024f0: fc071ce3 bnez a4,800024c8 <handle_fault+0x1c0>
800024f4: fa9ff06f j 8000249c <handle_fault+0x194>
800024f8: 10100693 li a3,257
800024fc: 04100713 li a4,65
80002500: 00001617 auipc a2,0x1
80002504: 95060613 addi a2,a2,-1712 # 80002e50 <pass+0xa0>
80002508: fffff797 auipc a5,0xfffff
8000250c: af878793 addi a5,a5,-1288 # 80001000 <tohost>
80002510: 03069693 slli a3,a3,0x30
80002514: 0007b503 ld a0,0(a5)
80002518: 00160613 addi a2,a2,1
8000251c: 00d765b3 or a1,a4,a3
80002520: 00050a63 beqz a0,80002534 <handle_fault+0x22c>
80002524: fffff717 auipc a4,0xfffff
80002528: b0073e23 sd zero,-1252(a4) # 80001040 <fromhost>
8000252c: 0007b703 ld a4,0(a5)
80002530: fe071ae3 bnez a4,80002524 <handle_fault+0x21c>
80002534: 00064703 lbu a4,0(a2)
80002538: 00b7b023 sd a1,0(a5)
8000253c: fc071ce3 bnez a4,80002514 <handle_fault+0x20c>
80002540: f5dff06f j 8000249c <handle_fault+0x194>
80002544: 10100693 li a3,257
80002548: 04100713 li a4,65
8000254c: 00001617 auipc a2,0x1
80002550: 91c60613 addi a2,a2,-1764 # 80002e68 <pass+0xb8>
80002554: fffff797 auipc a5,0xfffff
80002558: aac78793 addi a5,a5,-1364 # 80001000 <tohost>
8000255c: 03069693 slli a3,a3,0x30
80002560: 0007b503 ld a0,0(a5)
80002564: 00160613 addi a2,a2,1
80002568: 00d765b3 or a1,a4,a3
8000256c: 00050a63 beqz a0,80002580 <handle_fault+0x278>
80002570: fffff717 auipc a4,0xfffff
80002574: ac073823 sd zero,-1328(a4) # 80001040 <fromhost>
80002578: 0007b703 ld a4,0(a5)
8000257c: fe071ae3 bnez a4,80002570 <handle_fault+0x268>
80002580: 00064703 lbu a4,0(a2)
80002584: 00b7b023 sd a1,0(a5)
80002588: fc071ce3 bnez a4,80002560 <handle_fault+0x258>
8000258c: f11ff06f j 8000249c <handle_fault+0x194>
0000000080002590 <handle_trap>:
80002590: 11853583 ld a1,280(a0)
80002594: f8010113 addi sp,sp,-128
80002598: 06813823 sd s0,112(sp)
8000259c: 06113c23 sd ra,120(sp)
800025a0: 06913423 sd s1,104(sp)
800025a4: 07213023 sd s2,96(sp)
800025a8: 05313c23 sd s3,88(sp)
800025ac: 05413823 sd s4,80(sp)
800025b0: 05513423 sd s5,72(sp)
800025b4: 05613023 sd s6,64(sp)
800025b8: 03713c23 sd s7,56(sp)
800025bc: 03813823 sd s8,48(sp)
800025c0: 03913423 sd s9,40(sp)
800025c4: 03a13023 sd s10,32(sp)
800025c8: 01b13c23 sd s11,24(sp)
800025cc: 00800793 li a5,8
800025d0: 00050413 mv s0,a0
800025d4: 12f58663 beq a1,a5,80002700 <handle_trap+0x170>
800025d8: 00200793 li a5,2
800025dc: 06f58063 beq a1,a5,8000263c <handle_trap+0xac>
800025e0: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c>
800025e4: 00100713 li a4,1
800025e8: 00f77663 bgeu a4,a5,800025f4 <handle_trap+0x64>
800025ec: 00f00793 li a5,15
800025f0: 1cf59e63 bne a1,a5,800027cc <handle_trap+0x23c>
800025f4: 11043503 ld a0,272(s0)
800025f8: d11ff0ef jal ra,80002308 <handle_fault>
800025fc: 00040513 mv a0,s0
80002600: 07013403 ld s0,112(sp)
80002604: 07813083 ld ra,120(sp)
80002608: 06813483 ld s1,104(sp)
8000260c: 06013903 ld s2,96(sp)
80002610: 05813983 ld s3,88(sp)
80002614: 05013a03 ld s4,80(sp)
80002618: 04813a83 ld s5,72(sp)
8000261c: 04013b03 ld s6,64(sp)
80002620: 03813b83 ld s7,56(sp)
80002624: 03013c03 ld s8,48(sp)
80002628: 02813c83 ld s9,40(sp)
8000262c: 02013d03 ld s10,32(sp)
80002630: 01813d83 ld s11,24(sp)
80002634: 08010113 addi sp,sp,128
80002638: a85fd06f j 800000bc <pop_tf>
8000263c: 10853703 ld a4,264(a0)
80002640: 00377793 andi a5,a4,3
80002644: 06079863 bnez a5,800026b4 <handle_trap+0x124>
80002648: 008007ef jal a5,80002650 <handle_trap+0xc0>
8000264c: 00301073 fscsr zero
80002650: 00072703 lw a4,0(a4)
80002654: 0007a783 lw a5,0(a5)
80002658: 04f70a63 beq a4,a5,800026ac <handle_trap+0x11c>
8000265c: 10100513 li a0,257
80002660: 04100793 li a5,65
80002664: 00001697 auipc a3,0x1
80002668: 8dc68693 addi a3,a3,-1828 # 80002f40 <pass+0x190>
8000266c: fffff717 auipc a4,0xfffff
80002670: 99470713 addi a4,a4,-1644 # 80001000 <tohost>
80002674: 03051513 slli a0,a0,0x30
80002678: 00073583 ld a1,0(a4)
8000267c: 00168693 addi a3,a3,1
80002680: 00a7e633 or a2,a5,a0
80002684: 00058a63 beqz a1,80002698 <handle_trap+0x108>
80002688: fffff797 auipc a5,0xfffff
8000268c: 9a07bc23 sd zero,-1608(a5) # 80001040 <fromhost>
80002690: 00073783 ld a5,0(a4)
80002694: fe079ae3 bnez a5,80002688 <handle_trap+0xf8>
80002698: 0006c783 lbu a5,0(a3)
8000269c: 00c73023 sd a2,0(a4)
800026a0: fc079ce3 bnez a5,80002678 <handle_trap+0xe8>
800026a4: 00300513 li a0,3
800026a8: b91ff0ef jal ra,80002238 <terminate>
800026ac: 00100513 li a0,1
800026b0: b89ff0ef jal ra,80002238 <terminate>
800026b4: 10100793 li a5,257
800026b8: 00001617 auipc a2,0x1
800026bc: 86060613 addi a2,a2,-1952 # 80002f18 <pass+0x168>
800026c0: 04100693 li a3,65
800026c4: fffff717 auipc a4,0xfffff
800026c8: 93c70713 addi a4,a4,-1732 # 80001000 <tohost>
800026cc: 03079793 slli a5,a5,0x30
800026d0: 00073503 ld a0,0(a4)
800026d4: 00160613 addi a2,a2,1
800026d8: 00f6e5b3 or a1,a3,a5
800026dc: 00050a63 beqz a0,800026f0 <handle_trap+0x160>
800026e0: fffff697 auipc a3,0xfffff
800026e4: 9606b023 sd zero,-1696(a3) # 80001040 <fromhost>
800026e8: 00073683 ld a3,0(a4)
800026ec: fe069ae3 bnez a3,800026e0 <handle_trap+0x150>
800026f0: 00064683 lbu a3,0(a2)
800026f4: 00b73023 sd a1,0(a4)
800026f8: fc069ce3 bnez a3,800026d0 <handle_trap+0x140>
800026fc: fa9ff06f j 800026a4 <handle_trap+0x114>
80002700: 05052903 lw s2,80(a0)
80002704: 00001c37 lui s8,0x1
80002708: 00005497 auipc s1,0x5
8000270c: ce848493 addi s1,s1,-792 # 800073f0 <user_mapping>
80002710: 00001b97 auipc s7,0x1
80002714: 8f0b8b93 addi s7,s7,-1808 # 80003000 <begin_signature>
80002718: 00040b37 lui s6,0x40
8000271c: ffe00ab7 lui s5,0xffe00
80002720: 00005d97 auipc s11,0x5
80002724: 0c0d8d93 addi s11,s11,192 # 800077e0 <freelist_tail>
80002728: 00005a17 auipc s4,0x5
8000272c: 0c0a0a13 addi s4,s4,192 # 800077e8 <freelist_head>
80002730: 0003f9b7 lui s3,0x3f
80002734: 0180006f j 8000274c <handle_trap+0x1bc>
80002738: 00f73423 sd a5,8(a4)
8000273c: 00fdb023 sd a5,0(s11)
80002740: 000017b7 lui a5,0x1
80002744: 00fc0c33 add s8,s8,a5
80002748: 173c0063 beq s8,s3,800028a8 <handle_trap+0x318>
8000274c: 00cc5793 srli a5,s8,0xc
80002750: 00479413 slli s0,a5,0x4
80002754: 00848733 add a4,s1,s0
80002758: 00073703 ld a4,0(a4)
8000275c: fe0702e3 beqz a4,80002740 <handle_trap+0x1b0>
80002760: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00>
80002764: 00379793 slli a5,a5,0x3
80002768: 00fb87b3 add a5,s7,a5
8000276c: 0007bc83 ld s9,0(a5)
80002770: 040cf793 andi a5,s9,64
80002774: 0e078663 beqz a5,80002860 <handle_trap+0x2d0>
80002778: 100b2d73 csrrs s10,sstatus,s6
8000277c: 00001637 lui a2,0x1
80002780: 015c05b3 add a1,s8,s5
80002784: 000c0513 mv a0,s8
80002788: 00b13423 sd a1,8(sp)
8000278c: 985ff0ef jal ra,80002110 <memcmp>
80002790: 00050e63 beqz a0,800027ac <handle_trap+0x21c>
80002794: 080cfc93 andi s9,s9,128
80002798: 00813583 ld a1,8(sp)
8000279c: 060c8e63 beqz s9,80002818 <handle_trap+0x288>
800027a0: 00001637 lui a2,0x1
800027a4: 000c0513 mv a0,s8
800027a8: 859ff0ef jal ra,80002000 <memcpy>
800027ac: 008487b3 add a5,s1,s0
800027b0: 100d1073 csrw sstatus,s10
800027b4: 000db703 ld a4,0(s11)
800027b8: 0007b023 sd zero,0(a5)
800027bc: f6071ee3 bnez a4,80002738 <handle_trap+0x1a8>
800027c0: 00fdb023 sd a5,0(s11)
800027c4: 00fa3023 sd a5,0(s4)
800027c8: f79ff06f j 80002740 <handle_trap+0x1b0>
800027cc: 10100793 li a5,257
800027d0: 04100613 li a2,65
800027d4: 00000697 auipc a3,0x0
800027d8: 79c68693 addi a3,a3,1948 # 80002f70 <pass+0x1c0>
800027dc: fffff717 auipc a4,0xfffff
800027e0: 82470713 addi a4,a4,-2012 # 80001000 <tohost>
800027e4: 03079793 slli a5,a5,0x30
800027e8: 00073503 ld a0,0(a4)
800027ec: 00168693 addi a3,a3,1
800027f0: 00f665b3 or a1,a2,a5
800027f4: 00050a63 beqz a0,80002808 <handle_trap+0x278>
800027f8: fffff617 auipc a2,0xfffff
800027fc: 84063423 sd zero,-1976(a2) # 80001040 <fromhost>
80002800: 00073603 ld a2,0(a4)
80002804: fe061ae3 bnez a2,800027f8 <handle_trap+0x268>
80002808: 0006c603 lbu a2,0(a3)
8000280c: 00b73023 sd a1,0(a4)
80002810: fc061ce3 bnez a2,800027e8 <handle_trap+0x258>
80002814: e91ff06f j 800026a4 <handle_trap+0x114>
80002818: 10100793 li a5,257
8000281c: 04100613 li a2,65
80002820: 00000697 auipc a3,0x0
80002824: 6c068693 addi a3,a3,1728 # 80002ee0 <pass+0x130>
80002828: ffffe717 auipc a4,0xffffe
8000282c: 7d870713 addi a4,a4,2008 # 80001000 <tohost>
80002830: 03079793 slli a5,a5,0x30
80002834: 00168693 addi a3,a3,1
80002838: 00f665b3 or a1,a2,a5
8000283c: 00c0006f j 80002848 <handle_trap+0x2b8>
80002840: fffff617 auipc a2,0xfffff
80002844: 80063023 sd zero,-2048(a2) # 80001040 <fromhost>
80002848: 00073603 ld a2,0(a4)
8000284c: fe061ae3 bnez a2,80002840 <handle_trap+0x2b0>
80002850: 0006c603 lbu a2,0(a3)
80002854: 00b73023 sd a1,0(a4)
80002858: fc061ee3 bnez a2,80002834 <handle_trap+0x2a4>
8000285c: e49ff06f j 800026a4 <handle_trap+0x114>
80002860: 10100793 li a5,257
80002864: 04100613 li a2,65
80002868: 00000697 auipc a3,0x0
8000286c: 64068693 addi a3,a3,1600 # 80002ea8 <pass+0xf8>
80002870: ffffe717 auipc a4,0xffffe
80002874: 79070713 addi a4,a4,1936 # 80001000 <tohost>
80002878: 03079793 slli a5,a5,0x30
8000287c: 00168693 addi a3,a3,1
80002880: 00f665b3 or a1,a2,a5
80002884: 00c0006f j 80002890 <handle_trap+0x300>
80002888: ffffe617 auipc a2,0xffffe
8000288c: 7a063c23 sd zero,1976(a2) # 80001040 <fromhost>
80002890: 00073603 ld a2,0(a4)
80002894: fe061ae3 bnez a2,80002888 <handle_trap+0x2f8>
80002898: 0006c603 lbu a2,0(a3)
8000289c: 00b73023 sd a1,0(a4)
800028a0: fc061ee3 bnez a2,8000287c <handle_trap+0x2ec>
800028a4: e01ff06f j 800026a4 <handle_trap+0x114>
800028a8: 00090513 mv a0,s2
800028ac: 98dff0ef jal ra,80002238 <terminate>
00000000800028b0 <vm_boot>:
800028b0: f14027f3 csrr a5,mhartid
800028b4: 18079463 bnez a5,80002a3c <vm_boot+0x18c>
800028b8: 00002797 auipc a5,0x2
800028bc: 74878793 addi a5,a5,1864 # 80005000 <begin_signature+0x2000>
800028c0: ed010113 addi sp,sp,-304
800028c4: 00c7d793 srli a5,a5,0xc
800028c8: 12813023 sd s0,288(sp)
800028cc: 00003817 auipc a6,0x3
800028d0: 73480813 addi a6,a6,1844 # 80006000 <begin_signature+0x3000>
800028d4: 00050413 mv s0,a0
800028d8: 00a79793 slli a5,a5,0xa
800028dc: 00001517 auipc a0,0x1
800028e0: 72450513 addi a0,a0,1828 # 80004000 <begin_signature+0x1000>
800028e4: 12113423 sd ra,296(sp)
800028e8: 00c55693 srli a3,a0,0xc
800028ec: 00c85713 srli a4,a6,0xc
800028f0: 0017e793 ori a5,a5,1
800028f4: 00000897 auipc a7,0x0
800028f8: 70c88893 addi a7,a7,1804 # 80003000 <begin_signature>
800028fc: fff00613 li a2,-1
80002900: fef53c23 sd a5,-8(a0)
80002904: 00a69693 slli a3,a3,0xa
80002908: 00a71713 slli a4,a4,0xa
8000290c: 200007b7 lui a5,0x20000
80002910: 0016e693 ori a3,a3,1
80002914: 00176713 ori a4,a4,1
80002918: 00c8d593 srli a1,a7,0xc
8000291c: 03f61313 slli t1,a2,0x3f
80002920: 0cf78793 addi a5,a5,207 # 200000cf <_start-0x5fffff31>
80002924: fef83c23 sd a5,-8(a6)
80002928: 00d8b023 sd a3,0(a7)
8000292c: 00e53023 sd a4,0(a0)
80002930: 0065e7b3 or a5,a1,t1
80002934: 18079073 csrw satp,a5
80002938: 18002773 csrr a4,satp
8000293c: 14e79863 bne a5,a4,80002a8c <vm_boot+0x1dc>
80002940: 00b65613 srli a2,a2,0xb
80002944: 01f00793 li a5,31
80002948: 00000297 auipc t0,0x0
8000294c: 01428293 addi t0,t0,20 # 8000295c <vm_boot+0xac>
80002950: 305292f3 csrrw t0,mtvec,t0
80002954: 3b061073 csrw pmpaddr0,a2
80002958: 3a079073 csrw pmpcfg0,a5
8000295c: bff00813 li a6,-1025
80002960: 01581813 slli a6,a6,0x15
80002964: ffffd797 auipc a5,0xffffd
80002968: 7e078793 addi a5,a5,2016 # 80000144 <trap_entry>
8000296c: 010787b3 add a5,a5,a6
80002970: 10579073 csrw stvec,a5
80002974: 340027f3 csrr a5,mscratch
80002978: 010787b3 add a5,a5,a6
8000297c: 14079073 csrw sscratch,a5
80002980: 0000b7b7 lui a5,0xb
80002984: 1007879b addiw a5,a5,256
80002988: 30279073 csrw medeleg,a5
8000298c: 0001e7b7 lui a5,0x1e
80002990: 30079073 csrw mstatus,a5
80002994: 30405073 csrwi mie,0
80002998: 00004717 auipc a4,0x4
8000299c: 66870713 addi a4,a4,1640 # 80007000 <freelist_nodes>
800029a0: 010707b3 add a5,a4,a6
800029a4: 3e078693 addi a3,a5,992 # 1e3e0 <_start-0x7ffe1c20>
800029a8: 00005617 auipc a2,0x5
800029ac: e4f63023 sd a5,-448(a2) # 800077e8 <freelist_head>
800029b0: 000808b7 lui a7,0x80
800029b4: 00005797 auipc a5,0x5
800029b8: e2d7b623 sd a3,-468(a5) # 800077e0 <freelist_tail>
800029bc: 00005317 auipc t1,0x5
800029c0: a3430313 addi t1,t1,-1484 # 800073f0 <user_mapping>
800029c4: 00400793 li a5,4
800029c8: 03f88893 addi a7,a7,63 # 8003f <_start-0x7ff7ffc1>
800029cc: 01080813 addi a6,a6,16
800029d0: 0017d613 srli a2,a5,0x1
800029d4: 011786b3 add a3,a5,a7
800029d8: 00f647b3 xor a5,a2,a5
800029dc: 010705b3 add a1,a4,a6
800029e0: 00c69693 slli a3,a3,0xc
800029e4: 00579793 slli a5,a5,0x5
800029e8: 00d73023 sd a3,0(a4)
800029ec: 00b73423 sd a1,8(a4)
800029f0: 0207f793 andi a5,a5,32
800029f4: 01070713 addi a4,a4,16
800029f8: 00f667b3 or a5,a2,a5
800029fc: fce31ae3 bne t1,a4,800029d0 <vm_boot+0x120>
80002a00: 12000613 li a2,288
80002a04: 00000593 li a1,0
80002a08: 00010513 mv a0,sp
80002a0c: 00005797 auipc a5,0x5
80002a10: 9c07be23 sd zero,-1572(a5) # 800073e8 <freelist_nodes+0x3e8>
80002a14: e48ff0ef jal ra,8000205c <memset>
80002a18: 800007b7 lui a5,0x80000
80002a1c: 00f40433 add s0,s0,a5
80002a20: 00010513 mv a0,sp
80002a24: 10813423 sd s0,264(sp)
80002a28: e94fd0ef jal ra,800000bc <pop_tf>
80002a2c: 12813083 ld ra,296(sp)
80002a30: 12013403 ld s0,288(sp)
80002a34: 13010113 addi sp,sp,304
80002a38: 00008067 ret
80002a3c: 00100613 li a2,1
80002a40: 00a547b7 lui a5,0xa54
80002a44: 000805b7 lui a1,0x80
80002a48: 01f61513 slli a0,a2,0x1f
80002a4c: f8778793 addi a5,a5,-121 # a53f87 <_start-0x7f5ac079>
80002a50: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004>
80002a54: 03e61613 slli a2,a2,0x3e
80002a58: 01c0006f j 80002a74 <vm_boot+0x1c4>
80002a5c: 0007202f amoadd.w zero,zero,(a4)
80002a60: 0017d713 srli a4,a5,0x1
80002a64: 00e7c7b3 xor a5,a5,a4
80002a68: 03e79793 slli a5,a5,0x3e
80002a6c: 00c7f7b3 and a5,a5,a2
80002a70: 00e7e7b3 or a5,a5,a4
80002a74: 00b7f733 and a4,a5,a1
80002a78: 0017f693 andi a3,a5,1
80002a7c: 00a70733 add a4,a4,a0
80002a80: fc069ee3 bnez a3,80002a5c <vm_boot+0x1ac>
80002a84: 00072003 lw zero,0(a4)
80002a88: fd9ff06f j 80002a60 <vm_boot+0x1b0>
80002a8c: 10100793 li a5,257
80002a90: 04100613 li a2,65
80002a94: 00000697 auipc a3,0x0
80002a98: 50c68693 addi a3,a3,1292 # 80002fa0 <pass+0x1f0>
80002a9c: ffffe717 auipc a4,0xffffe
80002aa0: 56470713 addi a4,a4,1380 # 80001000 <tohost>
80002aa4: 03079793 slli a5,a5,0x30
80002aa8: 00073503 ld a0,0(a4)
80002aac: 00168693 addi a3,a3,1
80002ab0: 00f665b3 or a1,a2,a5
80002ab4: 00050a63 beqz a0,80002ac8 <vm_boot+0x218>
80002ab8: ffffe617 auipc a2,0xffffe
80002abc: 58063423 sd zero,1416(a2) # 80001040 <fromhost>
80002ac0: 00073603 ld a2,0(a4)
80002ac4: fe061ae3 bnez a2,80002ab8 <vm_boot+0x208>
80002ac8: 0006c603 lbu a2,0(a3)
80002acc: 00b73023 sd a1,0(a4)
80002ad0: fc061ce3 bnez a2,80002aa8 <vm_boot+0x1f8>
80002ad4: 00300513 li a0,3
80002ad8: f60ff0ef jal ra,80002238 <terminate>
0000000080002adc <extra_boot>:
80002adc: 00008067 ret
0000000080002ae0 <userstart>:
80002ae0: fff0009b addiw ra,zero,-1
80002ae4: 02709093 slli ra,ra,0x27
80002ae8: 4000d713 srai a4,ra,0x0
80002aec: fff00e9b addiw t4,zero,-1
80002af0: 027e9e93 slli t4,t4,0x27
80002af4: 00200193 li gp,2
80002af8: 2bd71463 bne a4,t4,80002da0 <fail>
0000000080002afc <test_3>:
80002afc: 800000b7 lui ra,0x80000
80002b00: 4010d713 srai a4,ra,0x1
80002b04: c0000eb7 lui t4,0xc0000
80002b08: 00300193 li gp,3
80002b0c: 29d71a63 bne a4,t4,80002da0 <fail>
0000000080002b10 <test_4>:
80002b10: 800000b7 lui ra,0x80000
80002b14: 4070d713 srai a4,ra,0x7
80002b18: ff000eb7 lui t4,0xff000
80002b1c: 00400193 li gp,4
80002b20: 29d71063 bne a4,t4,80002da0 <fail>
0000000080002b24 <test_5>:
80002b24: 800000b7 lui ra,0x80000
80002b28: 40e0d713 srai a4,ra,0xe
80002b2c: fffe0eb7 lui t4,0xfffe0
80002b30: 00500193 li gp,5
80002b34: 27d71663 bne a4,t4,80002da0 <fail>
0000000080002b38 <test_6>:
80002b38: 800000b7 lui ra,0x80000
80002b3c: 0010809b addiw ra,ra,1
80002b40: 41f0d713 srai a4,ra,0x1f
80002b44: fff00e93 li t4,-1
80002b48: 00600193 li gp,6
80002b4c: 25d71a63 bne a4,t4,80002da0 <fail>
0000000080002b50 <test_7>:
80002b50: 800000b7 lui ra,0x80000
80002b54: fff0809b addiw ra,ra,-1
80002b58: 4000d713 srai a4,ra,0x0
80002b5c: 80000eb7 lui t4,0x80000
80002b60: fffe8e9b addiw t4,t4,-1
80002b64: 00700193 li gp,7
80002b68: 23d71c63 bne a4,t4,80002da0 <fail>
0000000080002b6c <test_8>:
80002b6c: 800000b7 lui ra,0x80000
80002b70: fff0809b addiw ra,ra,-1
80002b74: 4010d713 srai a4,ra,0x1
80002b78: 40000eb7 lui t4,0x40000
80002b7c: fffe8e9b addiw t4,t4,-1
80002b80: 00800193 li gp,8
80002b84: 21d71e63 bne a4,t4,80002da0 <fail>
0000000080002b88 <test_9>:
80002b88: 800000b7 lui ra,0x80000
80002b8c: fff0809b addiw ra,ra,-1
80002b90: 4070d713 srai a4,ra,0x7
80002b94: 01000eb7 lui t4,0x1000
80002b98: fffe8e9b addiw t4,t4,-1
80002b9c: 00900193 li gp,9
80002ba0: 21d71063 bne a4,t4,80002da0 <fail>
0000000080002ba4 <test_10>:
80002ba4: 800000b7 lui ra,0x80000
80002ba8: fff0809b addiw ra,ra,-1
80002bac: 40e0d713 srai a4,ra,0xe
80002bb0: 00020eb7 lui t4,0x20
80002bb4: fffe8e9b addiw t4,t4,-1
80002bb8: 00a00193 li gp,10
80002bbc: 1fd71263 bne a4,t4,80002da0 <fail>
0000000080002bc0 <test_11>:
80002bc0: 800000b7 lui ra,0x80000
80002bc4: fff0809b addiw ra,ra,-1
80002bc8: 41f0d713 srai a4,ra,0x1f
80002bcc: 00000e93 li t4,0
80002bd0: 00b00193 li gp,11
80002bd4: 1dd71663 bne a4,t4,80002da0 <fail>
0000000080002bd8 <test_12>:
80002bd8: 818180b7 lui ra,0x81818
80002bdc: 1810809b addiw ra,ra,385
80002be0: 4000d713 srai a4,ra,0x0
80002be4: 81818eb7 lui t4,0x81818
80002be8: 181e8e9b addiw t4,t4,385
80002bec: 00c00193 li gp,12
80002bf0: 1bd71863 bne a4,t4,80002da0 <fail>
0000000080002bf4 <test_13>:
80002bf4: 818180b7 lui ra,0x81818
80002bf8: 1810809b addiw ra,ra,385
80002bfc: 4010d713 srai a4,ra,0x1
80002c00: c0c0ceb7 lui t4,0xc0c0c
80002c04: 0c0e8e9b addiw t4,t4,192
80002c08: 00d00193 li gp,13
80002c0c: 19d71a63 bne a4,t4,80002da0 <fail>
0000000080002c10 <test_14>:
80002c10: 818180b7 lui ra,0x81818
80002c14: 1810809b addiw ra,ra,385
80002c18: 4070d713 srai a4,ra,0x7
80002c1c: ff030eb7 lui t4,0xff030
80002c20: 303e8e9b addiw t4,t4,771
80002c24: 00e00193 li gp,14
80002c28: 17d71c63 bne a4,t4,80002da0 <fail>
0000000080002c2c <test_15>:
80002c2c: 818180b7 lui ra,0x81818
80002c30: 1810809b addiw ra,ra,385
80002c34: 40e0d713 srai a4,ra,0xe
80002c38: fffe0eb7 lui t4,0xfffe0
80002c3c: 606e8e9b addiw t4,t4,1542
80002c40: 00f00193 li gp,15
80002c44: 15d71e63 bne a4,t4,80002da0 <fail>
0000000080002c48 <test_16>:
80002c48: 818180b7 lui ra,0x81818
80002c4c: 1810809b addiw ra,ra,385
80002c50: 41f0d713 srai a4,ra,0x1f
80002c54: fff00e93 li t4,-1
80002c58: 01000193 li gp,16
80002c5c: 15d71263 bne a4,t4,80002da0 <fail>
0000000080002c60 <test_17>:
80002c60: 800000b7 lui ra,0x80000
80002c64: 4070d093 srai ra,ra,0x7
80002c68: ff000eb7 lui t4,0xff000
80002c6c: 01100193 li gp,17
80002c70: 13d09863 bne ra,t4,80002da0 <fail>
0000000080002c74 <test_18>:
80002c74: 00000213 li tp,0
80002c78: 800000b7 lui ra,0x80000
80002c7c: 4070d713 srai a4,ra,0x7
80002c80: 00070313 mv t1,a4
80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002c88: 00200293 li t0,2
80002c8c: fe5216e3 bne tp,t0,80002c78 <test_18+0x4>
80002c90: ff000eb7 lui t4,0xff000
80002c94: 01200193 li gp,18
80002c98: 11d31463 bne t1,t4,80002da0 <fail>
0000000080002c9c <test_19>:
80002c9c: 00000213 li tp,0
80002ca0: 800000b7 lui ra,0x80000
80002ca4: 40e0d713 srai a4,ra,0xe
80002ca8: 00000013 nop
80002cac: 00070313 mv t1,a4
80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002cb4: 00200293 li t0,2
80002cb8: fe5214e3 bne tp,t0,80002ca0 <test_19+0x4>
80002cbc: fffe0eb7 lui t4,0xfffe0
80002cc0: 01300193 li gp,19
80002cc4: 0dd31e63 bne t1,t4,80002da0 <fail>
0000000080002cc8 <test_20>:
80002cc8: 00000213 li tp,0
80002ccc: 800000b7 lui ra,0x80000
80002cd0: 0010809b addiw ra,ra,1
80002cd4: 41f0d713 srai a4,ra,0x1f
80002cd8: 00000013 nop
80002cdc: 00000013 nop
80002ce0: 00070313 mv t1,a4
80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002ce8: 00200293 li t0,2
80002cec: fe5210e3 bne tp,t0,80002ccc <test_20+0x4>
80002cf0: fff00e93 li t4,-1
80002cf4: 01400193 li gp,20
80002cf8: 0bd31463 bne t1,t4,80002da0 <fail>
0000000080002cfc <test_21>:
80002cfc: 00000213 li tp,0
80002d00: 800000b7 lui ra,0x80000
80002d04: 4070d713 srai a4,ra,0x7
80002d08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002d0c: 00200293 li t0,2
80002d10: fe5218e3 bne tp,t0,80002d00 <test_21+0x4>
80002d14: ff000eb7 lui t4,0xff000
80002d18: 01500193 li gp,21
80002d1c: 09d71263 bne a4,t4,80002da0 <fail>
0000000080002d20 <test_22>:
80002d20: 00000213 li tp,0
80002d24: 800000b7 lui ra,0x80000
80002d28: 00000013 nop
80002d2c: 40e0d713 srai a4,ra,0xe
80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002d34: 00200293 li t0,2
80002d38: fe5216e3 bne tp,t0,80002d24 <test_22+0x4>
80002d3c: fffe0eb7 lui t4,0xfffe0
80002d40: 01600193 li gp,22
80002d44: 05d71e63 bne a4,t4,80002da0 <fail>
0000000080002d48 <test_23>:
80002d48: 00000213 li tp,0
80002d4c: 800000b7 lui ra,0x80000
80002d50: 0010809b addiw ra,ra,1
80002d54: 00000013 nop
80002d58: 00000013 nop
80002d5c: 41f0d713 srai a4,ra,0x1f
80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80002d64: 00200293 li t0,2
80002d68: fe5212e3 bne tp,t0,80002d4c <test_23+0x4>
80002d6c: fff00e93 li t4,-1
80002d70: 01700193 li gp,23
80002d74: 03d71663 bne a4,t4,80002da0 <fail>
0000000080002d78 <test_24>:
80002d78: 40405093 srai ra,zero,0x4
80002d7c: 00000e93 li t4,0
80002d80: 01800193 li gp,24
80002d84: 01d09e63 bne ra,t4,80002da0 <fail>
0000000080002d88 <test_25>:
80002d88: 02100093 li ra,33
80002d8c: 40a0d013 srai zero,ra,0xa
80002d90: 00000e93 li t4,0
80002d94: 01900193 li gp,25
80002d98: 01d01463 bne zero,t4,80002da0 <fail>
80002d9c: 00301a63 bne zero,gp,80002db0 <pass>
0000000080002da0 <fail>:
80002da0: 00119513 slli a0,gp,0x1
80002da4: 00050063 beqz a0,80002da4 <fail+0x4>
80002da8: 00156513 ori a0,a0,1
80002dac: 00000073 ecall
0000000080002db0 <pass>:
80002db0: 00100513 li a0,1
80002db4: 00000073 ecall
80002db8: c0001073 unimp
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2011-2015 CrystaX.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY CrystaX ''AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL CrystaX OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those of the
* authors and should not be interpreted as representing official policies, either expressed
* or implied, of CrystaX.
*/
#include <errno.h>
#include "gen/errno.inc"
| {
"language": "Assembly"
} |
/*
* Kernel execution entry point code.
*
* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
* Initial PowerPC version.
* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
* Rewritten for PReP
* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
* Low-level exception handers, MMU support, and rewrite.
* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
* PowerPC 8xx modifications.
* Copyright (c) 1998-1999 TiVo, Inc.
* PowerPC 403GCX modifications.
* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
* PowerPC 403GCX/405GP modifications.
* Copyright 2000 MontaVista Software Inc.
* PPC405 modifications
* PowerPC 403GCX/405GP modifications.
* Author: MontaVista Software, Inc.
* frank_rowand@mvista.com or source@mvista.com
* debbie_chu@mvista.com
* Copyright 2002-2004 MontaVista Software, Inc.
* PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
* Copyright 2004 Freescale Semiconductor, Inc
* PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include "head_booke.h"
/* As with the other PowerPC ports, it is expected that when code
* execution begins here, the following registers contain valid, yet
* optional, information:
*
* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
* r4 - Starting address of the init RAM disk
* r5 - Ending address of the init RAM disk
* r6 - Start of kernel command line string (e.g. "mem=128")
* r7 - End of kernel command line string
*
*/
__HEAD
_ENTRY(_stext);
_ENTRY(_start);
/*
* Reserve a word at a fixed location to store the address
* of abatron_pteptrs
*/
nop
/*
* Save parameters we are passed
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
li r25,0 /* phys kernel start (low) */
li r24,0 /* CPU number */
li r23,0 /* phys kernel start (high) */
/* We try to not make any assumptions about how the boot loader
* setup or used the TLBs. We invalidate all mappings from the
* boot loader and load a single entry in TLB1[0] to map the
* first 64M of kernel memory. Any boot info passed from the
* bootloader needs to live in this first 64M.
*
* Requirement on bootloader:
* - The page we're executing in needs to reside in TLB1 and
* have IPROT=1. If not an invalidate broadcast could
* evict the entry we're currently executing in.
*
* r3 = Index of TLB1 were executing in
* r4 = Current MSR[IS]
* r5 = Index of TLB1 temp mapping
*
* Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
* if needed
*/
_ENTRY(__early_start)
/* 1. Find the index of the entry we're executing in */
bl invstr /* Find our address */
invstr: mflr r6 /* Make it accessible */
mfmsr r7
rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
mfspr r7, SPRN_PID0
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7,SPRN_MMUCFG
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
cmpwi r7,3
bne match_TLB /* skip if NPIDS != 3 */
mfspr r7,SPRN_PID1
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7, SPRN_PID2
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* Fall through, we had to match */
match_TLB:
mfspr r7,SPRN_MAS0
rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
oris r7,r7,MAS1_IPROT@h
mtspr SPRN_MAS1,r7
tlbwe
/* 2. Invalidate all entries except the entry we're executing in */
mfspr r9,SPRN_TLB1CFG
andi. r9,r9,0xfff
li r6,0 /* Set Entry counter to 0 */
1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
mtspr SPRN_MAS0,r7
tlbre
mfspr r7,SPRN_MAS1
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
cmpw r3,r6
beq skpinv /* Dont update the current execution TLB */
mtspr SPRN_MAS1,r7
tlbwe
isync
skpinv: addi r6,r6,1 /* Increment */
cmpw r6,r9 /* Are we done? */
bne 1b /* If not, repeat */
/* Invalidate TLB0 */
li r6,0x04
tlbivax 0,r6
TLBSYNC
/* Invalidate TLB1 */
li r6,0x0c
tlbivax 0,r6
TLBSYNC
/* 3. Setup a temp mapping and jump to it */
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
addi r5, r5, 0x1
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
mtspr SPRN_MAS0,r7
tlbre
/* grab and fixup the RPN */
mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
rlwinm r6,r6,25,27,31
li r8,-1
addi r6,r6,10
slw r6,r8,r6 /* convert to mask */
bl 1f /* Find our address */
1: mflr r7
mfspr r8,SPRN_MAS3
#ifdef CONFIG_PHYS_64BIT
mfspr r23,SPRN_MAS7
#endif
and r8,r6,r8
subfic r9,r6,-4096
and r9,r9,r7
or r25,r8,r9
ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
/* Just modify the entry ID and EPN for the temp mapping */
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
mtspr SPRN_MAS0,r7
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
slwi r6,r6,12
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
li r7,0 /* temp EPN = 0 */
rlwimi r7,r6,0,20,31
mtspr SPRN_MAS2,r7
mtspr SPRN_MAS3,r8
tlbwe
xori r6,r4,1
slwi r6,r6,5 /* setup new context with other address space */
bl 1f /* Find our address */
1: mflr r9
rlwimi r7,r9,0,20,31
addi r7,r7,24
mtspr SPRN_SRR0,r7
mtspr SPRN_SRR1,r6
rfi
/* 4. Clear out PIDs & Search info */
li r6,0
mtspr SPRN_MAS6,r6
mtspr SPRN_PID0,r6
mfspr r7,SPRN_MMUCFG
rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
cmpwi r7,3
bne 2f /* skip if NPIDS != 3 */
mtspr SPRN_PID1,r6
mtspr SPRN_PID2,r6
/* 5. Invalidate mapping we started in */
2:
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
mtspr SPRN_MAS0,r7
tlbre
mfspr r6,SPRN_MAS1
rlwinm r6,r6,0,2,0 /* clear IPROT */
mtspr SPRN_MAS1,r6
tlbwe
/* Invalidate TLB1 */
li r9,0x0c
tlbivax 0,r9
TLBSYNC
/* The mapping only needs to be cache-coherent on SMP */
#ifdef CONFIG_SMP
#define M_IF_SMP MAS2_M
#else
#define M_IF_SMP 0
#endif
/* 6. Setup KERNELBASE mapping in TLB1[0] */
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
mtspr SPRN_MAS0,r6
lis r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
mtspr SPRN_MAS1,r6
lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
mtspr SPRN_MAS2,r6
mtspr SPRN_MAS3,r8
tlbwe
/* 7. Jump to KERNELBASE mapping */
lis r6,(KERNELBASE & ~0xfff)@h
ori r6,r6,(KERNELBASE & ~0xfff)@l
lis r7,MSR_KERNEL@h
ori r7,r7,MSR_KERNEL@l
bl 1f /* Find our address */
1: mflr r9
rlwimi r6,r9,0,20,31
addi r6,r6,(2f - 1b)
mtspr SPRN_SRR0,r6
mtspr SPRN_SRR1,r7
rfi /* start execution out of TLB1[0] entry */
/* 8. Clear out the temp mapping */
2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
mtspr SPRN_MAS0,r7
tlbre
mfspr r8,SPRN_MAS1
rlwinm r8,r8,0,2,0 /* clear IPROT */
mtspr SPRN_MAS1,r8
tlbwe
/* Invalidate TLB1 */
li r9,0x0c
tlbivax 0,r9
TLBSYNC
/* Establish the interrupt vector offsets */
SET_IVOR(0, CriticalInput);
SET_IVOR(1, MachineCheck);
SET_IVOR(2, DataStorage);
SET_IVOR(3, InstructionStorage);
SET_IVOR(4, ExternalInput);
SET_IVOR(5, Alignment);
SET_IVOR(6, Program);
SET_IVOR(7, FloatingPointUnavailable);
SET_IVOR(8, SystemCall);
SET_IVOR(9, AuxillaryProcessorUnavailable);
SET_IVOR(10, Decrementer);
SET_IVOR(11, FixedIntervalTimer);
SET_IVOR(12, WatchdogTimer);
SET_IVOR(13, DataTLBError);
SET_IVOR(14, InstructionTLBError);
SET_IVOR(15, DebugCrit);
/* Establish the interrupt vector base */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
/* Setup the defaults for TLB entries */
li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
#ifdef CONFIG_E200
oris r2,r2,MAS4_TLBSELD(1)@h
#endif
mtspr SPRN_MAS4, r2
#if 0
/* Enable DOZE */
mfspr r2,SPRN_HID0
oris r2,r2,HID0_DOZE@h
mtspr SPRN_HID0, r2
#endif
#if !defined(CONFIG_BDI_SWITCH)
/*
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
*/
lis r2,DBCR0_IDM@h
mtspr SPRN_DBCR0,r2
isync
/* clear any residual debug events */
li r2,-1
mtspr SPRN_DBSR,r2
#endif
#ifdef CONFIG_SMP
/* Check to see if we're the second processor, and jump
* to the secondary_start code if so
*/
mfspr r24,SPRN_PIR
cmpwi r24,0
bne __secondary_start
#endif
/*
* This is where the main kernel code starts.
*/
/* ptr to current */
lis r2,init_task@h
ori r2,r2,init_task@l
/* ptr to current thread */
addi r4,r2,THREAD /* init task's THREAD */
mtspr SPRN_SPRG_THREAD,r4
/* stack */
lis r1,init_thread_union@h
ori r1,r1,init_thread_union@l
li r0,0
stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
bl early_init
#ifdef CONFIG_RELOCATABLE
lis r3,kernstart_addr@ha
la r3,kernstart_addr@l(r3)
#ifdef CONFIG_PHYS_64BIT
stw r23,0(r3)
stw r25,4(r3)
#else
stw r25,0(r3)
#endif
#endif
/*
* Decide what sort of machine this is and initialize the MMU.
*/
mr r3,r31
mr r4,r30
mr r5,r29
mr r6,r28
mr r7,r27
bl machine_init
bl MMU_init
/* Setup PTE pointers for the Abatron bdiGDB */
lis r6, swapper_pg_dir@h
ori r6, r6, swapper_pg_dir@l
lis r5, abatron_pteptrs@h
ori r5, r5, abatron_pteptrs@l
lis r4, KERNELBASE@h
ori r4, r4, KERNELBASE@l
stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
stw r6, 0(r5)
/* Let's move on */
lis r4,start_kernel@h
ori r4,r4,start_kernel@l
lis r3,MSR_KERNEL@h
ori r3,r3,MSR_KERNEL@l
mtspr SPRN_SRR0,r4
mtspr SPRN_SRR1,r3
rfi /* change context and jump to start_kernel */
/* Macros to hide the PTE size differences
*
* FIND_PTE -- walks the page tables given EA & pgdir pointer
* r10 -- EA of fault
* r11 -- PGDIR pointer
* r12 -- free
* label 2: is the bailout case
*
* if we find the pte (fall through):
* r11 is low pte word
* r12 is pointer to the pte
*/
#ifdef CONFIG_PTE_64BIT
#define FIND_PTE \
rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
beq 2f; /* Bail if no table */ \
rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
lwz r11, 4(r12); /* Get pte entry */
#else
#define FIND_PTE \
rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
lwz r11, 0(r11); /* Get L1 entry */ \
rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
beq 2f; /* Bail if no table */ \
rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
lwz r11, 0(r12); /* Get Linux PTE */
#endif
/*
* Interrupt vector entry code
*
* The Book E MMUs are always on so we don't need to handle
* interrupts in real mode as with previous PPC processors. In
* this case we handle interrupts in the kernel virtual address
* space.
*
* Interrupt vectors are dynamically placed relative to the
* interrupt prefix as determined by the address of interrupt_base.
* The interrupt vectors offsets are programmed using the labels
* for each interrupt vector entry.
*
* Interrupt vectors must be aligned on a 16 byte boundary.
* We align on a 32 byte cache line boundary for good measure.
*/
interrupt_base:
/* Critical Input Interrupt */
CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
/* Machine Check Interrupt */
#ifdef CONFIG_E200
/* no RFMCI, MCSRRs on E200 */
CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
#else
MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
#endif
/* Data Storage Interrupt */
START_EXCEPTION(DataStorage)
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
stw r5,_ESR(r11)
mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
andis. r10,r5,(ESR_ILK|ESR_DLK)@h
bne 1f
EXC_XFER_EE_LITE(0x0300, handle_page_fault)
1:
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x0300, CacheLockingException)
/* Instruction Storage Interrupt */
INSTRUCTION_STORAGE_EXCEPTION
/* External Input Interrupt */
EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
/* Alignment Interrupt */
ALIGNMENT_EXCEPTION
/* Program Interrupt */
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
#ifdef CONFIG_PPC_FPU
FP_UNAVAILABLE_EXCEPTION
#else
#ifdef CONFIG_E200
/* E200 treats 'normal' floating point instructions as FP Unavail exception */
EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
#else
EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
#endif
#endif
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
NORMAL_EXCEPTION_PROLOG
EXC_XFER_EE_LITE(0x0c00, DoSyscall)
/* Auxillary Processor Unavailable Interrupt */
EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
/* Decrementer Interrupt */
DECREMENTER_EXCEPTION
/* Fixed Internal Timer Interrupt */
/* TODO: Add FIT support */
EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
/* Watchdog Timer Interrupt */
#ifdef CONFIG_BOOKE_WDT
CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
#else
CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
#endif
/* Data TLB Error Interrupt */
START_EXCEPTION(DataTLBError)
mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
mtspr SPRN_SPRG_WSCRATCH1, r11
mtspr SPRN_SPRG_WSCRATCH2, r12
mtspr SPRN_SPRG_WSCRATCH3, r13
mfcr r11
mtspr SPRN_SPRG_WSCRATCH4, r11
mfspr r10, SPRN_DEAR /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
lis r11, PAGE_OFFSET@h
cmplw 5, r10, r11
blt 5, 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
mfspr r12,SPRN_MAS1 /* Set TID to 0 */
rlwinm r12,r12,0,16,1
mtspr SPRN_MAS1,r12
b 4f
/* Get the PGD for the current thread */
3:
mfspr r11,SPRN_SPRG_THREAD
lwz r11,PGDIR(r11)
4:
/* Mask of required permission bits. Note that while we
* do copy ESR:ST to _PAGE_RW position as trying to write
* to an RO page is pretty common, we don't do it with
* _PAGE_DIRTY. We could do it, but it's a fairly rare
* event so I'd rather take the overhead when it happens
* rather than adding an instruction here. We should measure
* whether the whole thing is worth it in the first place
* as we could avoid loading SPRN_ESR completely in the first
* place...
*
* TODO: Is it worth doing that mfspr & rlwimi in the first
* place or can we save a couple of instructions here ?
*/
mfspr r12,SPRN_ESR
#ifdef CONFIG_PTE_64BIT
li r13,_PAGE_PRESENT
oris r13,r13,_PAGE_ACCESSED@h
#else
li r13,_PAGE_PRESENT|_PAGE_ACCESSED
#endif
rlwimi r13,r12,11,29,29
FIND_PTE
andc. r13,r13,r11 /* Check permission */
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
#endif
bne 2f /* Bail if permission/valid mismach */
/* Jump to common tlb load */
b finish_tlb_load
2:
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
mfspr r11, SPRN_SPRG_RSCRATCH4
mtcr r11
mfspr r13, SPRN_SPRG_RSCRATCH3
mfspr r12, SPRN_SPRG_RSCRATCH2
mfspr r11, SPRN_SPRG_RSCRATCH1
mfspr r10, SPRN_SPRG_RSCRATCH0
b DataStorage
/* Instruction TLB Error Interrupt */
/*
* Nearly the same as above, except we get our
* information from different registers and bailout
* to a different point.
*/
START_EXCEPTION(InstructionTLBError)
mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
mtspr SPRN_SPRG_WSCRATCH1, r11
mtspr SPRN_SPRG_WSCRATCH2, r12
mtspr SPRN_SPRG_WSCRATCH3, r13
mfcr r11
mtspr SPRN_SPRG_WSCRATCH4, r11
mfspr r10, SPRN_SRR0 /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
lis r11, PAGE_OFFSET@h
cmplw 5, r10, r11
blt 5, 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
mfspr r12,SPRN_MAS1 /* Set TID to 0 */
rlwinm r12,r12,0,16,1
mtspr SPRN_MAS1,r12
b 4f
/* Get the PGD for the current thread */
3:
mfspr r11,SPRN_SPRG_THREAD
lwz r11,PGDIR(r11)
4:
/* Make up the required permissions */
#ifdef CONFIG_PTE_64BIT
li r13,_PAGE_PRESENT | _PAGE_EXEC
oris r13,r13,_PAGE_ACCESSED@h
#else
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
#endif
FIND_PTE
andc. r13,r13,r11 /* Check permission */
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
#endif
bne 2f /* Bail if permission mismach */
/* Jump to common TLB load point */
b finish_tlb_load
2:
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
mfspr r11, SPRN_SPRG_RSCRATCH4
mtcr r11
mfspr r13, SPRN_SPRG_RSCRATCH3
mfspr r12, SPRN_SPRG_RSCRATCH2
mfspr r11, SPRN_SPRG_RSCRATCH1
mfspr r10, SPRN_SPRG_RSCRATCH0
b InstructionStorage
#ifdef CONFIG_SPE
/* SPE Unavailable */
START_EXCEPTION(SPEUnavailable)
NORMAL_EXCEPTION_PROLOG
bne load_up_spe
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x2010, KernelSPE)
#else
EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
#endif /* CONFIG_SPE */
/* SPE Floating Point Data */
#ifdef CONFIG_SPE
EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
/* SPE Floating Point Round */
EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
#else
EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
#endif /* CONFIG_SPE */
/* Performance Monitor */
EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
/* Debug Interrupt */
DEBUG_DEBUG_EXCEPTION
DEBUG_CRIT_EXCEPTION
/*
* Local functions
*/
/*
* Both the instruction and data TLB miss get to this
* point to load the TLB.
* r10 - available to use
* r11 - TLB (info from Linux PTE)
* r12 - available to use
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
* CR5 - results of addr >= PAGE_OFFSET
* MAS0, MAS1 - loaded with proper value when we get here
* MAS2, MAS3 - will need additional info from Linux PTE
* Upon exit, we reload everything and RFI.
*/
finish_tlb_load:
/*
* We set execute, because we don't have the granularity to
* properly set this at the page level (Linux problem).
* Many of these bits are software only. Bits we don't set
* here we (properly should) assume have the appropriate value.
*/
mfspr r12, SPRN_MAS2
#ifdef CONFIG_PTE_64BIT
rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
#else
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
#endif
#ifdef CONFIG_SMP
ori r12, r12, MAS2_M
#endif
mtspr SPRN_MAS2, r12
#ifdef CONFIG_PTE_64BIT
rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
andi. r10, r11, _PAGE_DIRTY
bne 1f
li r10, MAS3_SW | MAS3_UW
andc r12, r12, r10
1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
mtspr SPRN_MAS3, r12
BEGIN_MMU_FTR_SECTION
srwi r10, r13, 12 /* grab RPN[12:31] */
mtspr SPRN_MAS7, r10
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
#else
li r10, (_PAGE_EXEC | _PAGE_PRESENT)
rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
and r12, r11, r10
andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
slwi r10, r12, 1
or r10, r10, r12
iseleq r12, r12, r10
rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
mtspr SPRN_MAS3, r11
#endif
#ifdef CONFIG_E200
/* Round robin TLB1 entries assignment */
mfspr r12, SPRN_MAS0
/* Extract TLB1CFG(NENTRY) */
mfspr r11, SPRN_TLB1CFG
andi. r11, r11, 0xfff
/* Extract MAS0(NV) */
andi. r13, r12, 0xfff
addi r13, r13, 1
cmpw 0, r13, r11
addi r12, r12, 1
/* check if we need to wrap */
blt 7f
/* wrap back to first free tlbcam entry */
lis r13, tlbcam_index@ha
lwz r13, tlbcam_index@l(r13)
rlwimi r12, r13, 0, 20, 31
7:
mtspr SPRN_MAS0,r12
#endif /* CONFIG_E200 */
tlbwe
/* Done...restore registers and get out of here. */
mfspr r11, SPRN_SPRG_RSCRATCH4
mtcr r11
mfspr r13, SPRN_SPRG_RSCRATCH3
mfspr r12, SPRN_SPRG_RSCRATCH2
mfspr r11, SPRN_SPRG_RSCRATCH1
mfspr r10, SPRN_SPRG_RSCRATCH0
rfi /* Force context change */
#ifdef CONFIG_SPE
/* Note that the SPE support is closely modeled after the AltiVec
* support. Changes to one are likely to be applicable to the
* other! */
load_up_spe:
/*
* Disable SPE for the task which had SPE previously,
* and save its SPE registers in its thread_struct.
* Enables SPE for use in the kernel on return.
* On SMP we know the SPE units are free, since we give it up every
* switch. -- Kumar
*/
mfmsr r5
oris r5,r5,MSR_SPE@h
mtmsr r5 /* enable use of SPE now */
isync
/*
* For SMP, we don't do lazy SPE switching because it just gets too
* horrendously complex, especially when a task switches from one CPU
* to another. Instead we call giveup_spe in switch_to.
*/
#ifndef CONFIG_SMP
lis r3,last_task_used_spe@ha
lwz r4,last_task_used_spe@l(r3)
cmpi 0,r4,0
beq 1f
addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
SAVE_32EVRS(0,r10,r4)
evxor evr10, evr10, evr10 /* clear out evr10 */
evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
li r5,THREAD_ACC
evstddx evr10, r4, r5 /* save off accumulator */
lwz r5,PT_REGS(r4)
lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
lis r10,MSR_SPE@h
andc r4,r4,r10 /* disable SPE for previous task */
stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1:
#endif /* !CONFIG_SMP */
/* enable use of SPE after return */
oris r9,r9,MSR_SPE@h
mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
li r4,1
li r10,THREAD_ACC
stw r4,THREAD_USED_SPE(r5)
evlddx evr4,r10,r5
evmra evr4,evr4
REST_32EVRS(0,r10,r5)
#ifndef CONFIG_SMP
subi r4,r5,THREAD
stw r4,last_task_used_spe@l(r3)
#endif /* !CONFIG_SMP */
/* restore registers and return */
2: REST_4GPRS(3, r11)
lwz r10,_CCR(r11)
REST_GPR(1, r11)
mtcr r10
lwz r10,_LINK(r11)
mtlr r10
REST_GPR(10, r11)
mtspr SPRN_SRR1,r9
mtspr SPRN_SRR0,r12
REST_GPR(9, r11)
REST_GPR(12, r11)
lwz r11,GPR11(r11)
rfi
/*
* SPE unavailable trap from kernel - print a message, but let
* the task use SPE in the kernel until it returns to user mode.
*/
KernelSPE:
lwz r3,_MSR(r1)
oris r3,r3,MSR_SPE@h
stw r3,_MSR(r1) /* enable use of SPE after return */
lis r3,87f@h
ori r3,r3,87f@l
mr r4,r2 /* current */
lwz r5,_NIP(r1)
bl printk
b ret_from_except
87: .string "SPE used in kernel (task=%p, pc=%x) \n"
.align 4,0
#endif /* CONFIG_SPE */
/*
* Global functions
*/
/* Adjust or setup IVORs for e200 */
_GLOBAL(__setup_e200_ivors)
li r3,DebugDebug@l
mtspr SPRN_IVOR15,r3
li r3,SPEUnavailable@l
mtspr SPRN_IVOR32,r3
li r3,SPEFloatingPointData@l
mtspr SPRN_IVOR33,r3
li r3,SPEFloatingPointRound@l
mtspr SPRN_IVOR34,r3
sync
blr
/* Adjust or setup IVORs for e500v1/v2 */
_GLOBAL(__setup_e500_ivors)
li r3,DebugCrit@l
mtspr SPRN_IVOR15,r3
li r3,SPEUnavailable@l
mtspr SPRN_IVOR32,r3
li r3,SPEFloatingPointData@l
mtspr SPRN_IVOR33,r3
li r3,SPEFloatingPointRound@l
mtspr SPRN_IVOR34,r3
li r3,PerformanceMonitor@l
mtspr SPRN_IVOR35,r3
sync
blr
/* Adjust or setup IVORs for e500mc */
_GLOBAL(__setup_e500mc_ivors)
li r3,DebugDebug@l
mtspr SPRN_IVOR15,r3
li r3,PerformanceMonitor@l
mtspr SPRN_IVOR35,r3
li r3,Doorbell@l
mtspr SPRN_IVOR36,r3
li r3,CriticalDoorbell@l
mtspr SPRN_IVOR37,r3
sync
blr
/*
* extern void giveup_altivec(struct task_struct *prev)
*
* The e500 core does not have an AltiVec unit.
*/
_GLOBAL(giveup_altivec)
blr
#ifdef CONFIG_SPE
/*
* extern void giveup_spe(struct task_struct *prev)
*
*/
_GLOBAL(giveup_spe)
mfmsr r5
oris r5,r5,MSR_SPE@h
mtmsr r5 /* enable use of SPE now */
isync
cmpi 0,r3,0
beqlr- /* if no previous owner, done */
addi r3,r3,THREAD /* want THREAD of task */
lwz r5,PT_REGS(r3)
cmpi 0,r5,0
SAVE_32EVRS(0, r4, r3)
evxor evr6, evr6, evr6 /* clear out evr6 */
evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
li r4,THREAD_ACC
evstddx evr6, r4, r3 /* save off accumulator */
mfspr r6,SPRN_SPEFSCR
stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
beq 1f
lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
lis r3,MSR_SPE@h
andc r4,r4,r3 /* disable SPE for previous task */
stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1:
#ifndef CONFIG_SMP
li r5,0
lis r4,last_task_used_spe@ha
stw r5,last_task_used_spe@l(r4)
#endif /* !CONFIG_SMP */
blr
#endif /* CONFIG_SPE */
/*
* extern void giveup_fpu(struct task_struct *prev)
*
* Not all FSL Book-E cores have an FPU
*/
#ifndef CONFIG_PPC_FPU
_GLOBAL(giveup_fpu)
blr
#endif
/*
* extern void abort(void)
*
* At present, this routine just applies a system reset.
*/
_GLOBAL(abort)
li r13,0
mtspr SPRN_DBCR0,r13 /* disable all debug events */
isync
mfmsr r13
ori r13,r13,MSR_DE@l /* Enable Debug Events */
mtmsr r13
isync
mfspr r13,SPRN_DBCR0
lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
mtspr SPRN_DBCR0,r13
isync
_GLOBAL(set_context)
#ifdef CONFIG_BDI_SWITCH
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is the second parameter.
*/
lis r5, abatron_pteptrs@h
ori r5, r5, abatron_pteptrs@l
stw r4, 0x4(r5)
#endif
mtspr SPRN_PID,r3
isync /* Force context change */
blr
_GLOBAL(flush_dcache_L1)
mfspr r3,SPRN_L1CFG0
rlwinm r5,r3,9,3 /* Extract cache block size */
twlgti r5,1 /* Only 32 and 64 byte cache blocks
* are currently defined.
*/
li r4,32
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
* log2(number of ways)
*/
slw r5,r4,r5 /* r5 = cache block size */
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
mulli r7,r7,13 /* An 8-way cache will require 13
* loads per set.
*/
slw r7,r7,r6
/* save off HID0 and set DCFA */
mfspr r8,SPRN_HID0
ori r9,r8,HID0_DCFA@l
mtspr SPRN_HID0,r9
isync
lis r4,KERNELBASE@h
mtctr r7
1: lwz r3,0(r4) /* Load... */
add r4,r4,r5
bdnz 1b
msync
lis r4,KERNELBASE@h
mtctr r7
1: dcbf 0,r4 /* ...and flush. */
add r4,r4,r5
bdnz 1b
/* restore HID0 */
mtspr SPRN_HID0,r8
isync
blr
#ifdef CONFIG_SMP
/* When we get here, r24 needs to hold the CPU # */
.globl __secondary_start
__secondary_start:
lis r3,__secondary_hold_acknowledge@h
ori r3,r3,__secondary_hold_acknowledge@l
stw r24,0(r3)
li r3,0
mr r4,r24 /* Why? */
bl call_setup_cpu
lis r3,tlbcam_index@ha
lwz r3,tlbcam_index@l(r3)
mtctr r3
li r26,0 /* r26 safe? */
/* Load each CAM entry */
1: mr r3,r26
bl loadcam_entry
addi r26,r26,1
bdnz 1b
/* get current_thread_info and current */
lis r1,secondary_ti@ha
lwz r1,secondary_ti@l(r1)
lwz r2,TI_TASK(r1)
/* stack */
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
li r0,0
stw r0,0(r1)
/* ptr to current thread */
addi r4,r2,THREAD /* address of our thread_struct */
mtspr SPRN_SPRG_THREAD,r4
/* Setup the defaults for TLB entries */
li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS4,r4
/* Jump to start_secondary */
lis r4,MSR_KERNEL@h
ori r4,r4,MSR_KERNEL@l
lis r3,start_secondary@h
ori r3,r3,start_secondary@l
mtspr SPRN_SRR0,r3
mtspr SPRN_SRR1,r4
sync
rfi
sync
.globl __secondary_hold_acknowledge
__secondary_hold_acknowledge:
.long -1
#endif
/*
* We put a few things here that have to be page-aligned. This stuff
* goes at the beginning of the data segment, which is page-aligned.
*/
.data
.align 12
.globl sdata
sdata:
.globl empty_zero_page
empty_zero_page:
.space 4096
.globl swapper_pg_dir
swapper_pg_dir:
.space PGD_TABLE_SIZE
/*
* Room for two PTE pointers, usually the kernel and current user pointers
* to their respective root page table.
*/
abatron_pteptrs:
.space 8
| {
"language": "Assembly"
} |
;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
;* File Name : startup_stm32l475xx.s
;* Author : MCD Application Team
;* Description : STM32L475xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
; REQUIRES: object-emission
; RUN: %llc_dwarf -O0 -filetype=obj -dwarf-linkage-names=All < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
; Generate from clang with the following source. Note that the definition of
; the inline function follows its use to workaround another bug that should be
; fixed soon.
; namespace ns {
; int func(int i);
; }
; extern int x;
; int main() { return ns::func(x); }
; int __attribute__((always_inline)) ns::func(int i) { return i * 2; }
; CHECK: DW_TAG_namespace
; CHECK-NEXT: DW_AT_name {{.*}} "ns"
; CHECK-NOT: DW_TAG
; CHECK: DW_TAG_subprogram
; CHECK-NOT: DW_TAG
; CHECK: DW_AT_linkage_name {{.*}} "_ZN2ns4funcEi"
; CHECK-NOT: DW_TAG
; CHECK: DW_TAG_formal_parameter
; CHECK: NULL
; CHECK-NOT: NULL
; CHECK: DW_TAG_subprogram
; CHECK-NOT: DW_TAG
; CHECK: DW_AT_abstract_origin {{.*}} "_ZN2ns4funcEi"
; CHECK-NOT: DW_TAG
; CHECK: DW_TAG_formal_parameter
; CHECK: DW_AT_abstract_origin {{.*}} "i"
; CHECK: NULL
; CHECK: NULL
; CHECK: NULL
@x = external global i32
; Function Attrs: uwtable
define i32 @main() #0 !dbg !4 {
entry:
%i.addr.i = alloca i32, align 4
%retval = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32, i32* @x, align 4, !dbg !16
store i32 %0, i32* %i.addr.i, align 4
call void @llvm.dbg.declare(metadata i32* %i.addr.i, metadata !117, metadata !DIExpression()), !dbg !18
%1 = load i32, i32* %i.addr.i, align 4, !dbg !18
%mul.i = mul nsw i32 %1, 2, !dbg !18
ret i32 %mul.i, !dbg !16
}
; Function Attrs: alwaysinline nounwind uwtable
define i32 @_ZN2ns4funcEi(i32 %i) #1 !dbg !9 {
entry:
%i.addr = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4
call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !17, metadata !DIExpression()), !dbg !19
%0 = load i32, i32* %i.addr, align 4, !dbg !19
%mul = mul nsw i32 %0, 2, !dbg !19
ret i32 %mul, !dbg !19
}
; Function Attrs: nounwind readnone
declare void @llvm.dbg.declare(metadata, metadata, metadata) #2
attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { alwaysinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind readnone }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!13, !14}
!llvm.ident = !{!15}
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
!1 = !DIFile(filename: "namespace_inline_function_definition.cpp", directory: "/tmp/dbginfo")
!2 = !{}
!4 = distinct !DISubprogram(name: "main", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2)
!5 = !DIFile(filename: "namespace_inline_function_definition.cpp", directory: "/tmp/dbginfo")
!6 = !DISubroutineType(types: !7)
!7 = !{!8}
!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!9 = distinct !DISubprogram(name: "func", linkageName: "_ZN2ns4funcEi", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 6, file: !1, scope: !10, type: !11, variables: !2)
!10 = !DINamespace(name: "ns", scope: null)
!11 = !DISubroutineType(types: !12)
!12 = !{!8, !8}
!13 = !{i32 2, !"Dwarf Version", i32 4}
!14 = !{i32 2, !"Debug Info Version", i32 3}
!15 = !{!"clang version 3.5.0 "}
!16 = !DILocation(line: 5, scope: !4)
!17 = !DILocalVariable(name: "i", line: 6, arg: 1, scope: !9, file: !5, type: !8)
!117 = !DILocalVariable(name: "i", line: 6, arg: 1, scope: !9, file: !5, type: !8)
!18 = !DILocation(line: 6, scope: !9, inlinedAt: !16)
!19 = !DILocation(line: 6, scope: !9)
| {
"language": "Assembly"
} |
; void __CALLEE__ l_qsort_callee(void *base, unsigned int size, void *cmp)
; 01.2007 aralbrec
PUBLIC l_qsort_callee
PUBLIC _l_qsort_callee
PUBLIC ASMDISP_L_QSORT_CALLEE
EXTERN Lqsort, l_jpiy
.l_qsort_callee
._l_qsort_callee
pop de
pop iy
pop hl
pop bc
push de
.centry
ld ix,compare
jp Lqsort
.compare
push hl
push de
push bc
call l_jpiy
ld a,l
pop bc
pop de
pop hl
ret
DEFC ASMDISP_L_QSORT_CALLEE = centry - l_qsort_callee
| {
"language": "Assembly"
} |
#include "arm-macros.h"
TEST_BEGIN
mov r2, #7
mvns r1, r2
TEST_END
| {
"language": "Assembly"
} |
/*
Copyright (C) 2018-2019 de4dot@gmail.com
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if FAST_FMT
using System;
namespace Iced.Intel.FastFormatterInternal {
static class MemorySizes {
public static readonly string[] AllMemorySizes = GetMemorySizes();
enum MemoryKeywords : byte {
None,
byte_ptr,
dword_bcst,
dword_ptr,
fpuenv14_ptr,
fpuenv28_ptr,
fpustate108_ptr,
fpustate94_ptr,
fword_ptr,
oword_ptr,
qword_bcst,
qword_ptr,
tbyte_ptr,
word_ptr,
xmmword_ptr,
ymmword_ptr,
zmmword_ptr,
mem384_ptr,
}
static string[] GetMemorySizes() {
var memSizes = new string[IcedConstants.NumberOfMemorySizes];
#if HAS_SPAN
System.ReadOnlySpan<byte> data =
#else
byte[] data =
#endif
new byte[IcedConstants.NumberOfMemorySizes] {
// GENERATOR-BEGIN: MemorySizes
// ⚠️This was generated by GENERATOR!🦹♂️
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.byte_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.byte_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.fword_ptr,
(byte)MemoryKeywords.tbyte_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.oword_ptr,
(byte)MemoryKeywords.fword_ptr,
(byte)MemoryKeywords.fword_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.tbyte_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.fpuenv14_ptr,
(byte)MemoryKeywords.fpuenv28_ptr,
(byte)MemoryKeywords.fpustate94_ptr,
(byte)MemoryKeywords.fpustate108_ptr,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.tbyte_ptr,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.None,
(byte)MemoryKeywords.tbyte_ptr,
(byte)MemoryKeywords.mem384_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.word_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.dword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.qword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.xmmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.ymmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.zmmword_ptr,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.qword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
(byte)MemoryKeywords.dword_bcst,
// GENERATOR-END: MemorySizes
};
for (int i = 0; i < memSizes.Length; i++) {
var keywords = (MemoryKeywords)data[i] switch {
MemoryKeywords.None => string.Empty,
MemoryKeywords.byte_ptr => "byte ptr ",
MemoryKeywords.dword_bcst => "dword bcst ",
MemoryKeywords.dword_ptr => "dword ptr ",
MemoryKeywords.fpuenv14_ptr => "fpuenv14 ptr ",
MemoryKeywords.fpuenv28_ptr => "fpuenv28 ptr ",
MemoryKeywords.fpustate108_ptr => "fpustate108 ptr ",
MemoryKeywords.fpustate94_ptr => "fpustate94 ptr ",
MemoryKeywords.fword_ptr => "fword ptr ",
MemoryKeywords.oword_ptr => "oword ptr ",
MemoryKeywords.qword_bcst => "qword bcst ",
MemoryKeywords.qword_ptr => "qword ptr ",
MemoryKeywords.tbyte_ptr => "tbyte ptr ",
MemoryKeywords.word_ptr => "word ptr ",
MemoryKeywords.xmmword_ptr => "xmmword ptr ",
MemoryKeywords.ymmword_ptr => "ymmword ptr ",
MemoryKeywords.zmmword_ptr => "zmmword ptr ",
MemoryKeywords.mem384_ptr => "mem384 ptr ",
_ => throw new InvalidOperationException(),
};
memSizes[i] = keywords;
}
return memSizes;
}
}
}
#endif
| {
"language": "Assembly"
} |
; RUN: llc < %s -mtriple=x86_64-apple-darwin
define i64 @__ashldi3(i64 %u, i64 %b) {
entry:
br i1 false, label %UnifiedReturnBlock, label %cond_next
cond_next: ; preds = %entry
%tmp9 = sub i64 32, %b ; <i64> [#uses=2]
%tmp11 = icmp slt i64 %tmp9, 1 ; <i1> [#uses=1]
%tmp2180 = trunc i64 %u to i32 ; <i32> [#uses=2]
%tmp2223 = trunc i64 %tmp9 to i32 ; <i32> [#uses=2]
br i1 %tmp11, label %cond_true14, label %cond_false
cond_true14: ; preds = %cond_next
%tmp24 = sub i32 0, %tmp2223 ; <i32> [#uses=1]
%tmp25 = shl i32 %tmp2180, %tmp24 ; <i32> [#uses=1]
%tmp2569 = zext i32 %tmp25 to i64 ; <i64> [#uses=1]
%tmp256970 = shl i64 %tmp2569, 32 ; <i64> [#uses=1]
ret i64 %tmp256970
cond_false: ; preds = %cond_next
%tmp35 = lshr i32 %tmp2180, %tmp2223 ; <i32> [#uses=1]
%tmp54 = or i32 %tmp35, 0 ; <i32> [#uses=1]
%tmp5464 = zext i32 %tmp54 to i64 ; <i64> [#uses=1]
%tmp546465 = shl i64 %tmp5464, 32 ; <i64> [#uses=1]
%tmp546465.ins = or i64 %tmp546465, 0 ; <i64> [#uses=1]
ret i64 %tmp546465.ins
UnifiedReturnBlock:
ret i64 %u
}
| {
"language": "Assembly"
} |
/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include <stdlib.h>
#include "freertos/FreeRTOS.h"
#include "freertos/list.h"
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void ICACHE_FLASH_ATTR
vListInitialise( xList * const pxList )
{
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
pxList->uxNumberOfItems = ( unsigned portBASE_TYPE ) 0U;
}
/*-----------------------------------------------------------*/
void ICACHE_FLASH_ATTR
vListInitialiseItem( xListItem * const pxItem )
{
/* Make sure the list item is not recorded as being on a list. */
pxItem->pvContainer = NULL;
}
/*-----------------------------------------------------------*/
void
vListInsertEnd( xList * const pxList, xListItem * const pxNewListItem )
{
xListItem * pxIndex;
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
pvListGetOwnerOfNextEntry. */
pxIndex = pxList->pxIndex;
pxNewListItem->pxNext = pxIndex;
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
pxIndex->pxPrevious->pxNext = pxNewListItem;
pxIndex->pxPrevious = pxNewListItem;
/* Remember which list the item is in. */
pxNewListItem->pvContainer = ( void * ) pxList;
( pxList->uxNumberOfItems )++;
}
/*-----------------------------------------------------------*/
void ICACHE_FLASH_ATTR
vListInsert( xList * const pxList, xListItem * const pxNewListItem )
{
xListItem *pxIterator;
portTickType xValueOfInsertion;
/* Insert the new list item into the list, sorted in ulListItem order. */
xValueOfInsertion = pxNewListItem->xItemValue;
/* If the list already contains a list item with the same item value then
the new list item should be placed after it. This ensures that TCB's which
are stored in ready lists (all of which have the same ulListItem value)
get an equal share of the CPU. However, if the xItemValue is the same as
the back marker the iteration loop below will not end. This means we need
to guard against this by checking the value first and modifying the
algorithm slightly if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
{
pxIterator = pxList->xListEnd.pxPrevious;
}
else
{
/* *** NOTE ***********************************************************
If you find your application is crashing here then likely causes are:
1) Stack overflow -
see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
2) Incorrect interrupt priority assignment, especially on Cortex-M3
parts where numerically high priority values denote low actual
interrupt priories, which can seem counter intuitive. See
configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html
3) Calling an API function from within a critical section or when
the scheduler is suspended, or calling an API function that does
not end in "FromISR" from an interrupt.
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
See http://www.freertos.org/FAQHelp.html for more tips.
**********************************************************************/
for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
{
/* There is nothing to do here, we are just iterating to the
wanted insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
pxNewListItem->pxPrevious = pxIterator;
pxIterator->pxNext = pxNewListItem;
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pvContainer = ( void * ) pxList;
( pxList->uxNumberOfItems )++;
}
/*-----------------------------------------------------------*/
unsigned portBASE_TYPE
uxListRemove( xListItem * const pxItemToRemove )
{
xList * pxList;
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
/* The list item knows which list it is in. Obtain the list from the list
item. */
pxList = ( xList * ) pxItemToRemove->pvContainer;
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
}
pxItemToRemove->pvContainer = NULL;
( pxList->uxNumberOfItems )--;
return pxList->uxNumberOfItems;
}
/*-----------------------------------------------------------*/
| {
"language": "Assembly"
} |
; RUN: opt < %s -basicaa -licm -disable-output
;%MoveArray = external global [64 x ulong]
define void @InitMoveArray() {
bb3:
%X = alloca [2 x i64] ; <[2 x i64]*> [#uses=1]
br i1 false, label %bb13, label %bb4
bb4: ; preds = %bb3
%reg3011 = getelementptr [2 x i64], [2 x i64]* %X, i64 0, i64 0 ; <i64*> [#uses=1]
br label %bb8
bb8: ; preds = %bb8, %bb4
store i64 0, i64* %reg3011
br i1 false, label %bb8, label %bb13
bb13: ; preds = %bb8, %bb3
ret void
}
| {
"language": "Assembly"
} |
;
; ZX Spectrum OPUS DISCOVERY specific routines
;
; Stefano Bodrato - Jun. 2006
;
; int opus_getblocks (int drive);
;
; $Id: opus_getblocks.asm,v 1.4 2016-06-27 19:16:34 dom Exp $
;
SECTION code_clib
PUBLIC opus_getblocks
PUBLIC _opus_getblocks
EXTERN opus_rommap
EXTERN P_DEVICE
opus_getblocks:
_opus_getblocks:
push ix ;save callers
ld ix,4
add ix,sp
ld hl,-1
ld a,(ix+0) ; drive
and a ; drive no. = 0 ?
jr z,getblocks_exit ; yes, return -1
dec a
cp 5 ; drive no. >5 ?
jr nc,getblocks_exit ; yes, return -1
;call $1708 ; Page in the Discovery ROM
call opus_rommap
ld a,(ix+0) ; drive
ld bc,$0400 ; inquire disk
call P_DEVICE
call $1748 ; Page out the Discovery ROM
; HL = number of blocks
.getblocks_exit
pop ix ; restore callers
ret
| {
"language": "Assembly"
} |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; SetMem64.Asm
;
; Abstract:
;
; SetMem64 function
;
; Notes:
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; VOID *
; InternalMemSetMem64 (
; IN VOID *Buffer,
; IN UINTN Count,
; IN UINT64 Value
; )
;------------------------------------------------------------------------------
global ASM_PFX(InternalMemSetMem64)
ASM_PFX(InternalMemSetMem64):
push edi
mov ecx, [esp + 12]
mov eax, [esp + 16]
mov edx, [esp + 20]
mov edi, [esp + 8]
.0:
mov [edi + ecx*8 - 8], eax
mov [edi + ecx*8 - 4], edx
loop .0
mov eax, edi
pop edi
ret
| {
"language": "Assembly"
} |
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f446xx.s
;* Author : MCD Application Team
;* Description : STM32F446xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SAI1_IRQHandler ; SAI1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QuadSPI
DCD CEC_IRQHandler ; CEC
DCD SPDIF_RX_IRQHandler ; SPDIF RX
DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK FMPI2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FMPI2C1_EV_IRQHandler
B FMPI2C1_EV_IRQHandler
PUBWEAK FMPI2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FMPI2C1_ER_IRQHandler
B FMPI2C1_ER_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
#------------------------------------------------------------------------------
# $File: plus5,v 1.6 2009/09/19 16:28:11 christos Exp $
# plus5: file(1) magic for Plus Five's UNIX MUMPS
#
# XXX - byte order? Paging Hokey....
#
0 short 0x259 mumps avl global
>2 byte >0 (V%d)
>6 byte >0 with %d byte name
>7 byte >0 and %d byte data cells
0 short 0x25a mumps blt global
>2 byte >0 (V%d)
>8 short >0 - %d byte blocks
>15 byte 0x00 - P/D format
>15 byte 0x01 - P/K/D format
>15 byte 0x02 - K/D format
>15 byte >0x02 - Bad Flags
| {
"language": "Assembly"
} |
/* Measure bcopy functions.
Copyright (C) 2013-2018 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#define TEST_BCOPY
#include "bench-memmove.c"
| {
"language": "Assembly"
} |
;--------------------------------------------------------------------------
; divsigned.s
;
; Copyright (C) 2000-2010, Michael Hope, Philipp Klaus Krause
;
; This library is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published by the
; Free Software Foundation; either version 2, or (at your option) any
; later version.
;
; This library is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this library; see the file COPYING. If not, write to the
; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
; MA 02110-1301, USA.
;
; As a special exception, if you link this library with other files,
; some of which are compiled with SDCC, to produce an executable,
; this library does not by itself cause the resulting executable to
; be covered by the GNU General Public License. This exception does
; not however invalidate any other reasons why the executable file
; might be covered by the GNU General Public License.
;--------------------------------------------------------------------------
.area _CODE
.globl __divsint
.globl __divschar
__divsint:
pop af
pop hl
pop de
push de
push hl
push af
jp __div16
__divschar:
ld hl, #2+1
add hl, sp
ld e, (hl)
dec hl
ld l, (hl)
__div8::
ld a, l ; Sign extend
rlca
sbc a,a
ld h, a
__div_signexte::
ld a, e ; Sign extend
rlca
sbc a,a
ld d, a
; Fall through to __div16
;; signed 16-bit division
;;
;; Entry conditions
;; HL = dividend
;; DE = divisor
;;
;; Exit conditions
;; HL = quotient
;; DE = remainder
;;
;; Register used: AF,B,DE,HL
__div16::
;; Determine sign of quotient by xor-ing high bytes of dividend
;; and divisor. Quotient is positive if signs are the same, negative
;; if signs are different
;; Remainder has same sign as dividend
ld a, h ; Get high byte of dividend
xor a, d ; Xor with high byte of divisor
rla ; Sign of quotient goes into the carry
ld a, h ; Get high byte of dividend
push af ; Save sign of both quotient and reminder
; Take absolute value of dividend
rla
jr NC, .chkde ; Jump if dividend is positive
sub a, a ; Substract dividend from 0
sub a, l
ld l, a
sbc a, a ; Propagate borrow (A=0xFF if borrow)
sub a, h
ld h, a
; Take absolute value of divisor
.chkde:
bit 7, d
jr Z, .dodiv ; Jump if divisor is positive
sub a, a ; Subtract divisor from 0
sub a, e
ld e, a
sbc a, a ; Propagate borrow (A=0xFF if borrow)
sub a, d
ld d, a
; Divide absolute values
.dodiv:
call __divu16
.fix_quotient:
; Negate quotient if it is negative
pop af ; recover sign of quotient
ret NC ; Jump if quotient is positive
ld b, a
sub a, a ; Subtract quotient from 0
sub a, l
ld l, a
sbc a, a ; Propagate borrow (A=0xFF if borrow)
sub a, h
ld h, a
ld a, b
ret
__get_remainder::
; Negate remainder if it is negative and move it into hl
rla
ex de, hl
ret NC ; Return if remainder is positive
sub a, a ; Subtract remainder from 0
sub a, l
ld l, a
sbc a, a ; Propagate remainder (A=0xFF if borrow)
sub a, h
ld h, a
ret
| {
"language": "Assembly"
} |
;---------------------------------------
;
; animation cel data
;
bizzaro0_data::
byte swing + 2
byte 0b00000000
byte bizzaro0_start_end - bizzaro0_data
byte no_cont
byte 244+right,28+left,255
byte 0b10000000
byte 0b01000000
byte 0b01100000
word bizzaro0_data_a - bizzaro0_data
word bizzaro0_data_b - bizzaro0_data
word bizzaro0_data_c - bizzaro0_data
bizzaro0_start_end:
byte 0,0,1,1,0,0,2,2
bizzaro0_data_a:
byte 0x07, 0x13, 0xfe, 0xfd, 0x00, 0x00
byte run,0x80+15
byte run,4,1
byte run,0x80+11
byte 1
byte 5
byte 21
byte run,5,85
byte run,0x80+7
byte 1
byte 5
byte 21
byte run,9,85
byte run,0x80+1
byte 31
byte 21
byte 31
byte 31
byte 95
byte run,3,85
byte 127
byte run,3,255
byte 253
byte run,5,85
byte 40
byte 184
byte 248
byte 248
byte 232
byte 232
byte 254
byte 255
byte 250
byte 239
byte 239
byte 255
byte 255
byte run,3,95
byte run,3,85
byte run,0x80+7
byte 128
byte 170
byte 255
byte 255
byte run,4,251
byte 255
byte run,3,85
byte run,0x80+8
byte 168
byte 248
byte 224
byte 128
byte 224
byte 248
byte 253
byte 253
byte run,3,85
bizzaro0_data_b:
byte 0x07, 0x13, 0xfd, 0xfd, 0x00, 0x00
byte run,0x80+9
byte 2
byte run,3,11
byte 1
byte run,5,5
byte run,0x80+8
byte 168
byte 254
byte 251
byte 239
byte 127
byte run,3,95
byte run,3,85
byte run,0x80+1
byte run,5,2
byte 11
byte 47
byte 190
byte 251
byte run,6,255
byte run,3,85
byte run,3,255
byte 170
byte 170
byte 255
byte 255
byte 175
byte 170
byte 255
byte 255
byte run,4,190
byte 255
byte run,3,85
byte run,0x80+1
byte run,5,128
byte 224
byte 248
byte 190
byte 239
byte run,6,255
byte run,3,85
byte run,0x80+8
byte 42
byte 191
byte 239
byte 251
byte 254
byte 255
byte 253
byte 253
byte run,3,85
byte run,0x80+9
byte 128
byte run,3,224
byte 64
byte run,5,80
bizzaro0_data_c:
byte 0x05, 0x09, 0xfe, 0xfa, 0x00, 0x00
byte run,0x80+3
byte 1
byte 5
byte run,4,85
byte run,0x80+1
byte 63
byte run,7,85
byte 252
byte 255
byte run,7,85
byte run,0x80+1
byte 240
byte run,7,85
byte run,0x80+3
byte 64
byte 80
byte 84
byte run,3,85
| {
"language": "Assembly"
} |
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 15. July 2011
* $Revision: V1.0.10
*
* Project: CMSIS DSP Library
* Title: arm_sin_cos_q31.c
*
* Description: Cosine & Sine calculation for Q31 values.
*
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
*
* Version 1.0.10 2011/7/15
* Big Endian support added and Merged M0 and M3/M4 Source code.
*
* Version 1.0.3 2010/11/29
* Re-organized the CMSIS folders and updated documentation.
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#include "arm_math.h"
/**
* @ingroup groupController
*/
/**
* @addtogroup SinCos
* @{
*/
/**
* \par
* Sine Table is generated from following loop
* <pre>for(i = 0; i < 360; i++)
* {
* sinTable[i]= sin((i-180) * PI/180.0);
* } </pre>
* Convert above coefficients to fixed point 1.31 format.
*/
static const int32_t sinTableQ31[360] = {
0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
0xf06695da,
0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
0xe108b40d, 0xdedf047d,
0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
0xd00ce422, 0xcdfc85bb,
0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
0xc0000000, 0xbe133b7c,
0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
0xb1320139, 0xaf726def,
0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
0xa3ecac65, 0xa263007d,
0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
0x98722192, 0x9726069c,
0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
0x8efb92c2, 0x8df37f8b,
0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
0x87b826f7, 0x86f93f50,
0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
0x82cc0f36, 0x825a0a5b,
0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
0x804fd23a, 0x802ce84c,
0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
0x804fd23a, 0x807cb130,
0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
0x82cc0f36, 0x8347d77b,
0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
0x87b826f7, 0x88806fc4,
0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
0x8efb92c2, 0x900c7621,
0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
0x98722192, 0x99c64fc5,
0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
0xa3ecac65, 0xa57d8666,
0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
0xb1320139, 0xb2f7b9af,
0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
0xc0000000, 0xc1f1c224,
0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
0xd00ce422, 0xd220ffc0,
0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
0xe108b40d, 0xe334cdc9,
0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
0xf29ecfb2, 0xf4d814a4,
0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
0x6b2f1d2,
0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
0x163a1a7e, 0x186c6ddd,
0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
0x278dde6e, 0x29ac37a0,
0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
0x381c8bb5, 0x3a1c5c57,
0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
0x4793a210, 0x496af3e2,
0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
0x55a6125c, 0x574bb8e6,
0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
0x620dbe8b, 0x637984d4,
0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
0x6c8cd70b, 0x6db7a87a,
0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
0x74ef0ebc, 0x75d31a61,
0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
0x7b0a9f8d, 0x7ba3751d,
0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
0x7ec11aa5, 0x7f0bc097,
0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
0x7fffffff, 0x7ffb0260,
0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
0x7ec11aa5, 0x7e6c9251,
0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
0x7b0a9f8d, 0x7a6831ba,
0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
0x74ef0ebc, 0x7401e4c1,
0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
0x6c8cd70b, 0x6b598ea3,
0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
0x620dbe8b, 0x609a52d3,
0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
0x55a6125c, 0x53f9be05,
0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
0x4793a210, 0x45b6bb5e,
0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
0x381c8bb5, 0x36185aee,
0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
0x278dde6e, 0x256c6f9f,
0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
0x163a1a7e, 0x14060b68,
0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
0x4779632, 0x23be165,
};
/**
* \par
* Cosine Table is generated from following loop
* <pre>for(i = 0; i < 360; i++)
* {
* cosTable[i]= cos((i-180) * PI/180.0);
* } </pre>
* \par
* Convert above coefficients to fixed point 1.31 format.
*/
static const int32_t cosTableQ31[360] = {
0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
0x80b381ac, 0x80f43f69,
0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
0x83cd5982, 0x845c8ae3,
0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
0x89520a1a, 0x8a2ce59f,
0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
0x9126145f, 0x92485786,
0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
0x9b2276b0, 0x9c867b2c,
0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
0xa7156f3c, 0xa8b4471a,
0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
0xb4c373ee, 0xb6950c1e,
0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
0xc3e85b18, 0xc5e3a3a9,
0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
0xd438af17, 0xd653c860,
0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
0xe5632654, 0xe7939223,
0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
0xf7123849, 0xf94d0e2e,
0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
0xb27eb5c,
0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
0x1a9cd9ac, 0x1ccb3237,
0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
0x2bc750e9, 0x2ddf0040,
0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
0x3c17a4e8, 0x3e0e3ddc,
0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
0x4b3c8c12, 0x4d084651,
0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
0x58ea90c4, 0x5a82799a,
0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
0x64dd8950, 0x6639b03b,
0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
0x6ed9eba1, 0x6ff389df,
0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
0x76adf5e6, 0x777f903c,
0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
0x7c32a67e, 0x7cb82885,
0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
0x7f4c7e54, 0x7f834ed0,
0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
0x7fec09e3, 0x7fd317b4,
0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
0x7e0e2e32, 0x7da5f5a5,
0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
0x79bc384d, 0x7906c0b0,
0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
0x730baeed, 0x720c8075,
0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
0x6a1de737, 0x68d9f964,
0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
0x5f1f5ea1, 0x5d9cff83,
0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
0x5246dd49, 0x508d9211,
0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
0x43d464fb, 0x41ecc484,
0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
0x340ff242, 0x32037a45,
0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
0x234815ba, 0x2120fb83,
0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
0x11d06c97, 0xf996a26,
0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
0xfdc41e9b,
0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
0xee2f9369, 0xebf9f498,
0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
0xdcb7ea46, 0xda939061,
0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
0xcbf00dbe, 0xc9e7a512,
0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
0xbc2b9b05, 0xba4944a2,
0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
0xadb922b7, 0xac0641fb,
0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
0xa0e0a15f, 0x9f65ad2d,
0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
0x95e218c9, 0x94a6715d,
0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
0x8cf45113, 0x8bfe1b3f,
0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
0x8643c7b3, 0x8597ce46,
0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
0x81f1d1ce, 0x81936daf,
0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
0x8013f61d, 0x8004fda0,
};
/**
* @brief Q31 sin_cos function.
* @param[in] theta scaled input value in degrees
* @param[out] *pSinVal points to the processed sine output.
* @param[out] *pCosVal points to the processed cosine output.
* @return none.
*
* The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180).
*
*/
void arm_sin_cos_q31(
q31_t theta,
q31_t * pSinVal,
q31_t * pCosVal)
{
q31_t x0; /* Nearest input value */
q31_t y0, y1; /* Nearest output values */
q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
uint32_t i; /* Index */
q31_t oneByXSpacing; /* 1/ xSpacing value */
q31_t out; /* temporary variable */
uint32_t sign_bits; /* No.of sign bits */
uint32_t firstX = 0x80000000; /* First X value */
/* Calculation of index */
i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
/* Calculation of first nearest input value */
x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
/* Reading nearest sine output values from table */
y0 = sinTableQ31[i];
y1 = sinTableQ31[i + 1u];
/* Calculation of 1/(x1-x0) */
/* (x1-x0) is xSpacing which is fixed value */
sign_bits = 8u;
oneByXSpacing = 0x5A000000;
/* Calculation of (theta - x0)/(x1-x0) */
out =
(((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
/* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
*pSinVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
/* Reading nearest cosine output values from table */
y0 = cosTableQ31[i];
y1 = cosTableQ31[i + 1u];
/* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
*pCosVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
}
/**
* @} end of SinCos group
*/
| {
"language": "Assembly"
} |
; RUN: llvm-mc -filetype=obj -triple=avr %s -mattr=avr6 | llvm-objdump -r - | FileCheck %s
; CHECK: RELOCATION RECORDS FOR
.global bar
bar:
jmp bar
; CHECK: R_AVR_LDI SYMBOL+3
ldi r21, SYMBOL+3
; CHECK-NEXT: R_AVR_6_ADIW FOO
adiw r24, FOO
; CHECK-NEXT: R_AVR_16 BAR+2
lds r8, BAR+2
; CHECK-NEXT: R_AVR_PORT5 foo
sbic foo, 1
; CHECK-NEXT: R_AVR_PORT6 Bar+2
in r30, Bar+2
; CHECK-NEXT: R_AVR_CALL foo+3
call foo+3
; CHECK-NEXT: R_AVR_13_PCREL foo-10
rjmp foo-10
; CHECK-NEXT: R_AVR_7_PCREL foo+2
brcs foo+2
; CHECK-NEXT: R_AVR_LO8_LDI bar+3
; CHECK-NEXT: R_AVR_LO8_LDI abc
; CHECK-NEXT: R_AVR_LO8_LDI abc
ldi r24, lo8(bar+3)
ldi r16, +lo8(abc)
ldi r16, lo8(+(abc))
; CHECK-NEXT: R_AVR_HI8_LDI abc
; CHECK-NEXT: R_AVR_HI8_LDI abc
; CHECK-NEXT: R_AVR_HI8_LDI abc
ldi r30, hi8(abc)
ldi r16, +hi8(abc)
ldi r16, hi8(+(abc))
; CHECK-NEXT: R_AVR_LO8_LDI_NEG abc
; CHECK-NEXT: R_AVR_LO8_LDI_NEG abc
ldi r16, -lo8(abc)
ldi r16, lo8(-(abc))
; CHECK-NEXT: R_AVR_HI8_LDI_NEG abc
; CHECK-NEXT: R_AVR_HI8_LDI_NEG abc
ldi r16, -hi8(abc)
ldi r16, hi8(-(abc))
; CHECK-NEXT: R_AVR_HH8_LDI foo
; CHECK-NEXT: R_AVR_HH8_LDI foo
; CHECK-NEXT: R_AVR_HH8_LDI foo
ldi r16, hh8(foo)
ldi r16, +hh8(foo)
ldi r16, hh8(+(foo))
; CHECK-NEXT: R_AVR_HH8_LDI_NEG foo
; CHECK-NEXT: R_AVR_HH8_LDI_NEG foo
ldi r16, -hh8(foo)
ldi r16, hh8(-(foo))
; CHECK-NEXT: R_AVR_HH8_LDI foo
; CHECK-NEXT: R_AVR_HH8_LDI foo
; CHECK-NEXT: R_AVR_HH8_LDI foo
ldi r24, hlo8(foo)
ldi r24, +hlo8(foo)
ldi r24, hlo8(+(foo))
; CHECK-NEXT: R_AVR_HH8_LDI_NEG foo
; CHECK-NEXT: R_AVR_HH8_LDI_NEG foo
ldi r24, -hlo8(foo)
ldi r24, hlo8(-(foo))
; CHECK-NEXT: R_AVR_MS8_LDI bar
; CHECK-NEXT: R_AVR_MS8_LDI bar
; CHECK-NEXT: R_AVR_MS8_LDI bar
ldi r24, hhi8(bar)
ldi r24, +hhi8(bar)
ldi r24, hhi8(+(bar))
; CHECK-NEXT: R_AVR_MS8_LDI_NEG bar
; CHECK-NEXT: R_AVR_MS8_LDI_NEG bar
ldi r24, -hhi8(bar)
ldi r24, hhi8(-(bar))
; CHECK-NEXT: R_AVR_LO8_LDI_PM foo
; CHECK-NEXT: R_AVR_LO8_LDI_PM foo
; CHECK-NEXT: R_AVR_LO8_LDI_PM foo
ldi r17, pm_lo8(foo)
ldi r25, +pm_lo8(foo)
ldi r25, pm_lo8(+(foo))
; CHECK-NEXT: R_AVR_HI8_LDI_PM bar
; CHECK-NEXT: R_AVR_HI8_LDI_PM foo
; CHECK-NEXT: R_AVR_HI8_LDI_PM foo
ldi r22, pm_hi8(bar)
ldi r25, +pm_hi8(foo)
ldi r25, pm_hi8(+(foo))
; CHECK-NEXT: R_AVR_HH8_LDI_PM baz
; CHECK-NEXT: R_AVR_HH8_LDI_PM foo
; CHECK-NEXT: R_AVR_HH8_LDI_PM foo
ldi r25, pm_hh8(baz)
ldi r25, +pm_hh8(foo)
ldi r25, pm_hh8(+(foo))
; CHECK-NEXT: R_AVR_LO8_LDI_PM_NEG foo
; CHECK-NEXT: R_AVR_LO8_LDI_PM_NEG foo
ldi r25, -pm_lo8(foo)
ldi r25, pm_lo8(-(foo))
; CHECK-NEXT: R_AVR_HI8_LDI_PM_NEG foo
; CHECK-NEXT: R_AVR_HI8_LDI_PM_NEG foo
ldi r25, -pm_hi8(foo)
ldi r25, pm_hi8(-(foo))
; CHECK-NEXT: R_AVR_HH8_LDI_PM_NEG foo
; CHECK-NEXT: R_AVR_HH8_LDI_PM_NEG foo
ldi r25, -pm_hh8(foo)
ldi r25, pm_hh8(-(foo))
; CHECK-NEXT: R_AVR_LO8_LDI_GS foo
ldi r17, lo8(gs(foo))
; CHECK-NEXT: R_AVR_HI8_LDI_GS foo
ldi r18, hi8(gs(foo))
; CHECK-NEXT: R_AVR_16
.short foo
; CHECK-NEXT: R_AVR_16_PM
.short gs(foo)
; CHECK-NEXT: R_AVR_8
.byte foo
; CHECK-NEXT: R_AVR_8_LO8
.byte lo8(foo)
; CHECK-NEXT: R_AVR_8_HI8
.byte hi8(foo)
; CHECK-NEXT: R_AVR_8_HLO8
.byte hlo8(foo)
; CHECK: R_AVR_DIFF8
.byte foo - bar
; CHECK: R_AVR_DIFF16
.short foo - bar
; CHECK: R_AVR_DIFF32
.long foo - bar
| {
"language": "Assembly"
} |
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# ScanMem32.S
#
# Abstract:
#
# ScanMem32 function
#
# Notes:
#
# The following BaseMemoryLib instances contain the same copy of this file:
#
# BaseMemoryLibRepStr
# BaseMemoryLibMmx
# BaseMemoryLibSse2
# BaseMemoryLibOptDxe
# BaseMemoryLibOptPei
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalMemScanMem32)
#------------------------------------------------------------------------------
# CONST VOID *
# EFIAPI
# InternalMemScanMem32 (
# IN CONST VOID *Buffer,
# IN UINTN Length,
# IN UINT32 Value
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMemScanMem32):
push %edi
movl 12(%esp), %ecx
movl 8(%esp), %edi
movl 16(%esp), %eax
repne scasl
leal -4(%edi), %eax
cmovnz %ecx, %eax
pop %edi
ret
| {
"language": "Assembly"
} |
void foo();
// RUN: c-index-test -index-file -working-directory=%S %s | FileCheck %s
// CHECK: [indexDeclaration]: kind: function | name: foo
| {
"language": "Assembly"
} |
// RUN: %dafny /compile:0 "%s" > "%t"
// RUN: %diff "%s.expect" "%t"
datatype Ballot = Ballot(seqno:int)
predicate BalLt(ba:Ballot, bb:Ballot)
{
ba.seqno < bb.seqno
}
lemma Cases()
{
var b1:Ballot;
var b2:Ballot;
if (b1 == b2) {
} else if (BalLt(b1,b2)) {
} else {
//assert b1.seqno == b1.seqno;
//assert b2.seqno == b2.seqno;
assert BalLt(b2, b1); // Fails without asserts above
}
} | {
"language": "Assembly"
} |
README - DOOM assembly code
Okay, I add the DOS assembly module for the historically
inclined here (may rec.games.programmer suffer). If anyone
feels the urge to port these to GNU GCC; either inline or
as separate modules including Makefile support, be my guest.
Module tmap.S includes the inner loops for texture mapping,
the interesting one being the floor/ceiling span rendering.
There was another module in the source dump, fpfunc.S, that
had both texture mapping and fixed point functions. It
contained implementations both for i386 and M68k. For
brevity, I include only the i386 fixed point stuff below.
//====================================================
// tmap.S as of January 10th, 1997
//================
//
// R_DrawColumn
//
//================
.data
loopcount .long 0
pixelcount .long 0
.text
.align 16
.globl _R_DrawColumn
_R_DrawColumn:
pushad
movl ebp,[_dc_yl]
movl ebx,ebp
movl edi,[_ylookup+ebx*4]
movl ebx,[_dc_x]
addl edi,[_columnofs + ebx*4]
movl eax,[_dc_yh]
incl eax
subl eax,ebp // pixel count
movl [pixelcount],eax // save for final pixel
js done // nothing to scale
shrl eax,1 // double pixel count
movl [loopcount],eax
movl ecx,[_dc_iscale]
movl eax,[_centery]
subl eax,ebp
imull ecx
movl ebp,[_dc_texturemid]
subl ebp,eax
shll ebp,9 // 7 significant bits, 25 frac
movl esi,[_dc_source]
movl ebx,[_dc_iscale]
shll ebx,9
movl eax,OFFSET patch1+2 // convice tasm to modify code...
movl [eax],ebx
movl eax,OFFSET patch2+2 // convice tasm to modify code...
movl [eax],ebx
// eax aligned colormap
// ebx aligned colormap
// ecx,edx scratch
// esi virtual source
// edi moving destination pointer
// ebp frac
movl ecx,ebp // begin calculating first pixel
addl ebp,ebx // advance frac pointer
shrl ecx,25 // finish calculation for first pixel
movl edx,ebp // begin calculating second pixel
addl ebp,ebx // advance frac pointer
shrl edx,25 // finish calculation for second pixel
movl eax,[_dc_colormap]
movl ebx,eax
movb al,[esi+ecx] // get first pixel
movb bl,[esi+edx] // get second pixel
movb al,[eax] // color translate first pixel
movb bl,[ebx] // color translate second pixel
testl [pixelcount],0fffffffeh
jnz doubleloop // at least two pixels to map
jmp checklast
.align 16
doubleloop:
movl ecx,ebp // begin calculating third pixel
patch1:
addl ebp,12345678h // advance frac pointer
movb [edi],al // write first pixel
shrl ecx,25 // finish calculation for third pixel
movl edx,ebp // begin calculating fourth pixel
patch2:
addl ebp,12345678h // advance frac pointer
movl [edi+SCREENWIDTH],bl // write second pixel
shrl edx,25 // finish calculation for fourth pixel
movb al,[esi+ecx] // get third pixel
addl edi,SCREENWIDTH*2 // advance to third pixel destination
movb bl,[esi+edx] // get fourth pixel
decl [loopcount] // done with loop?
movb al,[eax] // color translate third pixel
movb bl,[ebx] // color translate fourth pixel
jnz doubleloop
// check for final pixel
checklast:
testl [pixelcount],1
jz done
movb [edi],al // write final pixel
done:
popad
ret
//================
//
// R_DrawSpan
//
// Horizontal texture mapping
//
//================
.align 16
.globl _R_DrawSpan
_R_DrawSpan:
pushad
//
// find loop count
//
movl eax,[_ds_x2]
incl eax
subl eax,[_ds_x1] // pixel count
movl [pixelcount],eax // save for final pixel
js hdone // nothing to scale
shrl eax,1 // double pixel count
movl [loopcount],eax
//
// build composite position
//
movl ebp,[_ds_xfrac]
shll ebp,10
andl ebp,0ffff0000h
movl eax,[_ds_yfrac]
shrl eax,6
andl eax,0ffffh
orl ebp,eax
movl esi,[_ds_source]
//
// calculate screen dest
//
movl edi,[_ds_y]
movl edi,[_ylookup+edi*4]
movl eax,[_ds_x1]
addl edi,[_columnofs+eax*4]
//
// build composite step
//
movl ebx,[_ds_xstep]
shll ebx,10
andl ebx,0ffff0000h
movl eax,[_ds_ystep]
shrl eax,6
andl eax,0ffffh
orl ebx,eax
movl eax,OFFSET hpatch1+2 // convice tasm to modify code...
movl [eax],ebx
movl eax,OFFSET hpatch2+2 // convice tasm to modify code...
movl [eax],ebx
// eax aligned colormap
// ebx aligned colormap
// ecx,edx scratch
// esi virtual source
// edi moving destination pointer
// ebp frac
shldl ecx,ebp,22 // begin calculating third pixel (y units)
shldl ecx,ebp,6 // begin calculating third pixel (x units)
addl ebp,ebx // advance frac pointer
andl ecx,4095 // finish calculation for third pixel
shldl edx,ebp,22 // begin calculating fourth pixel (y units)
shldl edx,ebp,6 // begin calculating fourth pixel (x units)
addl ebp,ebx // advance frac pointer
andl edx,4095 // finish calculation for fourth pixel
movl eax,[_ds_colormap]
movl ebx,eax
movb al,[esi+ecx] // get first pixel
movb bl,[esi+edx] // get second pixel
movb al,[eax] // color translate first pixel
movb bl,[ebx] // color translate second pixel
testl [pixelcount],0fffffffeh
jnz hdoubleloop // at least two pixels to map
jmp hchecklast
.align 16
hdoubleloop:
shldl ecx,ebp,22 // begin calculating third pixel (y units)
shldl ecx,ebp,6 // begin calculating third pixel (x units)
hpatch1:
addl ebp,12345678h // advance frac pointer
movb [edi],al // write first pixel
andl ecx,4095 // finish calculation for third pixel
shldl edx,ebp,22 // begin calculating fourth pixel (y units)
shldl edx,ebp,6 // begin calculating fourth pixel (x units)
hpatch2:
addl ebp,12345678h // advance frac pointer
movb [edi+1],bl // write second pixel
andl edx,4095 // finish calculation for fourth pixel
movb al,[esi+ecx] // get third pixel
addl edi,2 // advance to third pixel destination
movb bl,[esi+edx] // get fourth pixel
decl [loopcount] // done with loop?
movb al,[eax] // color translate third pixel
movb bl,[ebx] // color translate fourth pixel
jnz hdoubleloop
// check for final pixel
hchecklast:
testl [pixelcount],1
jz hdone
movb [edi],al // write final pixel
hdone:
popad
ret
//====================================================
// fpfunc.S as of January 10th, 1997 (parts)
#ifdef i386
.text
.align 4
.globl _FixedMul
_FixedMul:
pushl %ebp
movl %esp,%ebp
movl 8(%ebp),%eax
imull 12(%ebp)
shrdl $16,%edx,%eax
popl %ebp
ret
.align 4
.globl _FixedDiv2
_FixedDiv2:
pushl %ebp
movl %esp,%ebp
movl 8(%ebp),%eax
cdq
shldl $16,%eax,%edx
sall $16,%eax
idivl 12(%ebp)
popl %ebp
ret
#endif
| {
"language": "Assembly"
} |
.TH ACPIDUMP 8
.SH NAME
acpidump \- dump a system's ACPI tables to an ASCII file
.SH SYNOPSIS
.B acpidump
.RI [ options ]
.br
.SH DESCRIPTION
.B acpidump
dumps the systems ACPI tables to an ASCII file appropriate for
attaching to a bug report.
Subsequently, they can be processed by utilities in the ACPICA package.
.SH OPTIONS
acpidump options are as follow:
.TP
.B Options
.TP
.B \-b
Dump tables to binary files
.TP
.B \-h \-?
This help message
.TP
.B \-o <File>
Redirect output to file
.TP
.B \-r <Address>
Dump tables from specified RSDP
.TP
.B \-s
Print table summaries only
.TP
.B \-v
Display version information
.TP
.B \-z
Verbose mode
.TP
.B Table Options
.TP
.B \-a <Address>
Get table via a physical address
.TP
.B \-c <on|off>
Turning on/off customized table dumping
.TP
.B \-f <BinaryFile>
Get table via a binary file
.TP
.B \-n <Signature>
Get table via a name/signature
.TP
.B \-x
Do not use but dump XSDT
.TP
.B \-x \-x
Do not use or dump XSDT
.TP
.fi
Invocation without parameters dumps all available tables.
.TP
Multiple mixed instances of -a, -f, and -n are supported.
.SH EXAMPLES
.nf
# acpidump > acpidump.out
$ acpixtract -a acpidump.out
Acpi table [DSDT] - 15974 bytes written to DSDT.dat
Acpi table [FACS] - 64 bytes written to FACS.dat
Acpi table [FACP] - 116 bytes written to FACP.dat
Acpi table [APIC] - 120 bytes written to APIC.dat
Acpi table [MCFG] - 60 bytes written to MCFG.dat
Acpi table [SSDT] - 444 bytes written to SSDT1.dat
Acpi table [SSDT] - 439 bytes written to SSDT2.dat
Acpi table [SSDT] - 439 bytes written to SSDT3.dat
Acpi table [SSDT] - 439 bytes written to SSDT4.dat
Acpi table [SSDT] - 439 bytes written to SSDT5.dat
Acpi table [RSDT] - 76 bytes written to RSDT.dat
Acpi table [RSDP] - 20 bytes written to RSDP.dat
$ iasl -d *.dat
...
.fi
creates *.dsl, a human readable form which can be edited
and compiled using iasl.
.SH NOTES
.B "acpidump "
must be run as root.
.SH REFERENCES
ACPICA: https://acpica.org/
.SH FILES
.ta
.nf
/dev/mem
/sys/firmware/acpi/tables/*
/sys/firmware/acpi/tables/dynamic/*
/sys/firmware/efi/systab
.fi
.SH AUTHOR
.TP
Original by:
Len Brown <len.brown@intel.com>
.TP
Written by:
Chao Guan <chao.guan@intel.com>
.TP
Updated by:
Bob Moore <robert.moore@intel.com>
Lv Zheng <lv.zheng@intel.com>
.SH SEE ALSO
\&\fIacpixtract\fR\|(8), \fIiasl\fR\|(8).
.SH COPYRIGHT
COPYRIGHT (c) 2013, Intel Corporation.
| {
"language": "Assembly"
} |
; MollenOS
; Copyright 2011-2016, Philip Meulengracht
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation?, either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
;
; MollenOS x86-32 Math LOG
bits 32
segment .text
;Functions in this asm
global _log
global _logf
global _logl
global __CIlog
; takes the logorithmic value in base 2
_log:
; Stack Frame
push ebp
mov ebp, esp
; Load log base e of 2
fldln2
; Load real from stack
fld qword [ebp + 8]
; Compute the natural log(x)
fyl2x
; Unwind & return
pop ebp
ret
; takes the logorithmic value in base 2 float
_logf:
; Stack Frame
push ebp
mov ebp, esp
; Load log base e of 2
fldln2
; Load real from stack
fld dword [ebp + 8]
; Compute the natural log(x)
fyl2x
; Unwind & return
pop ebp
ret
; takes the logorithmic value in base 2 float
_logl:
; Stack Frame
push ebp
mov ebp, esp
; Load log base e of 2
fldln2
; Load real from stack
fld tword [ebp + 8]
; Compute the natural log(x)
fyl2x
; Unwind & return
pop ebp
ret
; Msvc version of log
__CIlog:
fldln2
fxch
fyl2x
; Done
ret | {
"language": "Assembly"
} |
; RUN: llvm-undname < %s | FileCheck %s
; RUN: llvm-undname --no-calling-convention < %s | FileCheck %s --check-prefix=CHECK-NO-CALLING-CONV
; RUN: llvm-undname --no-return-type < %s | FileCheck %s --check-prefix=CHECK-NO-RETURN
; RUN: llvm-undname --no-access-specifier < %s | FileCheck %s --check-prefix=CHECK-NO-ACCESS
; RUN: llvm-undname --no-member-type < %s | FileCheck %s --check-prefix=CHECK-NO-MEMBER-TYPE
; RUN: llvm-undname --no-calling-convention --no-return-type --no-access-specifier --no-member-type < %s | FileCheck %s --check-prefix=CHECK-NO-ALL
?func@MyClass@@UEAAHHH@Z
; CHECK: public: virtual int __cdecl MyClass::func(int, int)
; CHECK-NO-CALLING-CONV: public: virtual int MyClass::func(int, int)
; CHECK-NO-RETURN: public: virtual __cdecl MyClass::func(int, int)
; CHECK-NO-ACCESS: {{^}}virtual int __cdecl MyClass::func(int, int)
; CHECK-NO-MEMBER-TYPE: public: int __cdecl MyClass::func(int, int)
; CHECK-NO-ALL: {{^}}MyClass::func(int, int)
| {
"language": "Assembly"
} |
.file "../openssl/crypto/ripemd/asm/rmd-586.s"
.text
.globl _ripemd160_block_asm_data_order
.align 4
_ripemd160_block_asm_data_order:
L_ripemd160_block_asm_data_order_begin:
movl 4(%esp),%edx
movl 8(%esp),%eax
pushl %esi
movl (%edx),%ecx
pushl %edi
movl 4(%edx),%esi
pushl %ebp
movl 8(%edx),%edi
pushl %ebx
subl $108,%esp
L000start:
movl (%eax),%ebx
movl 4(%eax),%ebp
movl %ebx,(%esp)
movl %ebp,4(%esp)
movl 8(%eax),%ebx
movl 12(%eax),%ebp
movl %ebx,8(%esp)
movl %ebp,12(%esp)
movl 16(%eax),%ebx
movl 20(%eax),%ebp
movl %ebx,16(%esp)
movl %ebp,20(%esp)
movl 24(%eax),%ebx
movl 28(%eax),%ebp
movl %ebx,24(%esp)
movl %ebp,28(%esp)
movl 32(%eax),%ebx
movl 36(%eax),%ebp
movl %ebx,32(%esp)
movl %ebp,36(%esp)
movl 40(%eax),%ebx
movl 44(%eax),%ebp
movl %ebx,40(%esp)
movl %ebp,44(%esp)
movl 48(%eax),%ebx
movl 52(%eax),%ebp
movl %ebx,48(%esp)
movl %ebp,52(%esp)
movl 56(%eax),%ebx
movl 60(%eax),%ebp
movl %ebx,56(%esp)
movl %ebp,60(%esp)
movl %edi,%eax
movl 12(%edx),%ebx
movl 16(%edx),%ebp
# 0
xorl %ebx,%eax
movl (%esp),%edx
xorl %esi,%eax
addl %edx,%ecx
roll $10,%edi
addl %eax,%ecx
movl %esi,%eax
roll $11,%ecx
addl %ebp,%ecx
# 1
xorl %edi,%eax
movl 4(%esp),%edx
xorl %ecx,%eax
addl %eax,%ebp
movl %ecx,%eax
roll $10,%esi
addl %edx,%ebp
xorl %esi,%eax
roll $14,%ebp
addl %ebx,%ebp
# 2
movl 8(%esp),%edx
xorl %ebp,%eax
addl %edx,%ebx
roll $10,%ecx
addl %eax,%ebx
movl %ebp,%eax
roll $15,%ebx
addl %edi,%ebx
# 3
xorl %ecx,%eax
movl 12(%esp),%edx
xorl %ebx,%eax
addl %eax,%edi
movl %ebx,%eax
roll $10,%ebp
addl %edx,%edi
xorl %ebp,%eax
roll $12,%edi
addl %esi,%edi
# 4
movl 16(%esp),%edx
xorl %edi,%eax
addl %edx,%esi
roll $10,%ebx
addl %eax,%esi
movl %edi,%eax
roll $5,%esi
addl %ecx,%esi
# 5
xorl %ebx,%eax
movl 20(%esp),%edx
xorl %esi,%eax
addl %eax,%ecx
movl %esi,%eax
roll $10,%edi
addl %edx,%ecx
xorl %edi,%eax
roll $8,%ecx
addl %ebp,%ecx
# 6
movl 24(%esp),%edx
xorl %ecx,%eax
addl %edx,%ebp
roll $10,%esi
addl %eax,%ebp
movl %ecx,%eax
roll $7,%ebp
addl %ebx,%ebp
# 7
xorl %esi,%eax
movl 28(%esp),%edx
xorl %ebp,%eax
addl %eax,%ebx
movl %ebp,%eax
roll $10,%ecx
addl %edx,%ebx
xorl %ecx,%eax
roll $9,%ebx
addl %edi,%ebx
# 8
movl 32(%esp),%edx
xorl %ebx,%eax
addl %edx,%edi
roll $10,%ebp
addl %eax,%edi
movl %ebx,%eax
roll $11,%edi
addl %esi,%edi
# 9
xorl %ebp,%eax
movl 36(%esp),%edx
xorl %edi,%eax
addl %eax,%esi
movl %edi,%eax
roll $10,%ebx
addl %edx,%esi
xorl %ebx,%eax
roll $13,%esi
addl %ecx,%esi
# 10
movl 40(%esp),%edx
xorl %esi,%eax
addl %edx,%ecx
roll $10,%edi
addl %eax,%ecx
movl %esi,%eax
roll $14,%ecx
addl %ebp,%ecx
# 11
xorl %edi,%eax
movl 44(%esp),%edx
xorl %ecx,%eax
addl %eax,%ebp
movl %ecx,%eax
roll $10,%esi
addl %edx,%ebp
xorl %esi,%eax
roll $15,%ebp
addl %ebx,%ebp
# 12
movl 48(%esp),%edx
xorl %ebp,%eax
addl %edx,%ebx
roll $10,%ecx
addl %eax,%ebx
movl %ebp,%eax
roll $6,%ebx
addl %edi,%ebx
# 13
xorl %ecx,%eax
movl 52(%esp),%edx
xorl %ebx,%eax
addl %eax,%edi
movl %ebx,%eax
roll $10,%ebp
addl %edx,%edi
xorl %ebp,%eax
roll $7,%edi
addl %esi,%edi
# 14
movl 56(%esp),%edx
xorl %edi,%eax
addl %edx,%esi
roll $10,%ebx
addl %eax,%esi
movl %edi,%eax
roll $9,%esi
addl %ecx,%esi
# 15
xorl %ebx,%eax
movl 60(%esp),%edx
xorl %esi,%eax
addl %eax,%ecx
movl $-1,%eax
roll $10,%edi
addl %edx,%ecx
movl 28(%esp),%edx
roll $8,%ecx
addl %ebp,%ecx
# 16
addl %edx,%ebp
movl %esi,%edx
subl %ecx,%eax
andl %ecx,%edx
andl %edi,%eax
orl %eax,%edx
movl 16(%esp),%eax
roll $10,%esi
leal 1518500249(%ebp,%edx,1),%ebp
movl $-1,%edx
roll $7,%ebp
addl %ebx,%ebp
# 17
addl %eax,%ebx
movl %ecx,%eax
subl %ebp,%edx
andl %ebp,%eax
andl %esi,%edx
orl %edx,%eax
movl 52(%esp),%edx
roll $10,%ecx
leal 1518500249(%ebx,%eax,1),%ebx
movl $-1,%eax
roll $6,%ebx
addl %edi,%ebx
# 18
addl %edx,%edi
movl %ebp,%edx
subl %ebx,%eax
andl %ebx,%edx
andl %ecx,%eax
orl %eax,%edx
movl 4(%esp),%eax
roll $10,%ebp
leal 1518500249(%edi,%edx,1),%edi
movl $-1,%edx
roll $8,%edi
addl %esi,%edi
# 19
addl %eax,%esi
movl %ebx,%eax
subl %edi,%edx
andl %edi,%eax
andl %ebp,%edx
orl %edx,%eax
movl 40(%esp),%edx
roll $10,%ebx
leal 1518500249(%esi,%eax,1),%esi
movl $-1,%eax
roll $13,%esi
addl %ecx,%esi
# 20
addl %edx,%ecx
movl %edi,%edx
subl %esi,%eax
andl %esi,%edx
andl %ebx,%eax
orl %eax,%edx
movl 24(%esp),%eax
roll $10,%edi
leal 1518500249(%ecx,%edx,1),%ecx
movl $-1,%edx
roll $11,%ecx
addl %ebp,%ecx
# 21
addl %eax,%ebp
movl %esi,%eax
subl %ecx,%edx
andl %ecx,%eax
andl %edi,%edx
orl %edx,%eax
movl 60(%esp),%edx
roll $10,%esi
leal 1518500249(%ebp,%eax,1),%ebp
movl $-1,%eax
roll $9,%ebp
addl %ebx,%ebp
# 22
addl %edx,%ebx
movl %ecx,%edx
subl %ebp,%eax
andl %ebp,%edx
andl %esi,%eax
orl %eax,%edx
movl 12(%esp),%eax
roll $10,%ecx
leal 1518500249(%ebx,%edx,1),%ebx
movl $-1,%edx
roll $7,%ebx
addl %edi,%ebx
# 23
addl %eax,%edi
movl %ebp,%eax
subl %ebx,%edx
andl %ebx,%eax
andl %ecx,%edx
orl %edx,%eax
movl 48(%esp),%edx
roll $10,%ebp
leal 1518500249(%edi,%eax,1),%edi
movl $-1,%eax
roll $15,%edi
addl %esi,%edi
# 24
addl %edx,%esi
movl %ebx,%edx
subl %edi,%eax
andl %edi,%edx
andl %ebp,%eax
orl %eax,%edx
movl (%esp),%eax
roll $10,%ebx
leal 1518500249(%esi,%edx,1),%esi
movl $-1,%edx
roll $7,%esi
addl %ecx,%esi
# 25
addl %eax,%ecx
movl %edi,%eax
subl %esi,%edx
andl %esi,%eax
andl %ebx,%edx
orl %edx,%eax
movl 36(%esp),%edx
roll $10,%edi
leal 1518500249(%ecx,%eax,1),%ecx
movl $-1,%eax
roll $12,%ecx
addl %ebp,%ecx
# 26
addl %edx,%ebp
movl %esi,%edx
subl %ecx,%eax
andl %ecx,%edx
andl %edi,%eax
orl %eax,%edx
movl 20(%esp),%eax
roll $10,%esi
leal 1518500249(%ebp,%edx,1),%ebp
movl $-1,%edx
roll $15,%ebp
addl %ebx,%ebp
# 27
addl %eax,%ebx
movl %ecx,%eax
subl %ebp,%edx
andl %ebp,%eax
andl %esi,%edx
orl %edx,%eax
movl 8(%esp),%edx
roll $10,%ecx
leal 1518500249(%ebx,%eax,1),%ebx
movl $-1,%eax
roll $9,%ebx
addl %edi,%ebx
# 28
addl %edx,%edi
movl %ebp,%edx
subl %ebx,%eax
andl %ebx,%edx
andl %ecx,%eax
orl %eax,%edx
movl 56(%esp),%eax
roll $10,%ebp
leal 1518500249(%edi,%edx,1),%edi
movl $-1,%edx
roll $11,%edi
addl %esi,%edi
# 29
addl %eax,%esi
movl %ebx,%eax
subl %edi,%edx
andl %edi,%eax
andl %ebp,%edx
orl %edx,%eax
movl 44(%esp),%edx
roll $10,%ebx
leal 1518500249(%esi,%eax,1),%esi
movl $-1,%eax
roll $7,%esi
addl %ecx,%esi
# 30
addl %edx,%ecx
movl %edi,%edx
subl %esi,%eax
andl %esi,%edx
andl %ebx,%eax
orl %eax,%edx
movl 32(%esp),%eax
roll $10,%edi
leal 1518500249(%ecx,%edx,1),%ecx
movl $-1,%edx
roll $13,%ecx
addl %ebp,%ecx
# 31
addl %eax,%ebp
movl %esi,%eax
subl %ecx,%edx
andl %ecx,%eax
andl %edi,%edx
orl %edx,%eax
movl $-1,%edx
roll $10,%esi
leal 1518500249(%ebp,%eax,1),%ebp
subl %ecx,%edx
roll $12,%ebp
addl %ebx,%ebp
# 32
movl 12(%esp),%eax
orl %ebp,%edx
addl %eax,%ebx
xorl %esi,%edx
movl $-1,%eax
roll $10,%ecx
leal 1859775393(%ebx,%edx,1),%ebx
subl %ebp,%eax
roll $11,%ebx
addl %edi,%ebx
# 33
movl 40(%esp),%edx
orl %ebx,%eax
addl %edx,%edi
xorl %ecx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1859775393(%edi,%eax,1),%edi
subl %ebx,%edx
roll $13,%edi
addl %esi,%edi
# 34
movl 56(%esp),%eax
orl %edi,%edx
addl %eax,%esi
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ebx
leal 1859775393(%esi,%edx,1),%esi
subl %edi,%eax
roll $6,%esi
addl %ecx,%esi
# 35
movl 16(%esp),%edx
orl %esi,%eax
addl %edx,%ecx
xorl %ebx,%eax
movl $-1,%edx
roll $10,%edi
leal 1859775393(%ecx,%eax,1),%ecx
subl %esi,%edx
roll $7,%ecx
addl %ebp,%ecx
# 36
movl 36(%esp),%eax
orl %ecx,%edx
addl %eax,%ebp
xorl %edi,%edx
movl $-1,%eax
roll $10,%esi
leal 1859775393(%ebp,%edx,1),%ebp
subl %ecx,%eax
roll $14,%ebp
addl %ebx,%ebp
# 37
movl 60(%esp),%edx
orl %ebp,%eax
addl %edx,%ebx
xorl %esi,%eax
movl $-1,%edx
roll $10,%ecx
leal 1859775393(%ebx,%eax,1),%ebx
subl %ebp,%edx
roll $9,%ebx
addl %edi,%ebx
# 38
movl 32(%esp),%eax
orl %ebx,%edx
addl %eax,%edi
xorl %ecx,%edx
movl $-1,%eax
roll $10,%ebp
leal 1859775393(%edi,%edx,1),%edi
subl %ebx,%eax
roll $13,%edi
addl %esi,%edi
# 39
movl 4(%esp),%edx
orl %edi,%eax
addl %edx,%esi
xorl %ebp,%eax
movl $-1,%edx
roll $10,%ebx
leal 1859775393(%esi,%eax,1),%esi
subl %edi,%edx
roll $15,%esi
addl %ecx,%esi
# 40
movl 8(%esp),%eax
orl %esi,%edx
addl %eax,%ecx
xorl %ebx,%edx
movl $-1,%eax
roll $10,%edi
leal 1859775393(%ecx,%edx,1),%ecx
subl %esi,%eax
roll $14,%ecx
addl %ebp,%ecx
# 41
movl 28(%esp),%edx
orl %ecx,%eax
addl %edx,%ebp
xorl %edi,%eax
movl $-1,%edx
roll $10,%esi
leal 1859775393(%ebp,%eax,1),%ebp
subl %ecx,%edx
roll $8,%ebp
addl %ebx,%ebp
# 42
movl (%esp),%eax
orl %ebp,%edx
addl %eax,%ebx
xorl %esi,%edx
movl $-1,%eax
roll $10,%ecx
leal 1859775393(%ebx,%edx,1),%ebx
subl %ebp,%eax
roll $13,%ebx
addl %edi,%ebx
# 43
movl 24(%esp),%edx
orl %ebx,%eax
addl %edx,%edi
xorl %ecx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1859775393(%edi,%eax,1),%edi
subl %ebx,%edx
roll $6,%edi
addl %esi,%edi
# 44
movl 52(%esp),%eax
orl %edi,%edx
addl %eax,%esi
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ebx
leal 1859775393(%esi,%edx,1),%esi
subl %edi,%eax
roll $5,%esi
addl %ecx,%esi
# 45
movl 44(%esp),%edx
orl %esi,%eax
addl %edx,%ecx
xorl %ebx,%eax
movl $-1,%edx
roll $10,%edi
leal 1859775393(%ecx,%eax,1),%ecx
subl %esi,%edx
roll $12,%ecx
addl %ebp,%ecx
# 46
movl 20(%esp),%eax
orl %ecx,%edx
addl %eax,%ebp
xorl %edi,%edx
movl $-1,%eax
roll $10,%esi
leal 1859775393(%ebp,%edx,1),%ebp
subl %ecx,%eax
roll $7,%ebp
addl %ebx,%ebp
# 47
movl 48(%esp),%edx
orl %ebp,%eax
addl %edx,%ebx
xorl %esi,%eax
movl $-1,%edx
roll $10,%ecx
leal 1859775393(%ebx,%eax,1),%ebx
movl %ecx,%eax
roll $5,%ebx
addl %edi,%ebx
# 48
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 4(%esp),%eax
roll $10,%ebp
leal 2400959708(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $11,%edi
addl %esi,%edi
# 49
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 36(%esp),%eax
roll $10,%ebx
leal 2400959708(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $12,%esi
addl %ecx,%esi
# 50
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl 44(%esp),%eax
roll $10,%edi
leal 2400959708(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $14,%ecx
addl %ebp,%ecx
# 51
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 40(%esp),%eax
roll $10,%esi
leal 2400959708(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $15,%ebp
addl %ebx,%ebp
# 52
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl (%esp),%eax
roll $10,%ecx
leal 2400959708(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $14,%ebx
addl %edi,%ebx
# 53
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 32(%esp),%eax
roll $10,%ebp
leal 2400959708(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $15,%edi
addl %esi,%edi
# 54
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 48(%esp),%eax
roll $10,%ebx
leal 2400959708(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $9,%esi
addl %ecx,%esi
# 55
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl 16(%esp),%eax
roll $10,%edi
leal 2400959708(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $8,%ecx
addl %ebp,%ecx
# 56
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 52(%esp),%eax
roll $10,%esi
leal 2400959708(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $9,%ebp
addl %ebx,%ebp
# 57
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl 12(%esp),%eax
roll $10,%ecx
leal 2400959708(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $14,%ebx
addl %edi,%ebx
# 58
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 28(%esp),%eax
roll $10,%ebp
leal 2400959708(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $5,%edi
addl %esi,%edi
# 59
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 60(%esp),%eax
roll $10,%ebx
leal 2400959708(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $6,%esi
addl %ecx,%esi
# 60
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl 56(%esp),%eax
roll $10,%edi
leal 2400959708(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $8,%ecx
addl %ebp,%ecx
# 61
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 20(%esp),%eax
roll $10,%esi
leal 2400959708(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $6,%ebp
addl %ebx,%ebp
# 62
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl 24(%esp),%eax
roll $10,%ecx
leal 2400959708(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $5,%ebx
addl %edi,%ebx
# 63
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 8(%esp),%eax
roll $10,%ebp
leal 2400959708(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
subl %ebp,%edx
roll $12,%edi
addl %esi,%edi
# 64
movl 16(%esp),%eax
orl %ebx,%edx
addl %eax,%esi
xorl %edi,%edx
movl $-1,%eax
roll $10,%ebx
leal 2840853838(%esi,%edx,1),%esi
subl %ebx,%eax
roll $9,%esi
addl %ecx,%esi
# 65
movl (%esp),%edx
orl %edi,%eax
addl %edx,%ecx
xorl %esi,%eax
movl $-1,%edx
roll $10,%edi
leal 2840853838(%ecx,%eax,1),%ecx
subl %edi,%edx
roll $15,%ecx
addl %ebp,%ecx
# 66
movl 20(%esp),%eax
orl %esi,%edx
addl %eax,%ebp
xorl %ecx,%edx
movl $-1,%eax
roll $10,%esi
leal 2840853838(%ebp,%edx,1),%ebp
subl %esi,%eax
roll $5,%ebp
addl %ebx,%ebp
# 67
movl 36(%esp),%edx
orl %ecx,%eax
addl %edx,%ebx
xorl %ebp,%eax
movl $-1,%edx
roll $10,%ecx
leal 2840853838(%ebx,%eax,1),%ebx
subl %ecx,%edx
roll $11,%ebx
addl %edi,%ebx
# 68
movl 28(%esp),%eax
orl %ebp,%edx
addl %eax,%edi
xorl %ebx,%edx
movl $-1,%eax
roll $10,%ebp
leal 2840853838(%edi,%edx,1),%edi
subl %ebp,%eax
roll $6,%edi
addl %esi,%edi
# 69
movl 48(%esp),%edx
orl %ebx,%eax
addl %edx,%esi
xorl %edi,%eax
movl $-1,%edx
roll $10,%ebx
leal 2840853838(%esi,%eax,1),%esi
subl %ebx,%edx
roll $8,%esi
addl %ecx,%esi
# 70
movl 8(%esp),%eax
orl %edi,%edx
addl %eax,%ecx
xorl %esi,%edx
movl $-1,%eax
roll $10,%edi
leal 2840853838(%ecx,%edx,1),%ecx
subl %edi,%eax
roll $13,%ecx
addl %ebp,%ecx
# 71
movl 40(%esp),%edx
orl %esi,%eax
addl %edx,%ebp
xorl %ecx,%eax
movl $-1,%edx
roll $10,%esi
leal 2840853838(%ebp,%eax,1),%ebp
subl %esi,%edx
roll $12,%ebp
addl %ebx,%ebp
# 72
movl 56(%esp),%eax
orl %ecx,%edx
addl %eax,%ebx
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ecx
leal 2840853838(%ebx,%edx,1),%ebx
subl %ecx,%eax
roll $5,%ebx
addl %edi,%ebx
# 73
movl 4(%esp),%edx
orl %ebp,%eax
addl %edx,%edi
xorl %ebx,%eax
movl $-1,%edx
roll $10,%ebp
leal 2840853838(%edi,%eax,1),%edi
subl %ebp,%edx
roll $12,%edi
addl %esi,%edi
# 74
movl 12(%esp),%eax
orl %ebx,%edx
addl %eax,%esi
xorl %edi,%edx
movl $-1,%eax
roll $10,%ebx
leal 2840853838(%esi,%edx,1),%esi
subl %ebx,%eax
roll $13,%esi
addl %ecx,%esi
# 75
movl 32(%esp),%edx
orl %edi,%eax
addl %edx,%ecx
xorl %esi,%eax
movl $-1,%edx
roll $10,%edi
leal 2840853838(%ecx,%eax,1),%ecx
subl %edi,%edx
roll $14,%ecx
addl %ebp,%ecx
# 76
movl 44(%esp),%eax
orl %esi,%edx
addl %eax,%ebp
xorl %ecx,%edx
movl $-1,%eax
roll $10,%esi
leal 2840853838(%ebp,%edx,1),%ebp
subl %esi,%eax
roll $11,%ebp
addl %ebx,%ebp
# 77
movl 24(%esp),%edx
orl %ecx,%eax
addl %edx,%ebx
xorl %ebp,%eax
movl $-1,%edx
roll $10,%ecx
leal 2840853838(%ebx,%eax,1),%ebx
subl %ecx,%edx
roll $8,%ebx
addl %edi,%ebx
# 78
movl 60(%esp),%eax
orl %ebp,%edx
addl %eax,%edi
xorl %ebx,%edx
movl $-1,%eax
roll $10,%ebp
leal 2840853838(%edi,%edx,1),%edi
subl %ebp,%eax
roll $5,%edi
addl %esi,%edi
# 79
movl 52(%esp),%edx
orl %ebx,%eax
addl %edx,%esi
xorl %edi,%eax
movl 128(%esp),%edx
roll $10,%ebx
leal 2840853838(%esi,%eax,1),%esi
movl %ecx,64(%esp)
roll $6,%esi
addl %ecx,%esi
movl (%edx),%ecx
movl %esi,68(%esp)
movl %edi,72(%esp)
movl 4(%edx),%esi
movl %ebx,76(%esp)
movl 8(%edx),%edi
movl %ebp,80(%esp)
movl 12(%edx),%ebx
movl 16(%edx),%ebp
# 80
movl $-1,%edx
subl %ebx,%edx
movl 20(%esp),%eax
orl %edi,%edx
addl %eax,%ecx
xorl %esi,%edx
movl $-1,%eax
roll $10,%edi
leal 1352829926(%ecx,%edx,1),%ecx
subl %edi,%eax
roll $8,%ecx
addl %ebp,%ecx
# 81
movl 56(%esp),%edx
orl %esi,%eax
addl %edx,%ebp
xorl %ecx,%eax
movl $-1,%edx
roll $10,%esi
leal 1352829926(%ebp,%eax,1),%ebp
subl %esi,%edx
roll $9,%ebp
addl %ebx,%ebp
# 82
movl 28(%esp),%eax
orl %ecx,%edx
addl %eax,%ebx
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ecx
leal 1352829926(%ebx,%edx,1),%ebx
subl %ecx,%eax
roll $9,%ebx
addl %edi,%ebx
# 83
movl (%esp),%edx
orl %ebp,%eax
addl %edx,%edi
xorl %ebx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1352829926(%edi,%eax,1),%edi
subl %ebp,%edx
roll $11,%edi
addl %esi,%edi
# 84
movl 36(%esp),%eax
orl %ebx,%edx
addl %eax,%esi
xorl %edi,%edx
movl $-1,%eax
roll $10,%ebx
leal 1352829926(%esi,%edx,1),%esi
subl %ebx,%eax
roll $13,%esi
addl %ecx,%esi
# 85
movl 8(%esp),%edx
orl %edi,%eax
addl %edx,%ecx
xorl %esi,%eax
movl $-1,%edx
roll $10,%edi
leal 1352829926(%ecx,%eax,1),%ecx
subl %edi,%edx
roll $15,%ecx
addl %ebp,%ecx
# 86
movl 44(%esp),%eax
orl %esi,%edx
addl %eax,%ebp
xorl %ecx,%edx
movl $-1,%eax
roll $10,%esi
leal 1352829926(%ebp,%edx,1),%ebp
subl %esi,%eax
roll $15,%ebp
addl %ebx,%ebp
# 87
movl 16(%esp),%edx
orl %ecx,%eax
addl %edx,%ebx
xorl %ebp,%eax
movl $-1,%edx
roll $10,%ecx
leal 1352829926(%ebx,%eax,1),%ebx
subl %ecx,%edx
roll $5,%ebx
addl %edi,%ebx
# 88
movl 52(%esp),%eax
orl %ebp,%edx
addl %eax,%edi
xorl %ebx,%edx
movl $-1,%eax
roll $10,%ebp
leal 1352829926(%edi,%edx,1),%edi
subl %ebp,%eax
roll $7,%edi
addl %esi,%edi
# 89
movl 24(%esp),%edx
orl %ebx,%eax
addl %edx,%esi
xorl %edi,%eax
movl $-1,%edx
roll $10,%ebx
leal 1352829926(%esi,%eax,1),%esi
subl %ebx,%edx
roll $7,%esi
addl %ecx,%esi
# 90
movl 60(%esp),%eax
orl %edi,%edx
addl %eax,%ecx
xorl %esi,%edx
movl $-1,%eax
roll $10,%edi
leal 1352829926(%ecx,%edx,1),%ecx
subl %edi,%eax
roll $8,%ecx
addl %ebp,%ecx
# 91
movl 32(%esp),%edx
orl %esi,%eax
addl %edx,%ebp
xorl %ecx,%eax
movl $-1,%edx
roll $10,%esi
leal 1352829926(%ebp,%eax,1),%ebp
subl %esi,%edx
roll $11,%ebp
addl %ebx,%ebp
# 92
movl 4(%esp),%eax
orl %ecx,%edx
addl %eax,%ebx
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ecx
leal 1352829926(%ebx,%edx,1),%ebx
subl %ecx,%eax
roll $14,%ebx
addl %edi,%ebx
# 93
movl 40(%esp),%edx
orl %ebp,%eax
addl %edx,%edi
xorl %ebx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1352829926(%edi,%eax,1),%edi
subl %ebp,%edx
roll $14,%edi
addl %esi,%edi
# 94
movl 12(%esp),%eax
orl %ebx,%edx
addl %eax,%esi
xorl %edi,%edx
movl $-1,%eax
roll $10,%ebx
leal 1352829926(%esi,%edx,1),%esi
subl %ebx,%eax
roll $12,%esi
addl %ecx,%esi
# 95
movl 48(%esp),%edx
orl %edi,%eax
addl %edx,%ecx
xorl %esi,%eax
movl $-1,%edx
roll $10,%edi
leal 1352829926(%ecx,%eax,1),%ecx
movl %edi,%eax
roll $6,%ecx
addl %ebp,%ecx
# 96
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 24(%esp),%eax
roll $10,%esi
leal 1548603684(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $9,%ebp
addl %ebx,%ebp
# 97
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl 44(%esp),%eax
roll $10,%ecx
leal 1548603684(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $13,%ebx
addl %edi,%ebx
# 98
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 12(%esp),%eax
roll $10,%ebp
leal 1548603684(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $15,%edi
addl %esi,%edi
# 99
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 28(%esp),%eax
roll $10,%ebx
leal 1548603684(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $7,%esi
addl %ecx,%esi
# 100
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl (%esp),%eax
roll $10,%edi
leal 1548603684(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $12,%ecx
addl %ebp,%ecx
# 101
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 52(%esp),%eax
roll $10,%esi
leal 1548603684(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $8,%ebp
addl %ebx,%ebp
# 102
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl 20(%esp),%eax
roll $10,%ecx
leal 1548603684(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $9,%ebx
addl %edi,%ebx
# 103
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 40(%esp),%eax
roll $10,%ebp
leal 1548603684(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $11,%edi
addl %esi,%edi
# 104
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 56(%esp),%eax
roll $10,%ebx
leal 1548603684(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $7,%esi
addl %ecx,%esi
# 105
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl 60(%esp),%eax
roll $10,%edi
leal 1548603684(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $7,%ecx
addl %ebp,%ecx
# 106
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 32(%esp),%eax
roll $10,%esi
leal 1548603684(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
movl %esi,%eax
roll $12,%ebp
addl %ebx,%ebp
# 107
subl %esi,%edx
andl %ebp,%eax
andl %ecx,%edx
orl %eax,%edx
movl 48(%esp),%eax
roll $10,%ecx
leal 1548603684(%ebx,%edx,1),%ebx
movl $-1,%edx
addl %eax,%ebx
movl %ecx,%eax
roll $7,%ebx
addl %edi,%ebx
# 108
subl %ecx,%edx
andl %ebx,%eax
andl %ebp,%edx
orl %eax,%edx
movl 16(%esp),%eax
roll $10,%ebp
leal 1548603684(%edi,%edx,1),%edi
movl $-1,%edx
addl %eax,%edi
movl %ebp,%eax
roll $6,%edi
addl %esi,%edi
# 109
subl %ebp,%edx
andl %edi,%eax
andl %ebx,%edx
orl %eax,%edx
movl 36(%esp),%eax
roll $10,%ebx
leal 1548603684(%esi,%edx,1),%esi
movl $-1,%edx
addl %eax,%esi
movl %ebx,%eax
roll $15,%esi
addl %ecx,%esi
# 110
subl %ebx,%edx
andl %esi,%eax
andl %edi,%edx
orl %eax,%edx
movl 4(%esp),%eax
roll $10,%edi
leal 1548603684(%ecx,%edx,1),%ecx
movl $-1,%edx
addl %eax,%ecx
movl %edi,%eax
roll $13,%ecx
addl %ebp,%ecx
# 111
subl %edi,%edx
andl %ecx,%eax
andl %esi,%edx
orl %eax,%edx
movl 8(%esp),%eax
roll $10,%esi
leal 1548603684(%ebp,%edx,1),%ebp
movl $-1,%edx
addl %eax,%ebp
subl %ecx,%edx
roll $11,%ebp
addl %ebx,%ebp
# 112
movl 60(%esp),%eax
orl %ebp,%edx
addl %eax,%ebx
xorl %esi,%edx
movl $-1,%eax
roll $10,%ecx
leal 1836072691(%ebx,%edx,1),%ebx
subl %ebp,%eax
roll $9,%ebx
addl %edi,%ebx
# 113
movl 20(%esp),%edx
orl %ebx,%eax
addl %edx,%edi
xorl %ecx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1836072691(%edi,%eax,1),%edi
subl %ebx,%edx
roll $7,%edi
addl %esi,%edi
# 114
movl 4(%esp),%eax
orl %edi,%edx
addl %eax,%esi
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ebx
leal 1836072691(%esi,%edx,1),%esi
subl %edi,%eax
roll $15,%esi
addl %ecx,%esi
# 115
movl 12(%esp),%edx
orl %esi,%eax
addl %edx,%ecx
xorl %ebx,%eax
movl $-1,%edx
roll $10,%edi
leal 1836072691(%ecx,%eax,1),%ecx
subl %esi,%edx
roll $11,%ecx
addl %ebp,%ecx
# 116
movl 28(%esp),%eax
orl %ecx,%edx
addl %eax,%ebp
xorl %edi,%edx
movl $-1,%eax
roll $10,%esi
leal 1836072691(%ebp,%edx,1),%ebp
subl %ecx,%eax
roll $8,%ebp
addl %ebx,%ebp
# 117
movl 56(%esp),%edx
orl %ebp,%eax
addl %edx,%ebx
xorl %esi,%eax
movl $-1,%edx
roll $10,%ecx
leal 1836072691(%ebx,%eax,1),%ebx
subl %ebp,%edx
roll $6,%ebx
addl %edi,%ebx
# 118
movl 24(%esp),%eax
orl %ebx,%edx
addl %eax,%edi
xorl %ecx,%edx
movl $-1,%eax
roll $10,%ebp
leal 1836072691(%edi,%edx,1),%edi
subl %ebx,%eax
roll $6,%edi
addl %esi,%edi
# 119
movl 36(%esp),%edx
orl %edi,%eax
addl %edx,%esi
xorl %ebp,%eax
movl $-1,%edx
roll $10,%ebx
leal 1836072691(%esi,%eax,1),%esi
subl %edi,%edx
roll $14,%esi
addl %ecx,%esi
# 120
movl 44(%esp),%eax
orl %esi,%edx
addl %eax,%ecx
xorl %ebx,%edx
movl $-1,%eax
roll $10,%edi
leal 1836072691(%ecx,%edx,1),%ecx
subl %esi,%eax
roll $12,%ecx
addl %ebp,%ecx
# 121
movl 32(%esp),%edx
orl %ecx,%eax
addl %edx,%ebp
xorl %edi,%eax
movl $-1,%edx
roll $10,%esi
leal 1836072691(%ebp,%eax,1),%ebp
subl %ecx,%edx
roll $13,%ebp
addl %ebx,%ebp
# 122
movl 48(%esp),%eax
orl %ebp,%edx
addl %eax,%ebx
xorl %esi,%edx
movl $-1,%eax
roll $10,%ecx
leal 1836072691(%ebx,%edx,1),%ebx
subl %ebp,%eax
roll $5,%ebx
addl %edi,%ebx
# 123
movl 8(%esp),%edx
orl %ebx,%eax
addl %edx,%edi
xorl %ecx,%eax
movl $-1,%edx
roll $10,%ebp
leal 1836072691(%edi,%eax,1),%edi
subl %ebx,%edx
roll $14,%edi
addl %esi,%edi
# 124
movl 40(%esp),%eax
orl %edi,%edx
addl %eax,%esi
xorl %ebp,%edx
movl $-1,%eax
roll $10,%ebx
leal 1836072691(%esi,%edx,1),%esi
subl %edi,%eax
roll $13,%esi
addl %ecx,%esi
# 125
movl (%esp),%edx
orl %esi,%eax
addl %edx,%ecx
xorl %ebx,%eax
movl $-1,%edx
roll $10,%edi
leal 1836072691(%ecx,%eax,1),%ecx
subl %esi,%edx
roll $13,%ecx
addl %ebp,%ecx
# 126
movl 16(%esp),%eax
orl %ecx,%edx
addl %eax,%ebp
xorl %edi,%edx
movl $-1,%eax
roll $10,%esi
leal 1836072691(%ebp,%edx,1),%ebp
subl %ecx,%eax
roll $7,%ebp
addl %ebx,%ebp
# 127
movl 52(%esp),%edx
orl %ebp,%eax
addl %edx,%ebx
xorl %esi,%eax
movl 32(%esp),%edx
roll $10,%ecx
leal 1836072691(%ebx,%eax,1),%ebx
movl $-1,%eax
roll $5,%ebx
addl %edi,%ebx
# 128
addl %edx,%edi
movl %ebp,%edx
subl %ebx,%eax
andl %ebx,%edx
andl %ecx,%eax
orl %eax,%edx
movl 24(%esp),%eax
roll $10,%ebp
leal 2053994217(%edi,%edx,1),%edi
movl $-1,%edx
roll $15,%edi
addl %esi,%edi
# 129
addl %eax,%esi
movl %ebx,%eax
subl %edi,%edx
andl %edi,%eax
andl %ebp,%edx
orl %edx,%eax
movl 16(%esp),%edx
roll $10,%ebx
leal 2053994217(%esi,%eax,1),%esi
movl $-1,%eax
roll $5,%esi
addl %ecx,%esi
# 130
addl %edx,%ecx
movl %edi,%edx
subl %esi,%eax
andl %esi,%edx
andl %ebx,%eax
orl %eax,%edx
movl 4(%esp),%eax
roll $10,%edi
leal 2053994217(%ecx,%edx,1),%ecx
movl $-1,%edx
roll $8,%ecx
addl %ebp,%ecx
# 131
addl %eax,%ebp
movl %esi,%eax
subl %ecx,%edx
andl %ecx,%eax
andl %edi,%edx
orl %edx,%eax
movl 12(%esp),%edx
roll $10,%esi
leal 2053994217(%ebp,%eax,1),%ebp
movl $-1,%eax
roll $11,%ebp
addl %ebx,%ebp
# 132
addl %edx,%ebx
movl %ecx,%edx
subl %ebp,%eax
andl %ebp,%edx
andl %esi,%eax
orl %eax,%edx
movl 44(%esp),%eax
roll $10,%ecx
leal 2053994217(%ebx,%edx,1),%ebx
movl $-1,%edx
roll $14,%ebx
addl %edi,%ebx
# 133
addl %eax,%edi
movl %ebp,%eax
subl %ebx,%edx
andl %ebx,%eax
andl %ecx,%edx
orl %edx,%eax
movl 60(%esp),%edx
roll $10,%ebp
leal 2053994217(%edi,%eax,1),%edi
movl $-1,%eax
roll $14,%edi
addl %esi,%edi
# 134
addl %edx,%esi
movl %ebx,%edx
subl %edi,%eax
andl %edi,%edx
andl %ebp,%eax
orl %eax,%edx
movl (%esp),%eax
roll $10,%ebx
leal 2053994217(%esi,%edx,1),%esi
movl $-1,%edx
roll $6,%esi
addl %ecx,%esi
# 135
addl %eax,%ecx
movl %edi,%eax
subl %esi,%edx
andl %esi,%eax
andl %ebx,%edx
orl %edx,%eax
movl 20(%esp),%edx
roll $10,%edi
leal 2053994217(%ecx,%eax,1),%ecx
movl $-1,%eax
roll $14,%ecx
addl %ebp,%ecx
# 136
addl %edx,%ebp
movl %esi,%edx
subl %ecx,%eax
andl %ecx,%edx
andl %edi,%eax
orl %eax,%edx
movl 48(%esp),%eax
roll $10,%esi
leal 2053994217(%ebp,%edx,1),%ebp
movl $-1,%edx
roll $6,%ebp
addl %ebx,%ebp
# 137
addl %eax,%ebx
movl %ecx,%eax
subl %ebp,%edx
andl %ebp,%eax
andl %esi,%edx
orl %edx,%eax
movl 8(%esp),%edx
roll $10,%ecx
leal 2053994217(%ebx,%eax,1),%ebx
movl $-1,%eax
roll $9,%ebx
addl %edi,%ebx
# 138
addl %edx,%edi
movl %ebp,%edx
subl %ebx,%eax
andl %ebx,%edx
andl %ecx,%eax
orl %eax,%edx
movl 52(%esp),%eax
roll $10,%ebp
leal 2053994217(%edi,%edx,1),%edi
movl $-1,%edx
roll $12,%edi
addl %esi,%edi
# 139
addl %eax,%esi
movl %ebx,%eax
subl %edi,%edx
andl %edi,%eax
andl %ebp,%edx
orl %edx,%eax
movl 36(%esp),%edx
roll $10,%ebx
leal 2053994217(%esi,%eax,1),%esi
movl $-1,%eax
roll $9,%esi
addl %ecx,%esi
# 140
addl %edx,%ecx
movl %edi,%edx
subl %esi,%eax
andl %esi,%edx
andl %ebx,%eax
orl %eax,%edx
movl 28(%esp),%eax
roll $10,%edi
leal 2053994217(%ecx,%edx,1),%ecx
movl $-1,%edx
roll $12,%ecx
addl %ebp,%ecx
# 141
addl %eax,%ebp
movl %esi,%eax
subl %ecx,%edx
andl %ecx,%eax
andl %edi,%edx
orl %edx,%eax
movl 40(%esp),%edx
roll $10,%esi
leal 2053994217(%ebp,%eax,1),%ebp
movl $-1,%eax
roll $5,%ebp
addl %ebx,%ebp
# 142
addl %edx,%ebx
movl %ecx,%edx
subl %ebp,%eax
andl %ebp,%edx
andl %esi,%eax
orl %eax,%edx
movl 56(%esp),%eax
roll $10,%ecx
leal 2053994217(%ebx,%edx,1),%ebx
movl $-1,%edx
roll $15,%ebx
addl %edi,%ebx
# 143
addl %eax,%edi
movl %ebp,%eax
subl %ebx,%edx
andl %ebx,%eax
andl %ecx,%edx
orl %eax,%edx
movl %ebx,%eax
roll $10,%ebp
leal 2053994217(%edi,%edx,1),%edi
xorl %ebp,%eax
roll $8,%edi
addl %esi,%edi
# 144
movl 48(%esp),%edx
xorl %edi,%eax
addl %edx,%esi
roll $10,%ebx
addl %eax,%esi
movl %edi,%eax
roll $8,%esi
addl %ecx,%esi
# 145
xorl %ebx,%eax
movl 60(%esp),%edx
xorl %esi,%eax
addl %eax,%ecx
movl %esi,%eax
roll $10,%edi
addl %edx,%ecx
xorl %edi,%eax
roll $5,%ecx
addl %ebp,%ecx
# 146
movl 40(%esp),%edx
xorl %ecx,%eax
addl %edx,%ebp
roll $10,%esi
addl %eax,%ebp
movl %ecx,%eax
roll $12,%ebp
addl %ebx,%ebp
# 147
xorl %esi,%eax
movl 16(%esp),%edx
xorl %ebp,%eax
addl %eax,%ebx
movl %ebp,%eax
roll $10,%ecx
addl %edx,%ebx
xorl %ecx,%eax
roll $9,%ebx
addl %edi,%ebx
# 148
movl 4(%esp),%edx
xorl %ebx,%eax
addl %edx,%edi
roll $10,%ebp
addl %eax,%edi
movl %ebx,%eax
roll $12,%edi
addl %esi,%edi
# 149
xorl %ebp,%eax
movl 20(%esp),%edx
xorl %edi,%eax
addl %eax,%esi
movl %edi,%eax
roll $10,%ebx
addl %edx,%esi
xorl %ebx,%eax
roll $5,%esi
addl %ecx,%esi
# 150
movl 32(%esp),%edx
xorl %esi,%eax
addl %edx,%ecx
roll $10,%edi
addl %eax,%ecx
movl %esi,%eax
roll $14,%ecx
addl %ebp,%ecx
# 151
xorl %edi,%eax
movl 28(%esp),%edx
xorl %ecx,%eax
addl %eax,%ebp
movl %ecx,%eax
roll $10,%esi
addl %edx,%ebp
xorl %esi,%eax
roll $6,%ebp
addl %ebx,%ebp
# 152
movl 24(%esp),%edx
xorl %ebp,%eax
addl %edx,%ebx
roll $10,%ecx
addl %eax,%ebx
movl %ebp,%eax
roll $8,%ebx
addl %edi,%ebx
# 153
xorl %ecx,%eax
movl 8(%esp),%edx
xorl %ebx,%eax
addl %eax,%edi
movl %ebx,%eax
roll $10,%ebp
addl %edx,%edi
xorl %ebp,%eax
roll $13,%edi
addl %esi,%edi
# 154
movl 52(%esp),%edx
xorl %edi,%eax
addl %edx,%esi
roll $10,%ebx
addl %eax,%esi
movl %edi,%eax
roll $6,%esi
addl %ecx,%esi
# 155
xorl %ebx,%eax
movl 56(%esp),%edx
xorl %esi,%eax
addl %eax,%ecx
movl %esi,%eax
roll $10,%edi
addl %edx,%ecx
xorl %edi,%eax
roll $5,%ecx
addl %ebp,%ecx
# 156
movl (%esp),%edx
xorl %ecx,%eax
addl %edx,%ebp
roll $10,%esi
addl %eax,%ebp
movl %ecx,%eax
roll $15,%ebp
addl %ebx,%ebp
# 157
xorl %esi,%eax
movl 12(%esp),%edx
xorl %ebp,%eax
addl %eax,%ebx
movl %ebp,%eax
roll $10,%ecx
addl %edx,%ebx
xorl %ecx,%eax
roll $13,%ebx
addl %edi,%ebx
# 158
movl 36(%esp),%edx
xorl %ebx,%eax
addl %edx,%edi
roll $10,%ebp
addl %eax,%edi
movl %ebx,%eax
roll $11,%edi
addl %esi,%edi
# 159
xorl %ebp,%eax
movl 44(%esp),%edx
xorl %edi,%eax
addl %eax,%esi
roll $10,%ebx
addl %edx,%esi
movl 128(%esp),%edx
roll $11,%esi
addl %ecx,%esi
movl 4(%edx),%eax
addl %eax,%ebx
movl 72(%esp),%eax
addl %eax,%ebx
movl 8(%edx),%eax
addl %eax,%ebp
movl 76(%esp),%eax
addl %eax,%ebp
movl 12(%edx),%eax
addl %eax,%ecx
movl 80(%esp),%eax
addl %eax,%ecx
movl 16(%edx),%eax
addl %eax,%esi
movl 64(%esp),%eax
addl %eax,%esi
movl (%edx),%eax
addl %eax,%edi
movl 68(%esp),%eax
addl %eax,%edi
movl 136(%esp),%eax
movl %ebx,(%edx)
movl %ebp,4(%edx)
movl %ecx,8(%edx)
subl $1,%eax
movl %esi,12(%edx)
movl %edi,16(%edx)
jle L001get_out
movl %eax,136(%esp)
movl %ecx,%edi
movl 132(%esp),%eax
movl %ebx,%ecx
addl $64,%eax
movl %ebp,%esi
movl %eax,132(%esp)
jmp L000start
L001get_out:
addl $108,%esp
popl %ebx
popl %ebp
popl %edi
popl %esi
ret
| {
"language": "Assembly"
} |