Datasets:

ggcristian

/

verilog-completition

like 0

data/full_repos/permissive/42434302/ivltests/assign_mem1.v

assign_mem1.v

v

[]

[]

[]

[Errno 2] No such file or directory: 'preprocess.output'

1: b'%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/assign_mem1.v:30: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 5 bits.\n : ... In instance test\n is[0] = i; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'

module

module test; reg [15:0] is[1:0]; reg [4:0] i; initial begin i = 0; is[0] = i; if (is[0] !== 16'd0) begin $display("FAILED -- is[0] --> %b", is[0]); $finish; end $display("PASSED"); end endmodule

module test;

reg [15:0] is[1:0]; reg [4:0] i; initial begin i = 0; is[0] = i; if (is[0] !== 16'd0) begin $display("FAILED -- is[0] --> %b", is[0]); $finish; end $display("PASSED"); end endmodule

data/full_repos/permissive/146618947/valid_tarea6/mux_tb.v

mux_tb.v

v

[]

[]

[]

[Errno 2] No such file or directory: 'preprocess.output'

1: b'%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_tb.v:2: Cannot find include file: mux.v\n`include "mux.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux.v\n data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux.v.v\n data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux.v.sv\n mux.v\n mux.v.v\n mux.v.sv\n obj_dir/mux.v\n obj_dir/mux.v.v\n obj_dir/mux.v.sv\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_tb.v:3: Cannot find include file: mux_tester.v\n`include "mux_tester.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_tb.v:4: Cannot find include file: mux_estructural.v\n`include "mux_estructural.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_tb.v:5: Cannot find include file: mycells.v\n`include "mycells.v" \n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'

module

module mux_tb; wire reset_L, clk; wire [3:0] data_0; wire [3:0] data_1; wire [3:0] data_out_cond; wire [3:0] data_out_est; wire valid_0; wire valid_1; wire valid_out_cond; wire valid_out_est; mux mux_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out (data_out_cond), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out (valid_out_cond) ); mux_tester mux_tester_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out_cond (data_out_cond), .data_out_est (data_out_est), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out_cond (valid_out_cond), .valid_out_est (valid_out_est) ); mux_estructural mux_est_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out (data_out_est), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out (valid_out_est) ); endmodule

module mux_tb;

wire reset_L, clk; wire [3:0] data_0; wire [3:0] data_1; wire [3:0] data_out_cond; wire [3:0] data_out_est; wire valid_0; wire valid_1; wire valid_out_cond; wire valid_out_est; mux mux_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out (data_out_cond), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out (valid_out_cond) ); mux_tester mux_tester_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out_cond (data_out_cond), .data_out_est (data_out_est), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out_cond (valid_out_cond), .valid_out_est (valid_out_est) ); mux_estructural mux_est_( .reset_L (reset_L), .clk (clk), .data_0 (data_0), .data_1 (data_1), .data_out (data_out_est), .valid_0 (valid_0), .valid_1 (valid_1), .valid_out (valid_out_est) ); endmodule

data/full_repos/permissive/119715647/sim/Display7Seg.v

Display7Seg.v

v

[]

[]

[]

[(1, 22)]

1: b"%Error: data/full_repos/permissive/119715647/sim/Display7Seg.v:13: Cannot find file containing module: 'Dec7Seg'\n Dec7Seg _display0(userID_score[31:28],display7), \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/119715647/sim,data/full_repos/permissive/119715647/Dec7Seg\n data/full_repos/permissive/119715647/sim,data/full_repos/permissive/119715647/Dec7Seg.v\n data/full_repos/permissive/119715647/sim,data/full_repos/permissive/119715647/Dec7Seg.sv\n Dec7Seg\n Dec7Seg.v\n Dec7Seg.sv\n obj_dir/Dec7Seg\n obj_dir/Dec7Seg.v\n obj_dir/Dec7Seg.sv\n%Error: Exiting due to 1 error(s)\n"

module

module Display7Seg( input [31:0] userID_score, output[6:0] display0, output[6:0] display1, output[6:0] display2, output[6:0] display3, output[6:0] display4, output[6:0] display5, output[6:0] display6, output[6:0] display7 ); Dec7Seg _display0(userID_score[31:28],display7), _display1(userID_score[27:24],display6), _display2(userID_score[23:20],display5), _display3(userID_score[19:16],display4), _display4(userID_score[15:12],display3), _display5(userID_score[11:8],display2), _display6(userID_score[7:4],display1), _display7(userID_score[3:0],display0); endmodule

module Display7Seg( input [31:0] userID_score, output[6:0] display0, output[6:0] display1, output[6:0] display2, output[6:0] display3, output[6:0] display4, output[6:0] display5, output[6:0] display6, output[6:0] display7 );

Dec7Seg _display0(userID_score[31:28],display7), _display1(userID_score[27:24],display6), _display2(userID_score[23:20],display5), _display3(userID_score[19:16],display4), _display4(userID_score[15:12],display3), _display5(userID_score[11:8],display2), _display6(userID_score[7:4],display1), _display7(userID_score[3:0],display0); endmodule

"data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/retiming/NV_(...TRUNCATED)

NV_NVDLA_RT_csc2cmac_a.v

v

[]

['open hardware license', 'open source project']

[]

[Errno 2] No such file or directory: 'preprocess.output'

"1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vm(...TRUNCATED)

module

"module NV_NVDLA_RT_csc2cmac_a (\r\n nvdla_core_clk\r\n ,nvdla_core_rstn\r\n ,sc2mac_wt_src_pvld(...TRUNCATED)

"module NV_NVDLA_RT_csc2cmac_a (\r\n nvdla_core_clk\r\n ,nvdla_core_rstn\r\n ,sc2mac_wt_src_pvld(...TRUNCATED)

"\r\n\r\n\n\n\ninput nvdla_core_clk;\r\ninput nvdla_core_rstn;\r\n\r\ninput sc2mac_wt_src_(...TRUNCATED)

data/full_repos/permissive/93755996/Project9.1_VGA_16_Color/VGA_Output.v

VGA_Output.v

v

[]

[]

[]

[(1, 27)]

data/verilator_xmls/2670e672-faed-4ed2-848b-814a2e697e4e.xml

module

"module VGA_Output (\r\n input [8:0] RrrGggBbb,\r\n input i_VGA_HSync,\r\n input i_VGA_VSync,\r\n(...TRUNCATED)

"module VGA_Output (\r\n input [8:0] RrrGggBbb,\r\n input i_VGA_HSync,\r\n input i_VGA_VSync,\r\n(...TRUNCATED)

"\r\n \r\n wire active = (i_VGA_HSync && i_VGA_VSync);\r\n\n assign o_VGA_Red_0 = active && RrrGg(...TRUNCATED)

data/full_repos/permissive/74998636/insns/insn_sltiu.v

insn_sltiu.v

v

['auto-generated']

[]

[]

line:23: before: "/"

"1: b\"%Error: data/full_repos/permissive/74998636/insns/insn_sltiu.v:5: Define or directive not def(...TRUNCATED)

module

"module rvfi_insn_sltiu (\r\n input rvfi_valid,\r\n input [`RISCV(...TRUNCATED)

"module rvfi_insn_sltiu (\r\n input rvfi_valid,\r\n input [`RISCV(...TRUNCATED)

"\r\n\r\n\n wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32;\r\n wire [`RISCV_FORMAL_(...TRUNCATED)

data/full_repos/permissive/281895416/day_9/lab1_1/src/fifo/FIFOTestBench.sv

FIFOTestBench.sv

sv

[]

[]

[]

line:68: before: "integer"

"1: b'%Warning-STMTDLY: data/full_repos/permissive/281895416/day_9/lab1_1/src/fifo/FIFOTestBench.sv:(...TRUNCATED)

module

"module FIFOTestBench();\r\nparameter RESOLUTION_H = 1280,\r\n\t\t RESOLUTION_V = 960,\r\n\t\t V_B(...TRUNCATED)

module FIFOTestBench();

"\r\nparameter RESOLUTION_H = 1280,\r\n\t\t RESOLUTION_V = 960,\r\n\t\t V_BOTTOM = 1,\r\n (...TRUNCATED)

data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v

lab7_clks.v

v

[]

[]

[]

[(24, 55), (57, 188), (190, 273), (276, 303), (306, 380)]

"1: b'%Error: data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v:294: Cannot find file contai(...TRUNCATED)

module

"module lab7_clks(\r\n input clkin,\r\n input greset,\n output clk,\r\n output digsel,\r(...TRUNCATED)

"module lab7_clks(\r\n input clkin,\r\n input greset,\n output clk,\r\n output digsel,\r(...TRUNCATED)

" \r\n \r\n wire clk_int;\r\n assign fastclk = clk_int;\r\n clk_wiz_0 my_clk(...TRUNCATED)

data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v

lab7_clks.v

v

[]

[]

[]

[(24, 55), (57, 188), (190, 273), (276, 303), (306, 380)]

"1: b'%Error: data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v:294: Cannot find file contai(...TRUNCATED)

module

"module clk_wiz_0\r\n\r\n (\n\n output clk_out1,\r\n\n input reset,\r\n output (...TRUNCATED)

"module clk_wiz_0\r\n\r\n (\n\n output clk_out1,\r\n\n input reset,\r\n output (...TRUNCATED)

"\r\n\n\nwire clk_in1_clk_wiz_0;\r\nwire clk_in2_clk_wiz_0;\r\n IBUF clkin1_ibufg\r\n (.O (clk_in(...TRUNCATED)

data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v

lab7_clks.v

v

[]

[]

[]

[(24, 55), (57, 188), (190, 273), (276, 303), (306, 380)]

"1: b'%Error: data/full_repos/permissive/469509877/rtl/libs/lab7_clks.v:294: Cannot find file contai(...TRUNCATED)

module

"module clkcntrl4(\r\n input clk_int,\r\n output seldig,\r\n output clk_out,\r\n out(...TRUNCATED)

"module clkcntrl4(\r\n input clk_int,\r\n output seldig,\r\n output clk_out,\r\n out(...TRUNCATED)

"\r\n\r\n wire XLXN_70;\r\n wire XLXN_71;\r\n wire XLXN_72;\r\n wire XLXN_74;\r\n wire XLX(...TRUNCATED)