Datasets:

gouthamsk

/

esp_idf_code

like 0

/* */ /* This header file describes this specific Xtensa processor's TIE extensions that extend basic Xtensa core functionality. It is customized to this Xtensa processor configuration. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _XTENSA_CORE_TIE_H #define _XTENSA_CORE_TIE_H #define XCHAL_CP_NUM 2 /* number of coprocessors */ #define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */ #define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */ #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ /* Basic parameters of each coprocessor: */ #define XCHAL_CP0_NAME "FPU" #define XCHAL_CP0_IDENT FPU #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ #define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ #define XCHAL_CP3_NAME "cop_ai" #define XCHAL_CP3_IDENT cop_ai #define XCHAL_CP3_SA_SIZE 208 /* size of state save area */ #define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */ #define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0.

.7) */ /* Filler info for unassigned coprocessors, to simplify arrays etc: */ #define XCHAL_CP1_SA_SIZE 0 #define XCHAL_CP1_SA_ALIGN 1 #define XCHAL_CP2_SA_SIZE 0 #define XCHAL_CP2_SA_ALIGN 1 #define XCHAL_CP4_SA_SIZE 0 #define XCHAL_CP4_SA_ALIGN 1 #define XCHAL_CP5_SA_SIZE 0 #define XCHAL_CP5_SA_ALIGN 1 #define XCHAL_CP6_SA_SIZE 0 #define XCHAL_CP6_SA_ALIGN 1 #define XCHAL_CP7_SA_SIZE 0 #define XCHAL_CP7_SA_ALIGN 1 /* Save area for non-coprocessor optional and custom (TIE) state: */ #define XCHAL_NCP_SA_SIZE 36 #define XCHAL_NCP_SA_ALIGN 4 /* Total save area for optional and custom state (NCP + CPn): */ #define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */ #define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */ /* */ #define XCHAL_NCP_SA_NUM 9 #define XCHAL_NCP_SA_LIST(s) \ XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) #define XCHAL_CP0_SA_NUM 18 #define XCHAL_CP0_SA_LIST(s) \ XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) #define XCHAL_CP1_SA_NUM 0 #define XCHAL_CP1_SA_LIST(s) /* empty */ #define XCHAL_CP2_SA_NUM 0 #define XCHAL_CP2_SA_LIST(s) /* empty */ #define XCHAL_CP3_SA_NUM 26 #define XCHAL_CP3_SA_LIST(s) \ XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_h_0, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_h_1, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_h_2, 4, 4, 4,0x0304, ur,4 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_h_3, 4, 4, 4,0x0305, ur,5 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_h_4, 4, 4, 4,0x0306, ur,6 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_0, 4, 4, 4,0x0307, ur,7 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_1, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0) #define XCHAL_CP4_SA_NUM 0 #define XCHAL_CP4_SA_LIST(s) /* empty */ #define XCHAL_CP5_SA_NUM 0 #define XCHAL_CP5_SA_LIST(s) /* empty */ #define XCHAL_CP6_SA_NUM 0 #define XCHAL_CP6_SA_LIST(s) /* empty */ #define XCHAL_CP7_SA_NUM 0 #define XCHAL_CP7_SA_LIST(s) /* empty */ /* Byte length of instruction from its first nibble (op0 field), per FLIX.

*/ #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4 /* Byte length of instruction from its first byte, per FLIX. */ #define XCHAL_BYTE0_FORMAT_LENGTHS \ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4 #endif /*_XTENSA_CORE_TIE_H*/

/* */ /* This header file contains assembly-language definitions (assembly macros, etc.) for this specific Xtensa processor's TIE extensions and options. It is customized to this Xtensa processor configuration. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _XTENSA_CORE_TIE_ASM_H #define _XTENSA_CORE_TIE_ASM_H /* Selection parameter values for save-area save/restore macros: */ /* Option vs. TIE: */ #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ /* Whether used automatically by compiler: */ #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ /* ABI handling across function calls: */ #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ /* Misc */ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI) ) /* */ .

macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Optional global registers used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 rur.THREADPTR \at1 // threadptr option s32i \at1, \ptr, .Lxchal_ofs_+0 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .endif // Optional caller-saved registers used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 1012, 4, 4 rsr.ACCLO \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+0 rsr.ACCHI \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1012, 4, 4 .

set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .endif // Optional caller-saved registers not used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 996, 4, 4 rsr.BR \at1 // boolean option s32i \at1, \ptr, .Lxchal_ofs_+0 rsr.SCOMPARE1 \at1 // conditional store option s32i \at1, \ptr, .Lxchal_ofs_+4 rsr.M0 \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+8 rsr.M1 \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+12 rsr.M2 \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+16 rsr.M3 \at1 // MAC16 option s32i \at1, \ptr, .Lxchal_ofs_+20 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 996, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .endif .endm // xchal_ncp_store /* */ .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Optional global registers used by default by the compiler: .

ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 l32i \at1, \ptr, .Lxchal_ofs_+0 wur.THREADPTR \at1 // threadptr option .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .endif // Optional caller-saved registers used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 1012, 4, 4 l32i \at1, \ptr, .Lxchal_ofs_+0 wsr.ACCLO \at1 // MAC16 option l32i \at1, \ptr, .Lxchal_ofs_+4 wsr.ACCHI \at1 // MAC16 option .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1012, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .endif // Optional caller-saved registers not used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 996, 4, 4 l32i \at1, \ptr, .

Lxchal_ofs_+0 wsr.BR \at1 // boolean option l32i \at1, \ptr, .Lxchal_ofs_+4 wsr.SCOMPARE1 \at1 // conditional store option l32i \at1, \ptr, .Lxchal_ofs_+8 wsr.M0 \at1 // MAC16 option l32i \at1, \ptr, .Lxchal_ofs_+12 wsr.M1 \at1 // MAC16 option l32i \at1, \ptr, .Lxchal_ofs_+16 wsr.M2 \at1 // MAC16 option l32i \at1, \ptr, .Lxchal_ofs_+20 wsr.M3 \at1 // MAC16 option .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 996, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .endif .endm // xchal_ncp_load #define XCHAL_NCP_NUM_ATMPS 1 /* */ #define xchal_cp_FPU_store xchal_cp0_store .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 948, 4, 4 rur.

FCR \at1 // ureg 232 s32i \at1, \ptr, .Lxchal_ofs_+0 rur.FSR \at1 // ureg 233 s32i \at1, \ptr, .Lxchal_ofs_+4 ssi f0, \ptr, .Lxchal_ofs_+8 ssi f1, \ptr, .Lxchal_ofs_+12 ssi f2, \ptr, .Lxchal_ofs_+16 ssi f3, \ptr, .Lxchal_ofs_+20 ssi f4, \ptr, .Lxchal_ofs_+24 ssi f5, \ptr, .Lxchal_ofs_+28 ssi f6, \ptr, .Lxchal_ofs_+32 ssi f7, \ptr, .Lxchal_ofs_+36 ssi f8, \ptr, .Lxchal_ofs_+40 ssi f9, \ptr, .Lxchal_ofs_+44 ssi f10, \ptr, .Lxchal_ofs_+48 ssi f11, \ptr, .Lxchal_ofs_+52 ssi f12, \ptr, .Lxchal_ofs_+56 ssi f13, \ptr, .Lxchal_ofs_+60 ssi f14, \ptr, .Lxchal_ofs_+64 ssi f15, \ptr, .Lxchal_ofs_+68 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 948, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .endif .endm // xchal_cp0_store /* */ #define xchal_cp_FPU_load xchal_cp0_load .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .

ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 948, 4, 4 l32i \at1, \ptr, .Lxchal_ofs_+0 wur.FCR \at1 // ureg 232 l32i \at1, \ptr, .Lxchal_ofs_+4 wur.FSR \at1 // ureg 233 lsi f0, \ptr, .Lxchal_ofs_+8 lsi f1, \ptr, .Lxchal_ofs_+12 lsi f2, \ptr, .Lxchal_ofs_+16 lsi f3, \ptr, .Lxchal_ofs_+20 lsi f4, \ptr, .Lxchal_ofs_+24 lsi f5, \ptr, .Lxchal_ofs_+28 lsi f6, \ptr, .Lxchal_ofs_+32 lsi f7, \ptr, .Lxchal_ofs_+36 lsi f8, \ptr, .Lxchal_ofs_+40 lsi f9, \ptr, .Lxchal_ofs_+44 lsi f10, \ptr, .Lxchal_ofs_+48 lsi f11, \ptr, .Lxchal_ofs_+52 lsi f12, \ptr, .Lxchal_ofs_+56 lsi f13, \ptr, .Lxchal_ofs_+60 lsi f14, \ptr, .Lxchal_ofs_+64 lsi f15, \ptr, .Lxchal_ofs_+68 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 948, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .endif .endm // xchal_cp0_load #define XCHAL_CP0_NUM_ATMPS 1 /* */ #define xchal_cp_cop_ai_store xchal_cp3_store .

macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 0, 16, 16 rur.ACCX_0 \at1 // ureg 0 s32i \at1, \ptr, .Lxchal_ofs_+0 rur.ACCX_1 \at1 // ureg 1 s32i \at1, \ptr, .Lxchal_ofs_+4 rur.QACC_H_0 \at1 // ureg 2 s32i \at1, \ptr, .Lxchal_ofs_+8 rur.QACC_H_1 \at1 // ureg 3 s32i \at1, \ptr, .Lxchal_ofs_+12 rur.QACC_H_2 \at1 // ureg 4 s32i \at1, \ptr, .Lxchal_ofs_+16 rur.QACC_H_3 \at1 // ureg 5 s32i \at1, \ptr, .Lxchal_ofs_+20 rur.QACC_H_4 \at1 // ureg 6 s32i \at1, \ptr, .Lxchal_ofs_+24 rur.QACC_L_0 \at1 // ureg 7 s32i \at1, \ptr, .Lxchal_ofs_+28 rur.QACC_L_1 \at1 // ureg 8 s32i \at1, \ptr, .Lxchal_ofs_+32 rur.QACC_L_2 \at1 // ureg 9 s32i \at1, \ptr, .Lxchal_ofs_+36 rur.QACC_L_3 \at1 // ureg 10 s32i \at1, \ptr, .Lxchal_ofs_+40 rur.

QACC_L_4 \at1 // ureg 11 s32i \at1, \ptr, .Lxchal_ofs_+44 rur.SAR_BYTE \at1 // ureg 13 s32i \at1, \ptr, .Lxchal_ofs_+48 rur.FFT_BIT_WIDTH \at1 // ureg 14 s32i \at1, \ptr, .Lxchal_ofs_+52 rur.UA_STATE_0 \at1 // ureg 15 s32i \at1, \ptr, .Lxchal_ofs_+56 rur.UA_STATE_1 \at1 // ureg 16 s32i \at1, \ptr, .Lxchal_ofs_+60 rur.UA_STATE_2 \at1 // ureg 17 s32i \at1, \ptr, .Lxchal_ofs_+64 rur.UA_STATE_3 \at1 // ureg 18 s32i \at1, \ptr, .Lxchal_ofs_+68 st.qr q0, \ptr, .Lxchal_ofs_+80 st.qr q1, \ptr, .Lxchal_ofs_+96 st.qr q2, \ptr, .Lxchal_ofs_+112 addi \ptr, \ptr, 128 st.qr q3, \ptr, .Lxchal_ofs_+0 st.qr q4, \ptr, .Lxchal_ofs_+16 st.qr q5, \ptr, .Lxchal_ofs_+32 st.qr q6, \ptr, .Lxchal_ofs_+48 st.qr q7, \ptr, .Lxchal_ofs_+64 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 .set .Lxchal_ofs_, .Lxchal_ofs_ + 80 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 0, 16, 16 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 .endif .endm // xchal_cp3_store /* */ #define xchal_cp_cop_ai_load xchal_cp3_load .

macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 0, 16, 16 l32i \at1, \ptr, .Lxchal_ofs_+0 wur.ACCX_0 \at1 // ureg 0 l32i \at1, \ptr, .Lxchal_ofs_+4 wur.ACCX_1 \at1 // ureg 1 l32i \at1, \ptr, .Lxchal_ofs_+8 wur.QACC_H_0 \at1 // ureg 2 l32i \at1, \ptr, .Lxchal_ofs_+12 wur.QACC_H_1 \at1 // ureg 3 l32i \at1, \ptr, .Lxchal_ofs_+16 wur.QACC_H_2 \at1 // ureg 4 l32i \at1, \ptr, .Lxchal_ofs_+20 wur.QACC_H_3 \at1 // ureg 5 l32i \at1, \ptr, .Lxchal_ofs_+24 wur.QACC_H_4 \at1 // ureg 6 l32i \at1, \ptr, .Lxchal_ofs_+28 wur.QACC_L_0 \at1 // ureg 7 l32i \at1, \ptr, .Lxchal_ofs_+32 wur.QACC_L_1 \at1 // ureg 8 l32i \at1, \ptr, .Lxchal_ofs_+36 wur.QACC_L_2 \at1 // ureg 9 l32i \at1, \ptr, .Lxchal_ofs_+40 wur.QACC_L_3 \at1 // ureg 10 l32i \at1, \ptr, .

Lxchal_ofs_+44 wur.QACC_L_4 \at1 // ureg 11 l32i \at1, \ptr, .Lxchal_ofs_+48 wur.SAR_BYTE \at1 // ureg 13 l32i \at1, \ptr, .Lxchal_ofs_+52 wur.FFT_BIT_WIDTH \at1 // ureg 14 l32i \at1, \ptr, .Lxchal_ofs_+56 wur.UA_STATE_0 \at1 // ureg 15 l32i \at1, \ptr, .Lxchal_ofs_+60 wur.UA_STATE_1 \at1 // ureg 16 l32i \at1, \ptr, .Lxchal_ofs_+64 wur.UA_STATE_2 \at1 // ureg 17 l32i \at1, \ptr, .Lxchal_ofs_+68 wur.UA_STATE_3 \at1 // ureg 18 ld.qr q0, \ptr, .Lxchal_ofs_+80 ld.qr q1, \ptr, .Lxchal_ofs_+96 ld.qr q2, \ptr, .Lxchal_ofs_+112 addi \ptr, \ptr, 128 ld.qr q3, \ptr, .Lxchal_ofs_+0 ld.qr q4, \ptr, .Lxchal_ofs_+16 ld.qr q5, \ptr, .Lxchal_ofs_+32 ld.qr q6, \ptr, .Lxchal_ofs_+48 ld.qr q7, \ptr, .Lxchal_ofs_+64 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 .set .Lxchal_ofs_, .Lxchal_ofs_ + 80 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 0, 16, 16 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 .endif .endm // xchal_cp3_load #define XCHAL_CP3_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1 /* Empty macros for unconfigured coprocessors: */ .

macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm #endif /*_XTENSA_CORE_TIE_ASM_H*/

/* */ /* Customer ID=15128; Build=0x90f1f; Copyright (c) 2000-2010 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef XTENSA_CONFIG_SYSTEM_H #define XTENSA_CONFIG_SYSTEM_H /*#include */ /* CONFIGURED SOFTWARE OPTIONS */ #define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ #define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ #define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ /* The above maps to one of the following constants: */ #define XTHAL_ABI_WINDOWED 0 #define XTHAL_ABI_CALL0 1 /* Alternatives: */ /*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ /*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ #define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ /* The above maps to one of the following constants: */ #define XTHAL_CLIB_NEWLIB 0 #define XTHAL_CLIB_UCLIBC 1 #define XTHAL_CLIB_XCLIB 2 /* Alternatives: */ /*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ /*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ /*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ #define XSHAL_USE_FLOATING_POINT 1 #define XSHAL_FLOATING_POINT_ABI 0 /* SW workarounds enabled for HW errata: */ /* SW options for functional safety: */ #define XSHAL_FUNC_SAFETY_ENABLED 0 /* DEVICE ADDRESSES */ /* */ /* I/O Block areas: */ #define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 #define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 #define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 #define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 #define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 /* System ROM: */ #define XSHAL_ROM_VADDR 0x50000000 #define XSHAL_ROM_PADDR 0x50000000 #define XSHAL_ROM_SIZE 0x01000000 /* Largest available area (free of vectors): */ #define XSHAL_ROM_AVAIL_VADDR 0x50000000 #define XSHAL_ROM_AVAIL_VSIZE 0x01000000 /* System RAM: */ #define XSHAL_RAM_VADDR 0x60000000 #define XSHAL_RAM_PADDR 0x60000000 #define XSHAL_RAM_VSIZE 0x20000000 #define XSHAL_RAM_PSIZE 0x20000000 #define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE /* Largest available area (free of vectors): */ #define XSHAL_RAM_AVAIL_VADDR 0x60000000 #define XSHAL_RAM_AVAIL_VSIZE 0x20000000 /* */ #define XSHAL_RAM_BYPASS_VADDR 0xA0000000 #define XSHAL_RAM_BYPASS_PADDR 0xA0000000 #define XSHAL_RAM_BYPASS_PSIZE 0x20000000 /* Alternate system RAM (different device than system RAM): */ /*#define XSHAL_ALTRAM_[VP]ADDR .

..not configured...*/ /*#define XSHAL_ALTRAM_SIZE ...not configured...*/ /* Some available location in which to place devices in a simulation (eg. XTMP): */ #define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 #define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 #define XSHAL_SIMIO_PADDR 0xC0000000 #define XSHAL_SIMIO_SIZE 0x20000000 /* */ #define XSHAL_MAGIC_EXIT 0x0 /* **/ /* BACKWARD COMPATIBILITY ... */ /* */ #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ /* GENERIC */ /* For the following, a 512MB region is used if it contains a system (PIF) RAM, /* These set any unused 512MB region to cache-BYPASS attribute: */ #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */ #define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ #define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ #define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* These set any unused 512MB region to ILLEGAL attribute: */ #define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */ #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ #define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ #define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* These set the first 512MB, if unused, to ILLEGAL attribute to help catch #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ #define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ #define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* ISS (Instruction Set Simulator) SPECIFIC .

.. */ /* For now, ISS defaults to the TRAPNULL settings: */ #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK #define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU #define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK #define XSHAL_ISS_PIPE_REGIONS 0 #define XSHAL_ISS_SDRAM_REGIONS 0 /* XT2000 BOARD SPECIFIC ... */ /* For the following, a 512MB region is used if it contains any system RAM, /* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ #define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */ #define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ #define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ #define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ #define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ /* VECTOR INFO AND SIZES */ #define XSHAL_VECTORS_PACKED 0 #define XSHAL_STATIC_VECTOR_SELECT 1 #define XSHAL_RESET_VECTOR_VADDR 0x40000400 #define XSHAL_RESET_VECTOR_PADDR 0x40000400 /* */ #define XSHAL_RESET_VECTOR_SIZE 0x00000300 #define XSHAL_RESET_VECTOR_ISROM 0 #define XSHAL_USER_VECTOR_SIZE 0x00000038 #define XSHAL_USER_VECTOR_ISROM 0 #define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 #define XSHAL_KERNEL_VECTOR_ISROM 0 #define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 #define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 #define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 #define XSHAL_WINDOW_VECTORS_ISROM 0 #define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL2_VECTOR_ISROM 0 #define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL3_VECTOR_ISROM 0 #define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL4_VECTOR_ISROM 0 #define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL5_VECTOR_ISROM 0 #define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL6_VECTOR_ISROM 0 #define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE #define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM #define XSHAL_NMI_VECTOR_SIZE 0x00000038 #define XSHAL_NMI_VECTOR_ISROM 0 #define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE #endif /*XTENSA_CONFIG_SYSTEM_H*/

/* */ /* Xtensa processor core configuration information. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H / Parameters Useful for Any Code, USER or PRIVILEGED / /* */ /* ISA */ #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ #define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ #define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */ #define XCHAL_HAVE_DEBUG 1 /* debug option */ #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ #define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ #define XCHAL_HAVE_L32R 1 /* L32R instruction */ #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ #define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.

W18 or B*.W15 instr's */ #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ #define XCHAL_HAVE_ABS 1 /* ABS instruction */ /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ #define XCHAL_HAVE_SPECULATION 0 /* speculation */ #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ #define XCHAL_NUM_CONTEXTS 1 /* */ #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ #define XCHAL_HAVE_PRID 1 /* processor ID register */ #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ #define XCHAL_HAVE_FUSION 0 /* Fusion*/ #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ #define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ #define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ #define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ #define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ #define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ #define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ #define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ #define XCHAL_HAVE_HIFI_MINI 0 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ #define XCHAL_HAVE_FP 1 /* single prec floating point */ #define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ #define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ #define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ #define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ #define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_FUSIONG 0 /* FusionG */ #define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ #define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ #define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ #define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ #define XCHAL_HAVE_PDX 0 /* PDX */ #define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ #define XCHAL_HAVE_PDX4 0 /* PDX4 */ #define XCHAL_HAVE_PDX8 0 /* PDX8 */ #define XCHAL_HAVE_PDX16 0 /* PDX16 */ #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ #define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ #define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ #define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ #define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ #define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ #define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ #define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ #define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ #define XCHAL_HAVE_VISIONC 0 /* Vision C */ /* MISC */ #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ #define XCHAL_DATA_WIDTH 16 /* data width in bytes */ #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */ #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ #define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct.

unit clock gating */ /* In T1050, applies to selected core load and store instructions (see ISA): */ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ #define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ #define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ #define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ #define XCHAL_SW_VERSION 1200012 /* sw version of this header */ #define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */ #define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */ /* */ #define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/ #define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/ #define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */ #define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ #define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */ #define XCHAL_HW_VERSION 270012 /* major*100+minor */ #define XCHAL_HW_REL_LX7 1 #define XCHAL_HW_REL_LX7_0 1 #define XCHAL_HW_REL_LX7_0_12 1 #define XCHAL_HW_CONFIGID_RELIABLE 1 /* If software targets a *range* of hardware versions, these are the bounds: */ #define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */ #define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */ /* CACHE */ #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref.

castout bufsz */ #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ / Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code / #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /* CACHE */ #define XCHAL_HAVE_PIF 1 /* any outbound bus present */ #define XCHAL_HAVE_AXI 0 /* AXI bus */ #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ #define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).

*/ /* Number of cache sets in log2(lines per way): */ #define XCHAL_ICACHE_SETWIDTH 0 #define XCHAL_DCACHE_SETWIDTH 0 /* Cache set associativity (number of ways): */ #define XCHAL_ICACHE_WAYS 1 #define XCHAL_DCACHE_WAYS 1 /* Cache features: */ #define XCHAL_ICACHE_LINE_LOCKABLE 0 #define XCHAL_DCACHE_LINE_LOCKABLE 0 #define XCHAL_ICACHE_ECC_PARITY 0 #define XCHAL_DCACHE_ECC_PARITY 0 #define XCHAL_ICACHE_ECC_WIDTH 1 #define XCHAL_DCACHE_ECC_WIDTH 1 /* Cache access size in bytes (affects operation of SICW instruction): */ #define XCHAL_ICACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_BANKS 0 /* number of banks */ /* Number of encoded cache attr bits (see for decoded bits): */ #define XCHAL_CA_BITS 4 /* INTERNAL I/D RAM/ROMs and XLMI */ #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ /* Instruction RAM 0: */ #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ #define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */ #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_HAVE_INSTRAM0 1 #define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ /* Data RAM 0: */ #define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */ #define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */ #define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */ #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ #define XCHAL_HAVE_DATARAM0 1 #define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ #define XCHAL_HAVE_IDMA 0 #define XCHAL_HAVE_IDMA_TRANSPOSE 0 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ /* INTERRUPTS and TIMERS */ #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri.

interrupts */ #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero) */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* Masks of interrupts at each interrupt level: */ #define XCHAL_INTLEVEL1_MASK 0x000637FF #define XCHAL_INTLEVEL2_MASK 0x00380000 #define XCHAL_INTLEVEL3_MASK 0x28C08800 #define XCHAL_INTLEVEL4_MASK 0x53000000 #define XCHAL_INTLEVEL5_MASK 0x84010000 #define XCHAL_INTLEVEL6_MASK 0x00000000 #define XCHAL_INTLEVEL7_MASK 0x00004000 /* Masks of interrupts at each range 1.

.n of interrupt levels: */ #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF /* Level of each interrupt: */ #define XCHAL_INT0_LEVEL 1 #define XCHAL_INT1_LEVEL 1 #define XCHAL_INT2_LEVEL 1 #define XCHAL_INT3_LEVEL 1 #define XCHAL_INT4_LEVEL 1 #define XCHAL_INT5_LEVEL 1 #define XCHAL_INT6_LEVEL 1 #define XCHAL_INT7_LEVEL 1 #define XCHAL_INT8_LEVEL 1 #define XCHAL_INT9_LEVEL 1 #define XCHAL_INT10_LEVEL 1 #define XCHAL_INT11_LEVEL 3 #define XCHAL_INT12_LEVEL 1 #define XCHAL_INT13_LEVEL 1 #define XCHAL_INT14_LEVEL 7 #define XCHAL_INT15_LEVEL 3 #define XCHAL_INT16_LEVEL 5 #define XCHAL_INT17_LEVEL 1 #define XCHAL_INT18_LEVEL 1 #define XCHAL_INT19_LEVEL 2 #define XCHAL_INT20_LEVEL 2 #define XCHAL_INT21_LEVEL 2 #define XCHAL_INT22_LEVEL 3 #define XCHAL_INT23_LEVEL 3 #define XCHAL_INT24_LEVEL 4 #define XCHAL_INT25_LEVEL 4 #define XCHAL_INT26_LEVEL 5 #define XCHAL_INT27_LEVEL 3 #define XCHAL_INT28_LEVEL 4 #define XCHAL_INT29_LEVEL 3 #define XCHAL_INT30_LEVEL 4 #define XCHAL_INT31_LEVEL 5 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI #define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F #define XCHAL_INTTYPE_MASK_TIMER 0x00018040 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 #define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 #define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 #define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 #define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 /* Interrupt numbers assigned to specific interrupt sources: */ #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ #define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ #define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ #define XCHAL_PROFILING_INTERRUPT 11 /* Interrupt numbers for levels at which only one interrupt is configured: */ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.

) */ /* */ /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ #define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ #define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ #define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ #define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ #define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ #define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ #define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ #define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ #define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ #define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ #define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ #define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ #define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ #define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ #define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ #define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ #define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ #define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ #define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ #define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ #define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ #define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ #define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ #define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ #define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ #define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ #define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ #define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ #define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ #define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ #define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ #define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ #define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ /* EXCEPTIONS and VECTORS */ #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) 0 == XEAX (extern) or TX */ #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch.

*/ #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ #define XCHAL_HAVE_HALT 0 /* halt architecture option */ #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ #define XCHAL_VECBASE_RESET_PADDR 0x40000000 #define XCHAL_RESET_VECBASE_OVERLAP 0 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 #define XCHAL_RESET_VECTOR_VADDR 0x40000400 #define XCHAL_RESET_VECTOR_PADDR 0x40000400 #define XCHAL_USER_VECOFS 0x00000340 #define XCHAL_USER_VECTOR_VADDR 0x40000340 #define XCHAL_USER_VECTOR_PADDR 0x40000340 #define XCHAL_KERNEL_VECOFS 0x00000300 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 #define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 #define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000002C0 #define XCHAL_NMI_VECTOR_VADDR 0x400002C0 #define XCHAL_NMI_VECTOR_PADDR 0x400002C0 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR /* DEBUG MODULE */ /* Misc */ #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ /* On-Chip Debug (OCD) */ #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ /* TRAX (in core) */ #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ #define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig.

*/ #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ /* Perf counters */ #define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ /* MMU */ /* See core-matmap.h header file for more details. */ #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ /* If none of the above last 5 are set, it's a custom TLB configuration. */ #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ #define XCHAL_MMU_RINGS 1 /* number of rings (1.

.4) */ #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ /* MPU */ #define XCHAL_HAVE_MPU 0 #define XCHAL_MPU_ENTRIES 0 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ #define XCHAL_MPU_ALIGN_BITS 0 #define XCHAL_MPU_ALIGN 0 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* _XTENSA_CORE_CONFIGURATION_H */

/* */ /* Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

/* */ /* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ /* Customer ID=15128; Build=0x90f1f; Copyright (c) 1998-2002 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H /* Include these special register bitfield definitions, for historical reasons: */ #include /* Special registers: */ #define LBEG 0 #define LEND 1 #define LCOUNT 2 #define SAR 3 #define BR 4 #define SCOMPARE1 12 #define ACCLO 16 #define ACCHI 17 #define MR_0 32 #define MR_1 33 #define MR_2 34 #define MR_3 35 #define WINDOWBASE 72 #define WINDOWSTART 73 #define IBREAKENABLE 96 #define MEMCTL 97 #define ATOMCTL 99 #define DDR 104 #define IBREAKA_0 128 #define IBREAKA_1 129 #define DBREAKA_0 144 #define DBREAKA_1 145 #define DBREAKC_0 160 #define DBREAKC_1 161 #define CONFIGID0 176 #define EPC_1 177 #define EPC_2 178 #define EPC_3 179 #define EPC_4 180 #define EPC_5 181 #define EPC_6 182 #define EPC_7 183 #define DEPC 192 #define EPS_2 194 #define EPS_3 195 #define EPS_4 196 #define EPS_5 197 #define EPS_6 198 #define EPS_7 199 #define CONFIGID1 208 #define EXCSAVE_1 209 #define EXCSAVE_2 210 #define EXCSAVE_3 211 #define EXCSAVE_4 212 #define EXCSAVE_5 213 #define EXCSAVE_6 214 #define EXCSAVE_7 215 #define CPENABLE 224 #define INTERRUPT 226 #define INTENABLE 228 #define PS 230 #define VECBASE 231 #define EXCCAUSE 232 #define DEBUGCAUSE 233 #define CCOUNT 234 #define PRID 235 #define ICOUNT 236 #define ICOUNTLEVEL 237 #define EXCVADDR 238 #define CCOMPARE_0 240 #define CCOMPARE_1 241 #define CCOMPARE_2 242 #define MISC_REG_0 244 #define MISC_REG_1 245 #define MISC_REG_2 246 #define MISC_REG_3 247 /* Special cases (bases of special register series): */ #define MR 32 #define IBREAKA 128 #define DBREAKA 144 #define DBREAKC 160 #define EPC 176 #define EPS 192 #define EXCSAVE 208 #define CCOMPARE 240 /* Special names for read-only and write-only interrupt registers: */ #define INTREAD 226 #define INTSET 226 #define INTCLEAR 227 #endif /* XTENSA_SPECREG_H */

/* */ // Copyright 2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #pragma once #define DSRSET 0x10200C

/* Definitions for Xtensa instructions, types, and protos. */ /* Copyright (c) 2003-2004 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ /* NOTE: This file exists only for backward compatibility with T1050 and earlier Xtensa releases. It includes only a subset of the available header files. */ #ifndef _XTENSA_BASE_HEADER #define _XTENSA_BASE_HEADER #ifdef __XTENSA__ #endif /* __XTENSA__ */ #endif /* !_XTENSA_BASE_HEADER */

/* */ /* */ #ifndef XTENSA_CONFIG_CORE_H #define XTENSA_CONFIG_CORE_H /* CONFIGURATION INDEPENDENT DEFINITIONS: */ #ifdef __XTENSA__ #include #include #else #include "../hal.h" #include "../xtensa-versions.h" #endif /* CONFIGURATION SPECIFIC DEFINITIONS: */ #ifdef __XTENSA__ #include #include #include #else #include "core-isa.h" #include "core-matmap.h" #include "tie.h" #endif #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) #ifdef __XTENSA__ #include #else #include "tie-asm.h" #endif #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ #ifdef __cplusplus extern "C" { #endif /* GENERAL */ /* */ /* Element separator for macros that expand into 1-dimensional arrays: */ #ifndef XCHAL_SEP #define XCHAL_SEP , #endif /* Array separator for macros that expand into 2-dimensional arrays: */ #ifndef XCHAL_SEP2 #define XCHAL_SEP2 },{ #endif /* ERRATA */ /* */ #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) !

= 0 \ || XCHAL_HW_RELEASE_AT(1050,0))) /* */ #if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ XCHAL_HW_MIN_VERSION = XTENSA_HWVERSION_RE_2012_0 && \ XCHAL_HW_MIN_VERSION = XTENSA_HWVERSION_RG_2015_0 && \ XCHAL_HW_MIN_VERSION . (Note that these have slightly */ #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ /*10.

.15 reserved*/ #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ /*21..23 reserved*/ #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ /*30..31 reserved*/ #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ /*40.

.63 reserved*/ /* */ /* DBREAKC (special register number 160): */ #define XCHAL_DBREAKC_VALIDMASK 0xC000003F #define XCHAL_DBREAKC_MASK_BITS 6 #define XCHAL_DBREAKC_MASK_NUM 64 #define XCHAL_DBREAKC_MASK_SHIFT 0 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F #define XCHAL_DBREAKC_LOADBREAK_BITS 1 #define XCHAL_DBREAKC_LOADBREAK_NUM 2 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 #define XCHAL_DBREAKC_STOREBREAK_BITS 1 #define XCHAL_DBREAKC_STOREBREAK_NUM 2 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* PS (special register number 230): */ #define XCHAL_PS_VALIDMASK 0x00070F3F #define XCHAL_PS_INTLEVEL_BITS 4 #define XCHAL_PS_INTLEVEL_NUM 16 #define XCHAL_PS_INTLEVEL_SHIFT 0 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F #define XCHAL_PS_EXCM_BITS 1 #define XCHAL_PS_EXCM_NUM 2 #define XCHAL_PS_EXCM_SHIFT 4 #define XCHAL_PS_EXCM_MASK 0x00000010 #define XCHAL_PS_UM_BITS 1 #define XCHAL_PS_UM_NUM 2 #define XCHAL_PS_UM_SHIFT 5 #define XCHAL_PS_UM_MASK 0x00000020 #define XCHAL_PS_RING_BITS 2 #define XCHAL_PS_RING_NUM 4 #define XCHAL_PS_RING_SHIFT 6 #define XCHAL_PS_RING_MASK 0x000000C0 #define XCHAL_PS_OWB_BITS 4 #define XCHAL_PS_OWB_NUM 16 #define XCHAL_PS_OWB_SHIFT 8 #define XCHAL_PS_OWB_MASK 0x00000F00 #define XCHAL_PS_CALLINC_BITS 2 #define XCHAL_PS_CALLINC_NUM 4 #define XCHAL_PS_CALLINC_SHIFT 16 #define XCHAL_PS_CALLINC_MASK 0x00030000 #define XCHAL_PS_WOE_BITS 1 #define XCHAL_PS_WOE_NUM 2 #define XCHAL_PS_WOE_SHIFT 18 #define XCHAL_PS_WOE_MASK 0x00040000 /* EXCCAUSE (special register number 232): */ #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F #define XCHAL_EXCCAUSE_BITS 6 #define XCHAL_EXCCAUSE_NUM 64 #define XCHAL_EXCCAUSE_SHIFT 0 #define XCHAL_EXCCAUSE_MASK 0x0000003F /* DEBUGCAUSE (special register number 233): */ #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* TIMERS */ /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ /* INTERNAL I/D RAM/ROMs and XLMI */ #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ /* CACHE */ /* Default PREFCTL value to enable prefetch.

*/ #if XCHAL_HW_MIN_VERSION = 16) && XCHAL_HAVE_CACHE_BLOCKOPS) #define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ #elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS) #define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ #else #define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ #endif /* Max for both I-cache and D-cache (used for general alignment): */ #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE #else # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE #endif #define XCHAL_ICACHE_SETSIZE (1 XCHAL_DCACHE_SETWIDTH # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE #else # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE #endif /* Instruction cache tag bits: */ #define XCHAL_ICACHE_TAG_V_SHIFT 0 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ #if XCHAL_ICACHE_WAYS > 1 # define XCHAL_ICACHE_TAG_F_SHIFT 1 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ #else # define XCHAL_ICACHE_TAG_F_SHIFT 0 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ #endif #if XCHAL_ICACHE_LINE_LOCKABLE # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) # define XCHAL_ICACHE_TAG_L (1 1 # define XCHAL_DCACHE_TAG_F_SHIFT 1 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ #else # define XCHAL_DCACHE_TAG_F_SHIFT 0 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ #endif #if XCHAL_DCACHE_IS_WRITEBACK # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) # define XCHAL_DCACHE_TAG_D (1 0) || \ XCHAL_DCACHE_IS_COHERENT || \ XCHAL_HAVE_ICACHE_DYN_WAYS || \ XCHAL_HAVE_DCACHE_DYN_WAYS) && \ (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) #if XCHAL_DCACHE_IS_COHERENT #define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ #else #define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ #endif #if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 #define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ #else #define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ #endif /* Default MEMCTL values: */ #if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS #define XCHAL_CACHE_MEMCTL_DEFAULT (0xFFFFFF00 | _MEMCTL_L0IBUF_EN) #else #define XCHAL_CACHE_MEMCTL_DEFAULT (0x00000000 | _MEMCTL_L0IBUF_EN) #endif #define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) /* MMU */ /* See for more details.

*/ /* Has different semantic in open source headers (where it means HAVE_PTP_MMU), so comment out starting with RB-2008.3 release; later, might get get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */ /*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ /* Indexing macros: */ #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) /* */ /* Number of entries per autorefill way: */ #define XCHAL_ITLB_ARF_ENTRIES (1 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ #else # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ #endif #endif /* */ #if XCHAL_HAVE_PTP_MMU && !

XCHAL_HAVE_SPANNING_WAY #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!

!!) */ #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ #endif /* MISC */ /* Data alignment required if used for instructions: */ #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH #else # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH #endif /* */ #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME /* COPROCESSORS and EXTRA STATE */ #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) /* Invoked at start of save area load/store sequence macro to setup macro */ .

macro xchal_sa_start continue totofs .ifeq \continue .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ .endif .if \totofs + 1 /* if totofs specified (not -1) */ .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ .endif .endm /* Align portion of save area and bring ptr in range if necessary. : XTHAL_MAYBE ) # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ : XTHAL_MAYBE ) # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) = 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) #endif #ifdef __cplusplus } #endif #endif /*XTENSA_CONFIG_CORE_H*/

/* */ /* This header file describes this specific Xtensa processor's TIE extensions that extend basic Xtensa core functionality. It is customized to this Xtensa processor configuration. Copyright (c) 1999-2018 Cadence Design Systems Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _XTENSA_CORE_TIE_H #define _XTENSA_CORE_TIE_H #define XCHAL_CP_NUM 0 /* number of coprocessors */ #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ /* Save area for non-coprocessor optional and custom (TIE) state: */ #define XCHAL_NCP_SA_SIZE 4 #define XCHAL_NCP_SA_ALIGN 4 /* Total save area for optional and custom state (NCP + CPn): */ #define XCHAL_TOTAL_SA_SIZE 16 /* with 16-byte align padding */ #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ /* */ #define XCHAL_NCP_SA_NUM 1 #define XCHAL_NCP_SA_LIST(s) \ XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) #define XCHAL_CP0_SA_NUM 0 #define XCHAL_CP0_SA_LIST(s) /* empty */ #define XCHAL_CP1_SA_NUM 0 #define XCHAL_CP1_SA_LIST(s) /* empty */ #define XCHAL_CP2_SA_NUM 0 #define XCHAL_CP2_SA_LIST(s) /* empty */ #define XCHAL_CP3_SA_NUM 0 #define XCHAL_CP3_SA_LIST(s) /* empty */ #define XCHAL_CP4_SA_NUM 0 #define XCHAL_CP4_SA_LIST(s) /* empty */ #define XCHAL_CP5_SA_NUM 0 #define XCHAL_CP5_SA_LIST(s) /* empty */ #define XCHAL_CP6_SA_NUM 0 #define XCHAL_CP6_SA_LIST(s) /* empty */ #define XCHAL_CP7_SA_NUM 0 #define XCHAL_CP7_SA_LIST(s) /* empty */ /* Byte length of instruction from its first nibble (op0 field), per FLIX.

*/ #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 /* Byte length of instruction from its first byte, per FLIX. */ #define XCHAL_BYTE0_FORMAT_LENGTHS \ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 #endif /*_XTENSA_CORE_TIE_H*/

/* */ /* This header file contains assembly-language definitions (assembly macros, etc.) for this specific Xtensa processor's TIE extensions and options. It is customized to this Xtensa processor configuration. Copyright (c) 1999-2018 Cadence Design Systems Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _XTENSA_CORE_TIE_ASM_H #define _XTENSA_CORE_TIE_ASM_H #ifdef __cplusplus extern "C" { #endif /* Selection parameter values for save-area save/restore macros: */ /* Option vs. TIE: */ #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ /* Whether used automatically by compiler: */ #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ /* ABI handling across function calls: */ #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ /* Misc */ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI) ) /* */ .

macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Optional global registers used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 rur.THREADPTR \at1 // threadptr option s32i \at1, \ptr, .Lxchal_ofs_+0 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .endif .endm // xchal_ncp_store /* */ .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 xchal_sa_start \continue, \ofs // Optional global registers used by default by the compiler: .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 l32i \at1, \ptr, .Lxchal_ofs_+0 wur.THREADPTR \at1 // threadptr option .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .

elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .endif .endm // xchal_ncp_load #define XCHAL_NCP_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1 #ifdef __cplusplus } #endif #endif /*_XTENSA_CORE_TIE_ASM_H*/

/* */ /* Copyright (c) 2000-2010 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef XTENSA_CONFIG_SYSTEM_H #define XTENSA_CONFIG_SYSTEM_H /*#include */ /* CONFIGURED SOFTWARE OPTIONS */ #define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ #define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ #define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ /* The above maps to one of the following constants: */ #define XTHAL_ABI_WINDOWED 0 #define XTHAL_ABI_CALL0 1 /* Alternatives: */ /*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ /*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ #define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ /* The above maps to one of the following constants: */ #define XTHAL_CLIB_NEWLIB 0 #define XTHAL_CLIB_UCLIBC 1 #define XTHAL_CLIB_XCLIB 2 /* Alternatives: */ /*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ /*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ /*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ #define XSHAL_USE_FLOATING_POINT 1 #define XSHAL_FLOATING_POINT_ABI 0 /* SW workarounds enabled for HW errata: */ /* SW options for functional safety: */ #define XSHAL_FUNC_SAFETY_ENABLED 0 /* DEVICE ADDRESSES */ /* */ /* I/O Block areas: */ #define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 #define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 #define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 #define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 #define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 /* System ROM: */ #define XSHAL_ROM_VADDR 0x50000000 #define XSHAL_ROM_PADDR 0x50000000 #define XSHAL_ROM_SIZE 0x01000000 /* Largest available area (free of vectors): */ #define XSHAL_ROM_AVAIL_VADDR 0x50000000 #define XSHAL_ROM_AVAIL_VSIZE 0x01000000 /* System RAM: */ #define XSHAL_RAM_VADDR 0x60000000 #define XSHAL_RAM_PADDR 0x60000000 #define XSHAL_RAM_VSIZE 0x20000000 #define XSHAL_RAM_PSIZE 0x20000000 #define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE /* Largest available area (free of vectors): */ #define XSHAL_RAM_AVAIL_VADDR 0x60000000 #define XSHAL_RAM_AVAIL_VSIZE 0x20000000 /* */ #define XSHAL_RAM_BYPASS_VADDR 0xA0000000 #define XSHAL_RAM_BYPASS_PADDR 0xA0000000 #define XSHAL_RAM_BYPASS_PSIZE 0x20000000 /* Alternate system RAM (different device than system RAM): */ /*#define XSHAL_ALTRAM_[VP]ADDR .

..not configured...*/ /*#define XSHAL_ALTRAM_SIZE ...not configured...*/ /* Some available location in which to place devices in a simulation (eg. XTMP): */ #define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 #define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 #define XSHAL_SIMIO_PADDR 0xC0000000 #define XSHAL_SIMIO_SIZE 0x20000000 /* */ #define XSHAL_MAGIC_EXIT 0x0 /* **/ /* BACKWARD COMPATIBILITY ... */ /* */ #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ /* GENERIC */ /* For the following, a 512MB region is used if it contains a system (PIF) RAM, /* These set any unused 512MB region to cache-BYPASS attribute: */ #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */ #define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ #define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ #define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* These set any unused 512MB region to ILLEGAL attribute: */ #define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */ #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ #define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ #define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* These set the first 512MB, if unused, to ILLEGAL attribute to help catch #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ #define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ #define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ /* ISS (Instruction Set Simulator) SPECIFIC .

.. */ /* For now, ISS defaults to the TRAPNULL settings: */ #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK #define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU #define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK #define XSHAL_ISS_PIPE_REGIONS 0 #define XSHAL_ISS_SDRAM_REGIONS 0 /* XT2000 BOARD SPECIFIC ... */ /* For the following, a 512MB region is used if it contains any system RAM, /* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ #define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */ #define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ #define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ #define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ #define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ /* VECTOR INFO AND SIZES */ #define XSHAL_VECTORS_PACKED 0 #define XSHAL_STATIC_VECTOR_SELECT 1 #define XSHAL_RESET_VECTOR_VADDR 0x40000400 #define XSHAL_RESET_VECTOR_PADDR 0x40000400 /* */ #define XSHAL_RESET_VECTOR_SIZE 0x00000300 #define XSHAL_RESET_VECTOR_ISROM 0 #define XSHAL_USER_VECTOR_SIZE 0x00000038 #define XSHAL_USER_VECTOR_ISROM 0 #define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 #define XSHAL_KERNEL_VECTOR_ISROM 0 #define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ #define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 #define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 #define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 #define XSHAL_WINDOW_VECTORS_ISROM 0 #define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL2_VECTOR_ISROM 0 #define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL3_VECTOR_ISROM 0 #define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL4_VECTOR_ISROM 0 #define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL5_VECTOR_ISROM 0 #define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 #define XSHAL_INTLEVEL6_VECTOR_ISROM 0 #define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE #define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM #define XSHAL_NMI_VECTOR_SIZE 0x00000038 #define XSHAL_NMI_VECTOR_ISROM 0 #define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE #endif /*XTENSA_CONFIG_SYSTEM_H*/

/* */ /* Xtensa processor core configuration information. Copyright (c) 1999-2018 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H / Parameters Useful for Any Code, USER or PRIVILEGED / /* */ /* ISA */ #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ #define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ #define XCHAL_HAVE_DEBUG 1 /* debug option */ #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ #define XCHAL_HAVE_L32R 1 /* L32R instruction */ #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ #define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.

W18 or B*.W15 instr's */ #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ #define XCHAL_HAVE_ABS 1 /* ABS instruction */ /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ #define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ #define XCHAL_HAVE_SPECULATION 0 /* speculation */ #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ #define XCHAL_NUM_CONTEXTS 1 /* */ #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ #define XCHAL_HAVE_PRID 1 /* processor ID register */ #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ #define XCHAL_HAVE_FUSION 0 /* Fusion*/ #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ #define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ #define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ #define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ #define XCHAL_HAVE_HIFI_MINI 0 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ #define XCHAL_HAVE_FP 0 /* single prec floating point */ #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_FUSIONG 0 /* FusionG */ #define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ #define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ #define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ #define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ #define XCHAL_HAVE_PDX 0 /* PDX */ #define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ #define XCHAL_HAVE_PDX4 0 /* PDX4 */ #define XCHAL_HAVE_PDX8 0 /* PDX8 */ #define XCHAL_HAVE_PDX16 0 /* PDX16 */ #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ #define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ #define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ #define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ #define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ #define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ #define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ #define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ #define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ #define XCHAL_HAVE_VISIONC 0 /* Vision C */ /* MISC */ #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ #define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */ #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct.

unit clock gating */ /* In T1050, applies to selected core load and store instructions (see ISA): */ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ #define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ #define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ #define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ #define XCHAL_SW_VERSION 1200008 /* sw version of this header */ #define XCHAL_CORE_ID "test_0731_1_TIE_GPIO_f" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */ #define XCHAL_BUILD_UNIQUE_ID 0x00075F76 /* 22-bit sw build ID */ /* */ #define XCHAL_HW_CONFIGID0 0xC2ECFAFE /* ConfigID hi 32 bits*/ #define XCHAL_HW_CONFIGID1 0x22075F76 /* ConfigID lo 32 bits*/ #define XCHAL_HW_VERSION_NAME "LX7.0.8" /* full version name */ #define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ #define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ #define XCHAL_HW_VERSION 270008 /* major*100+minor */ #define XCHAL_HW_REL_LX7 1 #define XCHAL_HW_REL_LX7_0 1 #define XCHAL_HW_REL_LX7_0_8 1 #define XCHAL_HW_CONFIGID_RELIABLE 1 /* If software targets a *range* of hardware versions, these are the bounds: */ #define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ #define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */ #define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 270008 /* latest targeted hw */ /* CACHE */ #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref.

castout bufsz */ #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ / Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code / #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /* CACHE */ #define XCHAL_HAVE_PIF 1 /* any outbound bus present */ #define XCHAL_HAVE_AXI 0 /* AXI bus */ #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ #define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).

*/ /* Number of cache sets in log2(lines per way): */ #define XCHAL_ICACHE_SETWIDTH 0 #define XCHAL_DCACHE_SETWIDTH 0 /* Cache set associativity (number of ways): */ #define XCHAL_ICACHE_WAYS 1 #define XCHAL_DCACHE_WAYS 1 /* Cache features: */ #define XCHAL_ICACHE_LINE_LOCKABLE 0 #define XCHAL_DCACHE_LINE_LOCKABLE 0 #define XCHAL_ICACHE_ECC_PARITY 0 #define XCHAL_DCACHE_ECC_PARITY 0 /* Cache access size in bytes (affects operation of SICW instruction): */ #define XCHAL_ICACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_BANKS 0 /* number of banks */ /* Number of encoded cache attr bits (see for decoded bits): */ #define XCHAL_CA_BITS 4 /* INTERNAL I/D RAM/ROMs and XLMI */ #define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ #define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ /* Instruction ROM 0: */ #define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ #define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ #define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Instruction RAM 0: */ #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ #define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_HAVE_INSTRAM0 1 #define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ /* Instruction RAM 1: */ #define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ #define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ #define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_HAVE_INSTRAM1 1 #define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ /* Data ROM 0: */ #define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ #define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ #define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ #define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATAROM0_BANKS 1 /* number of banks */ /* Data RAM 0: */ #define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ #define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ #define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ #define XCHAL_HAVE_DATARAM0 1 #define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ /* Data RAM 1: */ #define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ #define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ #define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ #define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATARAM1_BANKS 1 /* number of banks */ #define XCHAL_HAVE_DATARAM1 1 #define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ /* XLMI Port 0: */ #define XCHAL_XLMI0_VADDR 0x3FE00000 /* virtual address */ #define XCHAL_XLMI0_PADDR 0x3FE00000 /* physical address */ #define XCHAL_XLMI0_SIZE 1048576 /* size in bytes */ #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_HAVE_IDMA 0 #define XCHAL_HAVE_IDMA_TRANSPOSE 0 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ /* INTERRUPTS and TIMERS */ #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri.

interrupts */ #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero) */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* Masks of interrupts at each interrupt level: */ #define XCHAL_INTLEVEL1_MASK 0x000637FF #define XCHAL_INTLEVEL2_MASK 0x00380000 #define XCHAL_INTLEVEL3_MASK 0x28C08800 #define XCHAL_INTLEVEL4_MASK 0x53000000 #define XCHAL_INTLEVEL5_MASK 0x84010000 #define XCHAL_INTLEVEL6_MASK 0x00000000 #define XCHAL_INTLEVEL7_MASK 0x00004000 /* Masks of interrupts at each range 1.

.n of interrupt levels: */ #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF /* Level of each interrupt: */ #define XCHAL_INT0_LEVEL 1 #define XCHAL_INT1_LEVEL 1 #define XCHAL_INT2_LEVEL 1 #define XCHAL_INT3_LEVEL 1 #define XCHAL_INT4_LEVEL 1 #define XCHAL_INT5_LEVEL 1 #define XCHAL_INT6_LEVEL 1 #define XCHAL_INT7_LEVEL 1 #define XCHAL_INT8_LEVEL 1 #define XCHAL_INT9_LEVEL 1 #define XCHAL_INT10_LEVEL 1 #define XCHAL_INT11_LEVEL 3 #define XCHAL_INT12_LEVEL 1 #define XCHAL_INT13_LEVEL 1 #define XCHAL_INT14_LEVEL 7 #define XCHAL_INT15_LEVEL 3 #define XCHAL_INT16_LEVEL 5 #define XCHAL_INT17_LEVEL 1 #define XCHAL_INT18_LEVEL 1 #define XCHAL_INT19_LEVEL 2 #define XCHAL_INT20_LEVEL 2 #define XCHAL_INT21_LEVEL 2 #define XCHAL_INT22_LEVEL 3 #define XCHAL_INT23_LEVEL 3 #define XCHAL_INT24_LEVEL 4 #define XCHAL_INT25_LEVEL 4 #define XCHAL_INT26_LEVEL 5 #define XCHAL_INT27_LEVEL 3 #define XCHAL_INT28_LEVEL 4 #define XCHAL_INT29_LEVEL 3 #define XCHAL_INT30_LEVEL 4 #define XCHAL_INT31_LEVEL 5 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI #define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F #define XCHAL_INTTYPE_MASK_TIMER 0x00018040 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 #define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 #define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 #define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 #define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 /* Interrupt numbers assigned to specific interrupt sources: */ #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ #define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ #define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ #define XCHAL_PROFILING_INTERRUPT 11 /* Interrupt numbers for levels at which only one interrupt is configured: */ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.

) */ /* */ /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ #define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ #define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ #define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ #define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ #define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ #define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ #define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ #define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ #define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ #define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ #define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ #define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ #define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ #define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ #define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ #define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ #define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ #define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ #define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ #define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ #define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ #define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ #define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ #define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ #define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ #define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ #define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ #define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ #define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ #define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ #define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ #define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ #define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ /* EXCEPTIONS and VECTORS */ #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) 0 == XEAX (extern) or TX */ #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch.

*/ #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ #define XCHAL_HAVE_HALT 0 /* halt architecture option */ #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ #define XCHAL_VECBASE_RESET_PADDR 0x40000000 #define XCHAL_RESET_VECBASE_OVERLAP 0 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 #define XCHAL_RESET_VECTOR_VADDR 0x40000400 #define XCHAL_RESET_VECTOR_PADDR 0x40000400 #define XCHAL_USER_VECOFS 0x00000340 #define XCHAL_USER_VECTOR_VADDR 0x40000340 #define XCHAL_USER_VECTOR_PADDR 0x40000340 #define XCHAL_KERNEL_VECOFS 0x00000300 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 #define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 #define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000002C0 #define XCHAL_NMI_VECTOR_VADDR 0x400002C0 #define XCHAL_NMI_VECTOR_PADDR 0x400002C0 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR /* DEBUG MODULE */ /* Misc */ #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ /* On-Chip Debug (OCD) */ #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ /* TRAX (in core) */ #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ #define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig.

*/ #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ /* Perf counters */ #define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ /* MMU */ /* See core-matmap.h header file for more details. */ #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ /* If none of the above last 5 are set, it's a custom TLB configuration. */ #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ #define XCHAL_MMU_RINGS 1 /* number of rings (1.

.4) */ #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ /* MPU */ #define XCHAL_HAVE_MPU 0 #define XCHAL_MPU_ENTRIES 0 #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ #define XCHAL_MPU_ALIGN_BITS 0 #define XCHAL_MPU_ALIGN 0 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* _XTENSA_CORE_CONFIGURATION_H */

/* */ /* Copyright (c) 1999-2018 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

/* */ /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ /* Copyright (c) 1998-2002 Tensilica Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H /* Include these special register bitfield definitions, for historical reasons: */ #include /* Special registers: */ #define SAR 3 #define WINDOWBASE 72 #define WINDOWSTART 73 #define IBREAKENABLE 96 #define DDR 104 #define IBREAKA_0 128 #define IBREAKA_1 129 #define DBREAKA_0 144 #define DBREAKA_1 145 #define DBREAKC_0 160 #define DBREAKC_1 161 #define CONFIGID0 176 #define EPC_1 177 #define EPC_2 178 #define EPC_3 179 #define EPC_4 180 #define EPC_5 181 #define EPC_6 182 #define EPC_7 183 #define DEPC 192 #define EPS_2 194 #define EPS_3 195 #define EPS_4 196 #define EPS_5 197 #define EPS_6 198 #define EPS_7 199 #define CONFIGID1 208 #define EXCSAVE_1 209 #define EXCSAVE_2 210 #define EXCSAVE_3 211 #define EXCSAVE_4 212 #define EXCSAVE_5 213 #define EXCSAVE_6 214 #define EXCSAVE_7 215 #define CPENABLE 224 #define INTERRUPT 226 #define INTENABLE 228 #define PS 230 #define VECBASE 231 #define EXCCAUSE 232 #define DEBUGCAUSE 233 #define CCOUNT 234 #define PRID 235 #define ICOUNT 236 #define ICOUNTLEVEL 237 #define EXCVADDR 238 #define CCOMPARE_0 240 #define CCOMPARE_1 241 #define CCOMPARE_2 242 #define MISC_REG_0 244 #define MISC_REG_1 245 #define MISC_REG_2 246 #define MISC_REG_3 247 /* Special cases (bases of special register series): */ #define IBREAKA 128 #define DBREAKA 144 #define DBREAKC 160 #define EPC 176 #define EPS 192 #define EXCSAVE 208 #define CCOMPARE 240 /* Special names for read-only and write-only interrupt registers: */ #define INTREAD 226 #define INTSET 226 #define INTCLEAR 227 #endif /* XTENSA_SPECREG_H */

/* */ // Copyright 2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #pragma once #define DSRSET 0x10200C

/* */ #ifndef ESP_CORE_DUMP_H_ #define ESP_CORE_DUMP_H_ #include "sdkconfig.h" #include #include "esp_err.h" #include "esp_private/panic_internal.h" #include "esp_core_dump_summary_port.h" #ifdef __cplusplus extern "C" { #endif #define APP_ELF_SHA256_SZ (CONFIG_APP_RETRIEVE_LEN_ELF_SHA + 1) #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF /** */ typedef struct { uint32_t exc_tcb; /*!< TCB pointer to the task causing exception */ char exc_task[16]; /*!< Name of the task that caused exception */ uint32_t exc_pc; /*!< Program counter for exception */ esp_core_dump_bt_info_t exc_bt_info; /*!< Backtrace information for task causing exception */ uint32_t core_dump_version; /*!< Core dump version */ uint8_t app_elf_sha256[APP_ELF_SHA256_SZ]; /*!< Crashing application's SHA256 sum as a string */ esp_core_dump_summary_extra_info_t ex_info; /*!

< Architecture specific extra data */ } esp_core_dump_summary_t; #endif /* CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF */ // / EXCEPTION MODE API / // /** */ void esp_core_dump_init(void); // / USER MODE API / // /** /** */ void esp_core_dump_write(panic_info_t *info); /** */ esp_err_t esp_core_dump_image_check(void); /** */ esp_err_t esp_core_dump_image_get(size_t* out_addr, size_t *out_size); /** */ esp_err_t esp_core_dump_image_erase(void); #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF /** char panic_reason[200]; esp_err_t err = esp_core_dump_get_panic_reason(panic_reason, sizeof(panic_reason)); if (err == ESP_OK) { ESP_LOGW(TAG, "%s", panic_reason); } */ esp_err_t esp_core_dump_get_panic_reason(char *reason_buffer, size_t buffer_size); /** */ esp_err_t esp_core_dump_get_summary(esp_core_dump_summary_t *summary); #endif /* CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF */ #ifdef __cplusplus } #endif #endif

/* */ #pragma once #include "sdkconfig.h" #include #include #ifdef __cplusplus extern "C" { #endif #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF #define EPCx_REGISTER_COUNT XCHAL_NUM_INTLEVELS /** */ typedef struct { uint32_t bt[16]; /*!< Backtrace (array of PC) */ uint32_t depth; /*!< Number of backtrace entries */ bool corrupted; /*!< Status flag for backtrace is corrupt or not */ } esp_core_dump_bt_info_t; /** */ typedef struct { uint32_t exc_cause; /*!< Cause of exception */ uint32_t exc_vaddr; /*!< Virtual address of exception */ uint32_t exc_a[16]; /*!< a register set when the exception caused */ uint32_t epcx[EPCx_REGISTER_COUNT]; /*!< PC register address at exception level(1 to 7) */ uint8_t epcx_reg_bits; /*!< Bit mask of available EPCx registers */ } esp_core_dump_summary_extra_info_t; #endif /* CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF */ #ifdef __cplusplus } #endif

/* */ #pragma once #include "sdkconfig.h" #include #ifdef __cplusplus extern "C" { #endif #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF /** */ typedef struct { uint8_t stackdump[CONFIG_ESP_COREDUMP_SUMMARY_STACKDUMP_SIZE]; /*!< Stack dump of the crashing task. */ uint32_t dump_size; /*!< Size (in bytes) of the stack dump */ } esp_core_dump_bt_info_t; /** */ typedef struct { uint32_t mstatus; /* Machine Status */ uint32_t mtvec; /* Machine Trap-Vector Base Address */ uint32_t mcause; /* Machine Trap Cause */ uint32_t mtval; /* Machine Trap Value */ uint32_t ra; /* Return Address */ uint32_t sp; /* Stack pointer */ uint32_t exc_a[8]; /* A0-A7 registers when the exception caused */ } esp_core_dump_summary_extra_info_t; #endif /* CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF */ #ifdef __cplusplus } #endif

/* */ #ifndef ESP_CORE_DUMP_COMMON_H_ #define ESP_CORE_DUMP_COMMON_H_ #include "freertos/FreeRTOS.h" #include "esp_private/freertos_debug.h" #include "esp_app_format.h" #include "esp_core_dump_types.h" #ifdef __cplusplus extern "C" { #endif /** */ typedef enum { COREDUMP_MEMORY_DRAM, COREDUMP_MEMORY_IRAM, #if SOC_RTC_MEM_SUPPORTED COREDUMP_MEMORY_RTC, COREDUMP_MEMORY_RTC_FAST, #endif COREDUMP_MEMORY_MAX, COREDUMP_MEMORY_START = COREDUMP_MEMORY_DRAM } coredump_region_t; /** */ bool esp_core_dump_get_task_snapshot(core_dump_task_handle_t handle, core_dump_task_header_t *task, core_dump_mem_seg_header_t *interrupted_stack); /** */ void esp_core_dump_reset_tasks_snapshots_iter(void); /** */ bool esp_core_dump_tcb_addr_is_sane(uint32_t addr); /** */ uint32_t esp_core_dump_get_user_ram_segments(void); /** */ int esp_core_dump_get_user_ram_info(coredump_region_t region, uint32_t *start); /** */ bool esp_core_dump_in_isr_context(void); /** */ uint32_t esp_core_dump_get_user_ram_size(void); /** */ void esp_core_dump_print_write_start(void); /** */ void esp_core_dump_print_write_end(void); /** */ esp_err_t esp_core_dump_write_init(void); /** */ esp_err_t esp_core_dump_write_prepare(core_dump_write_data_t *wr_data, uint32_t *data_len); /** */ esp_err_t esp_core_dump_write_start(core_dump_write_data_t *wr_data); /** */ esp_err_t esp_core_dump_write_data(core_dump_write_data_t *wr_data, void *data, uint32_t data_len); /** */ esp_err_t esp_core_dump_write_end(core_dump_write_data_t *wr_data); /** */ esp_err_t esp_core_dump_store(void); /** */ static inline uint32_t esp_core_dump_get_tcb_len(void) { return (sizeof(StaticTask_t) % sizeof(uint32_t)) ?

((sizeof(StaticTask_t) / sizeof(uint32_t) + 1) * sizeof(uint32_t)) : sizeof(StaticTask_t); } /** */ static inline core_dump_task_handle_t esp_core_dump_get_current_task_handle(void) { return (core_dump_task_handle_t) xTaskGetCurrentTaskHandleForCore(xPortGetCoreID()); } /** */ static inline uint32_t esp_core_dump_get_memory_len(uint32_t start, uint32_t end) { const uint32_t len = end - start; // Take stack padding into account return (len + sizeof(uint32_t) - 1) & ~(sizeof(uint32_t) - 1); } /** */ static inline void esp_core_dump_task_iterator_init(TaskIterator_t *iter) { if (iter) { iter->uxCurrentListIndex = 0; iter->pxNextListItem = NULL; iter->pxTaskHandle = NULL; } } /** */ static inline int esp_core_dump_task_iterator_next(TaskIterator_t *task_iterator) { return xTaskGetNext(task_iterator); } #ifdef __cplusplus } #endif #endif

/* */ #ifndef ESP_CORE_DUMP_PRIV_H_ #define ESP_CORE_DUMP_PRIV_H_ #ifdef __cplusplus extern "C" { #endif #include "esp_err.h" #include "esp_attr.h" #include "esp_log.h" #include "esp_rom_sys.h" #include "sdkconfig.h" #include "esp_private/panic_internal.h" #include "core_dump_checksum.h" #if CONFIG_ESP_COREDUMP_LOGS #define ESP_COREDUMP_LOG( level, format, ... ) if (LOG_LOCAL_LEVEL >= level) { esp_rom_printf((format), esp_log_early_timestamp(), (const char *)TAG, ##__VA_ARGS__); } #else #define ESP_COREDUMP_LOG( level, format, ... ) // dummy define doing nothing #endif #define ESP_COREDUMP_LOGE( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_ERROR, LOG_FORMAT(E, format), ##__VA_ARGS__) #define ESP_COREDUMP_LOGW( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_WARN, LOG_FORMAT(W, format), ##__VA_ARGS__) #define ESP_COREDUMP_LOGI( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_INFO, LOG_FORMAT(I, format), ##__VA_ARGS__) #define ESP_COREDUMP_LOGD( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_DEBUG, LOG_FORMAT(D, format), ##__VA_ARGS__) #define ESP_COREDUMP_LOGV( format, .

.. ) ESP_COREDUMP_LOG(ESP_LOG_VERBOSE, LOG_FORMAT(V, format), ##__VA_ARGS__) /** */ #define ESP_COREDUMP_PRINT( format, ... ) do { esp_rom_printf((format), ##__VA_ARGS__); } while(0) /** */ #define ESP_COREDUMP_ASSERT( condition ) if(!(condition)){ abort(); } else { } /** */ #define ESP_COREDUMP_DEBUG_ASSERT( condition ) assert(condition) /** */ #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH #define ESP_COREDUMP_LOG_PROCESS( format, ... ) ESP_COREDUMP_LOGD(format, ##__VA_ARGS__) #else #define ESP_COREDUMP_LOG_PROCESS( format, ... ) do{/*(__VA_ARGS__);*/}while(0) #endif #define COREDUMP_MAX_TASK_STACK_SIZE (64*1024) /** */ #define COREDUMP_VERSION_MAKE(_maj_, _min_) ( \ (((COREDUMP_VERSION_CHIP)&0xFFFF) 0x0001 #define COREDUMP_VERSION_BIN_CURRENT COREDUMP_VERSION_MAKE(COREDUMP_VERSION_BIN, 3) // -> 0x0003 #define COREDUMP_VERSION_ELF_CRC32 COREDUMP_VERSION_MAKE(COREDUMP_VERSION_ELF, 2) // -> 0x0102 #define COREDUMP_VERSION_ELF_SHA256 COREDUMP_VERSION_MAKE(COREDUMP_VERSION_ELF, 3) // -> 0x0103 #define COREDUMP_CURR_TASK_MARKER 0xDEADBEEF #define COREDUMP_CURR_TASK_NOT_FOUND -1 /** */ #define COREDUMP_CACHE_SIZE 32 /** */ #if (COREDUMP_CACHE_SIZE % 16) !

= 0 #error "Coredump cache size must be a multiple of 16" #endif typedef uint32_t core_dump_crc_t; #if CONFIG_ESP_COREDUMP_CHECKSUM_CRC32 typedef struct { core_dump_crc_t crc; uint32_t total_bytes_checksum; /* Number of bytes used to calculate the checksum */ } core_dump_crc_ctx_t; typedef core_dump_crc_ctx_t checksum_ctx_t; #else #if CONFIG_IDF_TARGET_ESP32 #include "mbedtls/sha256.h" /* mbedtls_sha256_context */ typedef mbedtls_sha256_context sha256_ctx_t; #else #include "hal/sha_types.h" /* SHA_CTX */ typedef SHA_CTX sha256_ctx_t; #endif #define COREDUMP_SHA256_LEN 32 typedef struct { sha256_ctx_t ctx; uint8_t result[COREDUMP_SHA256_LEN]; uint32_t total_bytes_checksum; /* Number of bytes used to calculate the checksum */ } core_dump_sha_ctx_t; typedef core_dump_sha_ctx_t checksum_ctx_t; #endif /** */ #define COREDUMP_VERSION_CHIP CONFIG_IDF_FIRMWARE_CHIP_ID typedef struct _core_dump_write_data_t { uint32_t off; /*!< Current offset of data being written */ uint8_t cached_data[COREDUMP_CACHE_SIZE]; /*!

< Cache used to write to flash */ uint8_t cached_bytes; /*!< Number of bytes filled in the cached */ checksum_ctx_t checksum_ctx; /*!< Checksum context */ } core_dump_write_data_t; /** typedef struct _core_dump_header_t { uint32_t data_len; /*!< Data length */ uint32_t version; /*!< Core dump version */ uint32_t tasks_num; /*!< Number of tasks */ uint32_t tcb_sz; /*!< Size of a TCB, in bytes */ uint32_t mem_segs_num; /*!< Number of memory segments */ uint32_t chip_rev; /*!< Chip revision */ } core_dump_header_t; /** */ typedef void* core_dump_task_handle_t; /** */ typedef struct _core_dump_task_header_t { core_dump_task_handle_t tcb_addr; /*!< TCB address */ uint32_t stack_start; /*!< Start of the stack address */ uint32_t stack_end; /*!< End of the stack address */ } core_dump_task_header_t; /** */ typedef struct _core_dump_mem_seg_header_t { uint32_t start; /*!< Memory region start address */ uint32_t size; /*!

< Memory region size */ } core_dump_mem_seg_header_t; #ifdef __cplusplus } #endif #endif

/* */ /** */ #ifndef CORE_DUMP_CHECKSUM_H_ #define CORE_DUMP_CHECKSUM_H_ #include #ifdef __cplusplus extern "C" { #endif /** */ #define COREDUMP_CHECKSUM_MAX_LEN 32 /** */ typedef void* core_dump_checksum_ctx; /** */ typedef uint8_t* core_dump_checksum_bytes; /** */ uint32_t esp_core_dump_elf_version(void); /** */ void esp_core_dump_checksum_init(void *ctx); /** */ void esp_core_dump_checksum_update(void *ctx, void *data, size_t data_len); /** */ uint32_t esp_core_dump_checksum_finish(void *ctx, core_dump_checksum_bytes *chs_ptr); /** */ uint32_t esp_core_dump_checksum_size(void); /** */ void esp_core_dump_print_checksum(const char* msg, core_dump_checksum_bytes checksum); #ifdef __cplusplus } #endif #endif

/ *** *** This header was automatically generated from a Linux kernel header *** of the same name, to make information necessary for userspace to *** call into the kernel available to libc. It contains only constants, *** structures, and macros generated from the original header, and thus, *** contains no copyrightable information. *** / #ifndef _LINUX_ELF_H #define _LINUX_ELF_H #include #ifndef elf_read_implies_exec #define elf_read_implies_exec(ex, have_pt_gnu_stack) 0 #endif typedef uint32_t Elf32_Addr; typedef uint16_t Elf32_Half; typedef uint32_t Elf32_Off; typedef int32_t Elf32_Sword; typedef uint32_t Elf32_Word; typedef uint64_t Elf64_Addr; typedef uint16_t Elf64_Half; typedef int16_t Elf64_SHalf; typedef uint64_t Elf64_Off; typedef int32_t Elf64_Sword; typedef uint32_t Elf64_Word; typedef uint64_t Elf64_Xword; typedef int64_t Elf64_Sxword; #define PT_NULL 0 #define PT_LOAD 1 #define PT_DYNAMIC 2 #define PT_INTERP 3 #define PT_NOTE 4 #define PT_SHLIB 5 #define PT_PHDR 6 #define PT_TLS 7 #define PT_LOOS 0x60000000 #define PT_HIOS 0x6fffffff #define PT_LOPROC 0x70000000 #define PT_HIPROC 0x7fffffff #define PT_GNU_EH_FRAME 0x6474e550 #define PT_GNU_STACK (PT_LOOS + 0x474e551) #define ET_NONE 0 #define ET_REL 1 #define ET_EXEC 2 #define ET_DYN 3 #define ET_CORE 4 #define ET_LOPROC 0xff00 #define ET_HIPROC 0xffff #define DT_NULL 0 #define DT_NEEDED 1 #define DT_PLTRELSZ 2 #define DT_PLTGOT 3 #define DT_HASH 4 #define DT_STRTAB 5 #define DT_SYMTAB 6 #define DT_RELA 7 #define DT_RELASZ 8 #define DT_RELAENT 9 #define DT_STRSZ 10 #define DT_SYMENT 11 #define DT_INIT 12 #define DT_FINI 13 #define DT_SONAME 14 #define DT_RPATH 15 #define DT_SYMBOLIC 16 #define DT_REL 17 #define DT_RELSZ 18 #define DT_RELENT 19 #define DT_PLTREL 20 #define DT_DEBUG 21 #define DT_TEXTREL 22 #define DT_JMPREL 23 #define DT_LOPROC 0x70000000 #define DT_HIPROC 0x7fffffff #define STB_LOCAL 0 #define STB_GLOBAL 1 #define STB_WEAK 2 #define STT_NOTYPE 0 #define STT_OBJECT 1 #define STT_FUNC 2 #define STT_SECTION 3 #define STT_FILE 4 #define STT_COMMON 5 #define STT_TLS 6 #define ELF_ST_BIND(x) ((x) >> 4) #define ELF_ST_TYPE(x) (((unsigned int) x) & 0xf) #define ELF32_ST_BIND(x) ELF_ST_BIND(x) #define ELF32_ST_TYPE(x) ELF_ST_TYPE(x) #define ELF64_ST_BIND(x) ELF_ST_BIND(x) #define ELF64_ST_TYPE(x) ELF_ST_TYPE(x) typedef struct dynamic{ Elf32_Sword d_tag; union{ Elf32_Sword d_val; Elf32_Addr d_ptr; } d_un; } Elf32_Dyn; typedef struct { Elf64_Sxword d_tag; union { Elf64_Xword d_val; Elf64_Addr d_ptr; } d_un; } Elf64_Dyn; #define ELF32_R_SYM(x) ((x) >> 8) #define ELF32_R_TYPE(x) ((x) & 0xff) #define ELF64_R_SYM(i) ((i) >> 32) #define ELF64_R_TYPE(i) ((i) & 0xffffffff) typedef struct elf32_rel { Elf32_Addr r_offset; Elf32_Word r_info; } Elf32_Rel; typedef struct elf64_rel { Elf64_Addr r_offset; Elf64_Xword r_info; } Elf64_Rel; typedef struct elf32_rela{ Elf32_Addr r_offset; Elf32_Word r_info; Elf32_Sword r_addend; } Elf32_Rela; typedef struct elf64_rela { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; typedef struct elf32_sym{ Elf32_Word st_name; Elf32_Addr st_value; Elf32_Word st_size; unsigned char st_info; unsigned char st_other; Elf32_Half st_shndx; } Elf32_Sym; typedef struct elf64_sym { Elf64_Word st_name; unsigned char st_info; unsigned char st_other; Elf64_Half st_shndx; Elf64_Addr st_value; Elf64_Xword st_size; } Elf64_Sym; #define EI_NIDENT 16 typedef struct elf32_hdr{ unsigned char e_ident[EI_NIDENT]; Elf32_Half e_type; Elf32_Half e_machine; Elf32_Word e_version; Elf32_Addr e_entry; Elf32_Off e_phoff; Elf32_Off e_shoff; Elf32_Word e_flags; Elf32_Half e_ehsize; Elf32_Half e_phentsize; Elf32_Half e_phnum; Elf32_Half e_shentsize; Elf32_Half e_shnum; Elf32_Half e_shstrndx; } Elf32_Ehdr; typedef struct elf64_hdr { unsigned char e_ident[16]; Elf64_Half e_type; Elf64_Half e_machine; Elf64_Word e_version; Elf64_Addr e_entry; Elf64_Off e_phoff; Elf64_Off e_shoff; Elf64_Word e_flags; Elf64_Half e_ehsize; Elf64_Half e_phentsize; Elf64_Half e_phnum; Elf64_Half e_shentsize; Elf64_Half e_shnum; Elf64_Half e_shstrndx; } Elf64_Ehdr; #define PF_R 0x4 #define PF_W 0x2 #define PF_X 0x1 typedef struct elf32_phdr{ Elf32_Word p_type; Elf32_Off p_offset; Elf32_Addr p_vaddr; Elf32_Addr p_paddr; Elf32_Word p_filesz; Elf32_Word p_memsz; Elf32_Word p_flags; Elf32_Word p_align; } Elf32_Phdr; typedef struct elf64_phdr { Elf64_Word p_type; Elf64_Word p_flags; Elf64_Off p_offset; Elf64_Addr p_vaddr; Elf64_Addr p_paddr; Elf64_Xword p_filesz; Elf64_Xword p_memsz; Elf64_Xword p_align; } Elf64_Phdr; #define SHT_NULL 0 #define SHT_PROGBITS 1 #define SHT_SYMTAB 2 #define SHT_STRTAB 3 #define SHT_RELA 4 #define SHT_HASH 5 #define SHT_DYNAMIC 6 #define SHT_NOTE 7 #define SHT_NOBITS 8 #define SHT_REL 9 #define SHT_SHLIB 10 #define SHT_DYNSYM 11 #define SHT_NUM 12 #define SHT_LOPROC 0x70000000 #define SHT_HIPROC 0x7fffffff #define SHT_LOUSER 0x80000000 #define SHT_HIUSER 0xffffffff #define SHF_WRITE 0x1 #define SHF_ALLOC 0x2 #define SHF_EXECINSTR 0x4 #define SHF_MASKPROC 0xf0000000 #define SHN_UNDEF 0 #define SHN_LORESERVE 0xff00 #define SHN_LOPROC 0xff00 #define SHN_HIPROC 0xff1f #define SHN_ABS 0xfff1 #define SHN_COMMON 0xfff2 #define SHN_HIRESERVE 0xffff typedef struct elf32_shdr{ Elf32_Word sh_name; Elf32_Word sh_type; Elf32_Word sh_flags; Elf32_Addr sh_addr; Elf32_Off sh_offset; Elf32_Word sh_size; Elf32_Word sh_link; Elf32_Word sh_info; Elf32_Word sh_addralign; Elf32_Word sh_entsize; } Elf32_Shdr; typedef struct elf64_shdr { Elf64_Word sh_name; Elf64_Word sh_type; Elf64_Xword sh_flags; Elf64_Addr sh_addr; Elf64_Off sh_offset; Elf64_Xword sh_size; Elf64_Word sh_link; Elf64_Word sh_info; Elf64_Xword sh_addralign; Elf64_Xword sh_entsize; } Elf64_Shdr; #define EI_MAG0 0 #define EI_MAG1 1 #define EI_MAG2 2 #define EI_MAG3 3 #define EI_CLASS 4 #define EI_DATA 5 #define EI_VERSION 6 #define EI_OSABI 7 #define EI_PAD 8 #define ELFMAG0 0x7f #define ELFMAG1 'E' #define ELFMAG2 'L' #define ELFMAG3 'F' #define ELFMAG "\177ELF" #define SELFMAG 4 #define ELFCLASSNONE 0 #define ELFCLASS32 1 #define ELFCLASS64 2 #define ELFCLASSNUM 3 #define ELFDATANONE 0 #define ELFDATA2LSB 1 #define ELFDATA2MSB 2 #define EV_NONE 0 #define EV_CURRENT 1 #define EV_NUM 2 #define ELFOSABI_NONE 0 #define ELFOSABI_LINUX 3 #ifndef ELF_OSABI #define ELF_OSABI ELFOSABI_NONE #endif #define NT_PRSTATUS 1 #define NT_PRFPREG 2 #define NT_PRPSINFO 3 #define NT_TASKSTRUCT 4 #define NT_AUXV 6 #define NT_PRXFPREG 0x46e62b7f typedef struct elf32_note { Elf32_Word n_namesz; Elf32_Word n_descsz; Elf32_Word n_type; } Elf32_Nhdr; typedef struct elf64_note { Elf64_Word n_namesz; Elf64_Word n_descsz; Elf64_Word n_type; } Elf64_Nhdr; #if ELF_CLASS == ELFCLASS32 #define elfhdr Elf32_Ehdr #define elf_phdr Elf32_Phdr #define elf_note Elf32_Nhdr #define elf_shdr Elf32_Shdr #else #define elfhdr Elf64_Ehdr #define elf_phdr Elf64_Phdr #define elf_note Elf64_Nhdr #define elf_shdr Elf64_Shdr #endif #endif

/* */ #ifndef ESP_CORE_DUMP_PORT_H_ #define ESP_CORE_DUMP_PORT_H_ /** */ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "esp_app_format.h" #include "esp_core_dump_types.h" #include "esp_core_dump_port_impl.h" #include "esp_core_dump.h" #ifdef __cplusplus extern "C" { #endif /** */ uint16_t esp_core_dump_get_arch_id(void); /** */ void esp_core_dump_port_init(panic_info_t *info, bool isr_context); /** */ void esp_core_dump_reset_fake_stacks(void); /** */ uint32_t esp_core_dump_get_isr_stack_end(void); /** */ uint8_t* esp_core_dump_get_isr_stack_top(void); /** */ bool esp_core_dump_check_stack(core_dump_task_header_t *task); /** */ bool esp_core_dump_mem_seg_is_sane(uint32_t addr, uint32_t sz); /** */ uint32_t esp_core_dump_get_stack(core_dump_task_header_t* task_snapshot, uint32_t* stk_vaddr, uint32_t* stk_paddr); /** */ bool esp_core_dump_check_task(core_dump_task_header_t *task); /** */ uint32_t esp_core_dump_get_task_regs_dump(core_dump_task_header_t *task, void **reg_dump); /** */ void esp_core_dump_port_set_crashed_tcb(uint32_t handle); /** */ uint32_t esp_core_dump_get_extra_info(void **info); #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF /** */ void esp_core_dump_summary_parse_extra_info(esp_core_dump_summary_t *summary, void *ei_data); /** */ void esp_core_dump_summary_parse_exc_regs(esp_core_dump_summary_t *summary, void *stack_data); /** */ void esp_core_dump_summary_parse_backtrace_info(esp_core_dump_bt_info_t *bt_info, const void *vaddr, const void *paddr, uint32_t stack_size); #endif /* CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF */ #ifdef __cplusplus } #endif #endif

/* */ #ifndef ESP_CORE_DUMP_PORT_IMPL_H_ #define ESP_CORE_DUMP_PORT_IMPL_H_ /** */ #include "esp_core_dump_types.h" #include "esp_app_format.h" /** */ #include #include #ifdef __cplusplus extern "C" { #endif /** */ typedef struct { uint32_t sp; uint32_t a0; uint32_t ps; uint32_t windowbase; uint32_t windowstart; } core_dump_stack_context_t; /** */ FORCE_INLINE_ATTR void esp_core_dump_replace_sp(void* new_sp, core_dump_stack_context_t* old_ctx) { /* We have to spill all the windows to the stack first as the new stack pointer xthal_window_spill(); /* Backup the special registers PS, WindowBase and WindowStart. We will need to restore them later */ asm volatile("mov %0, sp \n" \ "mov %1, a0 \n" \ "rsr.ps %2 \n"\ "rsr.windowbase %3 \n"\ "rsr.windowstart %4 \n"\ : "=r"(old_ctx->sp), "=r"(old_ctx->a0), "=r"(old_ctx->ps), "=r"(old_ctx->windowbase), "=r"(old_ctx->windowstart) :); /* Set the new stack */ SET_STACK(new_sp); } /** */ FORCE_INLINE_ATTR void esp_core_dump_restore_sp(core_dump_stack_context_t* old_ctx) { /* Start by disabling WindowOverflowEnable bit from PS to make sure we won't get a Window Overflow exception const uint32_t ps_woe = old_ctx->ps & ~(PS_WOE_MASK); asm volatile(\ "wsr.

ps %0 \n"\ "rsync \n"\ "wsr.windowbase %1 \n"\ "rsync \n"\ "wsr.windowstart %2 \n"\ "rsync \n"\ "mov sp, %3 \n" \ "mov a0, %4 \n" \ "wsr.ps %5 \n"\ "rsync \n"\ :: "r"(ps_woe), "r"(old_ctx->windowbase), "r"(old_ctx->windowstart), "r"(old_ctx->sp), "r"(old_ctx->a0), "r"(old_ctx->ps)); } #ifdef __cplusplus } #endif #endif

/* */ #ifndef ESP_CORE_DUMP_PORT_IMPL_H_ #define ESP_CORE_DUMP_PORT_IMPL_H_ /** */ #include "sdkconfig.h" #include "esp_core_dump_types.h" #include "esp_app_format.h" #ifdef __cplusplus extern "C" { #endif /** */ typedef struct { uint32_t sp; #if CONFIG_ESP_SYSTEM_HW_STACK_GUARD uint32_t sp_min; uint32_t sp_max; #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD } core_dump_stack_context_t; /** */ FORCE_INLINE_ATTR void esp_core_dump_replace_sp(void* new_sp, core_dump_stack_context_t* old_ctx) { asm volatile("mv %0, sp \n\t\ mv sp, %1 \n\t\ " : "=&r"(old_ctx->sp) : "r"(new_sp)); } /** */ FORCE_INLINE_ATTR void esp_core_dump_restore_sp(core_dump_stack_context_t* old_ctx) { asm volatile("mv sp, %0 \n\t" :: "r"(old_ctx->sp)); } #ifdef __cplusplus } #endif #endif

/* */ /** */ #pragma once #include #include "soc/soc_caps.h" #if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY #include "mspi_timing_tuning_configs.h" #endif #ifdef __cplusplus extern "C" { #endif #if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY #define IS_DDR 1 #define IS_SDR (!IS_DDR) /** */ typedef struct { uint8_t spi_din_mode; // input signal delay mode uint8_t spi_din_num; // input signal delay number uint8_t extra_dummy_len; // extra dummy length } mspi_timing_tuning_param_t; /** */ typedef struct { mspi_timing_tuning_param_t tuning_config_table[MSPI_TIMING_CONFIG_NUM_MAX]; // Available timing tuning configs uint32_t available_config_num; // Available timing tuning config numbers uint32_t default_config_id; // If tuning fails, we use this one as default } mspi_timing_config_t; #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING /* **/ /** */ void mspi_timing_get_flash_tuning_configs(mspi_timing_config_t *config); /** */ void mspi_timing_flash_init(uint32_t flash_freq_mhz); /** */ void mspi_timing_config_flash_set_tuning_regs(const void *configs, uint8_t id); /** */ void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len); /** */ void mspi_timing_get_psram_tuning_configs(mspi_timing_config_t *config); /** */ void mspi_timing_psram_init(uint32_t psram_freq_mhz); /** */ void mspi_timing_config_psram_set_tuning_regs(const void *configs, uint8_t id); /** */ void mspi_timing_config_psram_prepare_reference_data(uint8_t *buf, uint32_t len); /** */ void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len); /** */ void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len); /* **/ /** */ uint32_t mspi_timing_flash_select_best_tuning_config(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr); /** */ void mspi_timing_flash_set_best_tuning_config(const void *configs, uint8_t best_id); /** */ uint32_t mspi_timing_psram_select_best_tuning_config(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr); /** */ void mspi_timing_psram_set_best_tuning_config(const void *configs, uint8_t best_id); /* **/ /** */ void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi); /* **/ /** */ /** */ void mspi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time); /** */ uint32_t mspi_timing_config_get_flash_clock_reg(void); /** */ uint8_t mspi_timing_config_get_flash_extra_dummy(void); #endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING #endif //#if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY #ifdef __cplusplus } #endif

/* */ #pragma once #include "sdkconfig.h" #include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { #endif typedef enum clock_out_channel { CLKOUT_CHANNEL_1, CLKOUT_CHANNEL_2, CLKOUT_CHANNEL_3, CLKOUT_CHANNEL_MAX, } clock_out_channel_t; #if SOC_GPIO_CLOCKOUT_BY_IO_MUX #if CONFIG_IDF_TARGET_ESP32 #define CLKOUT_CHANNEL1_GPIO GPIO_NUM_0 #define CLKOUT_CHANNEL2_GPIO GPIO_NUM_3 #define CLKOUT_CHANNEL3_GPIO GPIO_NUM_1 #define FUNC_CLK_OUT1 FUNC_GPIO0_CLK_OUT1 #define FUNC_CLK_OUT2 FUNC_U0RXD_CLK_OUT2 #define FUNC_CLK_OUT3 FUNC_U0TXD_CLK_OUT3 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define CLKOUT_CHANNEL1_GPIO GPIO_NUM_20 #define CLKOUT_CHANNEL2_GPIO GPIO_NUM_19 #define CLKOUT_CHANNEL3_GPIO GPIO_NUM_18 #define FUNC_CLK_OUT1 FUNC_GPIO20_CLK_OUT1 #define FUNC_CLK_OUT2 FUNC_GPIO19_CLK_OUT2 #define FUNC_CLK_OUT3 FUNC_DAC_2_CLK_OUT3 #endif #define IONUM_TO_CLKOUT_CHANNEL(gpio_num) ((gpio_num == CLKOUT_CHANNEL1_GPIO) ?

CLKOUT_CHANNEL_1 : \ (gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \ (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : 0) #define CLKOUT_CHANNEL_TO_IOMUX_FUNC(channel) ((channel == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : 0) #define IS_VALID_CLKOUT_IO(gpio_num) ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO)) #elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX #define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \ (channel == CLKOUT_CHANNEL_3) ?

CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX) #define IS_VALID_CLKOUT_IO(gpio_num) GPIO_IS_VALID_GPIO(gpio_num) #endif #define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0) #define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \ (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \ (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0) #ifdef __cplusplus } #endif

/* */ /** */ #pragma once #include #include "soc/soc_caps.h" #if SOC_MEMSPI_TIMING_TUNING_BY_DQS #include "mspi_timing_tuning_configs.h" #include "hal/mspi_timing_tuning_ll.h" #endif #ifdef __cplusplus extern "C" { #endif #if SOC_MEMSPI_TIMING_TUNING_BY_DQS #define IS_DDR 1 #define IS_SDR (!IS_DDR) /** */ typedef struct { uint8_t data_delayline; uint8_t dqs_delayline; } __attribute__((packed)) delayline_config_t; /** */ typedef struct { mspi_ll_dqs_phase_t phase[MSPI_LL_DQS_PHASE_MAX]; delayline_config_t delayline_table[MSPI_TIMING_CONFIG_NUM_MAX]; union { uint32_t available_config_num; uint32_t available_phase_num; }; } mspi_timing_config_t; /* **/ /** */ void mspi_timing_psram_init(uint32_t psram_freq_mhz); /** */ void mspi_timing_config_psram_prepare_reference_data(uint8_t *buf, uint32_t len); /** */ void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len); /** */ void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len); /** */ void mspi_timing_get_psram_tuning_phases(mspi_timing_config_t *configs); /** */ void mspi_timing_config_psram_set_tuning_phase(const void *configs, uint8_t id); /** */ uint32_t mspi_timing_psram_select_best_tuning_phase(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr); /** */ void mspi_timing_psram_set_best_tuning_phase(const void *configs, uint8_t best_id); /** */ void mspi_timing_get_psram_tuning_delaylines(mspi_timing_config_t *configs); /** */ void mspi_timing_config_psram_set_tuning_delayline(const void *configs, uint8_t id); /** */ uint32_t mspi_timing_psram_select_best_tuning_delayline(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr); /** */ void mspi_timing_psram_set_best_tuning_delayline(const void *configs, uint8_t best_id); /* **/ /** */ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi); /** */ void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi); #endif //#if SOC_MEMSPI_TIMING_TUNING_BY_DQS #ifdef __cplusplus } #endif

/* */ #pragma once #ifdef __cplusplus extern "C" { #endif #define ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL (ESP_ERR_HW_CRYPTO_BASE + 0x1) /*!< HMAC peripheral problem */ #define ESP_ERR_HW_CRYPTO_DS_INVALID_KEY (ESP_ERR_HW_CRYPTO_BASE + 0x2) /*!< given HMAC key isn't correct, HMAC peripheral problem */ #define ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST (ESP_ERR_HW_CRYPTO_BASE + 0x4) /*!< message digest check failed, result is invalid */ #define ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING (ESP_ERR_HW_CRYPTO_BASE + 0x5) /*!< padding check failed, but result is produced anyway and can be read*/ #ifdef __cplusplus } #endif

/* */ #pragma once #include #include #include "esp_err.h" #ifdef __cplusplus extern "C" { #endif /** */ typedef struct esp_etm_channel_t *esp_etm_channel_handle_t; /** */ typedef struct esp_etm_event_t *esp_etm_event_handle_t; /** */ typedef struct esp_etm_task_t *esp_etm_task_handle_t; /** */ typedef struct { } esp_etm_channel_config_t; /** */ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_channel_handle_t *ret_chan); /** */ esp_err_t esp_etm_del_channel(esp_etm_channel_handle_t chan); /** */ esp_err_t esp_etm_channel_enable(esp_etm_channel_handle_t chan); /** */ esp_err_t esp_etm_channel_disable(esp_etm_channel_handle_t chan); /** */ esp_err_t esp_etm_channel_connect(esp_etm_channel_handle_t chan, esp_etm_event_handle_t event, esp_etm_task_handle_t task); /** */ esp_err_t esp_etm_del_event(esp_etm_event_handle_t event); /** */ esp_err_t esp_etm_del_task(esp_etm_task_handle_t task); /** */ esp_err_t esp_etm_dump(FILE *out_stream); #ifdef __cplusplus } #endif

/* */ #pragma once #include "sdkconfig.h" #include #include #include "esp_cpu.h" #if __XTENSA__ #include "xtensa/xtruntime.h" #include "xt_utils.h" #else #include "riscv/rv_utils.h" #endif #ifdef __cplusplus extern "C" { #endif #ifdef CONFIG_SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK #define NEED_VOLATILE_MUX volatile #else #define NEED_VOLATILE_MUX #endif #define SPINLOCK_FREE 0xB33FFFFF #define SPINLOCK_WAIT_FOREVER (-1) #define SPINLOCK_NO_WAIT 0 #define SPINLOCK_INITIALIZER {.owner = SPINLOCK_FREE,.count = 0} #define SPINLOCK_OWNER_ID_0 0xCDCD /* Use these values to avoid 0 being a valid lock owner, same as CORE_ID_REGVAL_PRO on Xtensa */ #define SPINLOCK_OWNER_ID_1 0xABAB /* Same as CORE_ID_REGVAL_APP on Xtensa*/ #define CORE_ID_REGVAL_XOR_SWAP (0xCDCD ^ 0xABAB) #define SPINLOCK_OWNER_ID_XOR_SWAP CORE_ID_REGVAL_XOR_SWAP typedef struct { NEED_VOLATILE_MUX uint32_t owner; NEED_VOLATILE_MUX uint32_t count; } spinlock_t; /** */ static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock) { assert(lock); #if !