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ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/uart_tx6.vhd | 1 | 15872 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6
--
architecture low_level_definition of uart_tx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_tx6_1";
attribute hblknm of pointer3_flop : label is "uart_tx6_1";
attribute hblknm of pointer2_lut : label is "uart_tx6_1";
attribute hblknm of pointer2_flop : label is "uart_tx6_1";
attribute hblknm of pointer01_lut : label is "uart_tx6_1";
attribute hblknm of pointer1_flop : label is "uart_tx6_1";
attribute hblknm of pointer0_flop : label is "uart_tx6_1";
attribute hblknm of data_present_lut : label is "uart_tx6_1";
attribute hblknm of data_present_flop : label is "uart_tx6_1";
--
attribute hblknm of sm0_lut : label is "uart_tx6_2";
attribute hblknm of sm0_flop : label is "uart_tx6_2";
attribute hblknm of sm1_lut : label is "uart_tx6_2";
attribute hblknm of sm1_flop : label is "uart_tx6_2";
attribute hblknm of sm2_lut : label is "uart_tx6_2";
attribute hblknm of sm2_flop : label is "uart_tx6_2";
attribute hblknm of sm3_lut : label is "uart_tx6_2";
attribute hblknm of sm3_flop : label is "uart_tx6_2";
--
attribute hblknm of div01_lut : label is "uart_tx6_3";
attribute hblknm of div23_lut : label is "uart_tx6_3";
attribute hblknm of div0_flop : label is "uart_tx6_3";
attribute hblknm of div1_flop : label is "uart_tx6_3";
attribute hblknm of div2_flop : label is "uart_tx6_3";
attribute hblknm of div3_flop : label is "uart_tx6_3";
attribute hblknm of next_lut : label is "uart_tx6_3";
attribute hblknm of next_flop : label is "uart_tx6_3";
attribute hblknm of read_flop : label is "uart_tx6_3";
--
attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
attribute hblknm of msb_data_lut : label is "uart_tx6_4";
attribute hblknm of serial_lut : label is "uart_tx6_4";
attribute hblknm of serial_flop : label is "uart_tx6_4";
attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_tx6_5";
attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end low_level_definition;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
| mit |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwlink.vhd | 2 | 10334 | --
-- SpaceWire Exchange Level Controller.
--
-- This entity implements exchange level aspects of the SpaceWire protocol.
-- It handles connection setup, error detection and flow control.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwlink is
generic (
-- Reset time expressed in system clock cycles.
-- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard.
reset_time: integer
);
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
-- Disconnects, resets error conditions, puts the link state machine
-- in state ErrorReset.
rst: in std_logic;
-- Link level inputs.
linki: in spw_link_in_type;
-- Link level outputs.
linko: out spw_link_out_type;
-- Receiver enable signal to spwrecv.
rxen: out std_logic;
-- Output signals from spwrecv.
recvo: in spw_recv_out_type;
-- Input signals for spwxmit.
xmiti: out spw_xmit_in_type;
-- Output signals from spwxmit.
xmito: in spw_xmit_out_type
);
end entity spwlink;
architecture spwlink_arch of spwlink is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- State machine.
type state_type is (
S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run );
-- Registers
type regs_type is record
-- state machine
state: state_type;
-- credit accounting
tx_credit: unsigned(5 downto 0);
rx_credit: unsigned(5 downto 0);
errcred: std_ulogic;
-- reset timer
timercnt: unsigned(10 downto 0);
timerdone: std_ulogic;
-- signal to transmitter
xmit_fct_in: std_ulogic;
end record;
-- Initial state
constant regs_reset: regs_type := (
state => S_ErrorReset,
tx_credit => "000000",
rx_credit => "000000",
errcred => '0',
timercnt => to_unsigned(reset_time, 11),
timerdone => '0',
xmit_fct_in => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, linki, recvo, xmito) is
variable v: regs_type;
variable v_timerrst: std_logic;
begin
v := r;
v_timerrst := '0';
-- State machine.
case r.state is
when S_ErrorReset =>
-- Wait for timer.
if r.timercnt = 0 then
v.state := S_ErrorWait;
v_timerrst := '1';
end if;
v.errcred := '0';
v.xmit_fct_in := '0';
when S_ErrorWait =>
-- Wait for 2 timer periods.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
-- Note: spwrecv will never issue errpar, erresc, gotfct,
-- tick_out or rxchar before the first NULL has been seen.
-- Therefore it's ok here to bail on those conditions
-- without explicitly testing got_null.
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif r.timercnt = 0 then
if r.timerdone = '1' then
v.state := S_Ready;
v_timerrst := '1';
end if;
end if;
when S_Ready =>
-- Wait for link start.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and
((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then
v.state := S_Started; -- link enabled; start sending NULL
v_timerrst := '1';
end if;
when S_Started =>
-- Wait for NULL.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotnull = '1' then
v.state := S_Connecting; -- received null, continue
v_timerrst := '1';
end if;
when S_Connecting =>
-- Wait for FCT.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotfct = '1' then
v.state := S_Run; -- got FCT, init completed
end if;
when S_Run =>
-- All is well.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
(r.errcred = '1') or
(linki.linkdis = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
end if;
when others =>
v.state := S_ErrorReset; -- recover from invalid state
v_timerrst := '1';
end case;
-- Update credit counters.
if r.state = S_ErrorReset then
-- reset credit
v.tx_credit := to_unsigned(0, v.tx_credit'length);
v.rx_credit := to_unsigned(0, v.rx_credit'length);
else
-- update TX credit
if recvo.gotfct = '1' then
-- just received a FCT token
v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length);
if r.tx_credit > 48 then
-- received too many FCT tokens
v.errcred := '1';
end if;
end if;
if xmito.txack = '1' then
-- just sent one byte
v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length);
end if;
-- update RX credit after sending FCT
if xmito.fctack = '1' then
-- just sent a FCT token
v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length);
end if;
-- decide about sending FCT tokens
v.xmit_fct_in := bool_to_logic( (v.rx_credit <= 48) and
(v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom)) );
-- update RX credit after receiving character
if recvo.rxchar = '1' then
-- just received a character
v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length);
if r.rx_credit = 0 then
-- remote transmitter violated its credit
v.errcred := '1';
end if;
end if;
end if;
-- Update the initializaton reset timer.
if v_timerrst = '1' then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '0';
else
if r.timercnt = 0 then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '1';
else
v.timercnt := r.timercnt - 1;
end if;
end if;
-- Reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive link level outputs.
linko.started <= bool_to_logic(r.state = S_Started);
linko.connecting <= bool_to_logic(r.state = S_Connecting);
linko.running <= bool_to_logic(r.state = S_Run);
linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run);
linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run);
linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run);
linko.errcred <= r.errcred;
linko.txack <= xmito.txack;
linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run);
linko.ctrl_out <= recvo.ctrl_out;
linko.time_out <= recvo.time_out;
linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run);
linko.rxflag <= recvo.rxflag;
linko.rxdata <= recvo.rxdata;
-- Drive receiver inputs.
rxen <= bool_to_logic(r.state /= S_ErrorReset);
-- Drive transmitter input signals.
xmiti.txen <= bool_to_logic(r.state = S_Started or
r.state = S_Connecting or
r.state = S_Run);
xmiti.stnull <= bool_to_logic(r.state = S_Started);
xmiti.stfct <= bool_to_logic(r.state = S_Connecting);
xmiti.fct_in <= r.xmit_fct_in;
xmiti.tick_in <= linki.tick_in and bool_to_logic(r.state = S_Run);
xmiti.ctrl_in <= linki.ctrl_in;
xmiti.time_in <= linki.time_in;
xmiti.txwrite <= linki.txwrite and bool_to_logic(r.tx_credit /= 0);
xmiti.txflag <= linki.txflag;
xmiti.txdata <= linki.txdata;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwlink_arch;
| mit |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 1 | 8396 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
MUX_filters: process(IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val, RST)
begin
if rst = '1' then
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
else
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end if;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| mit |
ObKo/USBCore | Extra/blk_ep_in_ctl.vhdl | 1 | 6039 | --
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_in_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end blk_ep_in_ctl;
architecture blk_ep_in_ctl of blk_ep_in_ctl is
component blk_in_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : in std_logic;
axis_prog_full : out std_logic
);
end component;
type MACHINE is (S_Idle, S_Xfer);
signal state : MACHINE := S_Idle;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal s_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tlast : std_logic;
signal prog_full : std_logic;
signal was_last_usb : std_logic;
signal was_last : std_logic;
signal was_last_d : std_logic;
signal was_last_dd : std_logic;
begin
FSM: process(usb_clk) is
begin
if rst = '1' then
state <= S_Idle;
blk_xfer_in_has_data <= '0';
elsif rising_edge(usb_clk) then
case state is
when S_Idle =>
if was_last_usb = '1' OR prog_full = '1' then
blk_xfer_in_has_data <= '1';
end if;
if blk_in_xfer = '1' then
state <= S_Xfer;
end if;
when S_Xfer =>
if blk_in_xfer = '0' then
blk_xfer_in_has_data <= '0';
state <= S_Idle;
end if;
end case;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
-- 3 of data clk => axis_clk < 180 MHz if usb_clk = 60 MHz
was_last_usb <= was_last OR was_last_d OR was_last_dd;
FIFO: blk_in_fifo
port map (
m_aclk => usb_clk,
s_aclk => axis_clk,
s_aresetn => NOT rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
was_last_usb <= was_last;
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 64
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
prog_full => prog_full
);
end generate;
WAS_LAST_LATCHER: process(axis_clk) is
begin
if rst = '1' then
was_last <= '0';
was_last_d <= '0';
was_last_dd <= '0';
elsif rising_edge(axis_clk) then
if s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '1' then
was_last <= '1';
elsif s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '0' then
was_last <= '0';
end if;
was_last_d <= was_last;
was_last_dd <= was_last_d;
end if;
end process;
s_axis_tdata <= axis_tdata;
s_axis_tvalid <= axis_tvalid;
axis_tready <= s_axis_tready;
s_axis_tlast <= axis_tlast;
blk_xfer_in_data <= m_axis_tdata;
blk_xfer_in_data_valid <= m_axis_tvalid;
m_axis_tready <= blk_xfer_in_data_ready;
blk_xfer_in_data_last <= m_axis_tlast;
end blk_ep_in_ctl; | mit |
ObKo/USBCore | Extra/extra_pkg.vhdl | 1 | 3447 | --
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
package USBExtra is
component blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end component;
component blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end component;
component sync_fifo
generic (
constant FIFO_WIDTH : positive;
constant FIFO_DEPTH : positive;
constant PROG_FULL_VALUE: positive
);
port (
clk : in std_logic;
rst : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : out std_logic;
prog_full : out std_logic
);
end component;
end USBExtra; | mit |
timtian090/Playground | UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/datatypes/width_depth/width_depth_rtl.vhd | 1 | 616 | --
-- VHDL Architecture width_depth.width_depth.rtl
--
-- Created:
-- by - Ray.UNKNOWN (WRITINGMACHINE)
-- at - 07:46:00 05/ 4/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY width_depth IS
END ENTITY width_depth;
--
ARCHITECTURE rtl OF width_depth IS
signal halfbyte : std_logic_vector( 3 downto 0 ) ;
type reversebits_mem_type is array (7 downto 0) of std_logic_vector(1 to 8);
signal reversebits_mem: reversebits_mem_type;
BEGIN
END ARCHITECTURE rtl;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
ADR_I : in std_logic_vector( 7 downto 0);
CYC_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
RST_O : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- input/output
IO : in std_logic;
WE_I : in std_logic;
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal SERDAT : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(15 downto 0);
signal CLK_COUNT : std_logic_vector(16 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
RST_O <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
IO_RD_SERIAL <= SERDAT and not WE_I;
IO_WR_SERIAL <= SERDAT and WE_I;
ACK_O <= STB_I;
-- IO read process
--
process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
begin
case ADR_I is
when X"00" => IO_RDAT <= RX_DATA;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
when others => IO_RDAT <= CLK_COUNT(16 downto 9);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= X"0000";
else
if (IO = '1' and CYC_I = '1' and WE_I = '1') then
case ADR_I is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= '0' & X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
if (TIMER = 39999) then -- 1 ms at 40 MHz
TIMER_INT <= '1';
TIMER <= X"0000";
else
TIMER <= TIMER + 1;
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/input_output.vhd | 3 | 5695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
ADR_I : in std_logic_vector( 7 downto 0);
CYC_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
RST_O : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- input/output
IO : in std_logic;
WE_I : in std_logic;
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal SERDAT : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(15 downto 0);
signal CLK_COUNT : std_logic_vector(16 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
RST_O <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
IO_RD_SERIAL <= SERDAT and not WE_I;
IO_WR_SERIAL <= SERDAT and WE_I;
ACK_O <= STB_I;
-- IO read process
--
process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
begin
case ADR_I is
when X"00" => IO_RDAT <= RX_DATA;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
when others => IO_RDAT <= CLK_COUNT(16 downto 9);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= X"0000";
else
if (IO = '1' and CYC_I = '1' and WE_I = '1') then
case ADR_I is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= '0' & X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
if (TIMER = 39999) then -- 1 ms at 40 MHz
TIMER_INT <= '1';
TIMER <= X"0000";
else
TIMER <= TIMER + 1;
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/ds1722.vhd | 3 | 3623 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
RST_I: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
architecture DS1722_arch of DS1722 is
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
signal state : BIG_STATE;
signal bit_count: INTEGER range 0 to 7;
signal Write: std_logic;
begin
-- divide CLK_I by 256
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then counter <= "00000000";
else counter <= counter + "00000001";
end if;
end if;
end process;
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
Write <= ADDRESS(7);
-- convert byte commands to SPI and SPI to byte.
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end process;
end DS1722_arch;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/cpu_engine.vhd | 1 | 12526 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
else T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
end if;
end process;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_IMM <= X"FFFF";
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode... PORTATO FUORI
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_never_unknown_rtl.vhd | 1 | 5190 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never_unknown is
constant assert_name : string := "OVL_NEVER_UNKNOWN";
constant path : string := "";
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal qualifier_x01 : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
qualifier_x01 <= to_x01(qualifier);
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
-- No 2-state assertion for this checker.
fire(0) <= '0';
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((qualifier_x01 = '1') and ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_basic or cover_sanity)) generate
ovl_cover_p : process (clk)
variable prev_test_expr : std_logic_vector(width - 1 downto 0);
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (qualifier_x01 = '1') then
if (cover_basic) then
fire(2) <= '1';
ovl_cover_proc("qualifier covered", assert_name, path, controls, cover_count);
end if;
if (cover_sanity) then
if ((test_expr_x01 /= prev_test_expr) and not ovl_is_x(test_expr_x01) and not ovl_is_x(prev_test_expr)) then
fire(2) <= '1';
ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count);
end if;
prev_test_expr := test_expr_x01;
end if;
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not(cover_basic or cover_sanity)) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_cycle_sequence_rtl.vhd | 1 | 10459 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
constant path : string := "";
constant trig_on_most_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_MOST_PIPE);
constant trig_on_first_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_PIPE);
constant trig_on_first_nopipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_NOPIPE);
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal event_sequence_x01 : std_logic_vector(num_cks - 1 downto 0);
signal seq_queue : std_logic_vector(num_cks - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
event_sequence_x01 <= to_x01(event_sequence);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Shared logic --
------------------------------------------------------------------------------
ovl_seq_queue_gen : if (ovl_2state_is_on(controls, property_type) or
((controls.cover_ctrl = OVL_ON) and (coverage_level_ctrl /= OVL_COVER_NONE))) generate
ovl_seq_queue_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
seq_queue <= (others => '0');
else
if (trig_on_first_nopipe) then
seq_queue(num_cks - 1) <= not(or_reduce(seq_queue(num_cks - 1 downto 1))) and
event_sequence_x01(num_cks - 1);
else
seq_queue(num_cks - 1) <= event_sequence_x01(num_cks - 1);
end if;
seq_queue(num_cks - 2 downto 0) <= seq_queue(num_cks - 1 downto 1) and
event_sequence_x01(num_cks - 2 downto 0);
end if;
end if;
end process ovl_seq_queue_p;
end generate ovl_seq_queue_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
else
fire(0) <= '0';
if (trig_on_first_pipe or trig_on_first_nopipe) then
if (and_reduce((seq_queue(num_cks -1 downto 1) and event_sequence_x01(num_cks - 2 downto 0)) or
not(seq_queue(num_cks -1 downto 1))) = '0') then
fire(0) <= '1';
ovl_error_proc("First event occured but it is not followed by the rest of the events in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
else -- trig_on_most_pipe
if ((not(seq_queue(1)) or (seq_queue(1) and event_sequence_x01(0))) = '0') then
fire(0) <= '1';
ovl_error_proc("First num_cks-1 events occured but they are not followed by the last event in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
function init_valid_sequence_gate return std_logic_vector is
variable set : std_logic_vector(num_cks - 2 downto 0);
begin
if (num_cks > 2) then
set(num_cks - 2 downto 1) := (others => '1');
end if;
if (trig_on_most_pipe) then set(0) := '0'; else set(0) := '1'; end if;
return set;
end function init_valid_sequence_gate;
variable valid_first_event : std_logic;
variable valid_sequence : std_logic;
variable valid_last_event : std_logic;
constant valid_sequence_gate : std_logic_vector(num_cks - 2 downto 0) := init_valid_sequence_gate;
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
valid_first_event := event_sequence_x01(num_cks - 1);
valid_last_event := seq_queue(1) and event_sequence_x01(0);
valid_sequence := xor_reduce(seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0) and
valid_sequence_gate);
if (reset_n = '0') then
fire(1) <= '0';
else
fire(1) <= '0';
if (ovl_is_x(valid_first_event)) then
if (trig_on_most_pipe or trig_on_first_pipe) then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif (not(or_reduce(seq_queue(num_cks - 1 downto 1))) = '1') then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (ovl_is_x(valid_sequence)) then
if (trig_on_first_pipe or trig_on_first_nopipe) then
fire(1) <= '1';
ovl_error_proc("Subsequent events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (trig_on_most_pipe) then
if (ovl_is_x(valid_last_event)) then
if (seq_queue(1) = '1') then
fire(1) <= '1';
ovl_error_proc("Last event in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (((trig_on_first_pipe or trig_on_first_nopipe) and (event_sequence_x01(num_cks - 1) = '1')) or
(trig_on_most_pipe and (seq_queue(1) = '1'))) then
fire(2) <= '1';
ovl_cover_proc("sequence_trigger covered", assert_name, path, controls, cover_count);
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not cover_basic) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/opcode_fetch.vhd | 1 | 1454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LPC <= X"0000";
elsif (CE = '1' and T2 = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/uart._baudgen.vhd | 3 | 2497 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_baudgen is
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
RD : in std_logic;
WR : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_SEROUT : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_READY : out std_logic;
TX_BUSY : out std_logic
);
end uart_baudgen;
architecture Behavioral of uart_baudgen is
COMPONENT baudgen
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
CE_16 : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
END COMPONENT;
signal CE_16 : std_logic;
signal RX_FLAG : std_logic;
signal RX_OLD_FLAG : std_logic;
signal TX_FLAG : std_logic;
signal TX_FLAGQ : std_logic;
signal LTX_DATA : std_logic_vector(7 downto 0);
signal LRX_READY : std_logic;
begin
RX_READY <= LRX_READY;
TX_BUSY <= TX_FLAG xor TX_FLAGQ;
baud: baudgen
GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
PORT MAP(
CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16
);
urt: uart
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16,
TX_DATA => LTX_DATA,
TX_FLAG => TX_FLAG,
TX_SEROUT => TX_SEROUT,
TX_FLAGQ => TX_FLAGQ,
RX_SERIN => RX_SERIN,
RX_DATA => RX_DATA,
RX_FLAG => RX_FLAG
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
TX_FLAG <= '0';
LTX_DATA <= X"33";
else
if (RD = '1') then -- read Rx data
LRX_READY <= '0';
end if;
if (WR = '1') then -- write Tx data
TX_FLAG <= not TX_FLAG;
LTX_DATA <= TX_DATA;
end if;
if (RX_FLAG /= RX_OLD_FLAG) then
LRX_READY <= '1';
end if;
RX_OLD_FLAG <= RX_FLAG;
end if;
end if;
end process;
end Behavioral;
| mit |
bluemurder/chaotic-rngs | rng07-vhdl/chaoticMap.vhd | 2 | 1546 | -- This block describes the chaotic map used for the random generator --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end chaoticMap;
architecture Behavioral of chaoticMap is
-- Supposing 2 integer bits and two's complement, the constants
-- correspond to zero, one and minus one values
constant zero : signed(N_BIT-1 downto 0) := (others => '0');
constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => '1', others => '0');
constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => '1', N_BIT-2 => '1', others => '0');
-- Stores the current state
signal reg : signed(N_BIT-1 downto 0);
begin
-- update map
proc_map: process(clk,reset)
begin
if reset = '0' then
if rising_edge(clk) then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(N_BIT-2 downto 0) & '0' ) - ( "111" & reg(N_BIT-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(N_BIT-2 downto 0)&'0' ) - ( "000" & reg(N_BIT-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= X0;
end if;
end process;
output <= reg(N_BIT-1);
end Behavioral;
| mit |
bluemurder/chaotic-rngs | rng02-vhdl/CaosAlAl.vhd | 1 | 1808 | ----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosAlAl is
generic (nbit : integer := 32);
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
signal reg : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := "00000000000000000000000000000000";
constant one : signed(nbit-1 downto 0) := "01000000000000000000000000000000";
constant minusone : signed(nbit-1 downto 0) := "11000000000000000000000000000000";
constant x0 : signed(nbit-1 downto 0) := "00100000000000000000000000000000";
begin
out0 <= reg(nbit-1);
main:process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
if (reg < zero) then
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
end Behavioral; | mit |
bluemurder/chaotic-rngs | rng06-vhdl/test_randgen.vhd | 2 | 1675 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
use work.randgen_package.all;
ENTITY test_randgen IS
END test_randgen;
ARCHITECTURE behavior OF test_randgen IS
-- Component Declaration for the Unit Under Test (UUT)
component randgen is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic;
signal ready : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: randgen PORT MAP (
clk => clk,
reset => reset,
ready => ready,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (clk) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(clk) then
if ready = '1' and reset = '0' then
write(my_output_line,output);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng08-vhdl/testCaosComb.vhd | 1 | 2587 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 16:27:59 10/06/2011
-- Design Name:
-- Module Name: testCaosComb.vhd
-- Project Name: Caos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CaosComb
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testCaosComb IS
END testCaosComb;
ARCHITECTURE behavior OF testCaosComb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CaosComb
PORT(
res : IN std_logic;
out0 : OUT std_logic
);
END COMPONENT;
--Inputs
signal ck : std_logic := '0';
signal res : std_logic := '0';
--Outputs
signal out0 : std_logic;
constant ck_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CaosComb PORT MAP (
res => res,
out0 => out0
);
-- Clock process definitions
ck_process :process
begin
ck <= '0';
wait for ck_period/2;
ck <= '1';
wait for ck_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res <= '1';
wait for 100 ns;
res<='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (ck) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(ck) then
if res = '0' then
write(my_output_line,out0);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng08-vhdl/test.vhd | 1 | 3060 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 15:44:18 09/19/2011
-- Design Name:
-- Module Name: test.vhd
-- Project Name: NewCaos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: newCaoticGen2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
LIBRARY std;
USE std.textio.all;
use ieee.std_logic_textio.all;
--use ieee.Signed_to_Bit.all;
use work.variable_Caos.all ;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT newCaoticGen2
PORT(
Clk : IN std_logic;
reset : IN std_logic;
X_out : OUT signed(numbit-1 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal X_out : signed(numbit-1 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: newCaoticGen2 PORT MAP (
Clk => Clk,
reset => reset,
X_out => X_out
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*100;
reset <='1';
wait for Clk_period;
reset <='0';
wait for Clk_period*100;
wait;
end process;
process (clk)
variable wrbuf :line;
begin
if (Clk'event and Clk ='1') then
write(wrbuf, conv_std_logic_vector( X_out,numBit));
-- write(wrbuf, string'("; lfsr_2: ")); write(wrbuf, conv_integer(lfsr_2));
writeline(output, wrbuf);
end if;
end process;
-- Write file process
write_file: process (Clk) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_line : LINE;
variable my_output_line : LINE;
begin
if rising_edge(Clk) then
write(my_output_line,X_out(numBit-1));--std_logic_vector(X_out));
writeline(my_output, my_output_line);
end if;
end process write_file;
END;
| mit |
bluemurder/chaotic-rngs | rng06-vhdl/vonNeumannCorrector.vhd | 2 | 1603 | -- This block performs a Von Neumann correction --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.randgen_package.all;
entity vonNeumannCorrector is
Port ( clk : in std_logic;
reset : in std_logic;
data_in : in std_logic;
ready_in : in std_logic;
data_out : out std_logic;
ready_out : out std_logic);
end vonNeumannCorrector;
architecture Behavioral of vonNeumannCorrector is
signal counter : integer range 0 to 1;
signal reg : std_logic_vector(1 downto 0);
signal reg_xor : std_logic;
begin
proc_load_register : process(clk,reset)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) and ready_in = '1' then
reg(counter) <= data_in;
end if;
end process;
proc_counter : process(clk,reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) and ready_in = '1' then
if counter = 0 then
counter <= 1;
else
counter <= 0;
end if;
end if;
end process;
-- Xor between the two bits of reg
reg_xor <= reg(0) xor reg(1);
-- If the block is disabled, data_out equals data_in else
-- it is the first bit of the sequence of two bits
data_out <= data_in when ENABLE_VON_NEUMANN = false else
reg(0);
ready_out <= ready_in when ENABLE_VON_NEUMANN = false else
'1' when (counter = 1 and reg_xor = '1') else
'0';
end Behavioral;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/a27f5e107e0af35c/ila_0_sim_netlist.vhdl | 1 | 4901485 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/f5a61c81241cd760/srio_gen2_0_stub.vhdl | 1 | 6142 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 18 11:58:34 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/33e25e2781fab1df/srio_gen2_0_sim_netlist.vhdl | 1 | 8383546 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/678f058b09cf6220/srio_gen2_0_sim_netlist.vhdl | 1 | 8140888 | null | mit |
superboy0712/MIPS | MIPS_main_controller_sincle_cycle_redesign.vhd | 1 | 6128 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:30:31 10/19/2014
-- Design Name:
-- Module Name: MIPS_main_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MIPS_main_controller is
Port ( proc_en : in std_logic;
clk : in std_logic;
Opcode : in STD_LOGIC_VECTOR (31 downto 26);
PC_en : out STD_LOGIC;
IF_en : out STD_LOGIC; -- instruction register enable
ALUOp : out STD_LOGIC_VECTOR (1 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
Branch : out STD_LOGIC;
Jump : out STD_LOGIC;
RF_WriteSrc : OUT std_logic
);
end MIPS_main_controller;
architecture Behavioral of MIPS_main_controller is
type state_type is (IDLE, IFCH, ID, EX, MEM, WB);
signal state : state_type := IDLE;
begin
decoder_and_output : process(state, Opcode) -- using asynchronous or synchronous ? the control signals for function units are mostly synchronous
variable PC_en_tmp, IF_en_tmp, regdst_tmp, alusrc_tmp, memtoreg_tmp, regwrite_tmp, memread_tmp, memwrite_tmp, branch_tmp, jump_tmp, rf_writesrc_tmp : std_logic := '0';
variable aluop_tmp : std_logic_vector ( 1 downto 0 ) := "00";
begin
decode : case Opcode is
-- R format
when "000000" =>
regdst_tmp := '1'; alusrc_tmp := '0'; memtoreg_tmp := '0';
regwrite_tmp := '1'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0';
aluop_tmp := "10"; rf_writesrc_tmp := '0';
-- LW
when "100011" =>
regdst_tmp := '0'; alusrc_tmp := '1'; memtoreg_tmp := '1';
regwrite_tmp := '1'; memread_tmp := '1'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
-- SW
when "101011" =>
regdst_tmp := '-'; alusrc_tmp := '1'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '1';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
-- BEQ
when "000100" =>
regdst_tmp := '-'; alusrc_tmp := '0'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '1'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "01";
-- JUMP
when "000010" =>
regdst_tmp := '-'; alusrc_tmp := '-'; memtoreg_tmp := '-';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '-'; jump_tmp := '1'; rf_writesrc_tmp := '0';
aluop_tmp := "--";
-- LUI
when "001111" =>
regdst_tmp := '-'; alusrc_tmp := '-'; memtoreg_tmp := '-';
regwrite_tmp := '1'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; -- PC add 1
rf_writesrc_tmp := '1';
aluop_tmp := "--";
-- EXCEPTION
when others =>
regdst_tmp := '0'; alusrc_tmp := '0'; memtoreg_tmp := '0';
regwrite_tmp := '0'; memread_tmp := '0'; memwrite_tmp := '0';
branch_tmp := '0'; jump_tmp := '0'; rf_writesrc_tmp := '0';
aluop_tmp := "00";
end case;
output : case state is
when IDLE =>
PC_en <= '0';
IF_en <= '0';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
when IFCH =>
PC_en <= '0';
IF_en <= '1';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
when ID =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= "00";
when EX =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when MEM =>
PC_en <= '0';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= '0';
memread <= memread_tmp;
memwrite <= memwrite_tmp;
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when WB =>
PC_en <= '1';
IF_en <= '0';
regdst <= regdst_tmp;
alusrc <= alusrc_tmp;
memtoreg <= memtoreg_tmp;
regwrite <= regwrite_tmp;
memread <= memread_tmp;
memwrite <= memwrite_tmp;
branch <= branch_tmp;
Jump <= jump_tmp;
RF_WriteSrc <= rf_writesrc_tmp;
ALUOp <= aluop_tmp;
when others =>
PC_en <= '0';
IF_en <= '0';
regdst <= '0';
alusrc <= '0';
memtoreg <= '0';
regwrite <= '0';
memread <= '0';
memwrite <= '0';
branch <= '0';
Jump <= '0';
RF_WriteSrc <= '0';
ALUOp <= "00";
end case;
end process;
next_state: process(clk)
begin
if rising_edge(clk) then
if(proc_en = '0') then state <= IDLE;
elsif proc_en = '1' then
if state = IDLE then state <= IFCH;
elsif state = IFCH then state <= ID;
elsif state = ID then state <= EX;
elsif state = EX then state <= MEM;
elsif state = MEM then state <= WB;
elsif state = WB then state <= IFCH; -- don't forget
end if;
end if;
end if;
end process;
end Behavioral;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/7b44e6d6f6ec9fee/dbg_ila_stub.vhdl | 1 | 2721 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 25 13:52:36 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe19 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[31:0],probe22[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
| mit |
superboy0712/MIPS | pipeline files/MEMWB_register.vhd | 1 | 1883 | library ieee;
use ieee.std_logic_1164.all;
entity EXMEM_register is
port(Clk, reset : in std_logic;
ALU_ressult_i, data_mem_i: in std_logic_vector(31 downto 0);
ALU_ressult_o, data_mem_o: out std_logic_vector(31 downto 0);
register_address_i: in std_logic_vector(4 downto 0);
register_address_o: out std_logic_vector(4 downto 0);
MemtoReg_i, RegWrite_i: in std_logic;
MemtoReg_o, RegWrite_o: out std_logic);
end EXMEM_register;
architecture EXMEM_register_a of EXMEM_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
type tmp_array_short is array (0 to 1) of std_logic_vector(4 downto 0);
type tmp_array_logic is array (0 to 1) of std_logic;
signal data_mem_tmp, ALU_ressult_tmp: tmp_array;
signal register_address_tmp: tmp_array_short;
signal MemtoReg_tmp, RegWrite_tmp: tmp_array_logic;
begin
process (Clk)
begin
if (reset = '1') then
data_mem_tmp(1) <= (others => '0');
register_address_tmp(1) <= (others => '0');
ALU_ressult_tmp(1) <= (others => '0');
MemtoReg_tmp(1) <= '0';
RegWrite_tmp(1) <= '0';
elsif (rising_edge(clk)) then
data_mem_tmp(0) <= data_mem_tmp(1);
register_address_tmp(0) <= register_address_tmp(1);
ALU_ressult_tmp(0) <= ALU_ressult_tmp(1);
MemtoReg_tmp(0) <= MemtoReg_tmp(1);
RegWrite_tmp(0) <= RegWrite_tmp(1);
data_mem_tmp(1) <= data_mem_i;
register_address_tmp(1) <= register_address_i;
ALU_ressult_tmp(1) <= ALU_ressult_i;
MemtoReg_tmp(1) <= MemtoReg_i;
RegWrite_tmp(1) <= RegWrite_i;
end if;
end process;
data_mem_o <= data_mem_tmp(0);
register_address_o <= register_address_tmp(0);
ALU_ressult_o <= ALU_ressult_tmp(0);
MemtoReg_o <= MemtoReg_tmp(0);
RegWrite_o <= RegWrite_tmp(0);
end EXMEM_register_a; | mit |
GOOD-Stuff/srio_test | srio_test.ip_user_files/ip/srio_gen2_0/srio_gen2_0_stub.vhdl | 1 | 6019 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:31:45 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/srio_gen2_0/srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity srio_gen2_0 is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end srio_gen2_0;
architecture stub of srio_gen2_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_stub.vhdl | 1 | 1927 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[9:0],wr_data_count[8:0],prog_full,prog_empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/335f9682d9b26dcb/ila_0_sim_netlist.vhdl | 1 | 3666186 | null | mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/4768f0820c8fb678/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 309175 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:10:43 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
comp1 : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0020"
)
port map (
I0 => comp2,
I1 => \out\,
I2 => wr_en,
I3 => wr_rst_busy,
I4 => comp1,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9),
Q => rd_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[1]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[1]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8B8BBB8B"
)
port map (
I0 => \^prog_empty\,
I1 => \out\,
I2 => \gpe1.prog_empty_i_i_2_n_0\,
I3 => \gpe1.prog_empty_i_i_3_n_0\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7FFFFFFFFFFF"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[1]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair13";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_d1_reg[9]_0\(9 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \plusOp__1\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(5),
O => \plusOp__1\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
O => \plusOp__1\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B4"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
O => \plusOp__1\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(8),
O => \plusOp__1\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(8),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I2 => \gic0.gc0.count[9]_i_2_n_0\,
I3 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(9),
O => \plusOp__1\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(5),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^gic0.gc0.count_d1_reg[9]_0\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^gic0.gc0.count_d1_reg[9]_0\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => \^gic0.gc0.count_d1_reg[9]_0\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => \^gic0.gc0.count_d1_reg[9]_0\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => \^gic0.gc0.count_d1_reg[9]_0\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => \^gic0.gc0.count_d1_reg[9]_0\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => \^gic0.gc0.count_d1_reg[9]_0\(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => \^gic0.gc0.count_d1_reg[9]_0\(9)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
I2 => RD_PNTR_WR(8),
I3 => \^q\(8),
O => v1_reg(0)
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => \gdiff.diff_pntr_pad_reg[4]\(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => \gdiff.diff_pntr_pad_reg[4]\(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => \gdiff.diff_pntr_pad_reg[4]\(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => \gdiff.diff_pntr_pad_reg[4]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal NLW_minusOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => NLW_minusOp_carry_O_UNCONNECTED(0),
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \gic0.gc0.count_d2_reg[8]\(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d2_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal plusOp_carry_n_7 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_7,
Q => diff_pntr(0)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF004F0000004F"
)
port map (
I0 => \gpf1.prog_full_i_i_2_n_0\,
I1 => diff_pntr(6),
I2 => \gpf1.prog_full_i_i_3_n_0\,
I3 => wr_rst_busy,
I4 => ram_full_fb_i_reg,
I5 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => diff_pntr(2),
I1 => diff_pntr(3),
I2 => diff_pntr(0),
I3 => diff_pntr(1),
I4 => diff_pntr(5),
I5 => diff_pntr(4),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => diff_pntr(9),
I1 => diff_pntr(8),
I2 => diff_pntr(7),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => plusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d1_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d1_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
RD_PNTR_WR(9 downto 0) <= \^rd_pntr_wr\(9 downto 0);
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_reg[9]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_reg[9]\(1),
O => v1_reg_2(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_d1_reg[7]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_d1_reg[7]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_reg[9]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_reg[9]\(3),
O => v1_reg_2(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_d1_reg[7]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_d1_reg[7]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_reg[9]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_reg[9]\(5),
O => v1_reg_2(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_d1_reg[7]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_d1_reg[7]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_reg[9]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_reg[9]\(7),
O => v1_reg_2(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(8),
I1 => \gic0.gc0.count_reg[9]\(8),
I2 => \^rd_pntr_wr\(9),
I3 => \gic0.gc0.count_reg[9]\(9),
O => v1_reg_2(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => \^rd_pntr_wr\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => \^rd_pntr_wr\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => \^rd_pntr_wr\(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => \rd_dc_i_reg[9]\(3 downto 0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(7 downto 4),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal c2_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
v1_reg_0(0) => v1_reg_0(0)
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c2_n_0,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(9 downto 0) => D(9 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0),
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_23 : STD_LOGIC;
signal wpntr_n_24 : STD_LOGIC;
signal wpntr_n_25 : STD_LOGIC;
signal wpntr_n_26 : STD_LOGIC;
signal wpntr_n_27 : STD_LOGIC;
signal wpntr_n_28 : STD_LOGIC;
signal wpntr_n_29 : STD_LOGIC;
signal wpntr_n_30 : STD_LOGIC;
signal wpntr_n_31 : STD_LOGIC;
signal wpntr_n_32 : STD_LOGIC;
signal wpntr_n_33 : STD_LOGIC;
signal wpntr_n_34 : STD_LOGIC;
signal wpntr_n_35 : STD_LOGIC;
signal wpntr_n_36 : STD_LOGIC;
signal wpntr_n_37 : STD_LOGIC;
signal wpntr_n_38 : STD_LOGIC;
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
E(0) <= \^e\(0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
S(3) => wpntr_n_35,
S(2) => wpntr_n_36,
S(1) => wpntr_n_37,
S(0) => wpntr_n_38,
\gic0.gc0.count_d1_reg[7]\(3) => wpntr_n_27,
\gic0.gc0.count_d1_reg[7]\(2) => wpntr_n_28,
\gic0.gc0.count_d1_reg[7]\(1) => wpntr_n_29,
\gic0.gc0.count_d1_reg[7]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]\(1) => wpntr_n_12,
\gic0.gc0.count_d1_reg[9]\(0) => wpntr_n_13,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_rst_busy => wr_rst_busy
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_23,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_24,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_25,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_26,
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8 downto 0),
\gic0.gc0.count_d2_reg[9]\(1) => wpntr_n_0,
\gic0.gc0.count_d2_reg[9]\(0) => wpntr_n_1,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwas.wsts_n_1\,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_12,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[4]\(3) => wpntr_n_35,
\gdiff.diff_pntr_pad_reg[4]\(2) => wpntr_n_36,
\gdiff.diff_pntr_pad_reg[4]\(1) => wpntr_n_37,
\gdiff.diff_pntr_pad_reg[4]\(0) => wpntr_n_38,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_27,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_28,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_29,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) => \gic0.gc0.count_d1_reg[9]\(9 downto 0),
v1_reg(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
\wr_data_count_i_reg[7]\(3) => wpntr_n_23,
\wr_data_count_i_reg[7]\(2) => wpntr_n_24,
\wr_data_count_i_reg[7]\(1) => wpntr_n_25,
\wr_data_count_i_reg[7]\(0) => wpntr_n_26,
\wr_data_count_i_reg[9]\(1) => wpntr_n_0,
\wr_data_count_i_reg[9]\(0) => wpntr_n_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 1 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(9 downto 0) => plusOp(10 downto 1),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_13_out(7 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\gic0.gc0.count_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(9 downto 0) => minusOp(9 downto 0),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_2(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(9 downto 0) => plusOp(10 downto 1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => minusOp(9 downto 0),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_12_out(9 downto 0),
E(0) => p_18_out,
Q(7 downto 0) => p_13_out(7 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
full => full,
\gic0.gc0.count_d1_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
\out\ => rst_full_ff_i,
prog_full => prog_full,
v1_reg(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_18_out,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 956;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 957;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 956;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 957;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 65;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 64;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit |
GOOD-Stuff/srio_test | srio_test.cache/ip/31a2bbcb305771f0/fifo_generator_rx_inst_sim_netlist.vhdl | 1 | 179161 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 26 17:01:25 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 6) => \gc0.count_d1_reg[7]\(7 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 6) => Q(7 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => din(31 downto 0),
DIBDI(31 downto 0) => din(63 downto 32),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => dout(31 downto 0),
DOBDO(31 downto 0) => dout(63 downto 32),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => \out\(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 6 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_2\ : label is "soft_lutpair1";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
I2 => \^q\(5),
I3 => rd_pntr_plus1(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gc0.count[7]_i_2_n_0\,
I1 => rd_pntr_plus1(6),
I2 => \^q\(5),
I3 => \^q\(4),
I4 => rd_pntr_plus1(7),
O => plusOp(7)
);
\gc0.count[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \gc0.count[7]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => rd_pntr_plus1(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => rd_pntr_plus1(7)
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"90090000"
)
port map (
I0 => rd_pntr_plus1(7),
I1 => \gcc0.gc0.count_d1_reg[7]\(1),
I2 => rd_pntr_plus1(6),
I3 => \gcc0.gc0.count_d1_reg[7]\(0),
I4 => rd_en,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\gc0.count_d1[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_i
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_reg[7]\ : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gcc0.gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_empty_fb_i_i_10_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_7_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_8_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_9_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_3_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_6_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_fb_i_i_6 : label is "soft_lutpair5";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(4),
I1 => p_12_out(2),
I2 => p_12_out(0),
I3 => p_12_out(1),
I4 => p_12_out(3),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gcc0.gc0.count[7]_i_2_n_0\,
I1 => p_12_out(4),
I2 => p_12_out(5),
I3 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gcc0.gc0.count[7]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(5),
I3 => p_12_out(4),
I4 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \gcc0.gc0.count[7]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_12_out(7)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFEFEFCF000000"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => \out\,
I2 => wr_en,
I3 => \gc0.count_reg[7]\,
I4 => ram_empty_fb_i_i_4_n_0,
I5 => ram_empty_fb_i_reg_0,
O => ram_empty_i_reg
);
ram_empty_fb_i_i_10: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_reg[5]\(1),
I2 => \^q\(0),
I3 => \gc0.count_reg[5]\(0),
O => ram_empty_fb_i_i_10_n_0
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => ram_empty_fb_i_i_5_n_0,
I1 => ram_empty_fb_i_i_6_n_0,
I2 => ram_empty_fb_i_i_7_n_0,
I3 => ram_empty_fb_i_i_8_n_0,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8200008200000000"
)
port map (
I0 => ram_empty_fb_i_i_9_n_0,
I1 => \^q\(5),
I2 => \gc0.count_reg[5]\(5),
I3 => \^q\(4),
I4 => \gc0.count_reg[5]\(4),
I5 => ram_empty_fb_i_i_10_n_0,
O => ram_empty_fb_i_i_4_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^q\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => ram_empty_fb_i_i_6_n_0
);
ram_empty_fb_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^q\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => ram_empty_fb_i_i_7_n_0
);
ram_empty_fb_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^q\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => ram_empty_fb_i_i_8_n_0
);
ram_empty_fb_i_i_9: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(3),
I1 => \gc0.count_reg[5]\(3),
I2 => \^q\(2),
I3 => \gc0.count_reg[5]\(2),
O => ram_empty_fb_i_i_9_n_0
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C000EEEEC000C000"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => ram_empty_fb_i_reg,
I2 => ram_full_fb_i_i_3_n_0,
I3 => ram_full_fb_i_i_4_n_0,
I4 => wr_rst_busy,
I5 => \out\,
O => ram_full_comb
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090090000"
)
port map (
I0 => \gc0.count_d1_reg[7]\(7),
I1 => p_12_out(7),
I2 => \gc0.count_d1_reg[7]\(6),
I3 => p_12_out(6),
I4 => wr_en,
I5 => \out\,
O => ram_full_fb_i_i_3_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8200008200000000"
)
port map (
I0 => ram_full_fb_i_i_5_n_0,
I1 => p_12_out(5),
I2 => \gc0.count_d1_reg[7]\(5),
I3 => p_12_out(4),
I4 => \gc0.count_d1_reg[7]\(4),
I5 => ram_full_fb_i_i_6_n_0,
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => p_12_out(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => ram_full_fb_i_i_5_n_0
);
ram_full_fb_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => p_12_out(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => ram_full_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal p_7_out : STD_LOGIC;
begin
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
E(0) => p_7_out,
clk => clk,
empty => empty,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0,
rd_en => rd_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0),
E(0) => p_7_out,
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[7]\(1 downto 0) => \gcc0.gc0.count_d1_reg[7]\(1 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
rd_en => rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => rd_rst_reg(0),
I1 => rd_en,
I2 => ram_empty_fb_i_reg,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_reg[7]\ : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gwss.wsts_n_0\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwss.wsts_n_0\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[5]\(5 downto 0) => \gc0.count_reg[5]\(5 downto 0),
\gc0.count_reg[7]\ => \gc0.count_reg[7]\,
\out\ => \gwss.wsts_n_0\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg_0,
ram_empty_i_reg => ram_empty_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_17_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => p_0_out(7 downto 0),
Q(5 downto 0) => rd_pntr_plus1(5 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[7]\(1 downto 0) => p_11_out(7 downto 6),
\out\ => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.rd_n_9\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_8\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_1\,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_17_out,
Q(7 downto 0) => p_11_out(7 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\gc0.count_reg[5]\(5 downto 0) => rd_pntr_plus1(5 downto 0),
\gc0.count_reg[7]\ => \gntv_or_sync_fifo.gl0.rd_n_9\,
\out\ => rst_full_ff_i,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_8\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_17_out,
Q(7 downto 0) => p_11_out(7 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\out\(0) => rd_rst_i(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 254;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 253;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 254;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 253;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(7 downto 0) => NLW_U0_data_count_UNCONNECTED(7 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(7 downto 0) => B"00000000",
prog_empty_thresh_assert(7 downto 0) => B"00000000",
prog_empty_thresh_negate(7 downto 0) => B"00000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(7 downto 0) => B"00000000",
prog_full_thresh_assert(7 downto 0) => B"00000000",
prog_full_thresh_negate(7 downto 0) => B"00000000",
rd_clk => '0',
rd_data_count(7 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(7 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(7 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(7 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_atanlut.vhd | 10 | 165265 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATANLUT.VHD ***
--*** ***
--*** Function: ArcTangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_atanlut IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_atanlut;
ARCHITECTURE rtl OF fp_atanlut IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "0000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(255,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262058,18);
WHEN "0000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(511,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261461,18);
WHEN "0000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259840,18);
WHEN "0000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256682,18);
WHEN "0000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251477,18);
WHEN "0000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243713,18);
WHEN "0000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(1791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232877,18);
WHEN "0000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218459,18);
WHEN "0000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199947,18);
WHEN "0000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2559,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176830,18);
WHEN "0000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(2815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148596,18);
WHEN "0000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114736,18);
WHEN "0000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3327,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74739,18);
WHEN "0000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3583,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(28094,18);
WHEN "0000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(3838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236436,18);
WHEN "0000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174967,18);
WHEN "0000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105322,18);
WHEN "0000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26992,18);
WHEN "0000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(4861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201613,18);
WHEN "0000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104389,18);
WHEN "0000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5372,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259100,18);
WHEN "0000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5628,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140951,18);
WHEN "0000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(5884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11580,18);
WHEN "0000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132624,18);
WHEN "0000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241434,18);
WHEN "0000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75361,18);
WHEN "0000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(6905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158188,18);
WHEN "0000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227268,18);
WHEN "0000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7416,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19954,18);
WHEN "0000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7671,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60030,18);
WHEN "0000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(7926,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84851,18);
WHEN "0000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93916,18);
WHEN "0000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8436,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86725,18);
WHEN "0000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62776,18);
WHEN "0000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(8946,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21573,18);
WHEN "0000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9200,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224760,18);
WHEN "0000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(147552,18);
WHEN "0000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51596,18);
WHEN "0000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(9964,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198541,18);
WHEN "0000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63603,18);
WHEN "0000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170578,18);
WHEN "0000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10727,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256827,18);
WHEN "0000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(10982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59715,18);
WHEN "0000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103038,18);
WHEN "0000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124162,18);
WHEN "0000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11744,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122599,18);
WHEN "0000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(11998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97859,18);
WHEN "0000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12252,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49456,18);
WHEN "0000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239047,18);
WHEN "0000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(12759,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141859,18);
WHEN "0000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19553,18);
WHEN "0000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133790,18);
WHEN "0000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221944,18);
WHEN "0000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(13773,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21390,18);
WHEN "0000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14026,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55937,18);
WHEN "0000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62963,18);
WHEN "0000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14532,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41991,18);
WHEN "0000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(14784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254689,18);
WHEN "0000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176296,18);
WHEN "0000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68480,18);
WHEN "0000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192916,18);
WHEN "0000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(15795,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24844,18);
WHEN "0000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88083,18);
WHEN "0001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120021,18);
WHEN "0001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120191,18);
WHEN "0001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(16803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88130,18);
WHEN "0001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23371,18);
WHEN "0001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17306,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187599,18);
WHEN "0001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56063,18);
WHEN "0001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(17809,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152592,18);
WHEN "0001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214584,18);
WHEN "0001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241584,18);
WHEN "0001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233135,18);
WHEN "0001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(18813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188785,18);
WHEN "0001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108082,18);
WHEN "0001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252719,18);
WHEN "0001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97960,18);
WHEN "0001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(19815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167646,18);
WHEN "0001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20065,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199187,18);
WHEN "0001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192140,18);
WHEN "0001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146062,18);
WHEN "0001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(20815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60512,18);
WHEN "0001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197196,18);
WHEN "0001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21314,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31389,18);
WHEN "0001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86943,18);
WHEN "0001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(21812,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101281,18);
WHEN "0001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22061,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73969,18);
WHEN "0001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4579,18);
WHEN "0001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154826,18);
WHEN "0001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(22806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(262139,18);
WHEN "0001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(63948,18);
WHEN "0001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23303,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84120,18);
WHEN "0001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60088,18);
WHEN "0001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(23798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253578,18);
WHEN "0001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(139883,18);
WHEN "0001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242876,18);
WHEN "0001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37856,18);
WHEN "0001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(24788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48697,18);
WHEN "0001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(12847,18);
WHEN "0001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25281,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192040,18);
WHEN "0001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61583,18);
WHEN "0001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(25774,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145360,18);
WHEN "0001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180824,18);
WHEN "0001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167574,18);
WHEN "0001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105213,18);
WHEN "0001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(26757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255489,18);
WHEN "0001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93717,18);
WHEN "0001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27248,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143796,18);
WHEN "0001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27493,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143189,18);
WHEN "0001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27738,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91508,18);
WHEN "0001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(27982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250512,18);
WHEN "0001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95529,18);
WHEN "0001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150463,18);
WHEN "0001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152791,18);
WHEN "0001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(28959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102135,18);
WHEN "0001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260263,18);
WHEN "0001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102513,18);
WHEN "0001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29689,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152801,18);
WHEN "0001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(29932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148615,18);
WHEN "0001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30175,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89586,18);
WHEN "0001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30417,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237492,18);
WHEN "0001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67684,18);
WHEN "0001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(30902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104088,18);
WHEN "0001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31144,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84201,18);
WHEN "0001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31386,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7666,18);
WHEN "0001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31627,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136273,18);
WHEN "0001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(31868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207526,18);
WHEN "0010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(221074,18);
WHEN "0010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176570,18);
WHEN "0010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73668,18);
WHEN "0010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(32831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174167,18);
WHEN "0010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215584,18);
WHEN "0010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197579,18);
WHEN "0010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119815,18);
WHEN "0010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(33790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244102,18);
WHEN "0010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45819,18);
WHEN "0010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34269,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48923,18);
WHEN "0010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253089,18);
WHEN "0010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133701,18);
WHEN "0010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(34984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214724,18);
WHEN "0010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233694,18);
WHEN "0010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35460,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190291,18);
WHEN "0010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84200,18);
WHEN "0010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(35935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(177249,18);
WHEN "0010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206983,18);
WHEN "0010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173093,18);
WHEN "0010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75271,18);
WHEN "0010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(36882,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175356,18);
WHEN "0010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210901,18);
WHEN "0010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181607,18);
WHEN "0010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87173,18);
WHEN "0010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(37825,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(189450,18);
WHEN "0010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38060,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226000,18);
WHEN "0010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196531,18);
WHEN "0010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38530,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100754,18);
WHEN "0010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200528,18);
WHEN "0010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(38998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233423,18);
WHEN "0010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199158,18);
WHEN "0010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97454,18);
WHEN "0010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(190176,18);
WHEN "0010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(39932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214908,18);
WHEN "0010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171374,18);
WHEN "0010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59307,18);
WHEN "0010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40630,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140580,18);
WHEN "0010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(40862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152786,18);
WHEN "0010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41094,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95661,18);
WHEN "0010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231088,18);
WHEN "0010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41557,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34520,18);
WHEN "0010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(41788,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29989,18);
WHEN "0010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42018,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217242,18);
WHEN "0010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71738,18);
WHEN "0010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117517,18);
WHEN "0010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42709,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92187,18);
WHEN "0010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(42938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257648,18);
WHEN "0010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43168,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89371,18);
WHEN "0010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111402,18);
WHEN "0010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43626,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61360,18);
WHEN "0010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(43854,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201155,18);
WHEN "0010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6265,18);
WHEN "0010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44311,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184374,18);
WHEN "0010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44766,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32631,18);
WHEN "0010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(44993,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69583,18);
WHEN "0010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45220,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32865,18);
WHEN "0010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45446,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184401,18);
WHEN "0010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261830,18);
WHEN "0010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(45899,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2795,18);
WHEN "0010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193515,18);
WHEN "0010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46350,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47349,18);
WHEN "0010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88377,18);
WHEN "0010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(46800,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54250,18);
WHEN "0011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206908,18);
WHEN "0011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47249,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21864,18);
WHEN "0011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47473,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23207,18);
WHEN "0011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210741,18);
WHEN "0011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(47920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59984,18);
WHEN "0011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48143,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95032,18);
WHEN "0011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48366,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53554,18);
WHEN "0011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197504,18);
WHEN "0011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(48811,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2412,18);
WHEN "0011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254526,18);
WHEN "0011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49254,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167234,18);
WHEN "0011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49476,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2502,18);
WHEN "0011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49697,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22299,18);
WHEN "0011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(49917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226451,18);
WHEN "0011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90499,18);
WHEN "0011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50358,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138562,18);
WHEN "0011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50578,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108329,18);
WHEN "0011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(50797,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(261779,18);
WHEN "0011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74462,18);
WHEN "0011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51236,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70506,18);
WHEN "0011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249754,18);
WHEN "0011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87760,18);
WHEN "0011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(51891,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108660,18);
WHEN "0011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52109,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50158,18);
WHEN "0011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174249,18);
WHEN "0011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218642,18);
WHEN "0011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52760,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183192,18);
WHEN "0011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(52977,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67756,18);
WHEN "0011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53193,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134338,18);
WHEN "0011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53409,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120655,18);
WHEN "0011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(26571,18);
WHEN "0011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(53840,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114096,18);
WHEN "0011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54055,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(120953,18);
WHEN "0011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47013,18);
WHEN "0011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154291,18);
WHEN "0011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54698,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(180519,18);
WHEN "0011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(54912,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125572,18);
WHEN "0011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55125,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251472,18);
WHEN "0011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33813,18);
WHEN "0011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55551,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258909,18);
WHEN "0011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140212,18);
WHEN "0011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(55976,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201898,18);
WHEN "0011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181710,18);
WHEN "0011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79540,18);
WHEN "0011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56611,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157424,18);
WHEN "0011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(56822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153114,18);
WHEN "0011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57033,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66506,18);
WHEN "0011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57243,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159643,18);
WHEN "0011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170281,18);
WHEN "0011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98325,18);
WHEN "0011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(57872,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205822,18);
WHEN "0011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230535,18);
WHEN "0011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172373,18);
WHEN "0011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58499,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31247,18);
WHEN "0011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69214,18);
WHEN "0011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(58915,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24044,18);
WHEN "0011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157797,18);
WHEN "0011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59329,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208248,18);
WHEN "0011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59536,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175318,18);
WHEN "0011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58929,18);
WHEN "0011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(59949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121149,18);
WHEN "0011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99760,18);
WHEN "0011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60360,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256834,18);
WHEN "0011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60566,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68012,18);
WHEN "0100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60771,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57516,18);
WHEN "0100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(60975,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225277,18);
WHEN "0100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46944,18);
WHEN "0100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46741,18);
WHEN "0100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61587,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224608,18);
WHEN "0100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56198,18);
WHEN "0100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(61994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65741,18);
WHEN "0100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(253182,18);
WHEN "0100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62399,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94178,18);
WHEN "0100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62601,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112967,18);
WHEN "0100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(62803,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47353,18);
WHEN "0100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63004,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(159433,18);
WHEN "0100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187015,18);
WHEN "0100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63406,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130055,18);
WHEN "0100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250654,18);
WHEN "0100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(63807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24481,18);
WHEN "0100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237930,18);
WHEN "0100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104530,18);
WHEN "0100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64405,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148532,18);
WHEN "0100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64604,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107758,18);
WHEN "0100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(64802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244320,18);
WHEN "0100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65001,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33897,18);
WHEN "0100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(747,18);
WHEN "0100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65396,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144844,18);
WHEN "0100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65593,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204016,18);
WHEN "0100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65790,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178238,18);
WHEN "0100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(65987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67488,18);
WHEN "0100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66183,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133888,18);
WHEN "0100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115273,18);
WHEN "0100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11625,18);
WHEN "0100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66770,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(85072,18);
WHEN "0100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(66965,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73455,18);
WHEN "0100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67159,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238902,18);
WHEN "0100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67354,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57115,18);
WHEN "0100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52371,18);
WHEN "0100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67741,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224661,18);
WHEN "0100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(67935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49688,18);
WHEN "0100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51735,18);
WHEN "0100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68320,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230798,18);
WHEN "0100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68513,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62585,18);
WHEN "0100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68705,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(71382,18);
WHEN "0100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(68896,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257190,18);
WHEN "0100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69088,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95722,18);
WHEN "0100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69279,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111268,18);
WHEN "0100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69470,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41689,18);
WHEN "0100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69660,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149135,18);
WHEN "0100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(69850,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171468,18);
WHEN "0100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70040,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108696,18);
WHEN "0100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70229,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222974,18);
WHEN "0100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252170,18);
WHEN "0100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196294,18);
WHEN "0100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(55362,18);
WHEN "0100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(70984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91533,18);
WHEN "0100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71172,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42680,18);
WHEN "0100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71359,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170964,18);
WHEN "0100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71546,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214261,18);
WHEN "0100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172591,18);
WHEN "0100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(71920,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45977,18);
WHEN "0100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72106,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96586,18);
WHEN "0100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62298,18);
WHEN "0100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72477,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205284,18);
WHEN "0100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72663,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1281,18);
WHEN "0100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(72847,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236752,18);
WHEN "0100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125293,18);
WHEN "0101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73216,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191223,18);
WHEN "0101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73400,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172431,18);
WHEN "0101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68949,18);
WHEN "0101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73767,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(142957,18);
WHEN "0101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(73950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132346,18);
WHEN "0101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74133,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37152,18);
WHEN "0101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119559,18);
WHEN "0101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117461,18);
WHEN "0101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30899,18);
WHEN "0101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(74860,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122058,18);
WHEN "0101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128837,18);
WHEN "0101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51281,18);
WHEN "0101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151578,18);
WHEN "0101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75582,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167630,18);
WHEN "0101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75762,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(99484,18);
WHEN "0101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(75941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(209334,18);
WHEN "0101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76120,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235084,18);
WHEN "0101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76299,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176784,18);
WHEN "0101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76478,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34487,18);
WHEN "0101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70389,18);
WHEN "0101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(76834,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22400,18);
WHEN "0101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152718,18);
WHEN "0101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199256,18);
WHEN "0101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77365,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162070,18);
WHEN "0101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77542,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "0101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98901,18);
WHEN "0101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(77894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(73038,18);
WHEN "0101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78069,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225832,18);
WHEN "0101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78245,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33058,18);
WHEN "0101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78420,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19065,18);
WHEN "0101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78594,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183917,18);
WHEN "0101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3392,18);
WHEN "0101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(78943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1843,18);
WHEN "0101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79116,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179336,18);
WHEN "0101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79290,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11651,18);
WHEN "0101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23144,18);
WHEN "0101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79635,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213885,18);
WHEN "0101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59656,18);
WHEN "0101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(79980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(84815,18);
WHEN "0101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80152,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27291,18);
WHEN "0101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80323,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149301,18);
WHEN "0101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188773,18);
WHEN "0101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145784,18);
WHEN "0101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(80836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20408,18);
WHEN "0101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74865,18);
WHEN "0101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81176,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47089,18);
WHEN "0101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199302,18);
WHEN "0101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7293,18);
WHEN "0101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81683,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257575,18);
WHEN "0101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(81852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163796,18);
WHEN "0101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250325,18);
WHEN "0101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(255100,18);
WHEN "0101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178203,18);
WHEN "0101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82524,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19719,18);
WHEN "0101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82691,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41874,18);
WHEN "0101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(82857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244755,18);
WHEN "0101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104158,18);
WHEN "0101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83190,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144458,18);
WHEN "0101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83356,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(103598,18);
WHEN "0101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83521,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243810,18);
WHEN "0101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40895,18);
WHEN "0101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(83852,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19229,18);
WHEN "0101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84016,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178903,18);
WHEN "0101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84180,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257864,18);
WHEN "0110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84344,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(256201,18);
WHEN "0110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84508,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174008,18);
WHEN "0110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84672,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11377,18);
WHEN "0110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30546,18);
WHEN "0110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(84997,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(231607,18);
WHEN "0110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(90368,18);
WHEN "0110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85322,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131213,18);
WHEN "0110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92091,18);
WHEN "0110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85645,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235245,18);
WHEN "0110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36483,18);
WHEN "0110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(85968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20191,18);
WHEN "0110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186467,18);
WHEN "0110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86289,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11121,18);
WHEN "0110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86449,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18541,18);
WHEN "0110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86608,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208828,18);
WHEN "0110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86768,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57793,18);
WHEN "0110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(86927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89826,18);
WHEN "0110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87086,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42884,18);
WHEN "0110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87244,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179213,18);
WHEN "0110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236772,18);
WHEN "0110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215665,18);
WHEN "0110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87718,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115995,18);
WHEN "0110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(87875,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200010,18);
WHEN "0110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205672,18);
WHEN "0110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88189,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133084,18);
WHEN "0110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88345,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244498,18);
WHEN "0110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15731,18);
WHEN "0110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88657,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233323,18);
WHEN "0110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88813,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110948,18);
WHEN "0110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(88968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173002,18);
WHEN "0110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157449,18);
WHEN "0110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89278,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64397,18);
WHEN "0110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89432,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156101,18);
WHEN "0110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170525,18);
WHEN "0110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89740,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107780,18);
WHEN "0110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(89893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230119,18);
WHEN "0110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90047,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13365,18);
WHEN "0110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(244062,18);
WHEN "0110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90352,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135889,18);
WHEN "0110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213247,18);
WHEN "0110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214103,18);
WHEN "0110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(138570,18);
WHEN "0110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(90959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248907,18);
WHEN "0110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20937,18);
WHEN "0110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241208,18);
WHEN "0110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91412,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123401,18);
WHEN "0110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191920,18);
WHEN "0110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91712,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184734,18);
WHEN "0110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(91862,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101960,18);
WHEN "0110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92011,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205858,18);
WHEN "0110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92160,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234399,18);
WHEN "0110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92309,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187700,18);
WHEN "0110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92458,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(65877,18);
WHEN "0110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92606,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131192,18);
WHEN "0110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92754,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(121618,18);
WHEN "0110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(92902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37273,18);
WHEN "0110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93049,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140418,18);
WHEN "0110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93196,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169029,18);
WHEN "0110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93343,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123223,18);
WHEN "0110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93490,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3119,18);
WHEN "0110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70981,18);
WHEN "0110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93782,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64784,18);
WHEN "0110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(93927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246792,18);
WHEN "0110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94073,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92836,18);
WHEN "0111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127326,18);
WHEN "0111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88237,18);
WHEN "0111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237834,18);
WHEN "0111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51950,18);
WHEN "0111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54995,18);
WHEN "0111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(94939,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247090,18);
WHEN "0111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104069,18);
WHEN "0111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95226,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150342,18);
WHEN "0111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123886,18);
WHEN "0111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24825,18);
WHEN "0111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95654,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(115424,18);
WHEN "0111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95796,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133663,18);
WHEN "0111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(95938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79665,18);
WHEN "0111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96079,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215697,18);
WHEN "0111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17594,18);
WHEN "0111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96362,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9768,18);
WHEN "0111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192343,18);
WHEN "0111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41154,18);
WHEN "0111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80615,18);
WHEN "0111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(96923,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48704,18);
WHEN "0111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207691,18);
WHEN "0111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33412,18);
WHEN "0111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50281,18);
WHEN "0111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97479,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258422,18);
WHEN "0111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133671,18);
WHEN "0111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200444,18);
WHEN "0111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(97894,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196720,18);
WHEN "0111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98032,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122625,18);
WHEN "0111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98169,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240430,18);
WHEN "0111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25971,18);
WHEN "0111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98444,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3664,18);
WHEN "0111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173633,18);
WHEN "0111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11717,18);
WHEN "0111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98853,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42330,18);
WHEN "0111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(98989,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3456,18);
WHEN "0111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99124,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157363,18);
WHEN "0111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99259,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242035,18);
WHEN "0111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99394,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257599,18);
WHEN "0111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99529,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(204180,18);
WHEN "0111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99664,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81908,18);
WHEN "0111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99798,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153051,18);
WHEN "0111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(99932,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155593,18);
WHEN "0111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89662,18);
WHEN "0111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217528,18);
WHEN "0111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100333,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15031,18);
WHEN "0111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6586,18);
WHEN "0111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100598,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192320,18);
WHEN "0111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100731,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48074,18);
WHEN "0111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98261,18);
WHEN "0111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(100995,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80868,18);
WHEN "0111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101126,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258163,18);
WHEN "0111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101258,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105988,18);
WHEN "0111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101389,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148759,18);
WHEN "0111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124458,18);
WHEN "0111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33214,18);
WHEN "0111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101781,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137298,18);
WHEN "0111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(101911,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174695,18);
WHEN "0111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145532,18);
WHEN "0111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49937,18);
WHEN "0111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102300,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150182,18);
WHEN "0111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184251,18);
WHEN "0111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152273,18);
WHEN "0111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102687,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54374,18);
WHEN "0111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102815,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152827,18);
WHEN "1000000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(102943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185617,18);
WHEN "1000000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103071,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152870,18);
WHEN "1000000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103199,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54715,18);
WHEN "1000000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103326,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153425,18);
WHEN "1000000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103453,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(186982,18);
WHEN "1000000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155515,18);
WHEN "1000000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103707,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59152,18);
WHEN "1000000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103833,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160165,18);
WHEN "1000001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(103959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196538,18);
WHEN "1000001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168399,18);
WHEN "1000001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(75875,18);
WHEN "1000001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104336,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(181239,18);
WHEN "1000001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222475,18);
WHEN "1000001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104586,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199709,18);
WHEN "1000001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104711,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113070,18);
WHEN "1000001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104835,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224830,18);
WHEN "1000010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(104960,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10829,18);
WHEN "1000010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105083,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257625,18);
WHEN "1000010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178916,18);
WHEN "1000010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105331,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36971,18);
WHEN "1000010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105454,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94064,18);
WHEN "1000010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105577,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(88176,18);
WHEN "1000010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105700,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19436,18);
WHEN "1000010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150116,18);
WHEN "1000011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(105944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218198,18);
WHEN "1000011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106066,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223809,18);
WHEN "1000011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106188,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167077,18);
WHEN "1000011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106310,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48129,18);
WHEN "1000011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106431,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(129236,18);
WHEN "1000011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106552,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148382,18);
WHEN "1000011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105692,18);
WHEN "1000011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106794,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1293,18);
WHEN "1000100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(106914,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97458,18);
WHEN "1000100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107034,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(132167,18);
WHEN "1000100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107154,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105548,18);
WHEN "1000100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107274,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17728,18);
WHEN "1000100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107393,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130976,18);
WHEN "1000100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(183276,18);
WHEN "1000100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107631,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(174753,18);
WHEN "1000100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107750,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105533,18);
WHEN "1000101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107868,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(237887,18);
WHEN "1000101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(107987,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47653,18);
WHEN "1000101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108105,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59244,18);
WHEN "1000101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108223,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10643,18);
WHEN "1000101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(164119,18);
WHEN "1000101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108457,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257653,18);
WHEN "1000101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29228,18);
WHEN "1000101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108692,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3255,18);
WHEN "1000110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108808,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179862,18);
WHEN "1000110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(108925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34885,18);
WHEN "1000110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109041,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92737,18);
WHEN "1000110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109157,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91399,18);
WHEN "1000110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30995,18);
WHEN "1000110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173795,18);
WHEN "1000110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109503,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257779,18);
WHEN "1000110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20928,18);
WHEN "1000111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109733,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249798,18);
WHEN "1000111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158081,18);
WHEN "1000111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(109963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8045,18);
WHEN "1000111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61959,18);
WHEN "1000111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(57801,18);
WHEN "1000111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257841,18);
WHEN "1000111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110418,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137913,18);
WHEN "1000111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110531,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(222429,18);
WHEN "1001000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110644,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249369,18);
WHEN "1001000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218855,18);
WHEN "1001000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110870,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131010,18);
WHEN "1001000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(110982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248102,18);
WHEN "1001000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45965,18);
WHEN "1001000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111207,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49010,18);
WHEN "1001000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111318,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(257360,18);
WHEN "1001000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111430,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146848,18);
WHEN "1001001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111541,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241886,18);
WHEN "1001001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111653,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(18306,18);
WHEN "1001001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111764,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(520,18);
WHEN "1001001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111874,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188648,18);
WHEN "1001001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(111985,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58525,18);
WHEN "1001001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112095,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134560,18);
WHEN "1001001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112205,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154730,18);
WHEN "1001001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112315,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(119156,18);
WHEN "1001010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112425,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(27960,18);
WHEN "1001010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112534,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143406,18);
WHEN "1001010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203471,18);
WHEN "1001010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112752,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208276,18);
WHEN "1001010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157941,18);
WHEN "1001010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(112970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52586,18);
WHEN "1001010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154475,18);
WHEN "1001010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113186,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201584,18);
WHEN "1001011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194033,18);
WHEN "1001011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113402,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(131941,18);
WHEN "1001011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15429,18);
WHEN "1001011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113617,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106759,18);
WHEN "1001011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143905,18);
WHEN "1001011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113831,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126988,18);
WHEN "1001011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(113938,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(56126,18);
WHEN "1001011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114044,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193581,18);
WHEN "1001100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114151,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15184,18);
WHEN "1001100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114257,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45342,18);
WHEN "1001100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114363,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22027,18);
WHEN "1001100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114468,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207502,18);
WHEN "1001100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114574,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77597,18);
WHEN "1001100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114679,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156717,18);
WHEN "1001100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114784,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182836,18);
WHEN "1001100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114889,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156070,18);
WHEN "1001101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(114994,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(76538,18);
WHEN "1001101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206498,18);
WHEN "1001101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21782,18);
WHEN "1001101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115307,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46791,18);
WHEN "1001101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115411,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19500,18);
WHEN "1001101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115514,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202167,18);
WHEN "1001101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70622,18);
WHEN "1001101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(149267,18);
WHEN "1001110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115824,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(176075,18);
WHEN "1001110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(115927,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151160,18);
WHEN "1001110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74638,18);
WHEN "1001110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116132,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(208767,18);
WHEN "1001110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116235,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29375,18);
WHEN "1001110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116337,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(60864,18);
WHEN "1001110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41205,18);
WHEN "1001110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116540,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232655,18);
WHEN "1001111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116642,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111041,18);
WHEN "1001111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116743,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200765,18);
WHEN "1001111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116844,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239796,18);
WHEN "1001111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(116945,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228248,18);
WHEN "1001111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117046,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166234,18);
WHEN "1001111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117147,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(53867,18);
WHEN "1001111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117247,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153404,18);
WHEN "1001111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202814,18);
WHEN "1010000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117447,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202209,18);
WHEN "1010000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117547,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(151701,18);
WHEN "1010000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117647,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(51403,18);
WHEN "1010000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117746,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163571,18);
WHEN "1010000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(226171,18);
WHEN "1010000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(117944,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239317,18);
WHEN "1010000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203118,18);
WHEN "1010000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117687,18);
WHEN "1010001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118240,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245278,18);
WHEN "1010001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61714,18);
WHEN "1010001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118437,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(91393,18);
WHEN "1010001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118535,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(72282,18);
WHEN "1010001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4490,18);
WHEN "1010001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118730,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(150272,18);
WHEN "1010001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247594,18);
WHEN "1010001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(118925,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34421,18);
WHEN "1010010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119022,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35150,18);
WHEN "1010010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249890,18);
WHEN "1010010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119215,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154463,18);
WHEN "1010010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119312,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11120,18);
WHEN "1010010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119408,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82116,18);
WHEN "1010010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119504,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105413,18);
WHEN "1010010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81120,18);
WHEN "1010010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119696,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9344,18);
WHEN "1010011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(152339,18);
WHEN "1010011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248066,18);
WHEN "1010011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(119982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(34490,18);
WHEN "1010011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120077,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36005,18);
WHEN "1010011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120171,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252718,18);
WHEN "1010011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160448,18);
WHEN "1010011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120361,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21445,18);
WHEN "1010011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120455,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97961,18);
WHEN "1010100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120549,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(127955,18);
WHEN "1010100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120643,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111535,18);
WHEN "1010100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48807,18);
WHEN "1010100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120830,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202019,18);
WHEN "1010100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(120924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46988,18);
WHEN "1010100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121017,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(108109,18);
WHEN "1010100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121110,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123341,18);
WHEN "1010100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(92789,18);
WHEN "1010101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121296,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16558,18);
WHEN "1010101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156895,18);
WHEN "1010101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121480,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251761,18);
WHEN "1010101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39116,18);
WHEN "1010101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121665,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43350,18);
WHEN "1010101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2424,18);
WHEN "1010101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121848,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178584,18);
WHEN "1010101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(121940,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47646,18);
WHEN "1010110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122031,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134000,18);
WHEN "1010110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122122,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175604,18);
WHEN "1010110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122213,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172562,18);
WHEN "1010110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122304,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(124974,18);
WHEN "1010110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122395,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(32943,18);
WHEN "1010110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122485,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158715,18);
WHEN "1010110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122575,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240246,18);
WHEN "1010110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122666,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15495,18);
WHEN "1010111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122756,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8850,18);
WHEN "1010111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122845,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220412,18);
WHEN "1010111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(122935,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125994,18);
WHEN "1010111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123024,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249984,18);
WHEN "1010111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123114,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68194,18);
WHEN "1010111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123203,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105012,18);
WHEN "1010111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123292,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98395,18);
WHEN "1010111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48441,18);
WHEN "1011000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123469,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217394,18);
WHEN "1011000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123558,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81065,18);
WHEN "1011000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123646,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163841,18);
WHEN "1011000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123734,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(203676,18);
WHEN "1011000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123822,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200670,18);
WHEN "1011000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(154921,18);
WHEN "1011000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(123998,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(66526,18);
WHEN "1011000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197727,18);
WHEN "1011001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124173,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24335,18);
WHEN "1011001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124260,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70734,18);
WHEN "1011001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74878,18);
WHEN "1011001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124434,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(36865,18);
WHEN "1011001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124520,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(218933,18);
WHEN "1011001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124607,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(96893,18);
WHEN "1011001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124693,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195129,18);
WHEN "1011001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124779,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251593,18);
WHEN "1011010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124866,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4237,18);
WHEN "1011010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(124951,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239588,18);
WHEN "1011010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125037,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1011010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125123,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61644,18);
WHEN "1011010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(172827,18);
WHEN "1011010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125293,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242811,18);
WHEN "1011010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125379,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9546,18);
WHEN "1011010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125463,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259559,18);
WHEN "1011011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206512,18);
WHEN "1011011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125633,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112644,18);
WHEN "1011011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125717,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240192,18);
WHEN "1011011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(64962,18);
WHEN "1011011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125886,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(111335,18);
WHEN "1011011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(125970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(117261,18);
WHEN "1011011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126054,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82832,18);
WHEN "1011011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126138,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8142,18);
WHEN "1011100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(155428,18);
WHEN "1011100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126305,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(492,18);
WHEN "1011100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126388,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67717,18);
WHEN "1011100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126471,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95050,18);
WHEN "1011100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82582,18);
WHEN "1011100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126637,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30405,18);
WHEN "1011100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126719,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200755,18);
WHEN "1011100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126802,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(69435,18);
WHEN "1011101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160824,18);
WHEN "1011101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(126966,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212868,18);
WHEN "1011101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127048,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225659,18);
WHEN "1011101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(199286,18);
WHEN "1011101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127212,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133839,18);
WHEN "1011101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127294,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29409,18);
WHEN "1011101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127375,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(148230,18);
WHEN "1011101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(228246,18);
WHEN "1011110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127538,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7403,18);
WHEN "1011110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127619,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10079,18);
WHEN "1011110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127699,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(236362,18);
WHEN "1011110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162053,18);
WHEN "1011110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49384,18);
WHEN "1011110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(127941,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(160588,18);
WHEN "1011110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128021,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233609,18);
WHEN "1011110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(6390,18);
WHEN "1011111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128182,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3308,18);
WHEN "1011111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128261,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224450,18);
WHEN "1011111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(145614,18);
WHEN "1011111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128421,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29034,18);
WHEN "1011111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128500,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136938,18);
WHEN "1011111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128579,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(207270,18);
WHEN "1011111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128658,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(240116,18);
WHEN "1011111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128737,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235563,18);
WHEN "1100000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128816,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193696,18);
WHEN "1100000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(114602,18);
WHEN "1100000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(128973,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260510,18);
WHEN "1100000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129052,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107217,18);
WHEN "1100000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129130,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179097,18);
WHEN "1100000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214091,18);
WHEN "1100000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(212284,18);
WHEN "1100000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173760,18);
WHEN "1100001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129442,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98604,18);
WHEN "1100001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129519,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(249044,18);
WHEN "1100001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(100876,18);
WHEN "1100001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129674,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178473,18);
WHEN "1100001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129751,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(219772,18);
WHEN "1100001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129828,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(224859,18);
WHEN "1100001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129905,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(193817,18);
WHEN "1100001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(129982,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126728,18);
WHEN "1100010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130059,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23675,18);
WHEN "1100010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130135,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(146885,18);
WHEN "1100010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234296,18);
WHEN "1100010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130288,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23847,18);
WHEN "1100010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39908,18);
WHEN "1100010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(20417,18);
WHEN "1100010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(227599,18);
WHEN "1100010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130591,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(137248,18);
WHEN "1100011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11588,18);
WHEN "1100011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130742,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(112847,18);
WHEN "1100011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130817,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178959,18);
WHEN "1100011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130892,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210006,18);
WHEN "1100011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(130967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206068,18);
WHEN "1100011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131042,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167226,18);
WHEN "1100011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131117,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(93560,18);
WHEN "1100011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131191,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(247293,18);
WHEN "1100100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131266,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(104218,18);
WHEN "1100100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131340,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(188702,18);
WHEN "1100100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131414,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(238680,18);
WHEN "1100100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131488,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(254231,18);
WHEN "1100100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131562,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235435,18);
WHEN "1100100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182370,18);
WHEN "1100100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131710,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(95115,18);
WHEN "1100100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235893,18);
WHEN "1100101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131857,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(80492,18);
WHEN "1100101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(131930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153280,18);
WHEN "1100101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132003,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192190,18);
WHEN "1100101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132076,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197300,18);
WHEN "1100101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132149,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(168687,18);
WHEN "1100101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132222,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106429,18);
WHEN "1100101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132295,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(10602,18);
WHEN "1100101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132367,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(143428,18);
WHEN "1100110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132439,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(242839,18);
WHEN "1100110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132512,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46768,18);
WHEN "1100110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132584,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79578,18);
WHEN "1100110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132656,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(79203,18);
WHEN "1100110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(45718,18);
WHEN "1100110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132799,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(241342,18);
WHEN "1100110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132871,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(141864,18);
WHEN "1100110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(132943,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9502,18);
WHEN "1100111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133014,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(106476,18);
WHEN "1100111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133085,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170717,18);
WHEN "1100111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133156,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202300,18);
WHEN "1100111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133227,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201300,18);
WHEN "1100111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167790,18);
WHEN "1100111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133369,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(101845,18);
WHEN "1100111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3539,18);
WHEN "1100111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133510,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(135090,18);
WHEN "1101000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133580,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(234429,18);
WHEN "1101000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133651,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(39483,18);
WHEN "1101000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133721,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(74615,18);
WHEN "1101000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133791,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77754,18);
WHEN "1101000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133861,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(48973,18);
WHEN "1101000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(133930,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250488,18);
WHEN "1101000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134000,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158085,18);
WHEN "1101000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134070,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33979,18);
WHEN "1101001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134139,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(140388,18);
WHEN "1101001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134208,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215238,18);
WHEN "1101001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134277,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258603,18);
WHEN "1101001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134347,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(8409,18);
WHEN "1101001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134415,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(251160,18);
WHEN "1101001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134484,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200497,18);
WHEN "1101001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134553,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(118633,18);
WHEN "1101001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134622,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5640,18);
WHEN "1101010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123732,18);
WHEN "1101010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134758,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(210837,18);
WHEN "1101010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134827,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(4881,18);
WHEN "1101010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134895,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30222,18);
WHEN "1101010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(134963,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24786,18);
WHEN "1101010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250788,18);
WHEN "1101010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135098,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184008,18);
WHEN "1101010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86662,18);
WHEN "1101011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135233,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(220961,18);
WHEN "1101011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135301,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62688,18);
WHEN "1101011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135368,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(136199,18);
WHEN "1101011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179420,18);
WHEN "1101011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135502,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(192419,18);
WHEN "1101011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135569,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(175264,18);
WHEN "1101011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135636,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128025,18);
WHEN "1101011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135703,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50768,18);
WHEN "1101100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135769,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(205708,18);
WHEN "1101100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(68622,18);
WHEN "1101100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135902,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(163868,18);
WHEN "1101100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(135968,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(229368,18);
WHEN "1101100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136035,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(3045,18);
WHEN "1101100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136101,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(9256,18);
WHEN "1101100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136166,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(248067,18);
WHEN "1101100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136232,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195258,18);
WHEN "1101101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136298,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113037,18);
WHEN "1101101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136364,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1473,18);
WHEN "1101101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136429,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122776,18);
WHEN "1101101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136494,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(214867,18);
WHEN "1101101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136560,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(15669,18);
WHEN "1101101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(49536,18);
WHEN "1101101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(54389,18);
WHEN "1101101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30294,18);
WHEN "1101110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136819,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239461,18);
WHEN "1101110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136884,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(157665,18);
WHEN "1101110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(136949,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(47117,18);
WHEN "1101110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(170026,18);
WHEN "1101110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137078,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(2168,18);
WHEN "1101110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67895,18);
WHEN "1101110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137206,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(105128,18);
WHEN "1101110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137270,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113931,18);
WHEN "1101111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137334,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(94369,18);
WHEN "1101111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137398,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46504,18);
WHEN "1101111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137461,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232546,18);
WHEN "1101111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137525,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(128269,18);
WHEN "1101111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137588,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258024,18);
WHEN "1101111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97588,18);
WHEN "1101111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137715,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171311,18);
WHEN "1101111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137778,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217112,18);
WHEN "1110000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137841,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(235053,18);
WHEN "1110000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137904,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(225198,18);
WHEN "1110000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(137967,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(187609,18);
WHEN "1110000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138030,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122349,18);
WHEN "1110000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138093,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(29478,18);
WHEN "1110000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138155,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(171204,18);
WHEN "1110000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138218,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23299,18);
WHEN "1110000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(110115,18);
WHEN "1110001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138342,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(169567,18);
WHEN "1110001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138404,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(201718,18);
WHEN "1110001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138466,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206629,18);
WHEN "1110001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138528,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(184361,18);
WHEN "1110001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138590,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(134974,18);
WHEN "1110001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58530,18);
WHEN "1110001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138713,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(217232,18);
WHEN "1110001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138775,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(86854,18);
WHEN "1110010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138836,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191743,18);
WHEN "1110010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138898,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7673,18);
WHEN "1110010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(138959,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58989,18);
WHEN "1110010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139020,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(83609,18);
WHEN "1110010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139081,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(81593,18);
WHEN "1110010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139142,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(52999,18);
WHEN "1110010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139202,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(260030,18);
WHEN "1110010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139263,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(178459,18);
WHEN "1110011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139324,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(70488,18);
WHEN "1110011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139384,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198320,18);
WHEN "1110011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139445,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(37726,18);
WHEN "1110011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139505,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(113052,18);
WHEN "1110011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139565,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162212,18);
WHEN "1110011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139625,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(185266,18);
WHEN "1110011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139685,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(182271,18);
WHEN "1110011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139745,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(153286,18);
WHEN "1110100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139805,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98367,18);
WHEN "1110100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139865,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(17573,18);
WHEN "1110100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139924,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(173106,18);
WHEN "1110100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(139984,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(40734,18);
WHEN "1110100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140043,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144803,18);
WHEN "1110100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140102,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(223226,18);
WHEN "1110100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140162,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(13916,18);
WHEN "1110100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140221,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(41217,18);
WHEN "1110101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140280,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(43044,18);
WHEN "1110101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(19451,18);
WHEN "1110101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232640,18);
WHEN "1110101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140456,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(158378,18);
WHEN "1110101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140515,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58866,18);
WHEN "1110101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140573,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(196304,18);
WHEN "1110101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140632,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46459,18);
WHEN "1110101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140690,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133676,18);
WHEN "1110110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140748,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195865,18);
WHEN "1110110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140806,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(233082,18);
WHEN "1110110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140864,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(245382,18);
WHEN "1110110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140922,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(232821,18);
WHEN "1110110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(140980,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(195453,18);
WHEN "1110110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141038,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133334,18);
WHEN "1110110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141096,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(46517,18);
WHEN "1110110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141153,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197201,18);
WHEN "1110111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141211,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61153,18);
WHEN "1110111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141268,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(162716,18);
WHEN "1110111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141325,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
WHEN "1110111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141383,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(30311,18);
WHEN "1110111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141440,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(58595,18);
WHEN "1110111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141497,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(62561,18);
WHEN "1110111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141554,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(42262,18);
WHEN "1110111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141610,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(259896,18);
WHEN "1111000000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141667,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191228,18);
WHEN "1111000001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141724,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(98455,18);
WHEN "1111000010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141780,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(243774,18);
WHEN "1111000011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141837,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(102950,18);
WHEN "1111000100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(200324,18);
WHEN "1111000101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(141950,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11660,18);
WHEN "1111000110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142006,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61299,18);
WHEN "1111000111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142062,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(87149,18);
WHEN "1111001000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142118,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(89262,18);
WHEN "1111001001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142174,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(67691,18);
WHEN "1111001010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142230,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(22487,18);
WHEN "1111001011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142285,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(215847,18);
WHEN "1111001100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142341,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(123533,18);
WHEN "1111001101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142397,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(7742,18);
WHEN "1111001110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142452,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(130668,18);
WHEN "1111001111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142507,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230220,18);
WHEN "1111010000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142563,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44304,18);
WHEN "1111010001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142618,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(97259,18);
WHEN "1111010010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142673,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(126992,18);
WHEN "1111010011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142728,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(133554,18);
WHEN "1111010100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142783,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
WHEN "1111010101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142838,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(77368,18);
WHEN "1111010110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142893,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(14720,18);
WHEN "1111010111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(142947,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(191247,18);
WHEN "1111011000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143002,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(82710,18);
WHEN "1111011001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143056,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(213448,18);
WHEN "1111011010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143111,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(59223,18);
WHEN "1111011011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143165,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144372,18);
WHEN "1111011100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143219,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(206801,18);
WHEN "1111011101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143273,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
WHEN "1111011110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143328,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(1553,18);
WHEN "1111011111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143381,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258262,18);
WHEN "1111100000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143435,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(230304,18);
WHEN "1111100001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143489,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(179872,18);
WHEN "1111100010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143543,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(107014,18);
WHEN "1111100011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143597,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(11781,18);
WHEN "1111100100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143650,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(156363,18);
WHEN "1111100101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(16522,18);
WHEN "1111100110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143757,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(116595,18);
WHEN "1111100111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143810,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(194484,18);
WHEN "1111101000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143863,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250238,18);
WHEN "1111101001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143917,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(21762,18);
WHEN "1111101010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(143970,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(33391,18);
WHEN "1111101011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144023,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(23028,18);
WHEN "1111101100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144075,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(252866,18);
WHEN "1111101101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144128,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(198664,18);
WHEN "1111101110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144181,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(122614,18);
WHEN "1111101111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144234,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(24761,18);
WHEN "1111110000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144286,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(167299,18);
WHEN "1111110001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144339,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(25984,18);
WHEN "1111110010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144391,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(125154,18);
WHEN "1111110011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144443,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(202709,18);
WHEN "1111110100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144495,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(258698,18);
WHEN "1111110101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144548,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(31022,18);
WHEN "1111110110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144600,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(44016,18);
WHEN "1111110111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144652,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(35582,18);
WHEN "1111111000" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144704,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(5766,18);
WHEN "1111111001" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144755,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(216758,18);
WHEN "1111111010" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144807,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(144317,18);
WHEN "1111111011" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144859,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(50632,18);
WHEN "1111111100" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144910,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(197892,18);
WHEN "1111111101" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(144962,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(61856,18);
WHEN "1111111110" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145013,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(166857,18);
WHEN "1111111111" =>
data(36 DOWNTO 19) <= conv_std_logic_vector(145064,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(250795,18);
WHEN others =>
data(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
data(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_exp2_s5.vhd | 10 | 180176 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_s5
-- VHDL created on Fri Apr 5 13:35:21 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (5 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (22 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(32 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(32 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(11 downto 0);
signal rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(11 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(2 downto 0);
signal rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(2 downto 0);
signal memoryC0_uid123_exp2TabGen_q : std_logic_vector(27 downto 0);
signal memoryC1_uid125_exp2TabGen_q : std_logic_vector(20 downto 0);
signal memoryC2_uid127_exp2TabGen_q : std_logic_vector(11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid142_pT1_uid130_exp2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid145_pT2_uid136_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (32 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (9 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (10 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q : std_logic_vector (6 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (5 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (22 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (7 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (28 downto 0);
signal ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (24 downto 0);
signal ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (20 downto 0);
signal ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (30 downto 0);
signal ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (29 downto 0);
signal ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q : std_logic_vector (32 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(13 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (13 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (23 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (22 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (8 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (8 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (5 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (11 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (10 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(32 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(32 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(34 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (34 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (33 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (15 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (15 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (8 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (5 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (7 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (7 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (28 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (24 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (20 downto 0);
signal lowRangeB_uid131_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid131_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid132_exp2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid132_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid137_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid137_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid138_exp2PolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid138_exp2PolyEval_b : std_logic_vector (21 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (31 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (30 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (29 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (32 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (9 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (22 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (32 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (32 downto 0);
signal yT1_uid129_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid129_exp2PolyEval_b : std_logic_vector (11 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid133_exp2PolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid133_exp2PolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid139_exp2PolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid139_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (22 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (6 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (32 downto 0);
signal X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (16 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal s1_uid131_uid134_exp2PolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid137_uid140_exp2PolyEval_q : std_logic_vector (30 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (32 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (28 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (23 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (22 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (22 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable(LOGICAL,342)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q <= not ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,343)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top(CONSTANT,339)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q <= "011";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp(LOGICAL,340)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_mem_top_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q <= "1" when ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_a = ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_b else "0";
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg(REG,341)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,344)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,345)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(31 downto 31);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,187)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(22 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(22 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,184)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((34 downto 33 => onesCmpFxpIn_uid35_fpExp2Test_q(32)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(33 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(32 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(32 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 32);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,278)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000";
--rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((2 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 3, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,256)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000";
--rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((11 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 12, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((32 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 33, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad32_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,151)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 16);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad16_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X32dto16_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,150)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,149)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "100001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(30 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(30 downto 23);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000111";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(8 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(5 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(5 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,196)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,147)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((10 downto 9 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(8)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(11);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,148)@1
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel5Dto4_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 12);
--ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,266)@2
ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad12_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto12_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= cstZeroWE_uid13_fpExp2Test_q;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 8);
--ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,262)@2
ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad8_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto8_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 4);
--ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,258)@2
ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad4_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage032dto4_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,153)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(3 downto 0);
rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,319)@1
ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,152)@2
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel3Dto2_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 3);
--ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,284)@3
ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad3_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto3_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 2);
--ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,280)@3
ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad2_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage132dto2_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@1
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,277)@2
ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_in(32 downto 1);
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@3
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1Pad1_uid109_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_b_q & RightShiftStage132dto1_uid110_fxpInPostAlign_uid43_fpExp2Test_b;
--ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d(DELAY,289)@3
ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, xout => ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,155)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(1 downto 0);
rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_in(1 downto 0);
--ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a(DELAY,321)@1
ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,154)@3
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= ld_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_b_to_reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel1Dto0_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= ld_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_d_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(32 downto 23);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,156)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(9)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(10 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(7 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(7 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,238)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "00000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,233)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@0
InvSignX_uid62_fpExp2Test_a <= signX_uid7_fpExp2Test_b;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(8 downto 8);
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@0
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,230)@0
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,212)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,157)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(13);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,213)@0
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--posInf_uid67_fpExp2Test(LOGICAL,66)@0
posInf_uid67_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,228)@0
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,218)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@0
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= signX_uid7_fpExp2Test_b;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,217)@0
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(10)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(13);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,159)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (expRPostExc_uid78_fpExp2Test_s, en, cstZeroWE_uid13_fpExp2Test_q, ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, cstAllOWE_uid16_fpExp2Test_q, cstAllOWE_uid16_fpExp2Test_q)
BEGIN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,333)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt(COUNTER,335)
-- every=1, low=0, high=3, step=1, init=1
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_i,2));
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg(REG,336)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux(MUX,337)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux: PROCESS (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q, ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,334)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 4,
width_b => 8,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(7 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "00000000000000000000001";
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q(22 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(22 downto 0);
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(22 downto 16);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0(REG,160)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid127_exp2TabGen(LOOKUP,126)@5
memoryC2_uid127_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid127_exp2TabGen_q <= "001111011001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid127_exp2TabGen_q <= "001111011001";
WHEN "0000001" => memoryC2_uid127_exp2TabGen_q <= "001111100010";
WHEN "0000010" => memoryC2_uid127_exp2TabGen_q <= "001111100110";
WHEN "0000011" => memoryC2_uid127_exp2TabGen_q <= "001111101011";
WHEN "0000100" => memoryC2_uid127_exp2TabGen_q <= "001111110000";
WHEN "0000101" => memoryC2_uid127_exp2TabGen_q <= "001111110111";
WHEN "0000110" => memoryC2_uid127_exp2TabGen_q <= "001111111100";
WHEN "0000111" => memoryC2_uid127_exp2TabGen_q <= "010000000001";
WHEN "0001000" => memoryC2_uid127_exp2TabGen_q <= "010000000110";
WHEN "0001001" => memoryC2_uid127_exp2TabGen_q <= "010000001101";
WHEN "0001010" => memoryC2_uid127_exp2TabGen_q <= "010000010010";
WHEN "0001011" => memoryC2_uid127_exp2TabGen_q <= "010000010111";
WHEN "0001100" => memoryC2_uid127_exp2TabGen_q <= "010000011101";
WHEN "0001101" => memoryC2_uid127_exp2TabGen_q <= "010000100011";
WHEN "0001110" => memoryC2_uid127_exp2TabGen_q <= "010000101001";
WHEN "0001111" => memoryC2_uid127_exp2TabGen_q <= "010000101101";
WHEN "0010000" => memoryC2_uid127_exp2TabGen_q <= "010000110011";
WHEN "0010001" => memoryC2_uid127_exp2TabGen_q <= "010000111010";
WHEN "0010010" => memoryC2_uid127_exp2TabGen_q <= "010001000000";
WHEN "0010011" => memoryC2_uid127_exp2TabGen_q <= "010001000101";
WHEN "0010100" => memoryC2_uid127_exp2TabGen_q <= "010001001011";
WHEN "0010101" => memoryC2_uid127_exp2TabGen_q <= "010001010010";
WHEN "0010110" => memoryC2_uid127_exp2TabGen_q <= "010001010110";
WHEN "0010111" => memoryC2_uid127_exp2TabGen_q <= "010001011011";
WHEN "0011000" => memoryC2_uid127_exp2TabGen_q <= "010001100101";
WHEN "0011001" => memoryC2_uid127_exp2TabGen_q <= "010001101001";
WHEN "0011010" => memoryC2_uid127_exp2TabGen_q <= "010001110011";
WHEN "0011011" => memoryC2_uid127_exp2TabGen_q <= "010001110111";
WHEN "0011100" => memoryC2_uid127_exp2TabGen_q <= "010001111011";
WHEN "0011101" => memoryC2_uid127_exp2TabGen_q <= "010010000011";
WHEN "0011110" => memoryC2_uid127_exp2TabGen_q <= "010010001001";
WHEN "0011111" => memoryC2_uid127_exp2TabGen_q <= "010010001101";
WHEN "0100000" => memoryC2_uid127_exp2TabGen_q <= "010010010110";
WHEN "0100001" => memoryC2_uid127_exp2TabGen_q <= "010010011101";
WHEN "0100010" => memoryC2_uid127_exp2TabGen_q <= "010010100011";
WHEN "0100011" => memoryC2_uid127_exp2TabGen_q <= "010010101001";
WHEN "0100100" => memoryC2_uid127_exp2TabGen_q <= "010010101111";
WHEN "0100101" => memoryC2_uid127_exp2TabGen_q <= "010010110100";
WHEN "0100110" => memoryC2_uid127_exp2TabGen_q <= "010010111100";
WHEN "0100111" => memoryC2_uid127_exp2TabGen_q <= "010011000011";
WHEN "0101000" => memoryC2_uid127_exp2TabGen_q <= "010011001001";
WHEN "0101001" => memoryC2_uid127_exp2TabGen_q <= "010011001110";
WHEN "0101010" => memoryC2_uid127_exp2TabGen_q <= "010011010111";
WHEN "0101011" => memoryC2_uid127_exp2TabGen_q <= "010011011100";
WHEN "0101100" => memoryC2_uid127_exp2TabGen_q <= "010011100011";
WHEN "0101101" => memoryC2_uid127_exp2TabGen_q <= "010011101001";
WHEN "0101110" => memoryC2_uid127_exp2TabGen_q <= "010011110011";
WHEN "0101111" => memoryC2_uid127_exp2TabGen_q <= "010011110111";
WHEN "0110000" => memoryC2_uid127_exp2TabGen_q <= "010011111101";
WHEN "0110001" => memoryC2_uid127_exp2TabGen_q <= "010100001001";
WHEN "0110010" => memoryC2_uid127_exp2TabGen_q <= "010100001111";
WHEN "0110011" => memoryC2_uid127_exp2TabGen_q <= "010100010110";
WHEN "0110100" => memoryC2_uid127_exp2TabGen_q <= "010100011110";
WHEN "0110101" => memoryC2_uid127_exp2TabGen_q <= "010100100101";
WHEN "0110110" => memoryC2_uid127_exp2TabGen_q <= "010100101010";
WHEN "0110111" => memoryC2_uid127_exp2TabGen_q <= "010100110000";
WHEN "0111000" => memoryC2_uid127_exp2TabGen_q <= "010100110110";
WHEN "0111001" => memoryC2_uid127_exp2TabGen_q <= "010100111111";
WHEN "0111010" => memoryC2_uid127_exp2TabGen_q <= "010101000101";
WHEN "0111011" => memoryC2_uid127_exp2TabGen_q <= "010101001101";
WHEN "0111100" => memoryC2_uid127_exp2TabGen_q <= "010101010101";
WHEN "0111101" => memoryC2_uid127_exp2TabGen_q <= "010101011011";
WHEN "0111110" => memoryC2_uid127_exp2TabGen_q <= "010101100101";
WHEN "0111111" => memoryC2_uid127_exp2TabGen_q <= "010101101101";
WHEN "1000000" => memoryC2_uid127_exp2TabGen_q <= "010101110100";
WHEN "1000001" => memoryC2_uid127_exp2TabGen_q <= "010101111010";
WHEN "1000010" => memoryC2_uid127_exp2TabGen_q <= "010110000001";
WHEN "1000011" => memoryC2_uid127_exp2TabGen_q <= "010110001001";
WHEN "1000100" => memoryC2_uid127_exp2TabGen_q <= "010110010001";
WHEN "1000101" => memoryC2_uid127_exp2TabGen_q <= "010110011000";
WHEN "1000110" => memoryC2_uid127_exp2TabGen_q <= "010110100011";
WHEN "1000111" => memoryC2_uid127_exp2TabGen_q <= "010110101001";
WHEN "1001000" => memoryC2_uid127_exp2TabGen_q <= "010110110000";
WHEN "1001001" => memoryC2_uid127_exp2TabGen_q <= "010110111001";
WHEN "1001010" => memoryC2_uid127_exp2TabGen_q <= "010111000010";
WHEN "1001011" => memoryC2_uid127_exp2TabGen_q <= "010111001000";
WHEN "1001100" => memoryC2_uid127_exp2TabGen_q <= "010111001111";
WHEN "1001101" => memoryC2_uid127_exp2TabGen_q <= "010111011011";
WHEN "1001110" => memoryC2_uid127_exp2TabGen_q <= "010111100001";
WHEN "1001111" => memoryC2_uid127_exp2TabGen_q <= "010111100111";
WHEN "1010000" => memoryC2_uid127_exp2TabGen_q <= "010111110100";
WHEN "1010001" => memoryC2_uid127_exp2TabGen_q <= "010111111010";
WHEN "1010010" => memoryC2_uid127_exp2TabGen_q <= "011000000010";
WHEN "1010011" => memoryC2_uid127_exp2TabGen_q <= "011000001010";
WHEN "1010100" => memoryC2_uid127_exp2TabGen_q <= "011000010011";
WHEN "1010101" => memoryC2_uid127_exp2TabGen_q <= "011000011100";
WHEN "1010110" => memoryC2_uid127_exp2TabGen_q <= "011000100011";
WHEN "1010111" => memoryC2_uid127_exp2TabGen_q <= "011000101101";
WHEN "1011000" => memoryC2_uid127_exp2TabGen_q <= "011000110101";
WHEN "1011001" => memoryC2_uid127_exp2TabGen_q <= "011000111111";
WHEN "1011010" => memoryC2_uid127_exp2TabGen_q <= "011001000110";
WHEN "1011011" => memoryC2_uid127_exp2TabGen_q <= "011001001101";
WHEN "1011100" => memoryC2_uid127_exp2TabGen_q <= "011001011001";
WHEN "1011101" => memoryC2_uid127_exp2TabGen_q <= "011001100000";
WHEN "1011110" => memoryC2_uid127_exp2TabGen_q <= "011001101001";
WHEN "1011111" => memoryC2_uid127_exp2TabGen_q <= "011001110010";
WHEN "1100000" => memoryC2_uid127_exp2TabGen_q <= "011001111001";
WHEN "1100001" => memoryC2_uid127_exp2TabGen_q <= "011010000011";
WHEN "1100010" => memoryC2_uid127_exp2TabGen_q <= "011010001100";
WHEN "1100011" => memoryC2_uid127_exp2TabGen_q <= "011010011001";
WHEN "1100100" => memoryC2_uid127_exp2TabGen_q <= "011010100000";
WHEN "1100101" => memoryC2_uid127_exp2TabGen_q <= "011010101000";
WHEN "1100110" => memoryC2_uid127_exp2TabGen_q <= "011010110010";
WHEN "1100111" => memoryC2_uid127_exp2TabGen_q <= "011010111011";
WHEN "1101000" => memoryC2_uid127_exp2TabGen_q <= "011011000100";
WHEN "1101001" => memoryC2_uid127_exp2TabGen_q <= "011011001101";
WHEN "1101010" => memoryC2_uid127_exp2TabGen_q <= "011011011001";
WHEN "1101011" => memoryC2_uid127_exp2TabGen_q <= "011011100001";
WHEN "1101100" => memoryC2_uid127_exp2TabGen_q <= "011011101001";
WHEN "1101101" => memoryC2_uid127_exp2TabGen_q <= "011011110010";
WHEN "1101110" => memoryC2_uid127_exp2TabGen_q <= "011011111111";
WHEN "1101111" => memoryC2_uid127_exp2TabGen_q <= "011100000111";
WHEN "1110000" => memoryC2_uid127_exp2TabGen_q <= "011100010010";
WHEN "1110001" => memoryC2_uid127_exp2TabGen_q <= "011100011100";
WHEN "1110010" => memoryC2_uid127_exp2TabGen_q <= "011100100110";
WHEN "1110011" => memoryC2_uid127_exp2TabGen_q <= "011100110000";
WHEN "1110100" => memoryC2_uid127_exp2TabGen_q <= "011100111001";
WHEN "1110101" => memoryC2_uid127_exp2TabGen_q <= "011101000011";
WHEN "1110110" => memoryC2_uid127_exp2TabGen_q <= "011101001110";
WHEN "1110111" => memoryC2_uid127_exp2TabGen_q <= "011101011000";
WHEN "1111000" => memoryC2_uid127_exp2TabGen_q <= "011101100001";
WHEN "1111001" => memoryC2_uid127_exp2TabGen_q <= "011101101001";
WHEN "1111010" => memoryC2_uid127_exp2TabGen_q <= "011101111000";
WHEN "1111011" => memoryC2_uid127_exp2TabGen_q <= "011110000001";
WHEN "1111100" => memoryC2_uid127_exp2TabGen_q <= "011110001010";
WHEN "1111101" => memoryC2_uid127_exp2TabGen_q <= "011110010110";
WHEN "1111110" => memoryC2_uid127_exp2TabGen_q <= "011110100010";
WHEN "1111111" => memoryC2_uid127_exp2TabGen_q <= "011110101011";
WHEN OTHERS =>
memoryC2_uid127_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,200)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(15 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(15 downto 0);
--yT1_uid129_exp2PolyEval(BITSELECT,128)@5
yT1_uid129_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid129_exp2PolyEval_b <= yT1_uid129_exp2PolyEval_in(15 downto 4);
--reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0(REG,161)@5
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q <= yT1_uid129_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid142_pT1_uid130_exp2PolyEval(MULT,141)@6
prodXY_uid142_pT1_uid130_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_a),13)) * SIGNED(prodXY_uid142_pT1_uid130_exp2PolyEval_b);
prodXY_uid142_pT1_uid130_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= (others => '0');
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_a <= reg_yT1_uid129_exp2PolyEval_0_to_prodXY_uid142_pT1_uid130_exp2PolyEval_0_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_b <= memoryC2_uid127_exp2TabGen_q;
prodXY_uid142_pT1_uid130_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid142_pT1_uid130_exp2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid142_pT1_uid130_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid142_pT1_uid130_exp2PolyEval_q <= prodXY_uid142_pT1_uid130_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval(BITSELECT,142)@9
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in <= prodXY_uid142_pT1_uid130_exp2PolyEval_q;
prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_in(23 downto 11);
--highBBits_uid132_exp2PolyEval(BITSELECT,131)@9
highBBits_uid132_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b;
highBBits_uid132_exp2PolyEval_b <= highBBits_uid132_exp2PolyEval_in(12 downto 1);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a(DELAY,293)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid127_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid125_exp2TabGen(LOOKUP,124)@8
memoryC1_uid125_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid125_exp2TabGen_0_q_to_memoryC1_uid125_exp2TabGen_a_q) IS
WHEN "0000000" => memoryC1_uid125_exp2TabGen_q <= "001011000101110010001";
WHEN "0000001" => memoryC1_uid125_exp2TabGen_q <= "001011001001101000011";
WHEN "0000010" => memoryC1_uid125_exp2TabGen_q <= "001011001101100000100";
WHEN "0000011" => memoryC1_uid125_exp2TabGen_q <= "001011010001011010000";
WHEN "0000100" => memoryC1_uid125_exp2TabGen_q <= "001011010101010100101";
WHEN "0000101" => memoryC1_uid125_exp2TabGen_q <= "001011011001010000100";
WHEN "0000110" => memoryC1_uid125_exp2TabGen_q <= "001011011101001110001";
WHEN "0000111" => memoryC1_uid125_exp2TabGen_q <= "001011100001001100111";
WHEN "0001000" => memoryC1_uid125_exp2TabGen_q <= "001011100101001101010";
WHEN "0001001" => memoryC1_uid125_exp2TabGen_q <= "001011101001001110101";
WHEN "0001010" => memoryC1_uid125_exp2TabGen_q <= "001011101101010001101";
WHEN "0001011" => memoryC1_uid125_exp2TabGen_q <= "001011110001010110001";
WHEN "0001100" => memoryC1_uid125_exp2TabGen_q <= "001011110101011011111";
WHEN "0001101" => memoryC1_uid125_exp2TabGen_q <= "001011111001100011001";
WHEN "0001110" => memoryC1_uid125_exp2TabGen_q <= "001011111101101011101";
WHEN "0001111" => memoryC1_uid125_exp2TabGen_q <= "001100000001110110000";
WHEN "0010000" => memoryC1_uid125_exp2TabGen_q <= "001100000110000001100";
WHEN "0010001" => memoryC1_uid125_exp2TabGen_q <= "001100001010001110011";
WHEN "0010010" => memoryC1_uid125_exp2TabGen_q <= "001100001110011100110";
WHEN "0010011" => memoryC1_uid125_exp2TabGen_q <= "001100010010101100110";
WHEN "0010100" => memoryC1_uid125_exp2TabGen_q <= "001100010110111110010";
WHEN "0010101" => memoryC1_uid125_exp2TabGen_q <= "001100011011010000111";
WHEN "0010110" => memoryC1_uid125_exp2TabGen_q <= "001100011111100101100";
WHEN "0010111" => memoryC1_uid125_exp2TabGen_q <= "001100100011111011100";
WHEN "0011000" => memoryC1_uid125_exp2TabGen_q <= "001100101000010010011";
WHEN "0011001" => memoryC1_uid125_exp2TabGen_q <= "001100101100101011100";
WHEN "0011010" => memoryC1_uid125_exp2TabGen_q <= "001100110001000101100";
WHEN "0011011" => memoryC1_uid125_exp2TabGen_q <= "001100110101100001101";
WHEN "0011100" => memoryC1_uid125_exp2TabGen_q <= "001100111001111111100";
WHEN "0011101" => memoryC1_uid125_exp2TabGen_q <= "001100111110011110011";
WHEN "0011110" => memoryC1_uid125_exp2TabGen_q <= "001101000010111110111";
WHEN "0011111" => memoryC1_uid125_exp2TabGen_q <= "001101000111100001011";
WHEN "0100000" => memoryC1_uid125_exp2TabGen_q <= "001101001100000100110";
WHEN "0100001" => memoryC1_uid125_exp2TabGen_q <= "001101010000101010001";
WHEN "0100010" => memoryC1_uid125_exp2TabGen_q <= "001101010101010001000";
WHEN "0100011" => memoryC1_uid125_exp2TabGen_q <= "001101011001111001101";
WHEN "0100100" => memoryC1_uid125_exp2TabGen_q <= "001101011110100011110";
WHEN "0100101" => memoryC1_uid125_exp2TabGen_q <= "001101100011001111110";
WHEN "0100110" => memoryC1_uid125_exp2TabGen_q <= "001101100111111101000";
WHEN "0100111" => memoryC1_uid125_exp2TabGen_q <= "001101101100101011111";
WHEN "0101000" => memoryC1_uid125_exp2TabGen_q <= "001101110001011100101";
WHEN "0101001" => memoryC1_uid125_exp2TabGen_q <= "001101110110001111001";
WHEN "0101010" => memoryC1_uid125_exp2TabGen_q <= "001101111011000010110";
WHEN "0101011" => memoryC1_uid125_exp2TabGen_q <= "001101111111111000110";
WHEN "0101100" => memoryC1_uid125_exp2TabGen_q <= "001110000100110000000";
WHEN "0101101" => memoryC1_uid125_exp2TabGen_q <= "001110001001101001001";
WHEN "0101110" => memoryC1_uid125_exp2TabGen_q <= "001110001110100011011";
WHEN "0101111" => memoryC1_uid125_exp2TabGen_q <= "001110010011100000010";
WHEN "0110000" => memoryC1_uid125_exp2TabGen_q <= "001110011000011110100";
WHEN "0110001" => memoryC1_uid125_exp2TabGen_q <= "001110011101011101110";
WHEN "0110010" => memoryC1_uid125_exp2TabGen_q <= "001110100010011111100";
WHEN "0110011" => memoryC1_uid125_exp2TabGen_q <= "001110100111100010111";
WHEN "0110100" => memoryC1_uid125_exp2TabGen_q <= "001110101100100111111";
WHEN "0110101" => memoryC1_uid125_exp2TabGen_q <= "001110110001101110110";
WHEN "0110110" => memoryC1_uid125_exp2TabGen_q <= "001110110110110111101";
WHEN "0110111" => memoryC1_uid125_exp2TabGen_q <= "001110111100000010010";
WHEN "0111000" => memoryC1_uid125_exp2TabGen_q <= "001111000001001110101";
WHEN "0111001" => memoryC1_uid125_exp2TabGen_q <= "001111000110011100011";
WHEN "0111010" => memoryC1_uid125_exp2TabGen_q <= "001111001011101100100";
WHEN "0111011" => memoryC1_uid125_exp2TabGen_q <= "001111010000111110001";
WHEN "0111100" => memoryC1_uid125_exp2TabGen_q <= "001111010110010001100";
WHEN "0111101" => memoryC1_uid125_exp2TabGen_q <= "001111011011100111000";
WHEN "0111110" => memoryC1_uid125_exp2TabGen_q <= "001111100000111101111";
WHEN "0111111" => memoryC1_uid125_exp2TabGen_q <= "001111100110010111000";
WHEN "1000000" => memoryC1_uid125_exp2TabGen_q <= "001111101011110001111";
WHEN "1000001" => memoryC1_uid125_exp2TabGen_q <= "001111110001001111000";
WHEN "1000010" => memoryC1_uid125_exp2TabGen_q <= "001111110110101101110";
WHEN "1000011" => memoryC1_uid125_exp2TabGen_q <= "001111111100001110011";
WHEN "1000100" => memoryC1_uid125_exp2TabGen_q <= "010000000001110000111";
WHEN "1000101" => memoryC1_uid125_exp2TabGen_q <= "010000000111010101011";
WHEN "1000110" => memoryC1_uid125_exp2TabGen_q <= "010000001100111011011";
WHEN "1000111" => memoryC1_uid125_exp2TabGen_q <= "010000010010100100000";
WHEN "1001000" => memoryC1_uid125_exp2TabGen_q <= "010000011000001110011";
WHEN "1001001" => memoryC1_uid125_exp2TabGen_q <= "010000011101111010101";
WHEN "1001010" => memoryC1_uid125_exp2TabGen_q <= "010000100011101000101";
WHEN "1001011" => memoryC1_uid125_exp2TabGen_q <= "010000101001011001001";
WHEN "1001100" => memoryC1_uid125_exp2TabGen_q <= "010000101111001011100";
WHEN "1001101" => memoryC1_uid125_exp2TabGen_q <= "010000110100111111010";
WHEN "1001110" => memoryC1_uid125_exp2TabGen_q <= "010000111010110101110";
WHEN "1001111" => memoryC1_uid125_exp2TabGen_q <= "010001000000101110011";
WHEN "1010000" => memoryC1_uid125_exp2TabGen_q <= "010001000110101000001";
WHEN "1010001" => memoryC1_uid125_exp2TabGen_q <= "010001001100100100110";
WHEN "1010010" => memoryC1_uid125_exp2TabGen_q <= "010001010010100011011";
WHEN "1010011" => memoryC1_uid125_exp2TabGen_q <= "010001011000100011111";
WHEN "1010100" => memoryC1_uid125_exp2TabGen_q <= "010001011110100110100";
WHEN "1010101" => memoryC1_uid125_exp2TabGen_q <= "010001100100101011001";
WHEN "1010110" => memoryC1_uid125_exp2TabGen_q <= "010001101010110010001";
WHEN "1010111" => memoryC1_uid125_exp2TabGen_q <= "010001110000111011000";
WHEN "1011000" => memoryC1_uid125_exp2TabGen_q <= "010001110111000110000";
WHEN "1011001" => memoryC1_uid125_exp2TabGen_q <= "010001111101010011001";
WHEN "1011010" => memoryC1_uid125_exp2TabGen_q <= "010010000011100010110";
WHEN "1011011" => memoryC1_uid125_exp2TabGen_q <= "010010001001110100100";
WHEN "1011100" => memoryC1_uid125_exp2TabGen_q <= "010010010000000111111";
WHEN "1011101" => memoryC1_uid125_exp2TabGen_q <= "010010010110011110000";
WHEN "1011110" => memoryC1_uid125_exp2TabGen_q <= "010010011100110110010";
WHEN "1011111" => memoryC1_uid125_exp2TabGen_q <= "010010100011010000100";
WHEN "1100000" => memoryC1_uid125_exp2TabGen_q <= "010010101001101101011";
WHEN "1100001" => memoryC1_uid125_exp2TabGen_q <= "010010110000001100001";
WHEN "1100010" => memoryC1_uid125_exp2TabGen_q <= "010010110110101101001";
WHEN "1100011" => memoryC1_uid125_exp2TabGen_q <= "010010111101010000000";
WHEN "1100100" => memoryC1_uid125_exp2TabGen_q <= "010011000011110101111";
WHEN "1100101" => memoryC1_uid125_exp2TabGen_q <= "010011001010011110000";
WHEN "1100110" => memoryC1_uid125_exp2TabGen_q <= "010011010001001000001";
WHEN "1100111" => memoryC1_uid125_exp2TabGen_q <= "010011010111110100101";
WHEN "1101000" => memoryC1_uid125_exp2TabGen_q <= "010011011110100011101";
WHEN "1101001" => memoryC1_uid125_exp2TabGen_q <= "010011100101010100110";
WHEN "1101010" => memoryC1_uid125_exp2TabGen_q <= "010011101100001000000";
WHEN "1101011" => memoryC1_uid125_exp2TabGen_q <= "010011110010111110001";
WHEN "1101100" => memoryC1_uid125_exp2TabGen_q <= "010011111001110110101";
WHEN "1101101" => memoryC1_uid125_exp2TabGen_q <= "010100000000110001011";
WHEN "1101110" => memoryC1_uid125_exp2TabGen_q <= "010100000111101110000";
WHEN "1101111" => memoryC1_uid125_exp2TabGen_q <= "010100001110101101110";
WHEN "1110000" => memoryC1_uid125_exp2TabGen_q <= "010100010101101111101";
WHEN "1110001" => memoryC1_uid125_exp2TabGen_q <= "010100011100110011111";
WHEN "1110010" => memoryC1_uid125_exp2TabGen_q <= "010100100011111010110";
WHEN "1110011" => memoryC1_uid125_exp2TabGen_q <= "010100101011000100000";
WHEN "1110100" => memoryC1_uid125_exp2TabGen_q <= "010100110010001111111";
WHEN "1110101" => memoryC1_uid125_exp2TabGen_q <= "010100111001011110010";
WHEN "1110110" => memoryC1_uid125_exp2TabGen_q <= "010101000000101110111";
WHEN "1110111" => memoryC1_uid125_exp2TabGen_q <= "010101001000000010010";
WHEN "1111000" => memoryC1_uid125_exp2TabGen_q <= "010101001111011000001";
WHEN "1111001" => memoryC1_uid125_exp2TabGen_q <= "010101010110110000111";
WHEN "1111010" => memoryC1_uid125_exp2TabGen_q <= "010101011110001011010";
WHEN "1111011" => memoryC1_uid125_exp2TabGen_q <= "010101100101101001000";
WHEN "1111100" => memoryC1_uid125_exp2TabGen_q <= "010101101101001001010";
WHEN "1111101" => memoryC1_uid125_exp2TabGen_q <= "010101110100101011110";
WHEN "1111110" => memoryC1_uid125_exp2TabGen_q <= "010101111100010001000";
WHEN "1111111" => memoryC1_uid125_exp2TabGen_q <= "010110000011111001010";
WHEN OTHERS =>
memoryC1_uid125_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid133_exp2PolyEval(ADD,132)@9
sumAHighB_uid133_exp2PolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid125_exp2TabGen_q(20)) & memoryC1_uid125_exp2TabGen_q);
sumAHighB_uid133_exp2PolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid132_exp2PolyEval_b(11)) & highBBits_uid132_exp2PolyEval_b);
sumAHighB_uid133_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid133_exp2PolyEval_a) + SIGNED(sumAHighB_uid133_exp2PolyEval_b));
sumAHighB_uid133_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_o(21 downto 0);
--lowRangeB_uid131_exp2PolyEval(BITSELECT,130)@9
lowRangeB_uid131_exp2PolyEval_in <= prodXYTruncFR_uid143_pT1_uid130_exp2PolyEval_b(0 downto 0);
lowRangeB_uid131_exp2PolyEval_b <= lowRangeB_uid131_exp2PolyEval_in(0 downto 0);
--s1_uid131_uid134_exp2PolyEval(BITJOIN,133)@9
s1_uid131_uid134_exp2PolyEval_q <= sumAHighB_uid133_exp2PolyEval_q & lowRangeB_uid131_exp2PolyEval_b;
--reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1(REG,164)@9
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q <= s1_uid131_uid134_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor(LOGICAL,354)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_a or ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg(REG,352)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena(REG,355)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd(LOGICAL,356)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0(REG,163)@5
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q <= yPPolyEval_uid48_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg(DELAY,346)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q, xout => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt(COUNTER,348)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg(REG,349)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux(MUX,350)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem(DUALMEM,347)
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid145_pT2_uid136_exp2PolyEval(MULT,144)@10
prodXY_uid145_pT2_uid136_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_a),17)) * SIGNED(prodXY_uid145_pT2_uid136_exp2PolyEval_b);
prodXY_uid145_pT2_uid136_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= (others => '0');
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_a <= ld_reg_yPPolyEval_uid48_fpExp2Test_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_0_q_to_prodXY_uid145_pT2_uid136_exp2PolyEval_a_replace_mem_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_b <= reg_s1_uid131_uid134_exp2PolyEval_0_to_prodXY_uid145_pT2_uid136_exp2PolyEval_1_q;
prodXY_uid145_pT2_uid136_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid145_pT2_uid136_exp2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid145_pT2_uid136_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid145_pT2_uid136_exp2PolyEval_q <= prodXY_uid145_pT2_uid136_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval(BITSELECT,145)@13
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in <= prodXY_uid145_pT2_uid136_exp2PolyEval_q;
prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_in(38 downto 15);
--highBBits_uid138_exp2PolyEval(BITSELECT,137)@13
highBBits_uid138_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b;
highBBits_uid138_exp2PolyEval_b <= highBBits_uid138_exp2PolyEval_in(23 downto 2);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor(LOGICAL,367)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top(CONSTANT,363)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q <= "0100";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp(LOGICAL,364)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_mem_top_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q <= "1" when ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_a = ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_b else "0";
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg(REG,365)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena(REG,368)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd(LOGICAL,369)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg(DELAY,357)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt(COUNTER,359)
-- every=1, low=0, high=4, step=1, init=1
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i = 3 THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i - 4;
ELSE
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_i,3));
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg(REG,360)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux(MUX,361)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q, ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem(DUALMEM,358)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0(REG,165)@11
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid123_exp2TabGen(LOOKUP,122)@12
memoryC0_uid123_exp2TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid123_exp2TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid123_exp2TabGen_q <= "0100000000000000000000000100";
WHEN "0000001" => memoryC0_uid123_exp2TabGen_q <= "0100000001011000111101101111";
WHEN "0000010" => memoryC0_uid123_exp2TabGen_q <= "0100000010110010011010010100";
WHEN "0000011" => memoryC0_uid123_exp2TabGen_q <= "0100000100001100010101111110";
WHEN "0000100" => memoryC0_uid123_exp2TabGen_q <= "0100000101100110110000111001";
WHEN "0000101" => memoryC0_uid123_exp2TabGen_q <= "0100000111000001101011001111";
WHEN "0000110" => memoryC0_uid123_exp2TabGen_q <= "0100001000011101000101001010";
WHEN "0000111" => memoryC0_uid123_exp2TabGen_q <= "0100001001111000111110110111";
WHEN "0001000" => memoryC0_uid123_exp2TabGen_q <= "0100001011010101011000011111";
WHEN "0001001" => memoryC0_uid123_exp2TabGen_q <= "0100001100110010010010001111";
WHEN "0001010" => memoryC0_uid123_exp2TabGen_q <= "0100001110001111101100010001";
WHEN "0001011" => memoryC0_uid123_exp2TabGen_q <= "0100001111101101100110110000";
WHEN "0001100" => memoryC0_uid123_exp2TabGen_q <= "0100010001001100000001111000";
WHEN "0001101" => memoryC0_uid123_exp2TabGen_q <= "0100010010101010111101110100";
WHEN "0001110" => memoryC0_uid123_exp2TabGen_q <= "0100010100001010011010110000";
WHEN "0001111" => memoryC0_uid123_exp2TabGen_q <= "0100010101101010011000110110";
WHEN "0010000" => memoryC0_uid123_exp2TabGen_q <= "0100010111001010111000010011";
WHEN "0010001" => memoryC0_uid123_exp2TabGen_q <= "0100011000101011111001010010";
WHEN "0010010" => memoryC0_uid123_exp2TabGen_q <= "0100011010001101011011111111";
WHEN "0010011" => memoryC0_uid123_exp2TabGen_q <= "0100011011101111100000100101";
WHEN "0010100" => memoryC0_uid123_exp2TabGen_q <= "0100011101010010000111010000";
WHEN "0010101" => memoryC0_uid123_exp2TabGen_q <= "0100011110110101010000001101";
WHEN "0010110" => memoryC0_uid123_exp2TabGen_q <= "0100100000011000111011100110";
WHEN "0010111" => memoryC0_uid123_exp2TabGen_q <= "0100100001111101001001101000";
WHEN "0011000" => memoryC0_uid123_exp2TabGen_q <= "0100100011100001111010100000";
WHEN "0011001" => memoryC0_uid123_exp2TabGen_q <= "0100100101000111001110011000";
WHEN "0011010" => memoryC0_uid123_exp2TabGen_q <= "0100100110101101000101011110";
WHEN "0011011" => memoryC0_uid123_exp2TabGen_q <= "0100101000010011011111111101";
WHEN "0011100" => memoryC0_uid123_exp2TabGen_q <= "0100101001111010011110000001";
WHEN "0011101" => memoryC0_uid123_exp2TabGen_q <= "0100101011100001111111111000";
WHEN "0011110" => memoryC0_uid123_exp2TabGen_q <= "0100101101001010000101101110";
WHEN "0011111" => memoryC0_uid123_exp2TabGen_q <= "0100101110110010101111101110";
WHEN "0100000" => memoryC0_uid123_exp2TabGen_q <= "0100110000011011111110000111";
WHEN "0100001" => memoryC0_uid123_exp2TabGen_q <= "0100110010000101110001000011";
WHEN "0100010" => memoryC0_uid123_exp2TabGen_q <= "0100110011110000001000110001";
WHEN "0100011" => memoryC0_uid123_exp2TabGen_q <= "0100110101011011000101011100";
WHEN "0100100" => memoryC0_uid123_exp2TabGen_q <= "0100110111000110100111010010";
WHEN "0100101" => memoryC0_uid123_exp2TabGen_q <= "0100111000110010101110011111";
WHEN "0100110" => memoryC0_uid123_exp2TabGen_q <= "0100111010011111011011010001";
WHEN "0100111" => memoryC0_uid123_exp2TabGen_q <= "0100111100001100101101110101";
WHEN "0101000" => memoryC0_uid123_exp2TabGen_q <= "0100111101111010100110010111";
WHEN "0101001" => memoryC0_uid123_exp2TabGen_q <= "0100111111101001000101000101";
WHEN "0101010" => memoryC0_uid123_exp2TabGen_q <= "0101000001011000001010001101";
WHEN "0101011" => memoryC0_uid123_exp2TabGen_q <= "0101000011000111110101111010";
WHEN "0101100" => memoryC0_uid123_exp2TabGen_q <= "0101000100111000001000011100";
WHEN "0101101" => memoryC0_uid123_exp2TabGen_q <= "0101000110101001000001111111";
WHEN "0101110" => memoryC0_uid123_exp2TabGen_q <= "0101001000011010100010110010";
WHEN "0101111" => memoryC0_uid123_exp2TabGen_q <= "0101001010001100101011000000";
WHEN "0110000" => memoryC0_uid123_exp2TabGen_q <= "0101001011111111011010111001";
WHEN "0110001" => memoryC0_uid123_exp2TabGen_q <= "0101001101110010110010101011";
WHEN "0110010" => memoryC0_uid123_exp2TabGen_q <= "0101001111100110110010100010";
WHEN "0110011" => memoryC0_uid123_exp2TabGen_q <= "0101010001011011011010101101";
WHEN "0110100" => memoryC0_uid123_exp2TabGen_q <= "0101010011010000101011011010";
WHEN "0110101" => memoryC0_uid123_exp2TabGen_q <= "0101010101000110100100110111";
WHEN "0110110" => memoryC0_uid123_exp2TabGen_q <= "0101010110111101000111010010";
WHEN "0110111" => memoryC0_uid123_exp2TabGen_q <= "0101011000110100010010111001";
WHEN "0111000" => memoryC0_uid123_exp2TabGen_q <= "0101011010101100000111111011";
WHEN "0111001" => memoryC0_uid123_exp2TabGen_q <= "0101011100100100100110100111";
WHEN "0111010" => memoryC0_uid123_exp2TabGen_q <= "0101011110011101101111001001";
WHEN "0111011" => memoryC0_uid123_exp2TabGen_q <= "0101100000010111100001110010";
WHEN "0111100" => memoryC0_uid123_exp2TabGen_q <= "0101100010010001111110110000";
WHEN "0111101" => memoryC0_uid123_exp2TabGen_q <= "0101100100001101000110010001";
WHEN "0111110" => memoryC0_uid123_exp2TabGen_q <= "0101100110001000111000100101";
WHEN "0111111" => memoryC0_uid123_exp2TabGen_q <= "0101101000000101010101111001";
WHEN "1000000" => memoryC0_uid123_exp2TabGen_q <= "0101101010000010011110011110";
WHEN "1000001" => memoryC0_uid123_exp2TabGen_q <= "0101101100000000010010100001";
WHEN "1000010" => memoryC0_uid123_exp2TabGen_q <= "0101101101111110110010010011";
WHEN "1000011" => memoryC0_uid123_exp2TabGen_q <= "0101101111111101111110000010";
WHEN "1000100" => memoryC0_uid123_exp2TabGen_q <= "0101110001111101110101111110";
WHEN "1000101" => memoryC0_uid123_exp2TabGen_q <= "0101110011111110011010010110";
WHEN "1000110" => memoryC0_uid123_exp2TabGen_q <= "0101110101111111101011011010";
WHEN "1000111" => memoryC0_uid123_exp2TabGen_q <= "0101111000000001101001011000";
WHEN "1001000" => memoryC0_uid123_exp2TabGen_q <= "0101111010000100010100100001";
WHEN "1001001" => memoryC0_uid123_exp2TabGen_q <= "0101111100000111101101000100";
WHEN "1001010" => memoryC0_uid123_exp2TabGen_q <= "0101111110001011110011010010";
WHEN "1001011" => memoryC0_uid123_exp2TabGen_q <= "0110000000010000100111011001";
WHEN "1001100" => memoryC0_uid123_exp2TabGen_q <= "0110000010010110001001101010";
WHEN "1001101" => memoryC0_uid123_exp2TabGen_q <= "0110000100011100011010010110";
WHEN "1001110" => memoryC0_uid123_exp2TabGen_q <= "0110000110100011011001101011";
WHEN "1001111" => memoryC0_uid123_exp2TabGen_q <= "0110001000101011000111111010";
WHEN "1010000" => memoryC0_uid123_exp2TabGen_q <= "0110001010110011100101010101";
WHEN "1010001" => memoryC0_uid123_exp2TabGen_q <= "0110001100111100110010001010";
WHEN "1010010" => memoryC0_uid123_exp2TabGen_q <= "0110001111000110101110101010";
WHEN "1010011" => memoryC0_uid123_exp2TabGen_q <= "0110010001010001011011000111";
WHEN "1010100" => memoryC0_uid123_exp2TabGen_q <= "0110010011011100110111110000";
WHEN "1010101" => memoryC0_uid123_exp2TabGen_q <= "0110010101101001000100110111";
WHEN "1010110" => memoryC0_uid123_exp2TabGen_q <= "0110010111110110000010101100";
WHEN "1010111" => memoryC0_uid123_exp2TabGen_q <= "0110011010000011110001100000";
WHEN "1011000" => memoryC0_uid123_exp2TabGen_q <= "0110011100010010010001100101";
WHEN "1011001" => memoryC0_uid123_exp2TabGen_q <= "0110011110100001100011001011";
WHEN "1011010" => memoryC0_uid123_exp2TabGen_q <= "0110100000110001100110100011";
WHEN "1011011" => memoryC0_uid123_exp2TabGen_q <= "0110100011000010011011111111";
WHEN "1011100" => memoryC0_uid123_exp2TabGen_q <= "0110100101010100000011110001";
WHEN "1011101" => memoryC0_uid123_exp2TabGen_q <= "0110100111100110011110001001";
WHEN "1011110" => memoryC0_uid123_exp2TabGen_q <= "0110101001111001101011011001";
WHEN "1011111" => memoryC0_uid123_exp2TabGen_q <= "0110101100001101101011110100";
WHEN "1100000" => memoryC0_uid123_exp2TabGen_q <= "0110101110100010011111101010";
WHEN "1100001" => memoryC0_uid123_exp2TabGen_q <= "0110110000111000000111001110";
WHEN "1100010" => memoryC0_uid123_exp2TabGen_q <= "0110110011001110100010110010";
WHEN "1100011" => memoryC0_uid123_exp2TabGen_q <= "0110110101100101110010101000";
WHEN "1100100" => memoryC0_uid123_exp2TabGen_q <= "0110110111111101110111000001";
WHEN "1100101" => memoryC0_uid123_exp2TabGen_q <= "0110111010010110110000010000";
WHEN "1100110" => memoryC0_uid123_exp2TabGen_q <= "0110111100110000011110101000";
WHEN "1100111" => memoryC0_uid123_exp2TabGen_q <= "0110111111001011000010011011";
WHEN "1101000" => memoryC0_uid123_exp2TabGen_q <= "0111000001100110011011111011";
WHEN "1101001" => memoryC0_uid123_exp2TabGen_q <= "0111000100000010101011011100";
WHEN "1101010" => memoryC0_uid123_exp2TabGen_q <= "0111000110011111110001010000";
WHEN "1101011" => memoryC0_uid123_exp2TabGen_q <= "0111001000111101101101101001";
WHEN "1101100" => memoryC0_uid123_exp2TabGen_q <= "0111001011011100100000111011";
WHEN "1101101" => memoryC0_uid123_exp2TabGen_q <= "0111001101111100001011011001";
WHEN "1101110" => memoryC0_uid123_exp2TabGen_q <= "0111010000011100101101010111";
WHEN "1101111" => memoryC0_uid123_exp2TabGen_q <= "0111010010111110000111000110";
WHEN "1110000" => memoryC0_uid123_exp2TabGen_q <= "0111010101100000011000111011";
WHEN "1110001" => memoryC0_uid123_exp2TabGen_q <= "0111011000000011100011001010";
WHEN "1110010" => memoryC0_uid123_exp2TabGen_q <= "0111011010100111100110000101";
WHEN "1110011" => memoryC0_uid123_exp2TabGen_q <= "0111011101001100100010000001";
WHEN "1110100" => memoryC0_uid123_exp2TabGen_q <= "0111011111110010010111010001";
WHEN "1110101" => memoryC0_uid123_exp2TabGen_q <= "0111100010011001000110001001";
WHEN "1110110" => memoryC0_uid123_exp2TabGen_q <= "0111100101000000101110111110";
WHEN "1110111" => memoryC0_uid123_exp2TabGen_q <= "0111100111101001010010000011";
WHEN "1111000" => memoryC0_uid123_exp2TabGen_q <= "0111101010010010101111101101";
WHEN "1111001" => memoryC0_uid123_exp2TabGen_q <= "0111101100111101001000001111";
WHEN "1111010" => memoryC0_uid123_exp2TabGen_q <= "0111101111101000011100000000";
WHEN "1111011" => memoryC0_uid123_exp2TabGen_q <= "0111110010010100101011010010";
WHEN "1111100" => memoryC0_uid123_exp2TabGen_q <= "0111110101000001110110011011";
WHEN "1111101" => memoryC0_uid123_exp2TabGen_q <= "0111110111101111111101110000";
WHEN "1111110" => memoryC0_uid123_exp2TabGen_q <= "0111111010011111000001100101";
WHEN "1111111" => memoryC0_uid123_exp2TabGen_q <= "0111111101001111000010001111";
WHEN OTHERS =>
memoryC0_uid123_exp2TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid139_exp2PolyEval(ADD,138)@13
sumAHighB_uid139_exp2PolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => memoryC0_uid123_exp2TabGen_q(27)) & memoryC0_uid123_exp2TabGen_q);
sumAHighB_uid139_exp2PolyEval_b <= STD_LOGIC_VECTOR((28 downto 22 => highBBits_uid138_exp2PolyEval_b(21)) & highBBits_uid138_exp2PolyEval_b);
sumAHighB_uid139_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid139_exp2PolyEval_a) + SIGNED(sumAHighB_uid139_exp2PolyEval_b));
sumAHighB_uid139_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_o(28 downto 0);
--lowRangeB_uid137_exp2PolyEval(BITSELECT,136)@13
lowRangeB_uid137_exp2PolyEval_in <= prodXYTruncFR_uid146_pT2_uid136_exp2PolyEval_b(1 downto 0);
lowRangeB_uid137_exp2PolyEval_b <= lowRangeB_uid137_exp2PolyEval_in(1 downto 0);
--s2_uid137_uid140_exp2PolyEval(BITJOIN,139)@13
s2_uid137_uid140_exp2PolyEval_q <= sumAHighB_uid139_exp2PolyEval_q & lowRangeB_uid137_exp2PolyEval_b;
--peOR_uid50_fpExp2Test(BITSELECT,49)@13
peOR_uid50_fpExp2Test_in <= s2_uid137_uid140_exp2PolyEval_q(28 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(28 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@13
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(22 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(22 downto 0);
--ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b(DELAY,235)@7
ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 6 )
PORT MAP ( xin => excREnc_uid70_fpExp2Test_q, xout => ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid74_fpExp2Test(MUX,73)@13
fracRPostExc_uid74_fpExp2Test_s <= ld_excREnc_uid70_fpExp2Test_q_to_fracRPostExc_uid74_fpExp2Test_b_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, fracR_uid52_fpExp2Test_b, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= fracR_uid52_fpExp2Test_b;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@13
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@13
q <= RExp2_uid79_fpExp2Test_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_sgn_mul3s.vhd | 10 | 5383 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SGN_MUL3S.VHD ***
--*** ***
--*** Function: Signed Multiplier - 3 Pipe ***
--*** Stages ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_sgn_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_sgn_mul3s;
ARCHITECTURE SYN OF fp_sgn_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/dp_lnlutpow.vhd | 10 | 230947 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlutpow;
ARCHITECTURE rtl OF dp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "0000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "0000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1023,11);
WHEN "0000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1024,11);
WHEN "0000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1025,11);
WHEN "0000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1026,11);
WHEN "0000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1027,11);
WHEN "0000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1028,11);
WHEN "0001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1029,11);
WHEN "0010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1030,11);
WHEN "0101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "0111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1000111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1001111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1010111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28);
logexp <= conv_std_logic_vector(1031,11);
WHEN "1011100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1011111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1100111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1101111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1110111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111000111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111001111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111010111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111011111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111100111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111101111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111110111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111000" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111001" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111010" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111011" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111100" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111101" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111110" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN "1111111111" =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28);
logexp <= conv_std_logic_vector(1032,11);
WHEN others =>
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_div_est.vhd | 10 | 6558 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse ***
--*** ***
--*** Used by both single and double dividers ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_div_est;
ARCHITECTURE rtl OF fp_div_est IS
type twodelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type ziplutdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (17 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal twodelff : twodelfftype;
signal ziplutdelff : ziplutdelfftype;
signal invdivisorff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 17 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= divisor(18 DOWNTO 10);
two <= divisor(9 DOWNTO 1);
-- these register seperate to make the LUTs into memories
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
onelutff <= onelut;
ziplutff <= ziplut;
END IF;
END IF;
END PROCESS;
upper: fp_div_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_div_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 20 LOOP
invdivisorff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invdivisorff <= ziplutdelff(2)(20 DOWNTO 1) -
(zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
invdivisor <= invdivisorff(20 DOWNTO 3);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_lsftpipe36.vhd | 10 | 4409 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE36.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftpipe36;
ARCHITECTURE rtl OF hcc_lsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dotProduct64_safe_path_sv.vhd | 10 | 410 | -- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_normfp1x.vhd | 10 | 10480 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** ***
--***************************************************
-- normalize signed numbers (x input format) - for 1x multipliers
-- format signed32/36 bit mantissa, 10 bit exponent
-- unsigned numbers for divider (S,1,23 bit mantissa for divider)
-- divider packed into 32/36bit mantissa + exponent
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
| mit |
richjyoung/lfsr-package | src/LFSR/lfsr_components.vhd | 1 | 490 | library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package lfsr_components is
component pulse is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end component;
end lfsr_components; | mit |
pedabraham/MDSM | crs/bitsToNumbers.vhd | 1 | 948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end bitsToNumbers;
architecture Behavioral of bitsToNumbers is
begin
process(cadenaOriginalDeBits)
begin
case cadenaOriginalDeBits is
when "100000000" => numero <= "0001";
when "010000000" => numero <= "0010";
when "001000000" => numero <= "0011";
when "000100000" => numero <= "0100";
when "000010000" => numero <= "0101";
when "000001000" => numero <= "0110";
when "000000100" => numero <= "0111";
when "000000010" => numero <= "1000";
when "000000001" => numero <= "1001";
when others => numero <= "0000";
end case;
end process;
end architecture;
| mit |
peteg944/music-fpga | Experimental/Zedboard UART/i2c.vhd | 3 | 2393 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; | mit |
thoralt/KCVGA | FPGA/ColorGenerator.vhd | 1 | 2392 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ColorGenerator IS PORT
(
SIGNAL pixel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL r, g, b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ColorGenerator;
ARCHITECTURE Behavioral OF ColorGenerator IS
TYPE RGB_type IS RECORD R, G, B : STD_LOGIC_VECTOR(3 DOWNTO 0);
END RECORD;
TYPE COLORS_type IS ARRAY (0 TO 31) OF RGB_type;
CONSTANT COLORS : COLORS_type := (
-- "00xxx" => background, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0111"), -- 1 blau
("0111", "0000", "0000"), -- 2 rot
("0111", "0000", "0111"), -- 3 purpur
("0000", "0111", "0000"), -- 4 grün
("0000", "0111", "0111"), -- 5 türkis
("0111", "0111", "0000"), -- 6 gelb
("0111", "0111", "0111"), -- 7 weiß
-- "01xxx" => undefined
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
-- "10xxx" => foreground, highlight
("0000", "0000", "0000"), -- 8 schwarz #000000
("0110", "0000", "1111"), -- 9 violett #5901FF
("1111", "0110", "0000"), -- A orange #FF5901
("1111", "0000", "1011"), -- B purpurrot #FF01B3
("0000", "1111", "0110"), -- C grünblau #01FF5A
("0000", "1000", "1111"), -- D blaugrün #0186FF
("1000", "1111", "0000"), -- E gelbgrün #86FF01
("1111", "1111", "1111"), -- F weiß #FFFFFF
-- "11xxx" => foreground, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "1111"), -- 1 blau
("1111", "0000", "0000"), -- 2 rot
("1111", "0000", "1111"), -- 3 purpur
("0000", "1111", "0000"), -- 4 grün
("0000", "1111", "1111"), -- 5 türkis
("1111", "1111", "0000"), -- 6 gelb
("1111", "1111", "1111") -- 7 weiß
);
BEGIN
R <= COLORS(to_integer(unsigned(PIXEL))).R;
G <= COLORS(to_integer(unsigned(PIXEL))).G;
B <= COLORS(to_integer(unsigned(PIXEL))).B;
END Behavioral;
| mit |
migueljiarr/RV32I | src/left_XLEN_barrel_shifter.vhd | 1 | 1157 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity left_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end left_XLEN_barrel_shifter;
architecture structural of left_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i (30 downto 0) & '0';
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= s1 (29 downto 0) & "00";
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= s2 (27 downto 0) & "0000";
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= s3 (23 downto 0) & "00000000";
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= s4 (15 downto 0) & "0000000000000000";
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
| mit |
ou-cse-378/vhdl-tetris | whypcore.vhd | 1 | 7449 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: Whypcore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP Core
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity whypcore is
port (
p : out STD_LOGIC_VECTOR(15 downto 0);
destro : in STD_LOGIC_VECTOR(2 downto 0);
m : in STD_LOGIC_VECTOR(15 downto 0);
SW : in std_logic_vector(7 downto 0);
BTN4 : in std_logic;
b : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
digload : out STD_LOGIC;
ldload: out STD_LOGIC;
t : out STD_LOGIC_VECTOR(15 downto 0);
o_Clear_Lines : out std_logic
);
end whypcore;
architecture Behavioral of whypcore is
component mux2g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
sel : in std_logic;
y : out std_logic_vector(width-1 downto 0)
);
end component;
component PC
port (
d : in STD_LOGIC_VECTOR (15 downto 0);
clr : in STD_LOGIC;
clk : in STD_LOGIC;
inc : in STD_LOGIC;
pload : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component plus1a
Port ( input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end component;
component reg
generic(width: positive);
port (
d : in STD_LOGIC_VECTOR (width-1 downto 0);
load : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component WC16C_control
port (
oClearLines : out std_logic;
icode : in STD_LOGIC_VECTOR (15 downto 0);
M : in STD_LOGIC_VECTOR (15 downto 0);
BTN4 : in std_logic;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
fcode : out STD_LOGIC_VECTOR (5 downto 0);
pinc : out STD_LOGIC;
pload : out STD_LOGIC;
tload : out STD_LOGIC;
nload : out STD_LOGIC;
digload : out STD_LOGIC;
iload : out STD_LOGIC;
dpush : out STD_LOGIC;
dpop : out STD_LOGIC;
tsel : out STD_LOGIC_VECTOR (2 downto 0);
nsel : out STD_LOGIC_VECTOR (1 downto 0);
ssel : out STD_LOGIC;
R : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC_VECTOR (15 downto 0);
rsel : out STD_LOGIC;
rload : out STD_LOGIC;
rdec : out STD_LOGIC;
rpush : out STD_LOGIC;
rpop : out STD_LOGIC;
ldload : out STD_LOGIC;
psel : out STD_LOGIC;
rinsel : out STD_LOGIC
);
end component;
component ReturnStack
Port ( Rin : in std_logic_vector(15 downto 0);
rsel : in std_logic;
rload : in std_logic;
rdec : in std_logic;
clr : in std_logic;
clk : in std_logic;
rpush : in std_logic;
rpop : in std_logic;
R : out std_logic_vector(15 downto 0));
end component;
component mux8g
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
c : in std_logic_vector(width-1 downto 0);
d : in std_logic_vector(width-1 downto 0);
e : in std_logic_vector(width-1 downto 0);
f : in std_logic_vector(width-1 downto 0);
g : in std_logic_vector(width-1 downto 0);
h : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic_vector(width-1 downto 0)
);
end component;
component datastack
port (
TLoad : in std_logic;
y1 : in STD_LOGIC_VECTOR(15 downto 0);
nsel : in STD_LOGIC_VECTOR(1 downto 0);
nload : in STD_LOGIC;
ssel : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
dpush : in STD_LOGIC;
dpop : in STD_LOGIC;
Tin : in STD_LOGIC_VECTOR(15 downto 0);
T : out STD_LOGIC_VECTOR(15 downto 0);
N : out STD_LOGIC_VECTOR(15 downto 0);
N2 : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component funit1
generic(width:positive);
port (
a : in STD_LOGIC_VECTOR(width-1 downto 0);
b : in STD_LOGIC_VECTOR(width-1 downto 0);
sel : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end component;
constant bus_width: positive := 16;
signal Y: std_logic_vector(15 downto 0);
signal tC : std_logic_vector(15 downto 0);
signal tE : std_logic_vector(15 downto 0);
signal Y1: std_logic_vector(15 downto 0);
signal T1: std_logic_vector(15 downto 0);
signal TIN: std_logic_vector(15 downto 0);
signal N: std_logic_vector(15 downto 0);
signal N2: std_logic_vector(15 downto 0);
signal ICODE: std_logic_vector(15 downto 0);
signal FCODE: std_logic_vector(5 downto 0);
signal ILOAD: std_logic;
signal R: std_logic_vector(15 downto 0);
signal E1: std_logic_vector(15 downto 0);
signal E2: std_logic_vector(15 downto 0);
signal PLOAD: std_logic;
signal TLOAD: std_logic;
signal NLOAD: std_logic;
signal PINC: std_logic;
signal NSEL: std_logic_vector(1 downto 0);
signal DPUSH: std_logic;
signal DPOP: std_logic;
signal TSEL: std_logic_vector(2 downto 0);
signal SSEL: std_logic;
signal Pin: std_logic_vector(15 downto 0);
signal PS: std_logic_vector(15 downto 0);
signal P1: std_logic_vector(15 downto 0);
signal Rin: std_logic_vector(15 downto 0);
signal rsel: std_logic;
signal rload: std_logic;
signal rdec: std_logic;
signal rpush: std_logic;
signal rpop: std_logic;
signal rinsel: std_logic;
signal psel: STD_LOGIC;
begin
T <= T1;
P <= PS;
tE <= "0000000000000" & destro(2) & destro(1) & destro(0);
tC <= "00000000" & SW;
SWpmux : mux2g generic map (width => bus_width) port map
( a => M, b => R, sel => psel, y => Pin );
SWpc : pc port map
( d => Pin, clr => CLR, clk => CLK, inc => PINC, pload => PLOAD, q => PS );
SWplus1a : plus1a port map
( input => PS, output => P1 );
SWir : reg generic map (width => bus_width) port map
( d => M, load => ILOAD, clr => CLR, clk => CLK, q => ICODE );
SWwc16ccontrol : WC16C_control port map
( R => R, icode => ICODE, oClearLines => o_Clear_Lines, BTN4 => BTN4, M => M, clr => CLR, clk => CLK, fcode => FCODE, pinc => PINC, pload => PLOAD, tload => TLOAD, nload => NLOAD, digload => DIGLOAD, iload => ILOAD, dpush => DPUSH, dpop => DPOP, tsel => TSEL, nsel => NSEL, ssel => SSEL, T => T1, ldload => ldload, rload => rload, rdec => rdec, rinsel => rinsel, rsel => rsel, rpush => rpush, rpop => rpop, psel => psel );
SWrmux : mux2g generic map (width => bus_width) port map
( a => P1, b => T1, sel => rinsel, y => Rin );
SWreturnstack : ReturnStack port map
( Rin => Rin, rsel => rsel, rload => rload, rdec => rdec, clr => clr, clk => clk, rpush => rpush, rpop => rpop, r => R );
SWtmux : mux8g generic map (width => bus_width) port map
( a => Y, b => M, c => tC , d => R, e => tE, f => "0000000000000000", g => N2, h => N, sel => TSEL, y => TIN );
SWdatastack : datastack port map
( Tload => TLOAD, y1 => Y1, nsel => NSEL, nload => NLOAD, ssel => SSEL, clk => CLK, clr => CLR, dpush => DPUSH, dpop => DPOP, tin => TIN, N => N, N2 => N2, T => T1 );
SWfunit1 : funit1 generic map (width => bus_width) port map
( a => T1, b => N, sel => FCODE, y => Y );
end behavioral; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_mul5418s.vhd | 10 | 4973 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 3/Keyboard/keycode_to_ascii.vhd | 1 | 6905 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
ASCII : out STD_LOGIC_VECTOR(7 downto 0)--;
--KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0);
--WRITE_KEYBOARD: out STD_LOGIC;
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Caps_Lock : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"6C" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"66" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"74" when x"2D", -- r
x"73" when x"1B", -- s
x"72" when x"2C", -- t
x"79" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"75" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--special characters -- taking up unneaded ascii codes for simplicity
x"05" when x"58", -- Caps Lock
x"06" when x"14", -- Ctrl
x"07" when x"11", -- Alt
x"08" when x"66", -- Back Space
x"20" when x"29", -- Space
--Direction Keys -- taking up unneaded ascii codes for simplicity
x"01" when x"75", -- Up
x"02" when x"72", -- Down
x"03" when x"6B", -- Left
x"04" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"48" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"45" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"54" when x"1B", -- S
x"53" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,CLK, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '0' ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
state <= idle;
when idle =>
COMPLETE <= '0';
if VALID_SIGNAL= '1' then
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := true;
end if;
end if;
when READ_EXTENDED =>
if VALID_SIGNAL= '1' then
Extended := true;
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_BREAKCODE =>
if VALID_SIGNAL= '1' then
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_KEYCODE =>
if VALID_SIGNAL= '1' then
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"54") then
Shift_Key := false;
elsif (keycode=x"46") then
if (Caps_Lock = false) then
Caps_Lock := true;
else
Caps_Lock := false;
end if;
--state <= SEND_CAPS;
else
if (Shift_Key = true or Caps_Lock = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
state <= SEND_COMPLETE;
end if;
when SEND_COMPLETE =>
COMPLETE <= '1';
state <= idle;
--when SEND_CAPS =>
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_mulufp54.vhd | 10 | 5016 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (synthesize : integer := 1); -- 0 = behavioral, 1 = instantiated
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (5 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (5 DOWNTO 1);
component hcc_mul54usb
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54uss
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00000";
cczipff <= "00000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO 5 LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO 5 LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul54uss
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(5)(13 DOWNTO 1);
ccsat <= ccsatff(5);
cczip <= cczipff(5);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_clz23.vhd | 10 | 4166 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_usgnpos_sv.vhd | 20 | 6063 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp2x.vhd | 10 | 13893 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_tb.vhd | 10 | 7649 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_tb_vhd IS
END ALU_tb_vhd;
ARCHITECTURE behavior OF ALU_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR(7 downto 0);
RB : in STD_LOGIC_VECTOR(7 downto 0);
OPCODE : in STD_LOGIC_VECTOR(3 downto 0);
CCR : out STD_LOGIC_VECTOR(3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
--Outputs
SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
--Condition Codes
SIGNAL N : STD_LOGIC := '0';
SIGNAL Z : STD_LOGIC := '0';
SIGNAL V : STD_LOGIC := '0';
SIGNAL C : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP( CLK => CLK,
RA => RA,
RB => RB,
OPCODE => OPCODE,
CCR => CCR,
ALU_OUT => ALU_OUT,
LDST_OUT => LDST_OUT);
-- Assign condition code bits
N <= CCR(3); -- N - Negative
Z <= CCR(2); -- Z - Zero
V <= CCR(1); -- V - Overflow
C <= CCR(0); -- C - Carry/Borrow
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start ALU Test Bench" severity NOTE;
----- Register-Register Arithmetic Tests -----
RA <= "00000101"; -- 5
RB <= "00000011"; -- 3
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01100100"; -- 100
RB <= "00110010"; -- 50
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END Arithmetic Tests -----
----- CCR Tests -----
RA <= "00000000";
RB <= "00000000";
OPCODE <= "0000"; wait for period;
assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000001";
RB <= "11111111";
OPCODE <= "0000"; wait for period;
assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000000";
RB <= "00000001";
OPCODE <= "0001"; wait for period;
assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "11111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END CCR Tests -----
-- Mem Test --
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= X"16";
OPCODE <= "1010"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
-- END Mem Test --
report "Finish ALU Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/hcc_castytof.vhd | 10 | 3181 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>midnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,
cc=>cc);
END rtl;
| mit |
rtucker/nios_codebreaker | vhdl/lfsr_peripheral.vhd | 1 | 7660 | --************************** VHDL Source Code ****************************
--*************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan S. Tucker <rst7983@rit.edu>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: lfsr_peripheral.vhd
--
---------------------------------------------------------------------------
--
-- DESCRIPTION
--
-- This design will implement a 16-bit Galois linear-feedback shift
-- register for pseudorandom number generation.
--
-- About LFSRs:
-- https://en.wikipedia.org/wiki/Linear_feedback_shift_register
--
-- Addresses of this component:
-- 0 status R bit 0: 1 if LFSR is seeded, 0 if not
-- bit 1: 1 if seed value is nonzero, 0 if zero
-- 1 control W bit 0: 1 to reseed LFSR from seed register
-- (note: status bit 1 MUST be 1 first)
-- 2 lfsr R current 16-bit LFSR value
-- 3 seed RW seed value for LFSR
--
---------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- ______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+======+=====+==============================================
-- | | | |
-- | 04/21/13 | RST | 1.0 | Created
-- | | | |
-- |----------|------|-----|----------------------------------------------
--
--*************************************************************************
--*************************************************************************
library IEEE;
use IEEE.std_logic_1164.ALL;
--use IEEE.numeric_std.ALL;
--use IEEE.numeric_std_unsigned.ALL;
use IEEE.std_logic_unsigned.ALL;
entity lfsr_peripheral is
port (
-- inputs
clk : in std_logic;
reset_n : in std_logic;
we_n : in std_logic;
be_n : in std_logic_vector(1 downto 0);
a : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
-- outputs
dout : out std_logic_vector(15 downto 0)
);
end entity lfsr_peripheral;
architecture rtl of lfsr_peripheral is
-- constants
constant STAT_ADDR : std_logic_vector(1 downto 0) := "00";
constant CTRL_ADDR : std_logic_vector(1 downto 0) := "01";
constant LFSR_ADDR : std_logic_vector(1 downto 0) := "10";
constant SEED_ADDR : std_logic_vector(1 downto 0) := "11";
constant READ : std_logic := '1';
constant WRITE : std_logic := '0';
constant RESET : std_logic := '0';
constant BYTE_EN : std_logic := '0';
constant UNSEEDED : std_logic := '0';
constant SEEDED : std_logic := '1';
constant INVALID : std_logic := '0';
constant VALID : std_logic := '1';
constant NOTNOW : std_logic := '0';
constant DOITNOW : std_logic := '1';
constant ZEROS_8 : std_logic_vector := "00000000";
-- internal signals
signal din_h : std_logic_vector(7 downto 0);
signal din_l : std_logic_vector(7 downto 0);
signal be_n_h : std_logic;
signal be_n_l : std_logic;
-- registers
signal reg_seed_h : std_logic_vector(7 downto 0);
signal reg_seed_l : std_logic_vector(7 downto 0);
signal reg_lfsr : std_logic_vector(15 downto 0);
signal reg_stat : std_logic_vector(15 downto 0);
-- control and status flags
signal is_seeded : std_logic := UNSEEDED;
signal seed_valid : std_logic := INVALID;
signal ctrl_doseed : std_logic := NOTNOW;
begin
-- combinational logic: break down long signals into shorter ones, and
-- vice versa
din_h <= din(15 downto 8);
din_l <= din(7 downto 0);
be_n_h <= be_n(1);
be_n_l <= be_n(0);
-- test seed validity
seed_valid <= INVALID when (reg_seed_h = ZEROS_8 and reg_seed_l = ZEROS_8)
else VALID;
-- process: seed_register_p
-- handle writes to the seed register
-- control inputs: a, we_n, be_n_h
-- bus output: din
-- registers: reg_seed_h, reg_seed_l
seed_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
-- Reset seed register to zero
reg_seed_h <= (others => '0');
reg_seed_l <= (others => '0');
elsif (rising_edge(clk)) then
if (a = SEED_ADDR and we_n = WRITE and be_n_h = BYTE_EN) then
reg_seed_h <= din_h;
end if;
if (a = SEED_ADDR and we_n = WRITE and be_n_l = BYTE_EN) then
reg_seed_l <= din_l;
end if;
end if;
end process seed_register_p;
-- process: lfsr_register_p
-- implements the linear feedback shift register
-- control input: ctrl_doseed
-- status output: is_seeded
-- register: reg_lfsr
lfsr_register_p : process(clk, reset_n) is
variable carry_bit : std_logic;
variable new_lfsr : std_logic_vector(15 downto 0);
begin
if (reset_n = RESET) then
-- Reset LFSR register to all-ones
-- (as 0 is an invalid state)
reg_lfsr <= (others => '1');
is_seeded <= UNSEEDED;
elsif (rising_edge(clk)) then
if (ctrl_doseed = DOITNOW) then
-- replace our LFSR with the seed
reg_lfsr <= reg_seed_h & reg_seed_l;
is_seeded <= SEEDED;
else
-- recirculating shift right, with carry bit xor'd at
-- taps: 16, 14, 13, 11
carry_bit := reg_lfsr(0);
new_lfsr(15) := carry_bit;
new_lfsr(14) := reg_lfsr(15) ;
new_lfsr(13) := reg_lfsr(14) xor carry_bit;
new_lfsr(12) := reg_lfsr(13) xor carry_bit;
new_lfsr(11) := reg_lfsr(12);
new_lfsr(10) := reg_lfsr(11) xor carry_bit;
new_lfsr(9 downto 0) := reg_lfsr(10 downto 1);
-- update register
reg_lfsr <= new_lfsr;
end if;
end if;
end process lfsr_register_p;
-- process: ctrl_register_p
-- implements a write-only control register
-- control inputs: a, we_n, be_n_l, seed_valid
-- control output: ctrl_doseed
ctrl_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
ctrl_doseed <= NOTNOW;
elsif (rising_edge(clk)) then
if (a = CTRL_ADDR and we_n = WRITE and be_n_l = BYTE_EN
and seed_valid = VALID) then
ctrl_doseed <= DOITNOW;
else
ctrl_doseed <= NOTNOW;
end if;
end if;
end process ctrl_register_p;
-- process: stat_register_p
-- updates a read-only status register
-- status inputs: is_seeded, seed_valid
-- register: reg_stat
stat_register_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
reg_stat <= (others => '0');
elsif (rising_edge(clk)) then
reg_stat <= (others => '0');
reg_stat(0) <= is_seeded;
reg_stat(1) <= seed_valid;
end if;
end process stat_register_p;
-- process: register_read_p
-- selects requested register values to the dout bus
-- control input: a
-- bus output: dout
register_read_p : process(clk, reset_n) is
begin
if (reset_n = RESET) then
dout <= (others => '0');
elsif (rising_edge(clk)) then
case a is
when STAT_ADDR =>
dout <= reg_stat;
when LFSR_ADDR =>
dout <= reg_lfsr;
when SEED_ADDR =>
dout <= reg_seed_h & reg_seed_l;
when others =>
dout <= (others => '0');
end case;
end if;
end process register_read_p;
end architecture rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 2/ALU/alu_toplevel.vhd | 7 | 2688 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/dp_lsftpipe64x64.vhd | 10 | 4921 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_divfp2x.vhd | 10 | 22387 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVFP2X.VHD ***
--*** ***
--*** Function: Internal format double divide - ***
--*** unsigned mantissa ***
--*** ***
--*** Uses new multiplier based divider core ***
--*** from floating point library ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 23/04/09 - added NAN support ***
--*** 27/04/09 - added SIII/SIV support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 20 + 4*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 20 + 4*doublespeed (F) ***
--*** Latency = 20 + 4*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 19 + 2*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 19 + 2*doublespeed (F) ***
--*** Latency = 19 + 2*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--***************************************************
ENTITY hcc_divfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- output to another multiplier or divider (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_divfp2x;
ARCHITECTURE rtl OF hcc_divfp2x IS
-- SII: div_core latency 19+4*doublespeed
-- SIII/IV: div_core latency 18+2*doublespeed
constant midlatency : positive := 18+4*doublespeed - device - 2*device*doublespeed;
type divinexpfftype IS ARRAY (midlatency DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type divexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- divider core interface
signal divinaaman, divinbbman : STD_LOGIC_VECTOR(53 DOWNTO 1);
signal divinaaexp, divinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaaexpff, divinbbexpff : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaasat, divinaazip, divinaanan : STD_LOGIC;
signal divinbbsat, divinbbzip, divinbbnan : STD_LOGIC;
signal divinaasatff, divinaazipff, divinaananff : STD_LOGIC;
signal divinbbsatff, divinbbzipff, divinbbnanff : STD_LOGIC;
signal divinaasign, divinbbsign : STD_LOGIC;
signal divinaasignff, divinbbsignff : STD_LOGIC;
signal divinexpff : divinexpfftype;
signal divinsignff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal divinsatff, divinzipff, divinnanff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal dividend, divisor : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divmannode : STD_LOGIC_VECTOR (55 DOWNTO 1);
-- output section (x out)
signal signeddivmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divmanout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divymanff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divyexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divysatbitff, divyzipbitff, divynanbitff : STD_LOGIC;
signal divexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divyexpdelff : divexpdelfftype;
signal divysatdelff, divyzipdelff, divynandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal divsatbase, divzipbase : STD_LOGIC;
-- output section (divout)
signal normmannode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal divdivmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divdivexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divdivsatff, divdivzipff, divdivnanff : STD_LOGIC;
-- output section (ieeeout)
signal normsignff, normsatff, normzipff, normnanff : STD_LOGIC;
signal normalize : STD_LOGIC;
signal normalnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
component dp_div_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
end component;
-- latency 1
component hcc_divnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 2
component hcc_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 3
component hcc_divrndpipe
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT THE SIGN BIT IS PACKED IN THE MSB OF ***
--*** THE MANTISSA ***
--********************************************************
divinaaman <= aa(66 DOWNTO 14);
divinaaexp <= aa(13 DOWNTO 1);
divinbbman <= bb(66 DOWNTO 14);
divinbbexp <= bb(13 DOWNTO 1);
divinaasat <= aasat;
divinbbsat <= bbsat;
divinaazip <= aazip;
divinbbzip <= bbzip;
divinaanan <= aanan;
divinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
divinaasign <= aa(67);
divinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Divider Section ***
--*** ***
--**************************************************
dividend <= divinaaman & '0';
divisor <= divinbbman & '0';
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
div: dp_div_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dividend=>dividend,divisor=>divisor,
quotient=>divmannode);
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
divinaaexpff(k) <= '0';
divinbbexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO midlatency LOOP
FOR j IN 1 TO 13 LOOP
divinexpff(k)(j) <= '0';
END LOOP;
END LOOP;
divinaasignff <= '0';
divinbbsignff <= '0';
divinaasatff <= '0';
divinbbsatff <= '0';
divinaazipff <= '0';
divinbbzipff <= '0';
divinaananff <= '0';
divinbbnanff <= '0';
FOR k IN 1 TO midlatency LOOP
divinsignff(k) <= '0';
divinsatff(k) <= '0';
divinzipff(k) <= '0';
divinnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divinaaexpff <= divinaaexp;
divinbbexpff <= divinbbexp;
divinexpff(1)(13 DOWNTO 1) <= divinaaexpff - divinbbexpff;
divinexpff(2)(13 DOWNTO 1) <= divinexpff(1)(13 DOWNTO 1) + "0001111111111";
FOR k IN 3 TO midlatency LOOP
divinexpff(k)(13 DOWNTO 1) <= divinexpff(k-1)(13 DOWNTO 1);
END LOOP;
divinaasignff <= divinaasign;
divinbbsignff <= divinbbsign;
divinsignff(1) <= divinaasignff XOR divinbbsignff;
FOR k IN 2 TO midlatency LOOP
divinsignff(k) <= divinsignff(k-1);
END LOOP;
divinaasatff <= divinaasat;
divinbbsatff <= divinbbsat;
divinaazipff <= divinaazip;
divinbbzipff <= divinbbzip;
divinaananff <= divinaanan;
divinbbnanff <= divinbbnan;
-- special condition: infinity = x/0
divinsatff(1) <= (divinaasatff OR divinbbsatff) OR
(NOT(divinaazipff) AND divinbbzipff);
divinzipff(1) <= divinaazipff;
-- 0/0 or infinity/infinity is invalid OP, NAN out
divinnanff(1) <= divinaananff OR divinbbnanff OR
(divinaazipff AND divinbbzipff) OR
(divinaasatff AND divinbbsatff);
FOR k IN 2 TO midlatency LOOP
divinsatff(k) <= divinsatff(k-1);
divinzipff(k) <= divinzipff(k-1);
divinnanff(k) <= divinnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goya: IF (xoutput = 1) GENERATE
-- output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
-- if <1, SSSSSS1'manSSSSS
-- if >1, SSSSS1'manSSSS
goyb: FOR k IN 1 TO 4 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goyc: FOR k IN 1 TO 55 GENERATE
signeddivmannode(k+4) <= divmannode(k) XOR divinsignff(midlatency);
END GENERATE;
goyd: FOR k IN 60 TO 64 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goye: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goyf: IF (roundconvert = 0) GENERATE
divroundnode <= signeddivmannode;
END GENERATE;
goyg: IF (roundconvert = 1) GENERATE
divroundnode <= signeddivmannode + (zerovec(63 DOWNTO 1) & divinsignff(midlatency));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
divymanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divyexpff(j) <= '0';
END LOOP;
divysatbitff <= '0';
divyzipbitff <= '0';
divynanbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divymanff <= divroundnode;
divyexpff <= divinexpff(midlatency)(13 DOWNTO 1);
divysatbitff <= divinsatff(midlatency);
divyzipbitff <= divinzipff(midlatency);
divynanbitff <= divinnanff(midlatency);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divymanff;
cc(13 DOWNTO 1) <= divyexpff;
ccsat <= divysatbitff;
cczip <= divyzipbitff;
ccnan <= divynanbitff;
END GENERATE;
goyh: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
goyi: IF (synthesize = 0) GENERATE
rndaddone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
goyj: IF (synthesize = 1) GENERATE
rndaddtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO 13 LOOP
divyexpdelff(1)(j) <= '0';
divyexpdelff(2)(j) <= '0';
END LOOP;
divysatdelff <= "00";
divyzipdelff <= "00";
divynandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divyexpdelff(1)(13 DOWNTO 1) <= divinexpff(midlatency)(13 DOWNTO 1);
divyexpdelff(2)(13 DOWNTO 1) <= divyexpdelff(1)(13 DOWNTO 1);
divysatdelff(1) <= divinsatff(midlatency);
divysatdelff(2) <= divysatdelff(1);
divyzipdelff(1) <= divinzipff(midlatency);
divyzipdelff(2) <= divyzipdelff(1);
divynandelff(1) <= divinnanff(midlatency);
divynandelff(2) <= divynandelff(1);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divmanout;
cc(13 DOWNTO 1) <= divyexpdelff(2)(13 DOWNTO 1);
ccsat <= divysatdelff(2);
cczip <= divyzipdelff(2);
ccnan <= divynandelff(2);
END GENERATE;
END GENERATE;
--**************************************************
--*** if output to another multiplier or divider ***
--*** use output directly ***
--**************************************************
--*** NOTE: roundconvert options must still be added
gofa: IF (divoutput = 1) GENERATE
-- [55:1] output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
normalize <= NOT(divmannode(55));
gofb: FOR k IN 1 TO 53 GENERATE
normmannode(k) <= (divmannode(k+1) AND normalize) OR
(divmannode(k+2) AND NOT(normalize));
END GENERATE;
-- exp[54:1] always '1'manR
poda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
divdivmanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divdivexpff(j) <= '0';
END LOOP;
divdivsatff <= '0';
divdivzipff <= '0';
divdivnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
divdivmanff <= divinsignff(midlatency) & normmannode;
-- 20/05/09 add normalize adjustement
divdivexpff <= divinexpff(midlatency)(13 DOWNTO 1) - (zerovec(12 DOWNTO 1) & normalize);
divdivsatff <= divinsatff(midlatency);
divdivzipff <= divinzipff(midlatency);
divdivnanff <= divinnanff(midlatency);
END IF;
END PROCESS;
cc(67 DOWNTO 14) <= divdivmanff;
cc(13 DOWNTO 1) <= divdivexpff;
ccsat <= divdivsatff;
cczip <= divdivzipff;
ccnan <= divdivnanff;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "01XXXX..RR" (<2) or "1XXXX..RR" (>=2), need to make output
-- 01XXXX
normalize <= NOT(divmannode(55));
goeb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]R
normalnode(k) <= (divmannode(k+1) AND NOT(normalize)) OR
(divmannode(k) AND normalize);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
normsignff <= '0';
normsatff <= '0';
normzipff <= '0';
normnanff <= '0';
FOR k IN 1 TO 54 LOOP
normalff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
normalexpff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normsignff <= divinsignff(midlatency);
normsatff <= divinsatff(midlatency);
normzipff <= divinzipff(midlatency);
normnanff <= divinnanff(midlatency);
normalff <= normalnode;
normalexpff <= divinexpff(midlatency)(13 DOWNTO 1) -
(zerovec(12 DOWNTO 1) & normalize);
END IF;
END IF;
END PROCESS;
goec: IF (roundconvert = 0) GENERATE
norndout: hcc_divnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goed: IF ((roundconvert = 1) AND (doublespeed = 0)) GENERATE
rndout: hcc_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goee: IF ((roundconvert = 1) AND (doublespeed = 1)) GENERATE
rndpipout: hcc_divrndpipe
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
END GENERATE;
END rtl;
| mit |
Reiuiji/ECE368-Lab | Lab 3/VGA Part 2/clk25MHz.vhd | 11 | 2102 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 25Mhz clock for a vga controller
-- 50 Mhz to 25 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_25MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_25MHZ;
architecture Behavioral of CLK_25MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : Boolean := TRUE;
STARTUP_WAIT : boolean := FALSE);
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_pos51.vhd | 10 | 6864 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_POS51.VHD ***
--*** ***
--*** Function: 5 Bit Count Leading Zeros ***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_pos51 IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_pos51;
ARCHITECTURE sss of fp_pos51 IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,5);
WHEN "000001" => position <= conv_std_logic_vector(start+5,5);
WHEN "000010" => position <= conv_std_logic_vector(start+4,5);
WHEN "000011" => position <= conv_std_logic_vector(start+4,5);
WHEN "000100" => position <= conv_std_logic_vector(start+3,5);
WHEN "000101" => position <= conv_std_logic_vector(start+3,5);
WHEN "000110" => position <= conv_std_logic_vector(start+3,5);
WHEN "000111" => position <= conv_std_logic_vector(start+3,5);
WHEN "001000" => position <= conv_std_logic_vector(start+2,5);
WHEN "001001" => position <= conv_std_logic_vector(start+2,5);
WHEN "001010" => position <= conv_std_logic_vector(start+2,5);
WHEN "001011" => position <= conv_std_logic_vector(start+2,5);
WHEN "001100" => position <= conv_std_logic_vector(start+2,5);
WHEN "001101" => position <= conv_std_logic_vector(start+2,5);
WHEN "001110" => position <= conv_std_logic_vector(start+2,5);
WHEN "001111" => position <= conv_std_logic_vector(start+2,5);
WHEN "010000" => position <= conv_std_logic_vector(start+1,5);
WHEN "010001" => position <= conv_std_logic_vector(start+1,5);
WHEN "010010" => position <= conv_std_logic_vector(start+1,5);
WHEN "010011" => position <= conv_std_logic_vector(start+1,5);
WHEN "010100" => position <= conv_std_logic_vector(start+1,5);
WHEN "010101" => position <= conv_std_logic_vector(start+1,5);
WHEN "010110" => position <= conv_std_logic_vector(start+1,5);
WHEN "010111" => position <= conv_std_logic_vector(start+1,5);
WHEN "011000" => position <= conv_std_logic_vector(start+1,5);
WHEN "011001" => position <= conv_std_logic_vector(start+1,5);
WHEN "011010" => position <= conv_std_logic_vector(start+1,5);
WHEN "011011" => position <= conv_std_logic_vector(start+1,5);
WHEN "011100" => position <= conv_std_logic_vector(start+1,5);
WHEN "011101" => position <= conv_std_logic_vector(start+1,5);
WHEN "011110" => position <= conv_std_logic_vector(start+1,5);
WHEN "011111" => position <= conv_std_logic_vector(start+1,5);
WHEN "100000" => position <= conv_std_logic_vector(start,5);
WHEN "100001" => position <= conv_std_logic_vector(start,5);
WHEN "100010" => position <= conv_std_logic_vector(start,5);
WHEN "100011" => position <= conv_std_logic_vector(start,5);
WHEN "100100" => position <= conv_std_logic_vector(start,5);
WHEN "100101" => position <= conv_std_logic_vector(start,5);
WHEN "100110" => position <= conv_std_logic_vector(start,5);
WHEN "100111" => position <= conv_std_logic_vector(start,5);
WHEN "101000" => position <= conv_std_logic_vector(start,5);
WHEN "101001" => position <= conv_std_logic_vector(start,5);
WHEN "101010" => position <= conv_std_logic_vector(start,5);
WHEN "101011" => position <= conv_std_logic_vector(start,5);
WHEN "101100" => position <= conv_std_logic_vector(start,5);
WHEN "101101" => position <= conv_std_logic_vector(start,5);
WHEN "101110" => position <= conv_std_logic_vector(start,5);
WHEN "101111" => position <= conv_std_logic_vector(start,5);
WHEN "110000" => position <= conv_std_logic_vector(start,5);
WHEN "110001" => position <= conv_std_logic_vector(start,5);
WHEN "110010" => position <= conv_std_logic_vector(start,5);
WHEN "110011" => position <= conv_std_logic_vector(start,5);
WHEN "110100" => position <= conv_std_logic_vector(start,5);
WHEN "110101" => position <= conv_std_logic_vector(start,5);
WHEN "110110" => position <= conv_std_logic_vector(start,5);
WHEN "110111" => position <= conv_std_logic_vector(start,5);
WHEN "111000" => position <= conv_std_logic_vector(start,5);
WHEN "111001" => position <= conv_std_logic_vector(start,5);
WHEN "111010" => position <= conv_std_logic_vector(start,5);
WHEN "111011" => position <= conv_std_logic_vector(start,5);
WHEN "111100" => position <= conv_std_logic_vector(start,5);
WHEN "111101" => position <= conv_std_logic_vector(start,5);
WHEN "111110" => position <= conv_std_logic_vector(start,5);
WHEN "111111" => position <= conv_std_logic_vector(start,5);
WHEN others => position <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END sss;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/fp_del_var.vhd | 10 | 3103 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fp_invsqr_core.vhd | 10 | 8541 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** FP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 36 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_core IS
GENERIC (
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_core;
ARCHITECTURE rtl OF fp_invsqr_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(36 DOWNTO 18),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 12 LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 12 LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>36,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone,databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
invroot <= multonethr(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fpc_library_sv.vhd | 10 | 100780 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package.all;
USE work.math_package.all;
USE work.fpc_library_package.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
ou-cse-378/vhdl-tetris | ctr2bit.vhd | 1 | 860 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: ctr2bit.vhd
-- // Date: 12/9/2004
-- // Description: Display component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ctr2bit is
port (
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (1 downto 0)
);
end ctr2bit;
architecture ctr2bit_arch of ctr2bit is
begin
process (clk, clr)
variable COUNT: STD_LOGIC_VECTOR (1 downto 0);
begin
if clr = '1' then
COUNT := "00";
elsif clk'event and clk='1' then
COUNT := COUNT + 1;
end if;
q <= COUNT;
end process;
end ctr2bit_arch;
| mit |
danielcardoso/html-pages | example/All-Icons/file.vhdl | 12226531 | 0 | mit |
|
rflamino/StellaBlue | core/A6532/src/A6532.vhd | 1 | 7554 | -- A6532 RAM-I/O-Timer (RIOT)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end ram128x8;
architecture arch of ram128x8 is
type ram_type is array (0 to 127) of
std_logic_vector(7 downto 0);
signal ram: ram_type;
begin
process (clk, r, a)
begin
if (clk'event and clk = '1') then
if (r = '1') then
d_out <= ram(to_integer(unsigned(a)));
else
ram(to_integer(unsigned(a))) <= d_in;
end if;
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity A6532 is
port(clk: in std_logic;
r: in std_logic;
rs: in std_logic;
cs: in std_logic;
irq: out std_logic;
d: inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
pa7: in std_logic;
a: in std_logic_vector(6 downto 0));
end A6532;
architecture arch of A6532 is
component ram128x8 is
port(clk: in std_logic;
r: in std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(7 downto 0);
a: in std_logic_vector(6 downto 0));
end component;
signal pa_reg: std_logic_vector(7 downto 0) := "00000000";
signal pb_reg: std_logic_vector(7 downto 0) := "00000000";
signal pa_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pb_ddr: std_logic_vector(7 downto 0) := "00000000";
signal pa_in: std_logic_vector(7 downto 0);
signal pb_in: std_logic_vector(7 downto 0);
signal timer: std_logic_vector(7 downto 0) := "00000000";
signal timer_write: std_logic;
signal timer_read: std_logic;
signal timer_intr: std_logic := '0';
signal timer_intvl: std_logic_vector(1 downto 0) := "11";
signal timer_dvdr: std_logic_vector(10 downto 0) := "00000000001";
signal timer_inc: std_logic;
signal timer_irq_en: std_logic := '0';
signal edge_pol: std_logic := '0';
signal edge_irq_en: std_logic := '0';
signal edge_intr_lo: std_logic := '0';
signal edge_intr_hi: std_logic := '0';
signal edge_intr: std_logic;
signal intr_read: std_logic;
signal ram_d_out: std_logic_vector(7 downto 0);
signal ram_r: std_logic;
signal clk2: std_logic;
begin
-- This clock is phase shifted so that we can use Xilinx synchronous block RAM.
clk2 <= not clk;
io: for i in 0 to 7 generate
-- TEMPORARY FIX
--pa(i) <= pa_reg(i) when pa_ddr(i) = '1' else 'Z';
--pb(i) <= pb_reg(i) when pb_ddr(i) = '1' else 'Z';
pa(i) <= 'Z';
pb(i) <= 'Z';
pa_in(i) <= pa(i);
pb_in(i) <= pb(i) when pb_ddr(i) = '0' else pb_reg(i);
end generate;
ram: ram128x8 port map(clk2, ram_r, d, ram_d_out, a);
ram_r <= (not rs and r) or rs or not cs;
timer_write <= (not r) and rs and a(2) and a(4) and cs;
timer_read <= r and rs and a(2) and (not a(0)) and cs;
intr_read <= r and rs and a(0) and a(2) and cs;
irq <= not ((timer_intr and timer_irq_en) or (edge_intr and edge_irq_en));
edge_intr <= edge_intr_lo when edge_pol = '0' else edge_intr_hi;
process(clk, cs, r, rs, a, ram_d_out, pa_in, pa_ddr, pb_in, pb_ddr, timer, timer_intr, edge_intr)
begin
if r = '1' then
if (cs = '0') then
d <= "ZZZZZZZZ";
elsif rs = '0' then
d <= ram_d_out;
elsif a(2) = '0' then
case a(1 downto 0) is
when "00" =>
d <= pa_in;
when "01" =>
d <= pa_ddr;
when "10" =>
d <= pb_in;
when "11" =>
d <= pb_ddr;
when others =>
null;
end case;
elsif a(0) = '0' then
d <= timer;
elsif a(0) = '1' then
d <= timer_intr & edge_intr & "000000";
else
d <= "--------";
end if;
else
d <= "ZZZZZZZZ";
if (clk'event and clk = '1' and cs = '1') then
if (rs = '1') then
if a(2) = '0' then
case a(1 downto 0) is
when "00" =>
pa_reg <= d;
when "01" =>
pa_ddr <= d;
when "10" =>
pb_reg <= d;
when "11" =>
pb_ddr <= d;
when others =>
null;
end case;
elsif a(4) = '0' then
edge_pol <= a(0);
edge_irq_en <= a(1);
end if;
end if;
end if;
end if;
end process;
process(pa7, intr_read)
begin
if (intr_read = '1') then
edge_intr_lo <= '0';
elsif (pa7'event and pa7 = '1') then
edge_intr_lo <= '1';
end if;
if (intr_read = '1') then
edge_intr_hi <= '0';
elsif (pa7'event and pa7 = '0') then
edge_intr_hi <= '1';
end if;
end process;
with timer_intvl select timer_inc <=
timer_dvdr(0) when "00",
timer_dvdr(3) when "01",
timer_dvdr(6) when "10",
timer_dvdr(10) when "11",
'-' when others;
process(clk)
begin
if (clk'event and clk = '1') then
if (timer_inc = '1') then
timer_dvdr <= "00000000001";
else
timer_dvdr <= timer_dvdr + 1;
end if;
if (timer_write = '1') then
timer <= d;
timer_intvl <= a(1 downto 0);
timer_irq_en <= a(3);
timer_dvdr <= "00000000001";
elsif (timer_intr = '0') then
timer <= timer - timer_inc;
elsif (not (timer = X"00")) then
timer <= timer - 1;
end if;
if (timer = X"00" and timer_inc = '1' and timer_intr = '0' and timer_write = '0') then
timer_intr <= '1';
elsif (timer_read = '1' or timer_write = '1') then
timer_intr <= '0';
end if;
end if;
end process;
end arch;
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/single_rate.vhd | 2 | 370178 | `protect begin_protected
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`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/cntrl_delay.vhd | 2 | 9440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect data_block
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`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/components.vhd | 2 | 77934 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952)
`protect data_block
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`protect end_protected
| mit |
okaxaki/vm2413 | AttackTable.vhd | 2 | 2045 | --
-- AttackTable.vhd
-- Envelope attack shaping table for VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity AttackTable is
port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end AttackTable;
architecture RTL of AttackTable is
type AR_ADJUST_ARRAY is array (addr'range) of DB_TYPE;
constant ar_adjust : AR_ADJUST_ARRAY :=(
"1111111","1111111","1101100","1100010","1011010","1010100","1010000","1001011",
"1001000","1000101","1000010","1000000","0111101","0111011","0111001","0111000",
"0110110","0110100","0110011","0110001","0110000","0101111","0101101","0101100",
"0101011","0101010","0101001","0101000","0100111","0100110","0100101","0100100",
"0100100","0100011","0100010","0100001","0100001","0100000","0011111","0011110",
"0011110","0011101","0011101","0011100","0011011","0011011","0011010","0011010",
"0011001","0011000","0011000","0010111","0010111","0010110","0010110","0010101",
"0010101","0010101","0010100","0010100","0010011","0010011","0010010","0010010",
"0010001","0010001","0010001","0010000","0010000","0001111","0001111","0001111",
"0001110","0001110","0001110","0001101","0001101","0001101","0001100","0001100",
"0001100","0001011","0001011","0001011","0001010","0001010","0001010","0001001",
"0001001","0001001","0001001","0001000","0001000","0001000","0000111","0000111",
"0000111","0000111","0000110","0000110","0000110","0000110","0000101","0000101",
"0000101","0000100","0000100","0000100","0000100","0000100","0000011","0000011",
"0000011","0000011","0000010","0000010","0000010","0000010","0000001","0000001",
"0000001","0000001","0000001","0000000","0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= ar_adjust(addr'high - addr);
end if;
end process;
end RTL; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulsen1Altr.vhd | 8 | 3102 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsen1Altr is
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsen1Altr ;
architecture syn of alt_dspbuilder_sImpulsen1Altr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_clock.vhd | 10 | 2158 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
begin
alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "20 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/Instruct_Memory/simulation/checker.vhd | 69 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd | 20 | 1755 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_pipelined_adder_GNWEIMU3MK.vhd | 8 | 1300 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
signal cin_internal : std_logic;
Begin
cin_internal <= '1';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '0' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCCZ56SYK.vhd | 4 | 855 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; | mit |
Bourgeoisie/ECE368-RISC16 | 368RISC/Data Path/Fetch/fetch_tb.vhd | 1 | 2984 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:39:38 04/22/2015
-- Design Name:
-- Module Name: U:/Desktop/ECE368-RISC16-master/368RISC/fetch_tb.vhd
-- Project Name: RISC16
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fetch_struct
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fetch_tb IS
END fetch_tb;
ARCHITECTURE behavior OF fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch_struct
PORT(
clk : IN std_logic;
rst : IN std_logic;
PC_En : IN std_logic;
pc_out : OUT std_logic_vector(4 downto 0);
OPcode_out: OUT std_logic_vector(3 downto 0);
ADRS_A : OUT std_logic_vector(3 downto 0);
ADRS_B : OUT std_logic_vector(3 downto 0);
ADRS_IMM : OUT std_logic_vector(3 downto 0);
Instruction_out : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal PC_En : std_logic := '0';
--Outputs
signal pc_out : std_logic_vector(4 downto 0);
signal OPcode_out: std_logic_vector(3 downto 0);
signal ADRS_A : std_logic_vector(3 downto 0);
signal ADRS_B : std_logic_vector(3 downto 0);
signal ADRS_IMM : std_logic_vector(3 downto 0);
signal Instruction_out : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fetch_struct PORT MAP (
clk => clk,
rst => rst,
PC_En => PC_En,
pc_out => pc_out,
OPcode_out => OPcOdE_oUt,
ADRS_A => ADRS_A,
ADRS_B => ADRS_B,
ADRS_IMM => ADRS_IMM,
Instruction_out => Instruction_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
PC_En <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_decoder.vhd | 2 | 2462 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNEQGKKPXW_0: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_0: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_1: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_1: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_dividerAltr.vhd | 4 | 4072 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_if_statement_GNJ7D74ANQ.vhd | 4 | 1401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_MultAdd.vhd | 12 | 23128 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000011";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNLJWFEWBD is
Begin
-- Constant
output <= "0000000000000011";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNLJWFEWBD.vhd | 5 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNLJWFEWBD is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000011";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNLJWFEWBD is
Begin
-- Constant
output <= "0000000000000011";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd | 2 | 45577 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- sop.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNCPEUNC4M.vhd | 5 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCPEUNC4M is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCPEUNC4M is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_sImpulse1nAltr.vhd | 8 | 2837 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse1nAltr is
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse1nAltr ;
architecture syn of alt_dspbuilder_sImpulse1nAltr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
count <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
count <= (others=>'0');
elsif (ena='1') then
current_state <= next_state;
count <= count+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end process;
cp:process(count,current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsewidth,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000001111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNZEH3JAKA is
Begin
-- Constant
output <= "000000000000000000001111";
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_vcc_GN.vhd | 20 | 373 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_vcc_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_vcc_GN is
Begin
output <= '1';
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_port_GNEPKLLZKY.vhd | 17 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_if_statement_GNWHMBR6GA.vhd | 4 | 1493 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNWHMBR6GA is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>zero) and (a<b)) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNWHMBR6GA is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>zero) and (a<b)) or (a=c)) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_cast_GNMMXHT3UH.vhd | 4 | 852 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMMXHT3UH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMMXHT3UH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(3 downto 0) => input,
yout => output
);
end architecture; | mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd | 2 | 34606 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic := '0'; -- data_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0') -- counter.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
| mit |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator.vhd | 2 | 2091 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test_Pattern_Generator is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Test_Pattern_Generator;
architecture rtl of Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Test_Pattern_Generator_GN;
begin
Test_Pattern_Generator_GN_0: if true generate
inst_Test_Pattern_Generator_GN_0: Test_Pattern_Generator_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_case_statement_GNWMX2GCN2.vhd | 4 | 837 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic ( number_outputs : integer := 2;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 16);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(15 downto 0);
r0 : out std_logic;
r1 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GNWMX2GCN2 is
begin
caseproc:process( input )
begin
case input is
when "0000000000000100" =>
r0 <= '1';
r1 <= '0';
when others =>
r0 <= '0';
r1 <= '1';
end case;
end process;
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_counter_GNKAA2ZBZG.vhd | 4 | 1632 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNKAA2ZBZG is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := 8388608;
use_cnt_ena : string := "true";
width : natural := 24;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNKAA2ZBZG is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 24,
LPM_DIRECTION => "UP",
LPM_MODULUS => 8388608,
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
| mit |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_decoder.vhd | 2 | 1567 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(2-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNM4LOIHXZ_0: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_0: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |