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chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/papilio_stepper.vhd | 13 | 7399 | --**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget Factory (www.gadgetfactory.net)
-- This work is licensed under the Creative Commons Attribution 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
-- use work.zpuino_config.all;
-- use work.zpu_config.all;
-- use work.zpupkg.all;
entity papilio_stepper is
Generic (
timebase_g : std_logic_vector(15 downto 0) := (others => '0');
period_g : std_logic_vector(15 downto 0) := (others => '0')
);
port (
wb_clk_i: in std_logic; -- Wishbone clock
wb_rst_i: in std_logic; -- Wishbone reset (synchronous)
wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: in std_logic; -- Wishbone write enable signal
wb_cyc_i: in std_logic; -- Wishbone cycle signal
wb_stb_i: in std_logic; -- Wishbone strobe signal
wb_ack_o: out std_logic; -- Wishbone acknowledge out signal
-- External connections
st_home : in std_logic;
st_dir : out std_logic;
st_ms2 : out std_logic;
st_ms1 : out std_logic;
st_rst : out std_logic;
st_step : out std_logic;
st_enable : out std_logic;
st_sleep : out std_logic;
-- IRQ
st_irq : out std_logic
);
end entity papilio_stepper;
architecture rtl of papilio_stepper is
signal prescale_o : std_logic;
signal halfperiod_o : std_logic;
signal step_o : std_logic;
signal irq_o : std_logic;
signal Control_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Timebase_reg : std_logic_vector(15 downto 0) := timebase_g;
signal Period_reg : std_logic_vector(15 downto 0) := period_g;
signal StepCnt_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Steps_reg : std_logic_vector(15 downto 0) := (others => '0');
signal PrescaleCnt : std_logic_vector(15 downto 0);
signal HalfPeriodCnt : std_logic_vector(15 downto 0);
signal ack_i: std_logic; -- Internal ACK signal (flip flop)
begin
-- This example uses fully synchronous outputs.
-- General Output signals
st_dir <= Control_reg(3);
st_ms2 <= Control_reg(1);
st_ms1 <= Control_reg(0);
st_rst <= Control_reg(4);
st_step <= step_o;
st_sleep <= Control_reg(7);
st_enable <= not Control_reg(8);
st_irq <= irq_o;
wb_ack_o <= ack_i; -- Tie ACK output to our flip flop
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
-- Always set output data on rising edge, even if reset is set.
Control_reg(14) <= st_home;
Control_reg(15) <= irq_o;
wb_dat_o <= (others => 'X'); -- Return undefined by omission
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(Control_reg'RANGE) <= Control_reg;
when "001" =>
wb_dat_o(Timebase_reg'RANGE) <= Timebase_reg;
when "010" =>
wb_dat_o(Period_reg'RANGE) <= Period_reg;
when "011" =>
wb_dat_o(StepCnt_reg'RANGE) <= StepCnt_reg;
when "100" =>
wb_dat_o(Steps_reg'RANGE) <= Steps_reg;
when others =>
end case;
ack_i <= '0'; -- Reset ACK value by default
if wb_rst_i='1' then
Control_reg <= "0000000010010000";
Timebase_reg <= timebase_g;
Period_reg <= period_g;
StepCnt_reg <= (others => '0');
else -- Not reset
-- See if we did not acknowledged a cycle, otherwise we need to ignore
-- the apparent request, because wishbone signals are still set
if ack_i='0' then
-- Check if someone is accessing
if wb_cyc_i='1' and wb_stb_i='1' then
ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above.
if wb_we_i='1' then
-- It's a write. See for which register based on address
case wb_adr_i(4 downto 2) is
when "000" =>
Control_reg(8 downto 0) <= wb_dat_i(8 downto 0); -- Set register
when "001" =>
Timebase_reg <= wb_dat_i(Timebase_reg'RANGE);
when "010" =>
Period_reg <= wb_dat_i(Period_reg'RANGE);
when "011" =>
StepCnt_reg <= wb_dat_i(StepCnt_reg'RANGE);
when others =>
null; -- Nothing to do for other addresses
end case;
end if; -- if wb_we_i='1'
end if; -- if wb_cyc_i='1' and wb_stb_i='1'
end if; -- if ack_i='0'
end if; -- if wb_rst_i='1'
end if; -- if rising_edge(wb_clk_i)
end process;
-- Prescaler
Prescaler:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if(wb_rst_i='1') then
PrescaleCnt <= (others => '0');
else
if (Control_reg(8)='1') then
if (PrescaleCnt=Timebase_reg) then
PrescaleCnt <= "0000000000000001";
else
PrescaleCnt <= PrescaleCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Half period counter
Halfperiod:process(wb_clk_i,prescale_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
HalfPeriodCnt <= (others => '0');
elsif (PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
if (HalfPeriodCnt=('0'&Period_reg(15 downto 1))) then
HalfPeriodCnt <= "0000000000000001";
else
HalfPeriodCnt <= HalfPeriodCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Step output
Step_out:process(wb_clk_i,halfperiod_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
step_o <= '1';
Steps_reg <= (others => '0');
elsif (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
step_o <= not step_o;
if (step_o = '1') then
Steps_reg <= Steps_reg+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Stepper interrupt
Int_out:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
irq_o <= '0';
if (wb_rst_i='1') then
irq_o <= '0';
else
--elsif (wb_clk_i='1' and wb_clk_i'event) then
case (Control_reg(6 downto 5)) is
when "01" =>
--if (halfperiod_o='1') then
if (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
irq_o <= '1';
end if;
when "10" =>
if (Control_reg(14)='1') then
irq_o <= '1';
end if;
when "11" =>
if (Steps_reg = StepCnt_reg) then
irq_o <= '1';
end if;
when others =>
--irq_o <= '0';
end case;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/papilio_stepper.vhd | 13 | 7399 | --**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget Factory (www.gadgetfactory.net)
-- This work is licensed under the Creative Commons Attribution 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
-- use work.zpuino_config.all;
-- use work.zpu_config.all;
-- use work.zpupkg.all;
entity papilio_stepper is
Generic (
timebase_g : std_logic_vector(15 downto 0) := (others => '0');
period_g : std_logic_vector(15 downto 0) := (others => '0')
);
port (
wb_clk_i: in std_logic; -- Wishbone clock
wb_rst_i: in std_logic; -- Wishbone reset (synchronous)
wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
wb_we_i: in std_logic; -- Wishbone write enable signal
wb_cyc_i: in std_logic; -- Wishbone cycle signal
wb_stb_i: in std_logic; -- Wishbone strobe signal
wb_ack_o: out std_logic; -- Wishbone acknowledge out signal
-- External connections
st_home : in std_logic;
st_dir : out std_logic;
st_ms2 : out std_logic;
st_ms1 : out std_logic;
st_rst : out std_logic;
st_step : out std_logic;
st_enable : out std_logic;
st_sleep : out std_logic;
-- IRQ
st_irq : out std_logic
);
end entity papilio_stepper;
architecture rtl of papilio_stepper is
signal prescale_o : std_logic;
signal halfperiod_o : std_logic;
signal step_o : std_logic;
signal irq_o : std_logic;
signal Control_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Timebase_reg : std_logic_vector(15 downto 0) := timebase_g;
signal Period_reg : std_logic_vector(15 downto 0) := period_g;
signal StepCnt_reg : std_logic_vector(15 downto 0) := (others => '0');
signal Steps_reg : std_logic_vector(15 downto 0) := (others => '0');
signal PrescaleCnt : std_logic_vector(15 downto 0);
signal HalfPeriodCnt : std_logic_vector(15 downto 0);
signal ack_i: std_logic; -- Internal ACK signal (flip flop)
begin
-- This example uses fully synchronous outputs.
-- General Output signals
st_dir <= Control_reg(3);
st_ms2 <= Control_reg(1);
st_ms1 <= Control_reg(0);
st_rst <= Control_reg(4);
st_step <= step_o;
st_sleep <= Control_reg(7);
st_enable <= not Control_reg(8);
st_irq <= irq_o;
wb_ack_o <= ack_i; -- Tie ACK output to our flip flop
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
-- Always set output data on rising edge, even if reset is set.
Control_reg(14) <= st_home;
Control_reg(15) <= irq_o;
wb_dat_o <= (others => 'X'); -- Return undefined by omission
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(Control_reg'RANGE) <= Control_reg;
when "001" =>
wb_dat_o(Timebase_reg'RANGE) <= Timebase_reg;
when "010" =>
wb_dat_o(Period_reg'RANGE) <= Period_reg;
when "011" =>
wb_dat_o(StepCnt_reg'RANGE) <= StepCnt_reg;
when "100" =>
wb_dat_o(Steps_reg'RANGE) <= Steps_reg;
when others =>
end case;
ack_i <= '0'; -- Reset ACK value by default
if wb_rst_i='1' then
Control_reg <= "0000000010010000";
Timebase_reg <= timebase_g;
Period_reg <= period_g;
StepCnt_reg <= (others => '0');
else -- Not reset
-- See if we did not acknowledged a cycle, otherwise we need to ignore
-- the apparent request, because wishbone signals are still set
if ack_i='0' then
-- Check if someone is accessing
if wb_cyc_i='1' and wb_stb_i='1' then
ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above.
if wb_we_i='1' then
-- It's a write. See for which register based on address
case wb_adr_i(4 downto 2) is
when "000" =>
Control_reg(8 downto 0) <= wb_dat_i(8 downto 0); -- Set register
when "001" =>
Timebase_reg <= wb_dat_i(Timebase_reg'RANGE);
when "010" =>
Period_reg <= wb_dat_i(Period_reg'RANGE);
when "011" =>
StepCnt_reg <= wb_dat_i(StepCnt_reg'RANGE);
when others =>
null; -- Nothing to do for other addresses
end case;
end if; -- if wb_we_i='1'
end if; -- if wb_cyc_i='1' and wb_stb_i='1'
end if; -- if ack_i='0'
end if; -- if wb_rst_i='1'
end if; -- if rising_edge(wb_clk_i)
end process;
-- Prescaler
Prescaler:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if(wb_rst_i='1') then
PrescaleCnt <= (others => '0');
else
if (Control_reg(8)='1') then
if (PrescaleCnt=Timebase_reg) then
PrescaleCnt <= "0000000000000001";
else
PrescaleCnt <= PrescaleCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Half period counter
Halfperiod:process(wb_clk_i,prescale_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
HalfPeriodCnt <= (others => '0');
elsif (PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
if (HalfPeriodCnt=('0'&Period_reg(15 downto 1))) then
HalfPeriodCnt <= "0000000000000001";
else
HalfPeriodCnt <= HalfPeriodCnt+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Step output
Step_out:process(wb_clk_i,halfperiod_o,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if (wb_rst_i='1') then
step_o <= '1';
Steps_reg <= (others => '0');
elsif (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
if (Control_reg(8)='1') then
step_o <= not step_o;
if (step_o = '1') then
Steps_reg <= Steps_reg+1;
end if;
end if;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
-- Stepper interrupt
Int_out:process(wb_clk_i,wb_rst_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
irq_o <= '0';
if (wb_rst_i='1') then
irq_o <= '0';
else
--elsif (wb_clk_i='1' and wb_clk_i'event) then
case (Control_reg(6 downto 5)) is
when "01" =>
--if (halfperiod_o='1') then
if (HalfPeriodCnt="0000000000000001" and PrescaleCnt="0000000000000001") then
irq_o <= '1';
end if;
when "10" =>
if (Control_reg(14)='1') then
irq_o <= '1';
end if;
when "11" =>
if (Steps_reg = StepCnt_reg) then
irq_o <= '1';
end if;
when others =>
--irq_o <= '0';
end case;
end if;
end if; -- if rising_edge(wb_clk_i)
end process;
end rtl;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Papilio_Default_Wing_Pinout.vhd | 13 | 13006 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/Papilio_Default_Wing_Pinout.vhd | 13 | 13006 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd | 13 | 8035 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_UART is
generic (
bits: integer := 4
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
enabled: out std_logic; --An output that is active high when the UART is not in a reset state
tx: out std_logic; --UART Transmit pin
rx: in std_logic --UART Receive pin
);
end entity COMM_zpuino_wb_UART;
architecture behave of COMM_zpuino_wb_UART is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/rle.vhd | 13 | 7423 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/rle.vhd | 13 | 7423 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rle is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
raw_inp : in std_logic_vector (31 downto 0);
raw_inp_valid : in std_logic;
rle_out : out std_logic_vector (32 downto 0);
rle_out_valid : out std_logic;
rle_inp : in std_logic_vector (32 downto 0);
rle_inp_valid : in std_logic;
fmt_out : out std_logic_vector (31 downto 0);
busy : out std_logic;
rle_ready : out std_logic;
raw_ready : in std_logic;
-- start_count : in std_logic;
-- data_count : out std_logic_vector(15 downto 0);
data_size : in std_logic_vector(1 downto 0)
);
end rle;
architecture behavioral of rle is
component rle_enc
generic(
data_width : integer
);
port(
clock : in std_logic;
raw_inp : in std_logic_vector ((data_width-1) downto 0);
rle_out : out std_logic_vector ((data_width-1) downto 0);
raw_inp_valid : in std_logic;
rle_out_valid : out std_logic;
rle_bit : out std_logic
);
end component;
component rle_fmt
generic(
data_width : integer
);
port(
clock : in std_logic;
reset : in std_logic;
rle_inp : in std_logic_vector (data_width downto 0);
fmt_out : out std_logic_vector ((data_width-1) downto 0);
rle_inp_valid : in std_logic;
busy : out std_logic;
raw_ready : in std_logic;
rle_ready : out std_logic
);
end component;
signal rle_tmp, valid_out : std_logic;
begin
rle_out_valid <= valid_out;
format_block: block
signal fmt_out_8 : std_logic_vector (7 downto 0);
signal fmt_out_16 : std_logic_vector (15 downto 0);
signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0);
signal rle_inp_8 : std_logic_vector (8 downto 0);
signal rle_inp_16 : std_logic_vector (16 downto 0);
signal busy_i, busy_8, busy_16, busy_32 : std_logic;
signal delayed_ready : std_logic;
signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic;
begin
rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0);
rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0);
busy_i <=
'0' when enable = '0' else
busy_8 when data_size = "01" else
busy_16 when data_size = "10" else
busy_32 when data_size = "00" else
'X';
rle_ready_i <=
delayed_ready when enable = '0' else
rle_ready_8 when data_size = "01" else
rle_ready_16 when data_size = "10" else
rle_ready_32 when data_size = "00" else
'X';
fmt_out_i <=
rle_inp(31 downto 0) when enable = '0' else
x"000000" & fmt_out_8 when data_size = "01" else
x"0000" & fmt_out_16 when data_size = "10" else
fmt_out_32 when data_size = "00" else
(others => 'X');
-- register outputs
process(clock)
begin
if rising_edge(clock) then
fmt_out <= fmt_out_i;
busy <= busy_i;
rle_ready <= rle_ready_i;
delayed_ready <= raw_ready;
end if;
end process;
Inst_rle_fmt_8: rle_fmt
generic map(
data_width => 8
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_8,
fmt_out => fmt_out_8,
rle_inp_valid => rle_inp_valid,
busy => busy_8,
raw_ready => raw_ready,
rle_ready => rle_ready_8
);
Inst_rle_fmt_16: rle_fmt
generic map(
data_width => 16
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp_16,
fmt_out => fmt_out_16,
rle_inp_valid => rle_inp_valid,
busy => busy_16,
raw_ready => raw_ready,
rle_ready => rle_ready_16
);
Inst_rle_fmt_32: rle_fmt
generic map(
data_width => 32
)
port map (
clock => clock,
reset => reset,
rle_inp => rle_inp,
fmt_out => fmt_out_32,
rle_inp_valid => rle_inp_valid,
busy => busy_32,
raw_ready => raw_ready,
rle_ready => rle_ready_32
);
end block;
encoder_block: block
signal out_8 : std_logic_vector (7 downto 0);
signal out_16 : std_logic_vector (15 downto 0);
signal out_32 : std_logic_vector (31 downto 0);
signal val_out_8, val_out_16, val_out_32,
rle_bit_8, rle_bit_16, rle_bit_32 : std_logic;
begin
rle_tmp <=
rle_bit_8 when data_size = "01" else
rle_bit_16 when data_size = "10" else
rle_bit_32 when data_size = "00" else
'X';
valid_out <=
raw_inp_valid when enable = '0' else
val_out_8 when data_size = "01" else
val_out_16 when data_size = "10" else
val_out_32 when data_size = "00" else
'X';
rle_out <=
'0' & raw_inp when enable = '0' else
rle_tmp & x"000000" & out_8 when data_size = "01" else
rle_tmp & x"0000" & out_16 when data_size = "10" else
rle_tmp & out_32 when data_size = "00" else
(others => 'X');
Inst_rle_enc_8: rle_enc
generic map(
data_width => 8
)
port map (
clock => clock,
raw_inp => raw_inp(7 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_8,
rle_out_valid => val_out_8,
rle_bit => rle_bit_8
);
Inst_rle_enc_16: rle_enc
generic map(
data_width => 16
)
port map (
clock => clock,
raw_inp => raw_inp(15 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_16,
rle_out_valid => val_out_16,
rle_bit => rle_bit_16
);
Inst_rle_enc_32: rle_enc
generic map(
data_width => 32
)
port map (
clock => clock,
raw_inp => raw_inp(31 downto 0),
raw_inp_valid => raw_inp_valid,
rle_out => out_32,
rle_out_valid => val_out_32,
rle_bit => rle_bit_32
);
end block;
-- data counter
-- counter_block: block
-- type state_type is (S0, S1);
-- signal cs, ns : state_type;
-- signal dcnt, dcntreg : std_logic_vector (15 downto 0);
-- begin
-- -- synchronous
-- process(clock, reset)
-- begin
-- if rising_edge(clock) then
-- if reset = '1' then
-- cs <= S0;
-- else
-- cs <= ns;
-- end if;
-- dcntreg <= dcnt;
-- end if;
-- end process;
--
-- -- combinatorial
-- process(cs, dcntreg, rle_tmp, valid_out, start_count)
-- begin
-- case cs is
-- when S0 =>
-- if start_count = '1' then
-- ns <= S1;
-- else
-- ns <= cs;
-- end if;
-- dcnt <= (others => '0');
-- when S1 =>
-- -- counts the current data transitions
-- if valid_out = '1' and rle_tmp = '0' then
-- dcnt <= dcntreg + 1;
-- else
-- dcnt <= dcntreg;
-- end if;
-- ns <= cs;
-- end case;
-- end process;
--
-- data_count <= dcnt;
--
-- end block;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd | 13 | 19476 | --
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 002 return 00 on allpot when fast scan completed to fix self test
-- version 001 initial release (this version should be considered Beta
-- it seems to make all the right sort of sounds however ... )
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_pokey is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
data_out: out std_logic_vector(7 downto 0) --Digital data out - this should be fed into an audio mixer or Delta-Sigma DAC.
);
end;
architecture RTL of AUDIO_zpuino_wb_pokey is
type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array_4x8 is array (1 to 4) of std_logic_vector(7 downto 0);
type array_4x4 is array (1 to 4) of std_logic_vector(3 downto 0);
type array_4x9 is array (1 to 4) of std_logic_vector(8 downto 0);
type array_2x17 is array (1 to 2) of std_logic_vector(16 downto 0);
type bool_4 is array (1 to 4) of boolean;
--signal oe : std_logic;
--
signal ena : std_logic;
signal ena_64k_15k : std_logic;
signal cnt_64k : std_logic_vector(4 downto 0) := (others => '0');
signal ena_64k : std_logic;
signal cnt_15k : std_logic_vector(6 downto 0) := (others => '0');
signal ena_15k : std_logic;
--
signal poly4 : std_logic_vector(3 downto 0) := (others => '0');
signal poly5 : std_logic_vector(4 downto 0) := (others => '0');
signal poly9 : std_logic_vector(8 downto 0) := (others => '0');
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
signal poly_17_9 : std_logic;
-- registers wb_dat_i
signal audf : array_4x8 := (x"00",x"00",x"00",x"00");
signal audc : array_4x8 := (x"00",x"00",x"00",x"00");
signal audctl : std_logic_vector(7 downto 0) := "00000000";
signal stimer : std_logic_vector(7 downto 0);
signal skres : std_logic_vector(7 downto 0);
signal potgo : std_logic;
signal serout : std_logic_vector(7 downto 0);
signal irqen : std_logic_vector(7 downto 0);
signal skctls : std_logic_vector(7 downto 0);
--signal reset : std_logic;
--
-- registers wb_dat_o
--signal kbcode : std_logic_vector(7 downto 0);
signal random : std_logic_vector(7 downto 0);
--signal serin : std_logic_vector(7 downto 0);
--signal irqst : std_logic_vector(7 downto 0);
--signal skstat : std_logic_vector(7 downto 0);
--
--
--signal pot_fin : std_logic;
--signal pot_cnt : std_logic_vector(7 downto 0);
--signal pot_val : array_8x8;
--signal pin_reg : std_logic_vector(7 downto 0);
--signal pin_reg_gated : std_logic_vector(7 downto 0);
--
signal chan_ena : std_logic_vector(4 downto 1);
signal tone_gen_div : std_logic_vector(4 downto 1);
signal tone_gen_cnt : array_4x8 := (others => (others => '0'));
signal tone_gen_div_mux : std_logic_vector(4 downto 1);
signal tone_gen_zero : std_logic_vector(4 downto 1);
signal tone_gen_zero_t : array_4x8 := (others => (others => '0'));
signal chan_done_load : std_logic_vector(4 downto 1) := (others => '0');
--
signal poly_sel : std_logic_vector(4 downto 1);
signal poly_sel_hp : std_logic_vector(4 downto 1);
signal poly_sel_hp_t1 : std_logic_vector(4 downto 1);
signal poly_sel_hp_reg : std_logic_vector(4 downto 1);
signal tone_gen_final : std_logic_vector(4 downto 1) := (others => '0');
signal o_audio : std_logic_vector(7 downto 0) := (others => '0');
-- clock divider
constant PRE_CLOCK_DIVIDER: integer := 54;
signal clk177: std_logic := '0';
signal predivcnt: integer;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- wishbone signals
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
ena <= '1';
data_out <= o_audio;
predivider: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
clk177 <= '0';
predivcnt <= PRE_CLOCK_DIVIDER;
else
clk177 <='0';
if predivcnt=0 then
clk177 <='1';
predivcnt <= PRE_CLOCK_DIVIDER;
else
predivcnt <= predivcnt -1 ;
end if;
end if;
end if;
end process;
p_dividers : process
begin
wait until rising_edge(wb_clk_i);
if clk177='1' then
if (ena = '1') then
ena_64k <= '0';
if cnt_64k = "00000" then
cnt_64k <= "11011"; -- 28 - 1
ena_64k <= '1';
else
cnt_64k <= cnt_64k - "1";
end if;
ena_15k <= '0';
if cnt_15k = "0000000" then
cnt_15k <= "1110001"; -- 114 - 1
ena_15k <= '1';
else
cnt_15k <= cnt_15k - "1";
end if;
end if;
end if;
end process;
p_ena_64k_15k : process(ena_64k, ena_15k, audctl)
begin
if (audctl(0) = '1') then
ena_64k_15k <= ena_15k;
else
ena_64k_15k <= ena_64k;
end if;
end process;
p_poly : process
variable poly9_zero : std_logic;
variable poly17_zero : std_logic;
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
poly4 <= poly4(2 downto 0) & not (poly4(3) xor poly4(2));
poly5 <= poly5(3 downto 0) & not (poly5(4) xor poly4(2)); -- used inverted
-- not correct
poly9_zero := '0';
if (poly9 = "000000000") then poly9_zero := '1'; end if;
poly9 <= poly9(7 downto 0) & (poly9(8) xor poly9(3) xor poly9_zero);
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
poly17 <= poly17(15 downto 0) & (poly17(16) xor poly17(2) xor poly17_zero);
end if;
end process;
p_random_mux : process(audctl, poly9, poly17)
begin
-- bit unnecessary this ....
for i in 0 to 7 loop
if (audctl(7) = '1') then -- 9 bit poly
random(i) <= poly9(8-i);
else
random(i) <= poly17(16-i);
end if;
end loop;
if (audctl(7) = '1') then
poly_17_9 <= poly9(8);
else
poly_17_9 <= poly17(16);
end if;
end process;
p_wdata : process
begin
wait until rising_edge(wb_clk_i);
potgo <= '0';
--if (reset = '1') then
-- no idea what the reset state is
--audf <= (others => (others => '0'));
--audc <= (others => (others => '0'));
--audctl <= x"00";
--else
if (wb_we_i = '1' and wb_cyc_i='1' and wb_stb_i='1') then
case wb_adr_i(5 downto 2) is
when x"0" => audf(1) <= wb_dat_i(7 downto 0);
when x"1" => audc(1) <= wb_dat_i(7 downto 0);
when x"2" => audf(2) <= wb_dat_i(7 downto 0);
when x"3" => audc(2) <= wb_dat_i(7 downto 0);
when x"4" => audf(3) <= wb_dat_i(7 downto 0);
when x"5" => audc(3) <= wb_dat_i(7 downto 0);
when x"6" => audf(4) <= wb_dat_i(7 downto 0);
when x"7" => audc(4) <= wb_dat_i(7 downto 0);
when x"8" => audctl <= wb_dat_i(7 downto 0);
when x"9" => stimer <= wb_dat_i(7 downto 0);
when x"A" => skres <= wb_dat_i(7 downto 0);
when x"B" => potgo <= '1';
--when x"C" =>
when x"D" => serout <= wb_dat_i(7 downto 0);
when x"E" => irqen <= wb_dat_i(7 downto 0);
when x"F" => skctls <= wb_dat_i(7 downto 0);
when others => null;
end case;
end if;
--end if;
end process;
--p_reset : process(skctls)
--begin
-- chip in reset if bits 1..0 of skctls are both zero
--reset <= '0';
--if (skctls(1 downto 0) = "00") then
-- reset <= '1';
--end if;
--end process;
p_rdata : process(wb_adr_i, random) --,pin_reg_gated, pot_val, kbcode, serin, irqst, skstat)
begin
case wb_adr_i(5 downto 2) IS
when x"A" =>
wb_dat_o(7 downto 0) <= random;
when others =>
wb_dat_o(7 downto 0) <= (others => DontCareValue);
end case;
end process;
-- POT ANALOGUE IN UNTESTED !!
-- p_pot_cnt : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (potgo = '1') then
-- pot_cnt <= x"00";
-- elsif ((ena_15k = '1') or (skctls(2) = '1')) and (ena = '1') then -- fast scan mode
-- pot_cnt <= pot_cnt + "1";
-- end if;
-- end process;
--
-- p_pot_comp : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (reset = '1') then
-- pot_fin <= '1';
-- else
-- if (potgo = '1') then
-- pot_fin <= '0';
-- elsif (pot_cnt = x"E4") then -- 228
-- pot_fin <= '1';
-- end if;
-- end if;
-- end process;
--
-- p_pot_val : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- for i in 0 to 7 loop
-- if (pot_fin = '0') and (pin_reg(i) = '0') then
-- -- continue latching counter value until input reaches ViH threshold
-- pot_val(i) <= pot_cnt;
-- end if;
-- end loop;
-- end process;
-- dump transistors
--PIN <= x"00" when (pot_fin = '1') else (others => 'Z');
-- p_in_gate : process(pin_reg, reset) -- dump transistor fakeup
-- begin
-- pin_reg_gated <= pin_reg;
-- -- I think the datasheet lies about dump transistors being disabled
-- -- in fast scan mode, as the self test fails ....
-- if (reset = '1') or (pot_fin = '1') then --and (skctls(2) = '0'))
-- pin_reg_gated <= x"00";
-- end if;
-- end process;
p_tone_cnt_ena : process(audctl, ena_64k_15k, tone_gen_div)
variable chan_ena1, chan_ena3 : std_ulogic;
begin
if (audctl(6) = '1') then
chan_ena1 := '1'; -- 1.5 MHz,
else
chan_ena1 := ena_64k_15k;
end if;
chan_ena(1) <= chan_ena1;
if (audctl(4) = '1') then -- chan 1/2 joined
chan_ena(2) <= chan_ena1;
else
chan_ena(2) <= ena_64k_15k;
end if;
if (audctl(5) = '1') then
chan_ena3 := '1'; -- 1.5 MHz,
else
chan_ena3 := ena_64k_15k; -- 64 KHz
end if;
chan_ena(3) <= chan_ena3;
if (audctl(3) = '1') then -- chan 3/4 joined
chan_ena(4) <= chan_ena3;
else
chan_ena(4) <= ena_64k_15k; -- 64 KHz
end if;
end process;
p_tone_generator_zero : process(tone_gen_cnt, chan_ena)
begin
for i in 1 to 4 loop
if (tone_gen_cnt(i) = "00000000") and (chan_ena(i) = '1') then
tone_gen_zero(i) <= '1';
else
tone_gen_zero(i) <= '0';
end if;
end loop;
end process;
p_tone_generators : process
variable chan_load : std_logic_vector(4 downto 1);
variable chan_dec : std_logic_vector(4 downto 1);
begin
-- quite tricky this .. but I think it does the correct stuff
-- bet this is not how is was done originally !
--
-- nasty frig to easily get exact chip behaviour in high speed mode
-- fout = fin / 2(audf + n) when n=4 or 7 in 16 bit mode
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
tone_gen_div <= "0000";
if (audctl(4) = '1') then -- chan 1/2 joined
chan_load(1) := '0';
chan_load(2) := '0';
if (tone_gen_zero_t(1)(5) = '1') and (tone_gen_zero_t(2)(5) = '1') and (chan_done_load(1) = '0') then
chan_load(1) := '1';
chan_load(2) := '1';
end if;
chan_dec(1) := '1';
chan_dec(2) := tone_gen_zero(1);
else
chan_load(1) := tone_gen_zero_t(1)(2) and not chan_done_load(1);
chan_load(2) := tone_gen_zero_t(2)(2) and not chan_done_load(2);
chan_dec(1) := '1';
chan_dec(2) := '1';
end if;
if (audctl(3) = '1') then -- chan 1/2 joined
chan_load(3) := '0';
chan_load(4) := '0';
if (tone_gen_zero_t(3)(5) = '1') and (tone_gen_zero_t(4)(5) = '1') and (chan_done_load(3) = '0') then
chan_load(3) := '1';
chan_load(4) := '1';
end if;
chan_dec(3) := '1';
chan_dec(4) := tone_gen_zero(3);
else
chan_load(3) := tone_gen_zero_t(3)(2) and not chan_done_load(3);
chan_load(4) := tone_gen_zero_t(4)(2) and not chan_done_load(4);
chan_dec(3) := '1';
chan_dec(4) := '1';
end if;
for i in 1 to 4 loop
if (chan_load(i) = '1') then
chan_done_load(i) <= '1';
tone_gen_div(i) <= '1';
tone_gen_cnt(i) <= audf(i);
elsif (chan_dec(i) = '1') and (chan_ena(i) = '1') then
chan_done_load(i) <= '0';
tone_gen_cnt(i) <= tone_gen_cnt(i) - "1";
end if;
tone_gen_div(i) <= chan_load(i);
tone_gen_zero_t(i)(7 downto 0) <= tone_gen_zero_t(i)(6 downto 0) & tone_gen_zero(i);
end loop;
end if;
end process;
p_tone_generator_mux : process(audctl, tone_gen_div)
begin
if (audctl(4) = '1') then -- chan 1/2 joined
tone_gen_div_mux(1) <= tone_gen_div(1); -- do they both waggle
tone_gen_div_mux(2) <= tone_gen_div(2); -- or do I mute chan 1?
else
tone_gen_div_mux(1) <= tone_gen_div(1);
tone_gen_div_mux(2) <= tone_gen_div(2);
end if;
if (audctl(3) = '1') then -- chan 3/4 joined
tone_gen_div_mux(3) <= tone_gen_div(3); -- ditto
tone_gen_div_mux(4) <= tone_gen_div(4);
else
tone_gen_div_mux(3) <= tone_gen_div(3);
tone_gen_div_mux(4) <= tone_gen_div(4);
end if;
end process;
p_poly_gating : process(audc, poly4, poly5, poly_17_9, tone_gen_div_mux)
variable filter_a : std_logic_vector(4 downto 1);
variable filter_b : std_logic_vector(4 downto 1);
begin
for i in 1 to 4 loop
if (audc(i)(7) = '0') then
filter_a(i) := poly5(4) and tone_gen_div_mux(i);-- 5 bit poly
else
filter_a(i) := tone_gen_div_mux(i);
end if;
if (audc(i)(6) = '0') then
filter_b(i) := poly_17_9 and filter_a(i);-- 17 bit poly
else
filter_b(i) := poly4(3) and filter_a(i);-- 4 bit poly
end if;
if (audc(i)(5) = '0') then
poly_sel(i) <= filter_b(i);
else
poly_sel(i) <= filter_a(i);
end if;
end loop;
end process;
p_high_pass_filters : process(audctl, poly_sel, poly_sel_hp_reg)
begin
poly_sel_hp <= poly_sel;
if (audctl(2) = '1') then
poly_sel_hp(1) <= poly_sel(1) xor poly_sel_hp_reg(1);
end if;
if (audctl(1) = '1') then
poly_sel_hp(2) <= poly_sel(2) xor poly_sel_hp_reg(2);
end if;
end process;
p_audio_out : process
begin
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
for i in 1 to 4 loop
-- filter reg
if (tone_gen_div(3) = '1') then -- tone gen 1 clocked by gen 3
poly_sel_hp_reg(1) <= poly_sel(1);
end if;
if (tone_gen_div(4) = '1') then -- tone gen 2 clocked by gen 4
poly_sel_hp_reg(2) <= poly_sel(2);
end if;
poly_sel_hp_t1 <= poly_sel_hp;
if (poly_sel_hp(i) = '1') and (poly_sel_hp_t1(i) = '0') then -- rising edge
tone_gen_final(i) <= not tone_gen_final(i);
end if;
end loop;
end if;
end process;
p_op_mixer : process
variable vol : array_4x4;
variable sum12 : std_logic_vector(4 downto 0);
variable sum34 : std_logic_vector(4 downto 0);
variable sum : std_logic_vector(5 downto 0);
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
for i in 1 to 4 loop
if (audc(i)(4) = '1') then -- vol only
vol(i) := audc(i)(3 downto 0);
else
if (tone_gen_final(i) = '1') then
vol(i) := audc(i)(3 downto 0);
else
vol(i) := "0000";
end if;
end if;
end loop;
sum12 := ('0' & vol(1)) + ('0' & vol(2));
sum34 := ('0' & vol(3)) + ('0' & vol(4));
sum := ('0' & sum12) + ('0' & sum34);
if (wb_rst_i = '1') then
o_audio <= "00000000";
else
if (sum(5) = '0') then
o_audio <= sum(4 downto 0) & "000";
else -- clip
o_audio <= "11111111";
end if;
end if;
end if;
end process;
-- keyboard / serial etc to do
end architecture RTL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd | 13 | 19476 | --
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 002 return 00 on allpot when fast scan completed to fix self test
-- version 001 initial release (this version should be considered Beta
-- it seems to make all the right sort of sounds however ... )
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_pokey is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
data_out: out std_logic_vector(7 downto 0) --Digital data out - this should be fed into an audio mixer or Delta-Sigma DAC.
);
end;
architecture RTL of AUDIO_zpuino_wb_pokey is
type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array_4x8 is array (1 to 4) of std_logic_vector(7 downto 0);
type array_4x4 is array (1 to 4) of std_logic_vector(3 downto 0);
type array_4x9 is array (1 to 4) of std_logic_vector(8 downto 0);
type array_2x17 is array (1 to 2) of std_logic_vector(16 downto 0);
type bool_4 is array (1 to 4) of boolean;
--signal oe : std_logic;
--
signal ena : std_logic;
signal ena_64k_15k : std_logic;
signal cnt_64k : std_logic_vector(4 downto 0) := (others => '0');
signal ena_64k : std_logic;
signal cnt_15k : std_logic_vector(6 downto 0) := (others => '0');
signal ena_15k : std_logic;
--
signal poly4 : std_logic_vector(3 downto 0) := (others => '0');
signal poly5 : std_logic_vector(4 downto 0) := (others => '0');
signal poly9 : std_logic_vector(8 downto 0) := (others => '0');
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
signal poly_17_9 : std_logic;
-- registers wb_dat_i
signal audf : array_4x8 := (x"00",x"00",x"00",x"00");
signal audc : array_4x8 := (x"00",x"00",x"00",x"00");
signal audctl : std_logic_vector(7 downto 0) := "00000000";
signal stimer : std_logic_vector(7 downto 0);
signal skres : std_logic_vector(7 downto 0);
signal potgo : std_logic;
signal serout : std_logic_vector(7 downto 0);
signal irqen : std_logic_vector(7 downto 0);
signal skctls : std_logic_vector(7 downto 0);
--signal reset : std_logic;
--
-- registers wb_dat_o
--signal kbcode : std_logic_vector(7 downto 0);
signal random : std_logic_vector(7 downto 0);
--signal serin : std_logic_vector(7 downto 0);
--signal irqst : std_logic_vector(7 downto 0);
--signal skstat : std_logic_vector(7 downto 0);
--
--
--signal pot_fin : std_logic;
--signal pot_cnt : std_logic_vector(7 downto 0);
--signal pot_val : array_8x8;
--signal pin_reg : std_logic_vector(7 downto 0);
--signal pin_reg_gated : std_logic_vector(7 downto 0);
--
signal chan_ena : std_logic_vector(4 downto 1);
signal tone_gen_div : std_logic_vector(4 downto 1);
signal tone_gen_cnt : array_4x8 := (others => (others => '0'));
signal tone_gen_div_mux : std_logic_vector(4 downto 1);
signal tone_gen_zero : std_logic_vector(4 downto 1);
signal tone_gen_zero_t : array_4x8 := (others => (others => '0'));
signal chan_done_load : std_logic_vector(4 downto 1) := (others => '0');
--
signal poly_sel : std_logic_vector(4 downto 1);
signal poly_sel_hp : std_logic_vector(4 downto 1);
signal poly_sel_hp_t1 : std_logic_vector(4 downto 1);
signal poly_sel_hp_reg : std_logic_vector(4 downto 1);
signal tone_gen_final : std_logic_vector(4 downto 1) := (others => '0');
signal o_audio : std_logic_vector(7 downto 0) := (others => '0');
-- clock divider
constant PRE_CLOCK_DIVIDER: integer := 54;
signal clk177: std_logic := '0';
signal predivcnt: integer;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- wishbone signals
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
ena <= '1';
data_out <= o_audio;
predivider: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
clk177 <= '0';
predivcnt <= PRE_CLOCK_DIVIDER;
else
clk177 <='0';
if predivcnt=0 then
clk177 <='1';
predivcnt <= PRE_CLOCK_DIVIDER;
else
predivcnt <= predivcnt -1 ;
end if;
end if;
end if;
end process;
p_dividers : process
begin
wait until rising_edge(wb_clk_i);
if clk177='1' then
if (ena = '1') then
ena_64k <= '0';
if cnt_64k = "00000" then
cnt_64k <= "11011"; -- 28 - 1
ena_64k <= '1';
else
cnt_64k <= cnt_64k - "1";
end if;
ena_15k <= '0';
if cnt_15k = "0000000" then
cnt_15k <= "1110001"; -- 114 - 1
ena_15k <= '1';
else
cnt_15k <= cnt_15k - "1";
end if;
end if;
end if;
end process;
p_ena_64k_15k : process(ena_64k, ena_15k, audctl)
begin
if (audctl(0) = '1') then
ena_64k_15k <= ena_15k;
else
ena_64k_15k <= ena_64k;
end if;
end process;
p_poly : process
variable poly9_zero : std_logic;
variable poly17_zero : std_logic;
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
poly4 <= poly4(2 downto 0) & not (poly4(3) xor poly4(2));
poly5 <= poly5(3 downto 0) & not (poly5(4) xor poly4(2)); -- used inverted
-- not correct
poly9_zero := '0';
if (poly9 = "000000000") then poly9_zero := '1'; end if;
poly9 <= poly9(7 downto 0) & (poly9(8) xor poly9(3) xor poly9_zero);
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
poly17 <= poly17(15 downto 0) & (poly17(16) xor poly17(2) xor poly17_zero);
end if;
end process;
p_random_mux : process(audctl, poly9, poly17)
begin
-- bit unnecessary this ....
for i in 0 to 7 loop
if (audctl(7) = '1') then -- 9 bit poly
random(i) <= poly9(8-i);
else
random(i) <= poly17(16-i);
end if;
end loop;
if (audctl(7) = '1') then
poly_17_9 <= poly9(8);
else
poly_17_9 <= poly17(16);
end if;
end process;
p_wdata : process
begin
wait until rising_edge(wb_clk_i);
potgo <= '0';
--if (reset = '1') then
-- no idea what the reset state is
--audf <= (others => (others => '0'));
--audc <= (others => (others => '0'));
--audctl <= x"00";
--else
if (wb_we_i = '1' and wb_cyc_i='1' and wb_stb_i='1') then
case wb_adr_i(5 downto 2) is
when x"0" => audf(1) <= wb_dat_i(7 downto 0);
when x"1" => audc(1) <= wb_dat_i(7 downto 0);
when x"2" => audf(2) <= wb_dat_i(7 downto 0);
when x"3" => audc(2) <= wb_dat_i(7 downto 0);
when x"4" => audf(3) <= wb_dat_i(7 downto 0);
when x"5" => audc(3) <= wb_dat_i(7 downto 0);
when x"6" => audf(4) <= wb_dat_i(7 downto 0);
when x"7" => audc(4) <= wb_dat_i(7 downto 0);
when x"8" => audctl <= wb_dat_i(7 downto 0);
when x"9" => stimer <= wb_dat_i(7 downto 0);
when x"A" => skres <= wb_dat_i(7 downto 0);
when x"B" => potgo <= '1';
--when x"C" =>
when x"D" => serout <= wb_dat_i(7 downto 0);
when x"E" => irqen <= wb_dat_i(7 downto 0);
when x"F" => skctls <= wb_dat_i(7 downto 0);
when others => null;
end case;
end if;
--end if;
end process;
--p_reset : process(skctls)
--begin
-- chip in reset if bits 1..0 of skctls are both zero
--reset <= '0';
--if (skctls(1 downto 0) = "00") then
-- reset <= '1';
--end if;
--end process;
p_rdata : process(wb_adr_i, random) --,pin_reg_gated, pot_val, kbcode, serin, irqst, skstat)
begin
case wb_adr_i(5 downto 2) IS
when x"A" =>
wb_dat_o(7 downto 0) <= random;
when others =>
wb_dat_o(7 downto 0) <= (others => DontCareValue);
end case;
end process;
-- POT ANALOGUE IN UNTESTED !!
-- p_pot_cnt : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (potgo = '1') then
-- pot_cnt <= x"00";
-- elsif ((ena_15k = '1') or (skctls(2) = '1')) and (ena = '1') then -- fast scan mode
-- pot_cnt <= pot_cnt + "1";
-- end if;
-- end process;
--
-- p_pot_comp : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- if (reset = '1') then
-- pot_fin <= '1';
-- else
-- if (potgo = '1') then
-- pot_fin <= '0';
-- elsif (pot_cnt = x"E4") then -- 228
-- pot_fin <= '1';
-- end if;
-- end if;
-- end process;
--
-- p_pot_val : process
-- begin
-- wait until rising_edge(wb_clk_i);
-- for i in 0 to 7 loop
-- if (pot_fin = '0') and (pin_reg(i) = '0') then
-- -- continue latching counter value until input reaches ViH threshold
-- pot_val(i) <= pot_cnt;
-- end if;
-- end loop;
-- end process;
-- dump transistors
--PIN <= x"00" when (pot_fin = '1') else (others => 'Z');
-- p_in_gate : process(pin_reg, reset) -- dump transistor fakeup
-- begin
-- pin_reg_gated <= pin_reg;
-- -- I think the datasheet lies about dump transistors being disabled
-- -- in fast scan mode, as the self test fails ....
-- if (reset = '1') or (pot_fin = '1') then --and (skctls(2) = '0'))
-- pin_reg_gated <= x"00";
-- end if;
-- end process;
p_tone_cnt_ena : process(audctl, ena_64k_15k, tone_gen_div)
variable chan_ena1, chan_ena3 : std_ulogic;
begin
if (audctl(6) = '1') then
chan_ena1 := '1'; -- 1.5 MHz,
else
chan_ena1 := ena_64k_15k;
end if;
chan_ena(1) <= chan_ena1;
if (audctl(4) = '1') then -- chan 1/2 joined
chan_ena(2) <= chan_ena1;
else
chan_ena(2) <= ena_64k_15k;
end if;
if (audctl(5) = '1') then
chan_ena3 := '1'; -- 1.5 MHz,
else
chan_ena3 := ena_64k_15k; -- 64 KHz
end if;
chan_ena(3) <= chan_ena3;
if (audctl(3) = '1') then -- chan 3/4 joined
chan_ena(4) <= chan_ena3;
else
chan_ena(4) <= ena_64k_15k; -- 64 KHz
end if;
end process;
p_tone_generator_zero : process(tone_gen_cnt, chan_ena)
begin
for i in 1 to 4 loop
if (tone_gen_cnt(i) = "00000000") and (chan_ena(i) = '1') then
tone_gen_zero(i) <= '1';
else
tone_gen_zero(i) <= '0';
end if;
end loop;
end process;
p_tone_generators : process
variable chan_load : std_logic_vector(4 downto 1);
variable chan_dec : std_logic_vector(4 downto 1);
begin
-- quite tricky this .. but I think it does the correct stuff
-- bet this is not how is was done originally !
--
-- nasty frig to easily get exact chip behaviour in high speed mode
-- fout = fin / 2(audf + n) when n=4 or 7 in 16 bit mode
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
tone_gen_div <= "0000";
if (audctl(4) = '1') then -- chan 1/2 joined
chan_load(1) := '0';
chan_load(2) := '0';
if (tone_gen_zero_t(1)(5) = '1') and (tone_gen_zero_t(2)(5) = '1') and (chan_done_load(1) = '0') then
chan_load(1) := '1';
chan_load(2) := '1';
end if;
chan_dec(1) := '1';
chan_dec(2) := tone_gen_zero(1);
else
chan_load(1) := tone_gen_zero_t(1)(2) and not chan_done_load(1);
chan_load(2) := tone_gen_zero_t(2)(2) and not chan_done_load(2);
chan_dec(1) := '1';
chan_dec(2) := '1';
end if;
if (audctl(3) = '1') then -- chan 1/2 joined
chan_load(3) := '0';
chan_load(4) := '0';
if (tone_gen_zero_t(3)(5) = '1') and (tone_gen_zero_t(4)(5) = '1') and (chan_done_load(3) = '0') then
chan_load(3) := '1';
chan_load(4) := '1';
end if;
chan_dec(3) := '1';
chan_dec(4) := tone_gen_zero(3);
else
chan_load(3) := tone_gen_zero_t(3)(2) and not chan_done_load(3);
chan_load(4) := tone_gen_zero_t(4)(2) and not chan_done_load(4);
chan_dec(3) := '1';
chan_dec(4) := '1';
end if;
for i in 1 to 4 loop
if (chan_load(i) = '1') then
chan_done_load(i) <= '1';
tone_gen_div(i) <= '1';
tone_gen_cnt(i) <= audf(i);
elsif (chan_dec(i) = '1') and (chan_ena(i) = '1') then
chan_done_load(i) <= '0';
tone_gen_cnt(i) <= tone_gen_cnt(i) - "1";
end if;
tone_gen_div(i) <= chan_load(i);
tone_gen_zero_t(i)(7 downto 0) <= tone_gen_zero_t(i)(6 downto 0) & tone_gen_zero(i);
end loop;
end if;
end process;
p_tone_generator_mux : process(audctl, tone_gen_div)
begin
if (audctl(4) = '1') then -- chan 1/2 joined
tone_gen_div_mux(1) <= tone_gen_div(1); -- do they both waggle
tone_gen_div_mux(2) <= tone_gen_div(2); -- or do I mute chan 1?
else
tone_gen_div_mux(1) <= tone_gen_div(1);
tone_gen_div_mux(2) <= tone_gen_div(2);
end if;
if (audctl(3) = '1') then -- chan 3/4 joined
tone_gen_div_mux(3) <= tone_gen_div(3); -- ditto
tone_gen_div_mux(4) <= tone_gen_div(4);
else
tone_gen_div_mux(3) <= tone_gen_div(3);
tone_gen_div_mux(4) <= tone_gen_div(4);
end if;
end process;
p_poly_gating : process(audc, poly4, poly5, poly_17_9, tone_gen_div_mux)
variable filter_a : std_logic_vector(4 downto 1);
variable filter_b : std_logic_vector(4 downto 1);
begin
for i in 1 to 4 loop
if (audc(i)(7) = '0') then
filter_a(i) := poly5(4) and tone_gen_div_mux(i);-- 5 bit poly
else
filter_a(i) := tone_gen_div_mux(i);
end if;
if (audc(i)(6) = '0') then
filter_b(i) := poly_17_9 and filter_a(i);-- 17 bit poly
else
filter_b(i) := poly4(3) and filter_a(i);-- 4 bit poly
end if;
if (audc(i)(5) = '0') then
poly_sel(i) <= filter_b(i);
else
poly_sel(i) <= filter_a(i);
end if;
end loop;
end process;
p_high_pass_filters : process(audctl, poly_sel, poly_sel_hp_reg)
begin
poly_sel_hp <= poly_sel;
if (audctl(2) = '1') then
poly_sel_hp(1) <= poly_sel(1) xor poly_sel_hp_reg(1);
end if;
if (audctl(1) = '1') then
poly_sel_hp(2) <= poly_sel(2) xor poly_sel_hp_reg(2);
end if;
end process;
p_audio_out : process
begin
wait until rising_edge(wb_clk_i);
if (ena = '1' and clk177='1') then
for i in 1 to 4 loop
-- filter reg
if (tone_gen_div(3) = '1') then -- tone gen 1 clocked by gen 3
poly_sel_hp_reg(1) <= poly_sel(1);
end if;
if (tone_gen_div(4) = '1') then -- tone gen 2 clocked by gen 4
poly_sel_hp_reg(2) <= poly_sel(2);
end if;
poly_sel_hp_t1 <= poly_sel_hp;
if (poly_sel_hp(i) = '1') and (poly_sel_hp_t1(i) = '0') then -- rising edge
tone_gen_final(i) <= not tone_gen_final(i);
end if;
end loop;
end if;
end process;
p_op_mixer : process
variable vol : array_4x4;
variable sum12 : std_logic_vector(4 downto 0);
variable sum34 : std_logic_vector(4 downto 0);
variable sum : std_logic_vector(5 downto 0);
begin
wait until rising_edge(wb_clk_i);
if (ena = '1') then
for i in 1 to 4 loop
if (audc(i)(4) = '1') then -- vol only
vol(i) := audc(i)(3 downto 0);
else
if (tone_gen_final(i) = '1') then
vol(i) := audc(i)(3 downto 0);
else
vol(i) := "0000";
end if;
end if;
end loop;
sum12 := ('0' & vol(1)) + ('0' & vol(2));
sum34 := ('0' & vol(3)) + ('0' & vol(4));
sum := ('0' & sum12) + ('0' & sum34);
if (wb_rst_i = '1') then
o_audio <= "00000000";
else
if (sum(5) = '0') then
o_audio <= sum(4 downto 0) & "000";
else -- clip
o_audio <= "11111111";
end if;
end if;
end if;
end process;
-- keyboard / serial etc to do
end architecture RTL;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/wb_rom_ram_hyperion.vhd | 13 | 6196 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram_hyperion is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram_hyperion;
architecture behave of wb_rom_ram_hyperion is
component dualport_ram_hyperion is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram_hyperion;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram_hyperion
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/zpuino_gpio.vhd | 13 | 8192 | --
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end entity zpuino_gpio;
architecture behave of zpuino_gpio is
signal gpio_q: std_logic_vector(127 downto 0); -- GPIO output data FFs
signal gpio_tris_q: std_logic_vector(127 downto 0); -- Tristate FFs
signal ppspin_q: std_logic_vector(127 downto 0); -- SPP pin mode FFs
subtype input_number is integer range 0 to 127;
type mapper_q_type is array(0 to 127) of input_number;
signal input_mapper_q: mapper_q_type; -- Mapper for output pins (input data)
signal output_mapper_q: mapper_q_type; -- Mapper for input pins (output data)
signal gpio_r_i: std_logic_vector(127 downto 0);
signal gpio_tris_r_i: std_logic_vector(127 downto 0);
signal gpio_i_q: std_logic_vector(127 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
gpio_t <= gpio_tris_q(gpio_count-1 downto 0);
-- Generate muxers for output.
tgen: for i in 0 to gpio_count-1 generate
process( wb_clk_i )
begin
if rising_edge(wb_clk_i) then -- synchronous output
-- Enforce RST on gpio_o
if wb_rst_i='1' then
gpio_o(i)<='1';
else
if ppspin_q(i)='1' and spp_cap_out(i)='1' then
gpio_o(i) <= spp_data( input_mapper_q(i));
else
gpio_o(i) <= gpio_q(i);
end if;
end if;
end if;
end process;
end generate;
-- Generate muxers for input
spprgen: for i in 0 to gpio_count-1 generate
gpio_i_q(i) <= gpio_i(i) when spp_cap_in(i)='1' else DontCareValue;
process( gpio_i_q(i), output_mapper_q(i) )
begin
spp_read(i) <= gpio_i_q( output_mapper_q(i) );
end process;
end generate;
ilink1: for i in 0 to gpio_count-1 generate
gpio_r_i(i) <= gpio_i(i);
gpio_tris_r_i(i) <= gpio_tris_q(i);
end generate;
ilink2: for i in gpio_count to 127 generate
gpio_r_i(i) <= DontCareValue;
gpio_tris_r_i(i) <= DontCareValue;
end generate;
process(wb_adr_i,gpio_r_i,gpio_tris_r_i,ppspin_q)
begin
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_r_i(127 downto 96);
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_tris_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_tris_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_tris_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_tris_r_i(127 downto 96);
when others =>
end case;
when "10" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= ppspin_q(31 downto 0);
when "01" =>
wb_dat_o <= ppspin_q(63 downto 32);
when "10" =>
wb_dat_o <= ppspin_q(95 downto 64);
when "11" =>
wb_dat_o <= ppspin_q(127 downto 96);
when others =>
end case;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
gpio_tris_q <= (others => '1');
ppspin_q <= (others => '0');
gpio_q <= (others => DontCareValue);
-- Default values for input/output mapper
--for i in 0 to 127 loop
-- input_mapper_q(i) <= 0;
-- output_mapper_q(i) <= 0;
--end loop;
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(10 downto 9) is
when "00" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_tris_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_tris_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_tris_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_tris_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "10" =>
if zpuino_pps_enabled then
case wb_adr_i(3 downto 2) is
when "00" =>
ppspin_q(31 downto 0) <= wb_dat_i;
when "01" =>
ppspin_q(63 downto 32) <= wb_dat_i;
when "10" =>
ppspin_q(95 downto 64) <= wb_dat_i;
when "11" =>
ppspin_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
if zpuino_pps_enabled then
input_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when "10" =>
if zpuino_pps_enabled then
output_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/zpuino_gpio.vhd | 13 | 8192 | --
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_gpio is
generic (
gpio_count: integer := 32
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
spp_data: in std_logic_vector(gpio_count-1 downto 0);
spp_read: out std_logic_vector(gpio_count-1 downto 0);
gpio_o: out std_logic_vector(gpio_count-1 downto 0);
gpio_t: out std_logic_vector(gpio_count-1 downto 0);
gpio_i: in std_logic_vector(gpio_count-1 downto 0);
spp_cap_in: in std_logic_vector(gpio_count-1 downto 0); -- SPP capable pin for INPUT
spp_cap_out: in std_logic_vector(gpio_count-1 downto 0) -- SPP capable pin for OUTPUT
);
end entity zpuino_gpio;
architecture behave of zpuino_gpio is
signal gpio_q: std_logic_vector(127 downto 0); -- GPIO output data FFs
signal gpio_tris_q: std_logic_vector(127 downto 0); -- Tristate FFs
signal ppspin_q: std_logic_vector(127 downto 0); -- SPP pin mode FFs
subtype input_number is integer range 0 to 127;
type mapper_q_type is array(0 to 127) of input_number;
signal input_mapper_q: mapper_q_type; -- Mapper for output pins (input data)
signal output_mapper_q: mapper_q_type; -- Mapper for input pins (output data)
signal gpio_r_i: std_logic_vector(127 downto 0);
signal gpio_tris_r_i: std_logic_vector(127 downto 0);
signal gpio_i_q: std_logic_vector(127 downto 0);
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
gpio_t <= gpio_tris_q(gpio_count-1 downto 0);
-- Generate muxers for output.
tgen: for i in 0 to gpio_count-1 generate
process( wb_clk_i )
begin
if rising_edge(wb_clk_i) then -- synchronous output
-- Enforce RST on gpio_o
if wb_rst_i='1' then
gpio_o(i)<='1';
else
if ppspin_q(i)='1' and spp_cap_out(i)='1' then
gpio_o(i) <= spp_data( input_mapper_q(i));
else
gpio_o(i) <= gpio_q(i);
end if;
end if;
end if;
end process;
end generate;
-- Generate muxers for input
spprgen: for i in 0 to gpio_count-1 generate
gpio_i_q(i) <= gpio_i(i) when spp_cap_in(i)='1' else DontCareValue;
process( gpio_i_q(i), output_mapper_q(i) )
begin
spp_read(i) <= gpio_i_q( output_mapper_q(i) );
end process;
end generate;
ilink1: for i in 0 to gpio_count-1 generate
gpio_r_i(i) <= gpio_i(i);
gpio_tris_r_i(i) <= gpio_tris_q(i);
end generate;
ilink2: for i in gpio_count to 127 generate
gpio_r_i(i) <= DontCareValue;
gpio_tris_r_i(i) <= DontCareValue;
end generate;
process(wb_adr_i,gpio_r_i,gpio_tris_r_i,ppspin_q)
begin
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_r_i(127 downto 96);
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= gpio_tris_r_i(31 downto 0);
when "01" =>
wb_dat_o <= gpio_tris_r_i(63 downto 32);
when "10" =>
wb_dat_o <= gpio_tris_r_i(95 downto 64);
when "11" =>
wb_dat_o <= gpio_tris_r_i(127 downto 96);
when others =>
end case;
when "10" =>
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= ppspin_q(31 downto 0);
when "01" =>
wb_dat_o <= ppspin_q(63 downto 32);
when "10" =>
wb_dat_o <= ppspin_q(95 downto 64);
when "11" =>
wb_dat_o <= ppspin_q(127 downto 96);
when others =>
end case;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
gpio_tris_q <= (others => '1');
ppspin_q <= (others => '0');
gpio_q <= (others => DontCareValue);
-- Default values for input/output mapper
--for i in 0 to 127 loop
-- input_mapper_q(i) <= 0;
-- output_mapper_q(i) <= 0;
--end loop;
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(10 downto 9) is
when "00" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
gpio_tris_q(31 downto 0) <= wb_dat_i;
when "01" =>
gpio_tris_q(63 downto 32) <= wb_dat_i;
when "10" =>
gpio_tris_q(95 downto 64) <= wb_dat_i;
when "11" =>
gpio_tris_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
when "10" =>
if zpuino_pps_enabled then
case wb_adr_i(3 downto 2) is
when "00" =>
ppspin_q(31 downto 0) <= wb_dat_i;
when "01" =>
ppspin_q(63 downto 32) <= wb_dat_i;
when "10" =>
ppspin_q(95 downto 64) <= wb_dat_i;
when "11" =>
ppspin_q(127 downto 96) <= wb_dat_i;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
if zpuino_pps_enabled then
input_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when "10" =>
if zpuino_pps_enabled then
output_mapper_q( conv_integer(wb_adr_i(8 downto 2)) ) <= conv_integer(wb_dat_i(6 downto 0));
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/shifter.vhd | 14 | 3771 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lshifter is
generic (
stages: integer := 3
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end lshifter;
architecture behave of lshifter is
subtype word is signed(63 downto 0);
type mregtype is array(0 to stages-1) of word;
signal rq: mregtype;
signal d: std_logic_vector(0 to stages -1);
begin
process(clk,inputA,inputB)
variable r: signed(63 downto 0);
variable idx: signed(31 downto 0);
begin
if rising_edge(clk) then
if rst='1' then
done <= '0';
else
d <= (others =>'0');
if enable='1' then
if multorshift='1' then
idx := signed(inputB);
else
case inputB(4 downto 0) is
when "00000" => idx := "00000000000000000000000000000001";
when "00001" => idx := "00000000000000000000000000000010";
when "00010" => idx := "00000000000000000000000000000100";
when "00011" => idx := "00000000000000000000000000001000";
when "00100" => idx := "00000000000000000000000000010000";
when "00101" => idx := "00000000000000000000000000100000";
when "00110" => idx := "00000000000000000000000001000000";
when "00111" => idx := "00000000000000000000000010000000";
when "01000" => idx := "00000000000000000000000100000000";
when "01001" => idx := "00000000000000000000001000000000";
when "01010" => idx := "00000000000000000000010000000000";
when "01011" => idx := "00000000000000000000100000000000";
when "01100" => idx := "00000000000000000001000000000000";
when "01101" => idx := "00000000000000000010000000000000";
when "01110" => idx := "00000000000000000100000000000000";
when "01111" => idx := "00000000000000001000000000000000";
when "10000" => idx := "00000000000000010000000000000000";
when "10001" => idx := "00000000000000100000000000000000";
when "10010" => idx := "00000000000001000000000000000000";
when "10011" => idx := "00000000000010000000000000000000";
when "10100" => idx := "00000000000100000000000000000000";
when "10101" => idx := "00000000001000000000000000000000";
when "10110" => idx := "00000000010000000000000000000000";
when "10111" => idx := "00000000100000000000000000000000";
when "11000" => idx := "00000001000000000000000000000000";
when "11001" => idx := "00000010000000000000000000000000";
when "11010" => idx := "00000100000000000000000000000000";
when "11011" => idx := "00001000000000000000000000000000";
when "11100" => idx := "00010000000000000000000000000000";
when "11101" => idx := "00100000000000000000000000000000";
when "11110" => idx := "01000000000000000000000000000000";
when "11111" => idx := "10000000000000000000000000000000";
when others =>
end case;
end if;
r := signed(inputA) * idx;
rq(0) <= r(63 downto 0);
d(0) <= '1';
for i in 1 to stages-1 loop
rq(i) <= rq(i-1);
d(i) <= d(i-1);
end loop;
done <= d(stages-1);
output <= std_logic_vector(rq(stages-1));
else
done <= '0';
end if;
end if;
end if;
end process;
end behave; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_250k/prom-generic-dp-32.vhd | 13 | 102419 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(13 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(13 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity prom_generic_dualport;
architecture behave of prom_generic_dualport is
subtype RAM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type RAM_TABLE is array (0 to 4095) of RAM_WORD;
shared variable RAM0: RAM_TABLE := RAM_TABLE'(
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shared variable RAM1: RAM_TABLE := RAM_TABLE'(
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shared variable RAM2: RAM_TABLE := RAM_TABLE'(
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shared variable RAM3: RAM_TABLE := RAM_TABLE'(
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signal rwea: std_logic_vector(3 downto 0);
signal rweb: std_logic_vector(3 downto 0);
signal memaread0: std_logic_vector(7 downto 0);
signal membread0: std_logic_vector(7 downto 0);
signal memaread1: std_logic_vector(7 downto 0);
signal membread1: std_logic_vector(7 downto 0);
signal memaread2: std_logic_vector(7 downto 0);
signal membread2: std_logic_vector(7 downto 0);
signal memaread3: std_logic_vector(7 downto 0);
signal membread3: std_logic_vector(7 downto 0);
begin
rwea(0) <= WEA and MASKA(0);
rweb(0) <= WEB and MASKB(0);
rwea(1) <= WEA and MASKA(1);
rweb(1) <= WEB and MASKB(1);
rwea(2) <= WEA and MASKA(2);
rweb(2) <= WEB and MASKB(2);
rwea(3) <= WEA and MASKA(3);
rweb(3) <= WEB and MASKB(3);
DOA(7 downto 0) <= memaread0;
DOB(7 downto 0) <= membread0;
DOA(15 downto 8) <= memaread1;
DOB(15 downto 8) <= membread1;
DOA(23 downto 16) <= memaread2;
DOB(23 downto 16) <= membread2;
DOA(31 downto 24) <= memaread3;
DOB(31 downto 24) <= membread3;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(0)='1' then
RAM0( conv_integer(ADDRA) ) := DIA(7 downto 0);
end if;
memaread0 <= RAM0(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(0)='1' then
RAM0( conv_integer(ADDRB) ) := DIB(7 downto 0);
end if;
membread0 <= RAM0(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(1)='1' then
RAM1( conv_integer(ADDRA) ) := DIA(15 downto 8);
end if;
memaread1 <= RAM1(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(1)='1' then
RAM1( conv_integer(ADDRB) ) := DIB(15 downto 8);
end if;
membread1 <= RAM1(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(2)='1' then
RAM2( conv_integer(ADDRA) ) := DIA(23 downto 16);
end if;
memaread2 <= RAM2(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(2)='1' then
RAM2( conv_integer(ADDRB) ) := DIB(23 downto 16);
end if;
membread2 <= RAM2(conv_integer(ADDRB)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if rwea(3)='1' then
RAM3( conv_integer(ADDRA) ) := DIA(31 downto 24);
end if;
memaread3 <= RAM3(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if rweb(3)='1' then
RAM3( conv_integer(ADDRB) ) := DIB(31 downto 24);
end if;
membread3 <= RAM3(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config.vhd | 13 | 2676 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 14;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd | 13 | 5860 | -- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___800.000______0.000______50.0______170.542____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to800_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to800_pll;
architecture xilinx of clk_32to800_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to800_pll,clk_wiz_v3_6,{component_name=clk_32to800_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd | 13 | 5860 | -- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___800.000______0.000______50.0______170.542____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to800_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to800_pll;
architecture xilinx of clk_32to800_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to800_pll,clk_wiz_v3_6,{component_name=clk_32to800_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
| mit |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.f-mux21.vhd | 1 | 398 | library ieee;
use ieee.std_logic_1164.all;
-- a goes through with s = '1', b with s = '0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
a: in std_logic_vector(NBIT - 1 downto 0);
b: in std_logic_vector(NBIT - 1 downto 0);
s: in std_logic;
y: out std_logic_vector(NBIT - 1 downto 0)
);
end mux21;
architecture beh of mux21 is
begin
y <= a when S='1' else b;
end beh;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/lsu.vhd | 13 | 2970 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/BRAM8k36bit.vhd | 13 | 2520 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BRAM8k36bit is
generic (
address_bits: integer := 13;
data_bits: integer := 36
);
port (
clka: in std_logic;
-- ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dina: in std_logic_vector(data_bits-1 downto 0);
douta: out std_logic_vector(data_bits-1 downto 0)
);
end entity BRAM8k36bit;
architecture behave of BRAM8k36bit is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
signal ena : std_logic;
begin
ena <= '1';
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dina;
end if;
douta <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/BRAM8k36bit.vhd | 13 | 2520 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BRAM8k36bit is
generic (
address_bits: integer := 13;
data_bits: integer := 36
);
port (
clka: in std_logic;
-- ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dina: in std_logic_vector(data_bits-1 downto 0);
douta: out std_logic_vector(data_bits-1 downto 0)
);
end entity BRAM8k36bit;
architecture behave of BRAM8k36bit is
subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE;
signal ena : std_logic;
begin
ena <= '1';
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dina;
end if;
douta <= RAM(conv_integer(addra)) ;
end if;
end if;
end process;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COMM_zpuino_wb_i2c is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity COMM_zpuino_wb_i2c;
architecture structural of COMM_zpuino_wb_i2c is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COMM_zpuino_wb_i2c is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity COMM_zpuino_wb_i2c;
architecture structural of COMM_zpuino_wb_i2c is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity COMM_zpuino_wb_i2c is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity COMM_zpuino_wb_i2c;
architecture structural of COMM_zpuino_wb_i2c is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end controller;
architecture behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic;
signal output_i : std_logic_vector (31 downto 0);
begin
rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0';
ctr_delay <=
"00" & x"0000" when trig_delay = "01" else
"11" & x"fffe" when trig_delay = "10" else
"11" & x"fffd";
-- synchronization and reset logic
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= SAMPLE;
else
state <= nstate;
counter <= ncounter;
end if;
-- register outputs
output <= output_i;
memoryOut <= la_input;
memoryWrite <= memoryWrite_i;
memoryRead <= memoryRead_i;
send_i <= sendReg;
send <= sendReg;
rle_read <= rle_read_i;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy,
data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn)
begin
case state is
-- default mode: sample data from la_input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= ctr_delay;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if (counter = fwd & "00") or (abort = '1') then
ncounter <= (others => '1');
nstate <= READ;
else
if la_inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
if rle_busy = '1' then
ncounter <= counter;
nstate <= DATAWAIT;
rle_read_i <= '1';
else
ncounter <= (others => '0');
if rle_mode = '1' then
nstate <= RLE_POSTSCRIPT;
else
nstate <= SAMPLE;
end if;
rle_read_i <= '0';
end if;
memoryRead_i <= '0';
else
if rle_busy = '1' then
ncounter <= counter;
memoryRead_i <= '0';
else
ncounter <= counter + 1;
memoryRead_i <= '1';
end if;
nstate <= DATAWAIT;
rle_read_i <= '1';
end if;
memoryWrite_i <= '0';
sendReg <= '0';
output_i <= memoryIn;
when DATAWAIT =>
if data_ready = '1' then
nstate <= READWAIT;
sendReg <= '1';
else
nstate <= state;
sendReg <= '0';
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and send_i = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data
when RLE_POSTSCRIPT =>
if busy = '0' then
if counter = 5 then
sendReg <= '0';
ncounter <= (others => '0');
nstate <= SAMPLE;
output_i <= (others => '0');
elsif counter = 4 and send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= x"00000055";
elsif send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= (others => '0');
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end controller;
architecture behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic;
signal output_i : std_logic_vector (31 downto 0);
begin
rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0';
ctr_delay <=
"00" & x"0000" when trig_delay = "01" else
"11" & x"fffe" when trig_delay = "10" else
"11" & x"fffd";
-- synchronization and reset logic
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= SAMPLE;
else
state <= nstate;
counter <= ncounter;
end if;
-- register outputs
output <= output_i;
memoryOut <= la_input;
memoryWrite <= memoryWrite_i;
memoryRead <= memoryRead_i;
send_i <= sendReg;
send <= sendReg;
rle_read <= rle_read_i;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy,
data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn)
begin
case state is
-- default mode: sample data from la_input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= ctr_delay;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if (counter = fwd & "00") or (abort = '1') then
ncounter <= (others => '1');
nstate <= READ;
else
if la_inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
if rle_busy = '1' then
ncounter <= counter;
nstate <= DATAWAIT;
rle_read_i <= '1';
else
ncounter <= (others => '0');
if rle_mode = '1' then
nstate <= RLE_POSTSCRIPT;
else
nstate <= SAMPLE;
end if;
rle_read_i <= '0';
end if;
memoryRead_i <= '0';
else
if rle_busy = '1' then
ncounter <= counter;
memoryRead_i <= '0';
else
ncounter <= counter + 1;
memoryRead_i <= '1';
end if;
nstate <= DATAWAIT;
rle_read_i <= '1';
end if;
memoryWrite_i <= '0';
sendReg <= '0';
output_i <= memoryIn;
when DATAWAIT =>
if data_ready = '1' then
nstate <= READWAIT;
sendReg <= '1';
else
nstate <= state;
sendReg <= '0';
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and send_i = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data
when RLE_POSTSCRIPT =>
if busy = '0' then
if counter = 5 then
sendReg <= '0';
ncounter <= (others => '0');
nstate <= SAMPLE;
output_i <= (others => '0');
elsif counter = 4 and send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= x"00000055";
elsif send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= (others => '0');
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clock : in std_logic;
reset : in std_logic;
la_input : in std_logic_vector (32 downto 0);
la_inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in std_logic_vector (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector (31 downto 0);
memoryIn : in std_logic_vector (31 downto 0);
memoryOut : out std_logic_vector (32 downto 0);
memoryRead : out std_logic;
memoryWrite : out std_logic;
rle_busy : in std_logic;
rle_read : out std_logic;
rle_mode : in std_logic;
rdstate : out std_logic;
data_ready : in std_logic;
trig_delay : in std_logic_vector(1 downto 0);
abort : in std_logic
);
end controller;
architecture behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic;
signal output_i : std_logic_vector (31 downto 0);
begin
rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0';
ctr_delay <=
"00" & x"0000" when trig_delay = "01" else
"11" & x"fffe" when trig_delay = "10" else
"11" & x"fffd";
-- synchronization and reset logic
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
state <= SAMPLE;
else
state <= nstate;
counter <= ncounter;
end if;
-- register outputs
output <= output_i;
memoryOut <= la_input;
memoryWrite <= memoryWrite_i;
memoryRead <= memoryRead_i;
send_i <= sendReg;
send <= sendReg;
rle_read <= rle_read_i;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy,
data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn)
begin
case state is
-- default mode: sample data from la_input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= ctr_delay;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if (counter = fwd & "00") or (abort = '1') then
ncounter <= (others => '1');
nstate <= READ;
else
if la_inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite_i <= la_inputReady;
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
if rle_busy = '1' then
ncounter <= counter;
nstate <= DATAWAIT;
rle_read_i <= '1';
else
ncounter <= (others => '0');
if rle_mode = '1' then
nstate <= RLE_POSTSCRIPT;
else
nstate <= SAMPLE;
end if;
rle_read_i <= '0';
end if;
memoryRead_i <= '0';
else
if rle_busy = '1' then
ncounter <= counter;
memoryRead_i <= '0';
else
ncounter <= counter + 1;
memoryRead_i <= '1';
end if;
nstate <= DATAWAIT;
rle_read_i <= '1';
end if;
memoryWrite_i <= '0';
sendReg <= '0';
output_i <= memoryIn;
when DATAWAIT =>
if data_ready = '1' then
nstate <= READWAIT;
sendReg <= '1';
else
nstate <= state;
sendReg <= '0';
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and send_i = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite_i <= '0';
memoryRead_i <= '0';
sendReg <= '0';
rle_read_i <= '0';
output_i <= memoryIn;
-- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data
when RLE_POSTSCRIPT =>
if busy = '0' then
if counter = 5 then
sendReg <= '0';
ncounter <= (others => '0');
nstate <= SAMPLE;
output_i <= (others => '0');
elsif counter = 4 and send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= x"00000055";
elsif send_i = '0' then
sendReg <= '1';
ncounter <= counter + 1;
nstate <= state;
output_i <= (others => '0');
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
else
sendReg <= '0';
ncounter <= counter;
nstate <= state;
output_i <= (others => '0');
end if;
memoryWrite_i <= '0';
memoryRead_i <= '0';
rle_read_i <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
vgainst: BUFG
port map (
I => clkin_i,
O => vgaclkout
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_500k/stack.vhd | 13 | 1500 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_b_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(3 downto 0) := (others => '0');
begin
stack: RAMB16_S36_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
DOA => stack_a_read,
DOB => stack_b_read,
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr,
ADDRB => stack_b_addr,
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write,
DIB => stack_b_write,
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable,
WEB => stack_b_writeenable
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/board_Papilio_One_500k/stack.vhd | 13 | 1500 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_b_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(3 downto 0) := (others => '0');
begin
stack: RAMB16_S36_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
DOA => stack_a_read,
DOB => stack_b_read,
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr,
ADDRB => stack_b_addr,
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write,
DIB => stack_b_write,
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable,
WEB => stack_b_writeenable
);
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_One_250k/zpu_config.vhd | 13 | 2676 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpu_config is
-- generate trace output or not.
constant Generate_Trace : boolean := false;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := 'X';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 27;
constant maxAddrBitBRAM : integer := 13;
constant maxIOBit: integer := maxAddrBitIncIO - 1;
constant minIOBit: integer := 2;
constant stackSize_bits: integer := 9;
-- start byte address of stack.
-- point to top of RAM - 2*words
constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
constant enable_fmul16: boolean := false;
constant Undefined: std_logic := '0';
end zpu_config;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_Pro/bootloader.vhd | 13 | 13706 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity bootloader_dp_32;
architecture behave of bootloader_dp_32 is
subtype RAM_WORD is STD_LOGIC_VECTOR (31 downto 0);
type RAM_TABLE is array (0 to 1023) of RAM_WORD;
shared variable RAM: RAM_TABLE := RAM_TABLE'(
x"0b0b0b98",x"c0040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b98",x"a1040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fd0608",x"72830609",x"81058205",x"832b2a83",x"ffff0652",x"04000000",x"00000000",x"00000000",x"71fd0608",x"83ffff73",x"83060981",x"05820583",x"2b2b0906",x"7383ffff",x"0b0b0b0b",x"83a70400",x"72098105",x"72057373",x"09060906",x"73097306",x"070a8106",x"53510400",x"00000000",x"00000000",x"72722473",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71737109",x"71068106",x"30720a10",x"0a720a10",x"0a31050a",x"81065151",x"53510400",x"00000000",x"72722673",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"cc040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"720a722b",x"0a535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72729f06",x"0981050b",x"0b0b88af",x"05040000",x"00000000",x"00000000",x"00000000",x"00000000",x"72722aff",x"739f062a",x"0974090a",x"8106ff05",x"06075351",x"04000000",x"00000000",x"00000000",x"71715351",x"020d0406",x"73830609",x"81058205",x"832b0b2b",x"0772fc06",x"0c515104",x"00000000",x"72098105",x"72050970",x"81050906",x"0a810653",x"51040000",x"00000000",x"00000000",x"00000000",x"72098105",x"72050970",x"81050906",x"0a098106",x"53510400",x"00000000",x"00000000",x"00000000",x"71098105",x"52040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72720981",x"05055351",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097206",x"73730906",x"07535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fc0608",x"72830609",x"81058305",x"1010102a",x"81ff0652",x"04000000",x"00000000",x"00000000",x"71fc0608",x"0b0b0b9e",x"ec738306",x"10100508",x"060b0b0b",x"88b20400",x"00000000",x"00000000",x"0b0b0b89",x"80040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"e8040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097081",x"0509060a",x"8106ff05",x"70547106",x"73097274",x"05ff0506",x"07515151",x"04000000",x"72097081",x"0509060a",x"098106ff",x"05705471",x"06730972",x"7405ff05",x"06075151",x"51040000",x"05ff0504",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"810b0b0b",x"0b9fb40c",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71810552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"02840572",x"10100552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"717105ff",x"05715351",x"020d0400",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"81dd3f96",x"ba3f0400",x"00000000",x"00000000",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101053",x"51047381",x"ff067383",x"06098105",x"83051010",x"102b0772",x"fc060c51",x"51043c04",x"72728072",x"8106ff05",x"09720605",x"71105272",x"0a100a53",x"72ed3851",x"51535104",x"88088c08",x"90087575",x"99ed2d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90087575",x"99a92d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90088dff",x"2d900c8c",x"0c880c04",x"ff3d0d0b",x"0b0b9fc4",x"335170a6",x"389fc008",x"70085252",x"70802e92",x"3884129f",x"c00c702d",x"9fc00870",x"08525270",x"f038810b",x"0b0b0b9f",x"c434833d",x"0d040480",x"3d0d0b0b",x"0b9ff008",x"802e8e38",x"0b0b0b0b",x"800b802e",x"09810685",x"38823d0d",x"040b0b0b",x"9ff0510b",x"0b0bf5f8",x"3f823d0d",x"0404ff3d",x"0d80c480",x"80845271",x"0870822a",x"70810651",x"515170f3",x"38833d0d",x"04ff3d0d",x"80c48080",x"84527108",x"70812a70",x"81065151",x"5170f338",x"7382900a",x"0c833d0d",x"04fe3d0d",x"747080dc",x"8080880c",x"7081ff06",x"ff831154",x"51537181",x"268d3880",x"fd518aa9",x"2d72a032",x"51833972",x"518aa92d",x"843d0d04",x"803d0d83",x"ffff0b83",x"d00a0c80",x"fe518aa9",x"2d823d0d",x"04ff3d0d",x"83d00a08",x"70882a52",x"528ac92d",x"7181ff06",x"518ac92d",x"80fe518a",x"a92d833d",x"0d0482f6",x"ff0b80cc",x"8080880c",x"800b80cc",x"8080840c",x"9f0b8390",x"0a0c04ff",x"3d0d7370",x"08515180",x"c8808084",x"70087084",x"80800772",x"0c525283",x"3d0d04ff",x"3d0d80c8",x"80808470",x"0870fbff",x"ff06720c",x"5252833d",x"0d04a090",x"0ba0800c",x"9fc80ba0",x"840c98d9",x"2dff3d0d",x"73518b71",x"0c901152",x"98808072",x"0c80720c",x"700883ff",x"ff06880c",x"833d0d04",x"fa3d0d78",x"7a7dff1e",x"57575853",x"73ff2ea7",x"38805684",x"5275730c",x"72088818",x"0cff1252",x"71f33874",x"84167408",x"720cff16",x"56565273",x"ff2e0981",x"06dd3888",x"3d0d04f8",x"3d0d80c0",x"80808457",x"83d00a59",x"8be32d76",x"518c892d",x"9fc87088",x"08101098",x"80840571",x"70840553",x"0c5656fb",x"8084a1ad",x"750c9fa4",x"0b88170c",x"8070780c",x"770c7608",x"83ffff06",x"5683ffdf",x"800b8808",x"278338ff",x"3983ffff",x"790ca080",x"54880853",x"78527651",x"8ca82d76",x"518bc72d",x"78085574",x"762e8938",x"80c3518a",x"a92dff39",x"a0840855",x"74faa090",x"ae802e89",x"3880c251",x"8aa92dff",x"39900a70",x"0870ffbf",x"06720c56",x"568a8e2d",x"8bfa2dff",x"3d0d9fd4",x"0881119f",x"d40c5183",x"900a7008",x"70feff06",x"720c5252",x"833d0d04",x"803d0d8a",x"f82d7281",x"8007518a",x"c92d8b8d",x"2d823d0d",x"04fe3d0d",x"80c08080",x"84538be3",x"2d85730c",x"80730c72",x"087081ff",x"06745351",x"528bc72d",x"71880c84",x"3d0d04fc",x"3d0d7681",x"11338212",x"33718180",x"0a297184",x"80802905",x"83143370",x"82802912",x"84163352",x"7105a080",x"05861685",x"17335752",x"53535557",x"5553ff13",x"5372ff2e",x"91387370",x"81055533",x"52717570",x"81055734",x"e9398951",x"8e9c2d86",x"3d0d04f9",x"3d0d7957",x"80c08080",x"84568be3",x"2d811733",x"82183371",x"82802905",x"53537180",x"2e943885",x"17725553",x"72708105",x"5433760c",x"ff145473",x"f3388317",x"33841833",x"71828029",x"05565280",x"54737527",x"97387358",x"77760c73",x"17760853",x"53717334",x"81145474",x"7426ed38",x"75518bc7",x"2d8af82d",x"8184518a",x"c92d7488",x"2a518ac9",x"2d74518a",x"c92d8054",x"7375278f",x"38731770",x"3352528a",x"c92d8114",x"54ee398b",x"8d2d893d",x"0d04f93d",x"0d795680",x"c0808084",x"558be32d",x"86750c74",x"518bc72d",x"8be32d81",x"ad70760c",x"81173382",x"18337182",x"80290583",x"1933780c",x"84193378",x"0c851933",x"780c5953",x"53805473",x"7727b338",x"72587380",x"2e87388b",x"e32d7775",x"0c731686",x"1133760c",x"87113376",x"0c527451",x"8bc72d8e",x"b12d8808",x"81065271",x"f6388214",x"54767426",x"d1388be3",x"2d84750c",x"74518bc7",x"2d8af82d",x"8187518a",x"c92d8b8d",x"2d893d0d",x"04fc3d0d",x"76811133",x"82123371",x"902b7188",x"2b078314",x"33707207",x"882b8416",x"33710751",x"52535757",x"54528851",x"8e9c2d81",x"ff518aa9",x"2d80c480",x"80845372",x"0870812a",x"70810651",x"515271f3",x"38738480",x"800780c4",x"8080840c",x"863d0d04",x"fe3d0d8e",x"b12d8808",x"88088106",x"535371f3",x"388af82d",x"8183518a",x"c92d7251",x"8ac92d8b",x"8d2d843d",x"0d04fe3d",x"0d800b9f",x"d40c8af8",x"2d818151",x"8ac92d9f",x"a4538f52",x"72708105",x"5433518a",x"c92dff12",x"5271ff2e",x"098106ec",x"388b8d2d",x"843d0d04",x"fe3d0d80",x"0b9fd40c",x"8af82d81",x"82518ac9",x"2d80c080",x"8084528b",x"e32d81f9",x"0a0b80c0",x"80809c0c",x"71087252",x"538bc72d",x"729fdc0c",x"72902a51",x"8ac92d9f",x"dc08882a",x"518ac92d",x"9fdc0851",x"8ac92d8e",x"b12d8808",x"518ac92d",x"8b8d2d84",x"3d0d0480",x"3d0d810b",x"9fd80c80",x"0b83900a",x"0c85518e",x"9c2d823d",x"0d04803d",x"0d800b9f",x"d80c8bae",x"2d86518e",x"9c2d823d",x"0d04fd3d",x"0d80c080",x"8084548a",x"518e9c2d",x"8be32d9f",x"c8745253",x"8c892d72",x"88081010",x"98808405",x"71708405",x"530c52fb",x"8084a1ad",x"720c9fa4",x"0b88140c",x"73518bc7",x"2d8a8e2d",x"8bfa2dfc",x"3d0d80c0",x"80808470",x"52558bc7",x"2d8be32d",x"8b750c76",x"80c08080",x"940c8075",x"0ca08054",x"775383d0",x"0a527451",x"8ca82d74",x"518bc72d",x"8a8e2d8b",x"fa2dffab",x"3d0d800b",x"9fd80c80",x"0b9fd40c",x"800b8dff",x"0ba0800c",x"5780c480",x"80845584",x"80b3750c",x"80c88080",x"a453fbff",x"ff730870",x"7206750c",x"535480c8",x"80809470",x"08707606",x"720c5353",x"a8709aa5",x"71708405",x"530c9b82",x"710c539c",x"9b0b8812",x"0c9daa0b",x"8c120c94",x"bb0b9012",x"0c53880b",x"80d08080",x"840c80d0",x"0a538173",x"0c8bae2d",x"8288880b",x"80dc8080",x"840c81f2",x"0b900a0c",x"80c08080",x"84705252",x"8bc72d8b",x"e32d7151",x"8bc72d8b",x"e32d8472",x"0c71518b",x"c72d7677",x"7675933d",x"41415b5b",x"5b83d00a",x"5c780870",x"81065152",x"719d389f",x"d8085372",x"f0389fd4",x"085287e8",x"7227e638",x"727e0c72",x"83900a0c",x"98d12d82",x"900a0853",x"79802e81",x"b4387280",x"fe2e0981",x"0680f438",x"76802ec1",x"38807d78",x"58565a82",x"7727ffb5",x"3883ffff",x"7c0c79fe",x"18535379",x"72279838",x"80dc8080",x"88725558",x"72157033",x"790c5281",x"13537373",x"26f238ff",x"16751154",x"7505ff05",x"70337433",x"7072882b",x"077f0853",x"51555152",x"71732e09",x"8106feed",x"38743353",x"728a26fe",x"e4387210",x"109ef805",x"75527008",x"5152712d",x"fed33972",x"80fd2e09",x"81068638",x"815bfec5",x"3976829f",x"269e387a",x"802e8738",x"8073a032",x"545b80d7",x"3d7705fd",x"e0055272",x"72348117",x"57fea239",x"805afe9d",x"397280fe",x"2e098106",x"fe933879",x"5783ffff",x"7c0c8177",x"5c5afe85",x"39803d0d",x"88088c08",x"9008a080",x"0851702d",x"900c8c0c",x"8a0c810b",x"80d00a0c",x"823d0d04",x"ff3d0d98",x"fd2d8052",x"805194f2",x"2d833d0d",x"0483ffff",x"f80d8ce3",x"0483ffff",x"f80da088",x"04000000",x"00000000",x"00000000",x"00000000",x"820b80d0",x"8080900c",x"0b0b0b04",x"0083f00a",x"0b800ba0",x"80721208",x"720c8412",x"5271712e",x"ff05f238",x"028c050d",x"98f00400",x"00000000",x"00000000",x"00000000",x"00fb3d0d",x"77795555",x"80567575",x"24ab3880",x"74249d38",x"80537352",x"745180e1",x"3f880854",x"75802e85",x"38880830",x"5473880c",x"873d0d04",x"73307681",x"325754dc",x"39743055",x"81567380",x"25d238ec",x"39fa3d0d",x"787a5755",x"80577675",x"24a43875",x"9f2c5481",x"53757432",x"74315274",x"519b3f88",x"08547680",x"2e853888",x"08305473",x"880c883d",x"0d047430",x"558157d7",x"39fc3d0d",x"76785354",x"81538074",x"73265255",x"72802e98",x"3870802e",x"a9388072",x"24a43871",x"10731075",x"72265354",x"5272ea38",x"73517883",x"38745170",x"880c863d",x"0d047281",x"2a72812a",x"53537280",x"2ee63871",x"7426ef38",x"73723175",x"74077481",x"2a74812a",x"55555654",x"e539fc3d",x"0d767079",x"7b555555",x"558f7227",x"8c387275",x"07830651",x"70802ea7",x"38ff1252",x"71ff2e98",x"38727081",x"05543374",x"70810556",x"34ff1252",x"71ff2e09",x"8106ea38",x"74880c86",x"3d0d0474",x"51727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0cf01252",x"718f26c9",x"38837227",x"95387270",x"84055408",x"71708405",x"530cfc12",x"52718326",x"ed387054",x"ff8339fc",x"3d0d7679",x"71028c05",x"9f053357",x"55535583",x"72278a38",x"74830651",x"70802ea2",x"38ff1252",x"71ff2e93",x"38737370",x"81055534",x"ff125271",x"ff2e0981",x"06ef3874",x"880c863d",x"0d047474",x"882b7507",x"7071902b",x"07515451",x"8f7227a5",x"38727170",x"8405530c",x"72717084",x"05530c72",x"71708405",x"530c7271",x"70840553",x"0cf01252",x"718f26dd",x"38837227",x"90387271",x"70840553",x"0cfc1252",x"718326f2",x"387053ff",x"9039fb3d",x"0d777970",x"72078306",x"53545270",x"93387173",x"73085456",x"54717308",x"2e80c438",x"73755452",x"71337081",x"ff065254",x"70802e9d",x"38723355",x"70752e09",x"81069538",x"81128114",x"71337081",x"ff065456",x"545270e5",x"38723355",x"7381ff06",x"7581ff06",x"71713188",x"0c525287",x"3d0d0471",x"0970f7fb",x"fdff1406",x"70f88482",x"81800651",x"51517097",x"38841484",x"16710854",x"56547175",x"082edc38",x"73755452",x"ff963980",x"0b880c87",x"3d0d04ff",x"3d0d9fe4",x"0bfc0570",x"08525270",x"ff2e9138",x"702dfc12",x"70085252",x"70ff2e09",x"8106f138",x"833d0d04",x"04eac13f",x"04000000",x"00ffffff",x"ff00ffff",x"ffff00ff",x"ffffff00",x"00000946",x"00000978",x"00000920",x"000007ab",x"000009cf",x"000009e6",x"0000083e",x"000008cd",x"00000757",x"000009fa",x"01090600",x"007fef80",x"05b8d800",x"a4041700",x"00000000",x"00000000",x"00000000",x"00000fec",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"ffffffff",x"00000000",x"ffffffff",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if WEA='1' then
RAM(conv_integer(ADDRA) ) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if WEB='1' then
RAM( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave; | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/zpu_core_extreme_hyperion.vhd | 13 | 42758 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg_hyperion.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_hyperion;
architecture behave of zpu_core_extreme_hyperion is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_Store,
State_StoreB,
State_StoreB2,
State_Load,
State_LoadMemory,
State_LoadStack,
State_Loadb,
State_Resync1,
State_Resync2,
State_LoadSP,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := 10;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
dbg_out.stacka <= std_logic_vector(exr.tos);
dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(rom_wb_dat_i, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(rom_wb_dat_i(31 downto 24));
when 1 => tOpcode := std_logic_vector(rom_wb_dat_i(23 downto 16));
when 2 => tOpcode := std_logic_vector(rom_wb_dat_i(15 downto 8));
when 3 => tOpcode := std_logic_vector(rom_wb_dat_i(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
sampledOpWillFreeze<='1';
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
rom_wb_stb_o <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, rom_wb_ack_i, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, rom_wb_stall_i
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
rom_wb_adr_o <= std_logic_vector(pc_to_memaddr(decr.fetchpc));
rom_wb_cti_o <= CTI_CYCLE_INCRADDR;
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
rom_wb_cyc_o <= '0';
else
rom_wb_cyc_o <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and rom_wb_stall_i='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
rom_wb_cyc_o <='0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
w.valid := rom_wb_ack_i;
end if;
if rom_wb_ack_i='1' then
w.im := sampledOpcode(7);
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and rom_wb_stall_i='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
if rom_wb_stall_i='0' then
w.opcode := sampledOpcode;
end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
w.valid := decr.valid;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
| Decoded_Load
| Decoded_Store
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(10 downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(10 downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
wb_adr_o(maxAddrBitIncIO downto 0) <= std_logic_vector(exr.tos_save(maxAddrBitIncIO downto 0));
wb_cyc_o <= exr.wb_cyc;
wb_stb_o <= exr.wb_stb;
wb_we_o <= exr.wb_we;
wb_dat_o <= std_logic_vector( exr.nos_save );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= '0';
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= '0';
wroteback := wroteback_q;
stack_b_writeenable <= '0';
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
case exr.state is
when State_Resync1 =>
exu_busy <= '1';
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(10 downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<='1';
wroteback:='1';
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= '1';
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<='1';
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= '1';
when Decoded_StoreSP =>
stack_a_writeenable <= '1';
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<='1';
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store =>
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(nos);
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_StoreB =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(10 downto 2));
stack_a_enable<='1';
w.state := State_LoadStack;
else
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
w.wb_we :='0';
w.wb_cyc :='1';
w.wb_stb :='1';
w.state := State_Load;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Store =>
exu_busy <= '1';
-- Keep writeback flag
wroteback := wroteback_q;
if wb_ack_i='1' then
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
stack_b_enable<='1';
wroteback := '0';
--exu_busy <= '1';
w.wb_cyc := '0';
w.state := State_Resync2;
else
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_enable<='0';
stack_b_enable<='0';
end if;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Load =>
if wb_ack_i='0' then
exu_busy<='1';
else
w.tos := unsigned(wb_dat_i);
w.wb_cyc := '0';
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state := State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state := State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
end if;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Storeb then
exu_busy<='1';
w.state:=State_Storeb;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when State_StoreB =>
exu_busy <= '1';
--
-- At this point, we have loaded the 32-bit, and it's in TOS
-- The IO address is still saved in save_TOS.
-- The original write value is still at save_NOS
--
-- So we mangle the write value, and update save_NOS, and restore
-- the IO address to TOS
--
-- This is still buggy - don't use. Problems arise when writing to stack.
--
w.nos_save := exr.tos;
case exr.tos_save(1 downto 0) is
when "00" =>
w.nos_save(31 downto 24) := exr.nos_save(7 downto 0);
when "01" =>
w.nos_save(23 downto 16) := exr.nos_save(7 downto 0);
when "10" =>
w.nos_save(15 downto 8) := exr.nos_save(7 downto 0);
when "11" =>
w.nos_save(7 downto 0) := exr.nos_save(7 downto 0);
when others =>
null;
end case;
w.tos := exr.tos_save;
w.state := State_StoreB2;
when State_StoreB2 =>
exu_busy <= '1';
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(10 downto 2));
stack_a_write <= std_logic_vector(exr.nos_save); -- hmm I don't like this
stack_a_writeenable<='1';
w.state := State_ResyncFromStoreStack;
else
w.wb_we := '1';
w.wb_cyc := '1';
w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
stack_a_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable<='0';
instruction_executed := '0';
w.state := State_Store;
end if;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
| mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_rsft32x5.vhd | 10 | 4329 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT32X5.VHD ***
--*** ***
--*** Function: Single Precision Right Shift ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft32x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END fp_rsft32x5;
ARCHITECTURE rtl OF fp_rsft32x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 29 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(30) <= (inbus(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(31) AND NOT(shift(2)) AND shift(1)) OR
(inbus(32) AND shift(2) AND NOT(shift(1)));
rightone(31) <= (inbus(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(32) AND NOT(shift(2)) AND shift(1));
rightone(32) <= inbus(32) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 20 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 21 TO 24 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 25 TO 28 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 29 TO 32 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_normus64.vhd | 10 | 4503 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_castytof.vhd | 10 | 3181 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>midnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,
cc=>cc);
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_expnornd.vhd | 10 | 4802 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPNORND.VHD ***
--*** ***
--*** Function: DP Exponent Output Block - ***
--*** Simple ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_expnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_expnornd;
ARCHITECTURE rtl OF dp_expnornd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
signal nanff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= '0';
overflowff <= '0';
underflowff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff <= nanin;
overflowff <= overflownode;
underflowff <= underflownode;
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (mantissaexp(k+1) AND setmanzero) OR setmanmax;
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= (exponentexp(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentexp(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentexp(k);
END GENERATE;
-- zero if exponent == 0
zerogen(1) <= exponentexp(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentexp(k);
END GENERATE;
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth)) AND zerogen(expwidth) AND NOT(rangeerror);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth) OR rangeerror;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponentff;
-----------------------------------------------
nanout <= nanff;
overflowout <= overflowff;
underflowout <= underflowff;
END rtl;
| mit |
LorhanSohaky/UFSCar | 2017/lab_cd/aula4/Segmentos7/simulation/qsim/work/@etapa1_vlg_vec_tst/_primary.vhd | 1 | 96 | library verilog;
use verilog.vl_types.all;
entity Etapa1_vlg_vec_tst is
end Etapa1_vlg_vec_tst;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_sin_s5.vhd | 10 | 431526 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sin_s5
-- VHDL created on Wed Mar 13 12:44:09 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sin_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sin_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal exc_R_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal cstBiasMwShift_uid22_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid23_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpSinPiTest_q : std_logic_vector (13 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal cPi_uid52_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal p_uid54_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid54_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal biasM1_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expP_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid59_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal multSecondOperand_uid66_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multSecondOperand_uid66_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal fracNaN_uid86_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal InvSinXIsXRR_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid139_rrx_uid28_fpSinPiTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid169_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid172_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (62 downto 0);
signal zs_uid177_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal zs_uid183_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (52 downto 0);
signal reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q : std_logic_vector (67 downto 0);
signal reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q : std_logic_vector (25 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q : std_logic_vector (65 downto 0);
signal ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q : std_logic_vector (22 downto 0);
signal ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q : std_logic_vector (7 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (64 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q : std_logic_vector (64 downto 0);
signal ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q : std_logic_vector (64 downto 0);
signal ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal pad_one_uid43_fpSinPiTest_q : std_logic_vector (66 downto 0);
signal signExtExpXRR_uid57_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal udf_uid80_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal udf_uid80_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal udf_uid80_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal udf_uid80_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal udf_uid80_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal InvSinXIsX_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid36_uid36_fpSinPiTest_q : std_logic_vector (53 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal exp_uid9_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid99_px_uid27_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid99_px_uid27_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal oneMinusY_uid43_fpSinPiTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal z_uid48_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid48_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal expHardCase_uid56_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid56_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid56_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid56_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excSel_uid85_fpSinPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid88_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid88_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid92_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid92_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal finalExp_uid142_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid142_rrx_uid28_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid182_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid182_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid200_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid200_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal normBit_uid68_fpSinPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid68_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid69_fpSinPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid69_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid70_fpSinPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid70_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid140_rrx_uid28_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal cStage_uid174_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid129_rrx_uid28_fpSinPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid141_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid141_rrx_uid28_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal join_uid73_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal sinXR_uid97_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid143_rrx_uid28_fpSinPiTest_q : std_logic_vector (61 downto 0);
signal vStagei_uid176_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid176_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal excSelBits_uid84_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid120_rrx_uid28_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid120_rrx_uid28_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid65_fpSinPiTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid65_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal R_uid100_px_uid27_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal InvExpXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid46_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal oMyBottom_uid46_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal zAddr_uid61_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal zAddr_uid61_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid62_fpSinPiTest_in : std_logic_vector (56 downto 0);
signal zPPolyEval_uid62_fpSinPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid170_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid170_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid173_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal vStage_uid173_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal rVStage_uid184_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid184_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid186_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid186_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid196_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid196_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid198_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid198_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid202_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid202_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid204_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid204_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid147_fxpX_uid40_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid147_fxpX_uid40_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid150_fxpX_uid40_fpSinPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid150_fxpX_uid40_fpSinPiTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid153_fxpX_uid40_fpSinPiTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid153_fxpX_uid40_fpSinPiTest_b : std_logic_vector (55 downto 0);
signal fracRCompPreRnd_uid71_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid71_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal lowRangeB_uid256_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid256_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid257_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid257_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid262_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid262_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid263_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid263_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid41_fpSinPiTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid41_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid42_fpSinPiTest_in : std_logic_vector (66 downto 0);
signal y_uid42_fpSinPiTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal rndOp_uid74_uid75_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal expXRR_uid32_fpSinPiTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid32_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid33_fpSinPiTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid33_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal rVStage_uid178_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid178_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid180_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid180_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid119_rrx_uid28_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid119_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid254_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid254_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid188_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid188_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid206_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid206_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal signComp_uid95_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal yBottom_uid47_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal yBottom_uid47_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_a : std_logic_vector(34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_b : std_logic_vector(34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_o : std_logic_vector (34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_q : std_logic_vector (33 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_q : std_logic_vector (9 downto 0);
signal multFracBits_uid132_rrx_uid28_fpSinPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid132_rrx_uid28_fpSinPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvExc_N_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid190_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid190_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid192_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid192_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid208_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid208_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal s1_uid256_uid259_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid262_uid265_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal signR_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRCompE_uid78_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal expRCompE_uid78_fpSinPiTest_b : std_logic_vector (8 downto 0);
signal fxpXShiftVal_uid38_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid38_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid136_rrx_uid28_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid136_rrx_uid28_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal fxpSinRes_uid64_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid64_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal pHigh_uid53_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid53_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (13 downto 0);
signal r_uid210_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid138_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid138_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--X55dto0_uid153_fxpX_uid40_fpSinPiTest(BITSELECT,152)@15
X55dto0_uid153_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(55 downto 0);
X55dto0_uid153_fxpX_uid40_fpSinPiTest_b <= X55dto0_uid153_fxpX_uid40_fpSinPiTest_in(55 downto 0);
--leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest(CONSTANT,151)
leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest(BITJOIN,153)@15
leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q <= X55dto0_uid153_fxpX_uid40_fpSinPiTest_b & leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q;
--X59dto0_uid150_fxpX_uid40_fpSinPiTest(BITSELECT,149)@15
X59dto0_uid150_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(59 downto 0);
X59dto0_uid150_fxpX_uid40_fpSinPiTest_b <= X59dto0_uid150_fxpX_uid40_fpSinPiTest_in(59 downto 0);
--cstAllZWE_uid8_fpSinPiTest(CONSTANT,7)
cstAllZWE_uid8_fpSinPiTest_q <= "00000000";
--leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest(BITJOIN,150)@15
leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q <= X59dto0_uid150_fxpX_uid40_fpSinPiTest_b & cstAllZWE_uid8_fpSinPiTest_q;
--X63dto0_uid147_fxpX_uid40_fpSinPiTest(BITSELECT,146)@15
X63dto0_uid147_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(63 downto 0);
X63dto0_uid147_fxpX_uid40_fpSinPiTest_b <= X63dto0_uid147_fxpX_uid40_fpSinPiTest_in(63 downto 0);
--leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest(CONSTANT,145)
leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q <= "0000";
--leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest(BITJOIN,147)@15
leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q <= X63dto0_uid147_fxpX_uid40_fpSinPiTest_b & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--cstZwShiftP1_uid25_fpSinPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpSinPiTest_q <= "00000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable(LOGICAL,818)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q <= not ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor(LOGICAL,971)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q <= not (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a or ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b);
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top(CONSTANT,967)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q <= "01010";
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp(LOGICAL,968)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q <= "1" when ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a = ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b else "0";
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg(REG,969)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena(REG,972)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd(LOGICAL,973)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b <= en;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a and ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b;
--expFracX_uid99_px_uid27_fpSinPiTest(BITSELECT,98)@0
expFracX_uid99_px_uid27_fpSinPiTest_in <= a(30 downto 0);
expFracX_uid99_px_uid27_fpSinPiTest_b <= expFracX_uid99_px_uid27_fpSinPiTest_in(30 downto 0);
--R_uid100_px_uid27_fpSinPiTest(BITJOIN,99)@0
R_uid100_px_uid27_fpSinPiTest_q <= GND_q & expFracX_uid99_px_uid27_fpSinPiTest_b;
--expX_uid119_rrx_uid28_fpSinPiTest(BITSELECT,118)@0
expX_uid119_rrx_uid28_fpSinPiTest_in <= R_uid100_px_uid27_fpSinPiTest_q(30 downto 0);
expX_uid119_rrx_uid28_fpSinPiTest_b <= expX_uid119_rrx_uid28_fpSinPiTest_in(30 downto 23);
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg(DELAY,961)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid119_rrx_uid28_fpSinPiTest_b, xout => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt(COUNTER,963)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg(REG,964)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux(MUX,965)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s <= en;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux: PROCESS (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem(DUALMEM,962)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq,
address_a => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa,
data_a => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia
);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid183_lzcZ_uid50_fpSinPiTest(CONSTANT,182)
zs_uid183_lzcZ_uid50_fpSinPiTest_q <= "0000000000000000";
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor(LOGICAL,945)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q <= not (ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a or ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b);
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg(REG,841)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena(REG,946)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q = "1") THEN
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd(LOGICAL,947)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b <= en;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a and ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg(DELAY,937)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid100_px_uid27_fpSinPiTest_q, xout => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt(COUNTER,837)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i,1));
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg(REG,838)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux(MUX,839)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s <= en;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux: PROCESS (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s, ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q, ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem(DUALMEM,938)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq,
address_a => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa,
data_a => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia
);
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid120_rrx_uid28_fpSinPiTest(BITSELECT,119)@4
fracX_uid120_rrx_uid28_fpSinPiTest_in <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q(22 downto 0);
fracX_uid120_rrx_uid28_fpSinPiTest_b <= fracX_uid120_rrx_uid28_fpSinPiTest_in(22 downto 0);
--oFracX_uid130_uid130_rrx_uid28_fpSinPiTest(BITJOIN,129)@4
oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q <= VCC_q & fracX_uid120_rrx_uid28_fpSinPiTest_b;
--prod_uid131_rrx_uid28_fpSinPiTest_b_0(BITSELECT,337)@4
prod_uid131_rrx_uid28_fpSinPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q);
prod_uid131_rrx_uid28_fpSinPiTest_b_0_b <= prod_uid131_rrx_uid28_fpSinPiTest_b_0_in(26 downto 0);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1(REG,354)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q <= prod_uid131_rrx_uid28_fpSinPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid22_fpSinPiTest(CONSTANT,21)
cstBiasMwShift_uid22_fpSinPiTest_q <= "01110011";
--expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest(SUB,124)@0
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid119_rrx_uid28_fpSinPiTest_b);
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid22_fpSinPiTest_q);
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a) - UNSIGNED(expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b));
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q <= expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o(8 downto 0);
--expXTableAddr_uid126_rrx_uid28_fpSinPiTest(BITSELECT,125)@0
expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in <= expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q(7 downto 0);
expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b <= expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0(REG,349)@0
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q <= expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem(DUALMEM,333)@1
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia <= (others => '0');
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa <= (others => '0');
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab <= reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q;
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq,
address_a => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa,
data_a => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia
);
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0 <= areset;
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q <= rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1(REG,352)@3
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q <= rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem(DUALMEM,332)@1
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia <= (others => '0');
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa <= (others => '0');
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab <= reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q;
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq,
address_a => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa,
data_a => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia
);
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0 <= areset;
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q <= rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0(REG,351)@3
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q <= rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid129_rrx_uid28_fpSinPiTest(BITJOIN,128)@4
os_uid129_rrx_uid28_fpSinPiTest_q <= reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q & reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q;
--prod_uid131_rrx_uid28_fpSinPiTest_a_2(BITSELECT,336)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid129_rrx_uid28_fpSinPiTest_q);
prod_uid131_rrx_uid28_fpSinPiTest_a_2_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_2_in(80 downto 54);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0(REG,357)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a2_b0(MULT,340)@5
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a(DELAY,736)@8
ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q, xout => ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid131_rrx_uid28_fpSinPiTest_align_2(BITSHIFT,343)@9
prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int <= ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid131_rrx_uid28_fpSinPiTest_align_2_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int(107 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_a_1(BITSELECT,335)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_1_in <= os_uid129_rrx_uid28_fpSinPiTest_q(53 downto 0);
prod_uid131_rrx_uid28_fpSinPiTest_a_1_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_1_in(53 downto 27);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0(REG,355)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a1_b0(MULT,339)@5
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_align_1(BITSHIFT,342)@8
prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int <= prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid131_rrx_uid28_fpSinPiTest_align_1_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int(80 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_a_0(BITSELECT,334)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_0_in <= os_uid129_rrx_uid28_fpSinPiTest_q(26 downto 0);
prod_uid131_rrx_uid28_fpSinPiTest_a_0_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_0_in(26 downto 0);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0(REG,353)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a0_b0(MULT,338)@5
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_align_0(BITSHIFT,341)@8
prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int <= prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q;
prod_uid131_rrx_uid28_fpSinPiTest_align_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int(53 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0(ADD,344)@8
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid131_rrx_uid28_fpSinPiTest_align_0_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid131_rrx_uid28_fpSinPiTest_align_1_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a) + UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o(81 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0(ADD,345)@9
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid131_rrx_uid28_fpSinPiTest_align_2_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a) + UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b));
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid132_rrx_uid28_fpSinPiTest(BITSELECT,131)@9
multFracBits_uid132_rrx_uid28_fpSinPiTest_in <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid132_rrx_uid28_fpSinPiTest_b <= multFracBits_uid132_rrx_uid28_fpSinPiTest_in(75 downto 0);
--multFracBitsTop_uid133_rrx_uid28_fpSinPiTest(BITSELECT,132)@9
multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b;
multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in(75 downto 46);
--rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,267)@9
rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b;
rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in(29 downto 14);
--reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1(REG,359)@9
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q <= rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,268)@10
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a <= reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q;
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b <= zs_uid183_lzcZ_uid50_fpSinPiTest_q;
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a(DELAY,762)@10
ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q, xout => ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4(REG,367)@11
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q <= ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,270)@9
vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b(13 downto 0);
vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in(13 downto 0);
--mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest(CONSTANT,269)
mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "11";
--cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest(BITJOIN,271)@9
cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q <= vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b & mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q;
--reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,361)@9
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,273)@10
vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q, reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,275)@10
rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in(15 downto 8);
--vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,276)@10
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b) THEN
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1";
ELSE
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d(DELAY,684)@11
ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q, xout => ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,277)@10
vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q(7 downto 0);
vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,363)@10
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,362)@10
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,279)@11
vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q, reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,281)@11
rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in(7 downto 4);
--vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,282)@11
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b <= leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,366)@11
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest(CONSTANT,159)
leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q <= "00";
--vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,283)@11
vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q(3 downto 0);
vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in(3 downto 0);
--vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,285)@11
vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b, vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b)
BEGIN
CASE vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b;
WHEN "1" => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,287)@11
rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in(3 downto 2);
--vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,288)@11
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b <= leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b) THEN
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1";
ELSE
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,289)@11
vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q(1 downto 0);
vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in(1 downto 0);
--reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,365)@11
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,364)@11
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,291)@12
vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q, reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,293)@12
rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in(1 downto 1);
--vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,294)@12
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b <= GND_q;
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest(BITJOIN,295)@12
r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q & ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q & reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q & vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q & vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q;
--biasM1_uid55_fpSinPiTest(CONSTANT,54)
biasM1_uid55_fpSinPiTest_q <= "01111110";
--expCompOutExt_uid137_rrx_uid28_fpSinPiTest(SUB,136)@12
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid55_fpSinPiTest_q);
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q);
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a) - UNSIGNED(expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b));
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q <= expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o(8 downto 0);
--expCompOut_uid138_rrx_uid28_fpSinPiTest(BITSELECT,137)@12
expCompOut_uid138_rrx_uid28_fpSinPiTest_in <= expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q(7 downto 0);
expCompOut_uid138_rrx_uid28_fpSinPiTest_b <= expCompOut_uid138_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2(REG,374)@12
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q <= expCompOut_uid138_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid124_rrx_uid28_fpSinPiTest(COMPARE,123)@0
xBranch_uid124_rrx_uid28_fpSinPiTest_cin <= GND_q;
xBranch_uid124_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid22_fpSinPiTest_q) & '0';
xBranch_uid124_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid119_rrx_uid28_fpSinPiTest_b) & xBranch_uid124_rrx_uid28_fpSinPiTest_cin(0);
xBranch_uid124_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid124_rrx_uid28_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid124_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid124_rrx_uid28_fpSinPiTest_a) - UNSIGNED(xBranch_uid124_rrx_uid28_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid124_rrx_uid28_fpSinPiTest_n(0) <= not xBranch_uid124_rrx_uid28_fpSinPiTest_o(10);
--ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b(DELAY,530)@1
ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid124_rrx_uid28_fpSinPiTest_n, xout => ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid142_rrx_uid28_fpSinPiTest(MUX,141)@13
finalExp_uid142_rrx_uid28_fpSinPiTest_s <= ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q;
finalExp_uid142_rrx_uid28_fpSinPiTest: PROCESS (finalExp_uid142_rrx_uid28_fpSinPiTest_s, en, reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid142_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b(DELAY,534)@13
ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid142_rrx_uid28_fpSinPiTest_q, xout => ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor(LOGICAL,958)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q <= not (ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a or ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b);
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top(CONSTANT,815)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp(LOGICAL,816)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q);
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q <= "1" when ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a = ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b else "0";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg(REG,817)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena(REG,959)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q = "1") THEN
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd(LOGICAL,960)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b <= en;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a and ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,948)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid120_rrx_uid28_fpSinPiTest_b, xout => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt(COUNTER,811)
-- every=1, low=0, high=7, step=1, init=1
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg(REG,812)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux(MUX,813)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s, ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q, ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem(DUALMEM,949)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia
);
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid139_rrx_uid28_fpSinPiTest(CONSTANT,138)
ZerosGB_uid139_rrx_uid28_fpSinPiTest_q <= "000000000000000000000000000000";
--fracXRExt_uid140_rrx_uid28_fpSinPiTest(BITJOIN,139)@14
fracXRExt_uid140_rrx_uid28_fpSinPiTest_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q & ZerosGB_uid139_rrx_uid28_fpSinPiTest_q;
--LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,321)@13
LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,322)@13
leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b & GND_q;
--X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,305)@9
X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(51 downto 0);
X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in(51 downto 0);
--ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,998)
ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,691)@9
ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest(CONSTANT,225)
leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,306)@12
leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q;
--X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,302)@9
X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(59 downto 0);
X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in(59 downto 0);
--ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,997)
ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,689)@9
ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,303)@12
leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & zs_uid183_lzcZ_uid50_fpSinPiTest_q;
--X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,299)@9
X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(67 downto 0);
X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in(67 downto 0);
--ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,996)
ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,687)@9
ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,300)@12
leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & cstAllZWE_uid8_fpSinPiTest_q;
--ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg(DELAY,999)
ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid132_rrx_uid28_fpSinPiTest_b, xout => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c(DELAY,694)@9
ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q, xout => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,307)@12
leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q;
leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in(4 downto 3);
--leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,308)@12
leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b;
leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q, leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q;
WHEN "01" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,316)@12
LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in(69 downto 0);
--leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest(CONSTANT,236)
leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q <= "000000";
--leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,317)@12
leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q;
--reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5(REG,372)@12
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q <= leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,313)@12
LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,314)@12
leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4(REG,371)@12
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q <= leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,310)@12
LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,311)@12
leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3(REG,370)@12
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q <= leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2(REG,369)@12
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,318)@12
leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1(REG,368)@12
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,319)@13
leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s <= reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q;
leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q, reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q, reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q, reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q;
WHEN "10" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q;
WHEN "11" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,323)@12
leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,324)@13
leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q;
leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "1" => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid136_rrx_uid28_fpSinPiTest(BITSELECT,135)@13
fracCompOut_uid136_rrx_uid28_fpSinPiTest_in <= leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q(74 downto 0);
fracCompOut_uid136_rrx_uid28_fpSinPiTest_b <= fracCompOut_uid136_rrx_uid28_fpSinPiTest_in(74 downto 22);
--reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2(REG,373)@13
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q <= fracCompOut_uid136_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b(DELAY,527)@1
ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid124_rrx_uid28_fpSinPiTest_n, xout => ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid141_rrx_uid28_fpSinPiTest(MUX,140)@14
finalFrac_uid141_rrx_uid28_fpSinPiTest_s <= ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q;
finalFrac_uid141_rrx_uid28_fpSinPiTest: PROCESS (finalFrac_uid141_rrx_uid28_fpSinPiTest_s, en, reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q, fracXRExt_uid140_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE finalFrac_uid141_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= fracXRExt_uid140_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid143_rrx_uid28_fpSinPiTest(BITJOIN,142)@14
RRangeRed_uid143_rrx_uid28_fpSinPiTest_q <= GND_q & ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q & finalFrac_uid141_rrx_uid28_fpSinPiTest_q;
--fracXRR_uid33_fpSinPiTest(BITSELECT,32)@14
fracXRR_uid33_fpSinPiTest_in <= RRangeRed_uid143_rrx_uid28_fpSinPiTest_q(52 downto 0);
fracXRR_uid33_fpSinPiTest_b <= fracXRR_uid33_fpSinPiTest_in(52 downto 0);
--ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a(DELAY,436)@14
ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid33_fpSinPiTest_b, xout => ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid36_uid36_fpSinPiTest(BITJOIN,35)@15
oFracXRR_uid36_uid36_fpSinPiTest_q <= VCC_q & ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@15
extendedFracX_uid39_fpSinPiTest_q <= cstZwShiftP1_uid25_fpSinPiTest_q & oFracXRR_uid36_uid36_fpSinPiTest_q;
--cstBiasMwShiftM2_uid24_fpSinPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpSinPiTest_q <= "01110000";
--expXRR_uid32_fpSinPiTest(BITSELECT,31)@14
expXRR_uid32_fpSinPiTest_in <= RRangeRed_uid143_rrx_uid28_fpSinPiTest_q(60 downto 0);
expXRR_uid32_fpSinPiTest_b <= expXRR_uid32_fpSinPiTest_in(60 downto 53);
--fxpXShiftValExt_uid37_fpSinPiTest(SUB,36)@14
fxpXShiftValExt_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid32_fpSinPiTest_b(7)) & expXRR_uid32_fpSinPiTest_b);
fxpXShiftValExt_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpSinPiTest_q);
fxpXShiftValExt_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid37_fpSinPiTest_a) - SIGNED(fxpXShiftValExt_uid37_fpSinPiTest_b));
fxpXShiftValExt_uid37_fpSinPiTest_q <= fxpXShiftValExt_uid37_fpSinPiTest_o(9 downto 0);
--fxpXShiftVal_uid38_fpSinPiTest(BITSELECT,37)@14
fxpXShiftVal_uid38_fpSinPiTest_in <= fxpXShiftValExt_uid37_fpSinPiTest_q(3 downto 0);
fxpXShiftVal_uid38_fpSinPiTest_b <= fxpXShiftVal_uid38_fpSinPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest(BITSELECT,154)@14
leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in <= fxpXShiftVal_uid38_fpSinPiTest_b;
leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1(REG,375)@14
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest(MUX,155)@15
leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q;
leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest: PROCESS (leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q, leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q, leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest(BITSELECT,163)@15
LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b(DELAY,552)@15
ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest(CONSTANT,162)
leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q <= "000";
--leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest(BITJOIN,164)@16
leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q & leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest(BITSELECT,160)@15
LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(65 downto 0);
LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b(DELAY,550)@15
ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest(BITJOIN,161)@16
leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest(BITSELECT,157)@15
LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(66 downto 0);
LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b(DELAY,548)@15
ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest(BITJOIN,158)@16
leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2(REG,377)@15
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest(BITSELECT,165)@14
leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in <= fxpXShiftVal_uid38_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1(REG,376)@14
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q <= leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b(DELAY,554)@15
ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest(MUX,166)@16
leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s <= ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q;
leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest: PROCESS (leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s, en, reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q, leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q, leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q, leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid41_fpSinPiTest(BITSELECT,40)@16
intXParity_uid41_fpSinPiTest_in <= leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q;
intXParity_uid41_fpSinPiTest_b <= intXParity_uid41_fpSinPiTest_in(67 downto 67);
--exp_uid9_fpSinPiTest(BITSELECT,8)@0
exp_uid9_fpSinPiTest_in <= a(30 downto 0);
exp_uid9_fpSinPiTest_b <= exp_uid9_fpSinPiTest_in(30 downto 23);
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid22_fpSinPiTest_q) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinPiTest_b) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_n(0) <= not sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a(DELAY,501)@0
ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_n, xout => ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid93_fpSinPiTest(LOGICAL,92)@16
InvSinXIsX_uid93_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q;
InvSinXIsX_uid93_fpSinPiTest_q <= not InvSinXIsX_uid93_fpSinPiTest_a;
--cstBiasMwShiftM2_uid23_fpSinPiTest(CONSTANT,22)
cstBiasMwShiftM2_uid23_fpSinPiTest_q <= "01110001";
--sinXIsXRR_uid35_fpSinPiTest(COMPARE,34)@14
sinXIsXRR_uid35_fpSinPiTest_cin <= GND_q;
sinXIsXRR_uid35_fpSinPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid23_fpSinPiTest_q) & '0';
sinXIsXRR_uid35_fpSinPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid32_fpSinPiTest_b(7)) & expXRR_uid32_fpSinPiTest_b) & sinXIsXRR_uid35_fpSinPiTest_cin(0);
sinXIsXRR_uid35_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid35_fpSinPiTest_a) - SIGNED(sinXIsXRR_uid35_fpSinPiTest_b));
sinXIsXRR_uid35_fpSinPiTest_n(0) <= not sinXIsXRR_uid35_fpSinPiTest_o(11);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a(DELAY,502)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid94_fpSinPiTest(LOGICAL,93)@15
InvSinXIsXRR_uid94_fpSinPiTest_a <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q;
InvSinXIsXRR_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvSinXIsXRR_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvSinXIsXRR_uid94_fpSinPiTest_q <= not InvSinXIsXRR_uid94_fpSinPiTest_a;
END IF;
END PROCESS;
--signComp_uid95_fpSinPiTest(LOGICAL,94)@16
signComp_uid95_fpSinPiTest_a <= InvSinXIsXRR_uid94_fpSinPiTest_q;
signComp_uid95_fpSinPiTest_b <= InvSinXIsX_uid93_fpSinPiTest_q;
signComp_uid95_fpSinPiTest_c <= intXParity_uid41_fpSinPiTest_b;
signComp_uid95_fpSinPiTest_q <= signComp_uid95_fpSinPiTest_a and signComp_uid95_fpSinPiTest_b and signComp_uid95_fpSinPiTest_c;
--signX_uid31_fpSinPiTest(BITSELECT,30)@0
signX_uid31_fpSinPiTest_in <= a;
signX_uid31_fpSinPiTest_b <= signX_uid31_fpSinPiTest_in(31 downto 31);
--ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a(DELAY,506)@0
ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signX_uid31_fpSinPiTest_b, xout => ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid96_fpSinPiTest(LOGICAL,95)@16
signR_uid96_fpSinPiTest_a <= ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q;
signR_uid96_fpSinPiTest_b <= signComp_uid95_fpSinPiTest_q;
signR_uid96_fpSinPiTest_q <= signR_uid96_fpSinPiTest_a xor signR_uid96_fpSinPiTest_b;
--ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c(DELAY,510)@16
ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => signR_uid96_fpSinPiTest_q, xout => ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstAllOWE_uid6_fpSinPiTest(CONSTANT,5)
cstAllOWE_uid6_fpSinPiTest_q <= "11111111";
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor(LOGICAL,934)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q <= not (ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a or ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b);
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top(CONSTANT,917)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q <= "0100001";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp(LOGICAL,918)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a = ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg(REG,919)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena(REG,935)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd(LOGICAL,936)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a and ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg(DELAY,924)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinPiTest_b, xout => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt(COUNTER,913)
-- every=1, low=0, high=33, step=1, init=1
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i = 32 THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i - 33;
ELSE
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg(REG,914)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux(MUX,915)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem(DUALMEM,925)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 34,
width_b => 8,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a(DELAY,804)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1(REG,409)@33
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor(LOGICAL,832)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a or ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top(CONSTANT,828)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q <= "01100";
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp(LOGICAL,829)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a = ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg(REG,830)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena(REG,833)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd(LOGICAL,834)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid65_fpSinPiTest(BITSELECT,64)@15
oFracXRRSmallXRR_uid65_fpSinPiTest_in <= oFracXRR_uid36_uid36_fpSinPiTest_q;
oFracXRRSmallXRR_uid65_fpSinPiTest_b <= oFracXRRSmallXRR_uid65_fpSinPiTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg(DELAY,822)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid65_fpSinPiTest_b, xout => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt(COUNTER,824)
-- every=1, low=0, high=12, step=1, init=1
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i = 11 THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i - 12;
ELSE
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg(REG,825)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux(MUX,826)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem(DUALMEM,823)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 13,
width_b => 26,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq(25 downto 0);
--y_uid42_fpSinPiTest(BITSELECT,41)@16
y_uid42_fpSinPiTest_in <= leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q(66 downto 0);
y_uid42_fpSinPiTest_b <= y_uid42_fpSinPiTest_in(66 downto 1);
--reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1(REG,379)@16
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q <= y_uid42_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid43_fpSinPiTest(BITJOIN,42)@16
pad_one_uid43_fpSinPiTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0(REG,378)@16
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q <= pad_one_uid43_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid43_fpSinPiTest(SUB,43)@17
oneMinusY_uid43_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q);
oneMinusY_uid43_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q);
oneMinusY_uid43_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid43_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid43_fpSinPiTest_b));
oneMinusY_uid43_fpSinPiTest_q <= oneMinusY_uid43_fpSinPiTest_o(67 downto 0);
--oMyBottom_uid46_fpSinPiTest(BITSELECT,45)@17
oMyBottom_uid46_fpSinPiTest_in <= oneMinusY_uid43_fpSinPiTest_q(64 downto 0);
oMyBottom_uid46_fpSinPiTest_b <= oMyBottom_uid46_fpSinPiTest_in(64 downto 0);
--ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a(DELAY,777)@17
ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => oMyBottom_uid46_fpSinPiTest_b, xout => ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3(REG,382)@18
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q <= ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--yBottom_uid47_fpSinPiTest(BITSELECT,46)@16
yBottom_uid47_fpSinPiTest_in <= y_uid42_fpSinPiTest_b(64 downto 0);
yBottom_uid47_fpSinPiTest_b <= yBottom_uid47_fpSinPiTest_in(64 downto 0);
--ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a(DELAY,776)@16
ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 65, depth => 2 )
PORT MAP ( xin => yBottom_uid47_fpSinPiTest_b, xout => ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2(REG,381)@18
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q <= ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b(DELAY,445)@16
ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid42_fpSinPiTest_b, xout => ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0(REG,380)@17
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q <= oneMinusY_uid43_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid45_fpSinPiTest(COMPARE,44)@18
cmpYToOneMinusY_uid45_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q) & cmpYToOneMinusY_uid45_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid45_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid45_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid45_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid45_fpSinPiTest_o(70);
--z_uid48_fpSinPiTest(MUX,47)@19
z_uid48_fpSinPiTest_s <= cmpYToOneMinusY_uid45_fpSinPiTest_c;
z_uid48_fpSinPiTest: PROCESS (z_uid48_fpSinPiTest_s, en, reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q, reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q)
BEGIN
CASE z_uid48_fpSinPiTest_s IS
WHEN "0" => z_uid48_fpSinPiTest_q <= reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q;
WHEN "1" => z_uid48_fpSinPiTest_q <= reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q;
WHEN OTHERS => z_uid48_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid61_fpSinPiTest(BITSELECT,60)@19
zAddr_uid61_fpSinPiTest_in <= z_uid48_fpSinPiTest_q;
zAddr_uid61_fpSinPiTest_b <= zAddr_uid61_fpSinPiTest_in(64 downto 57);
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0(REG,398)@19
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid61_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid252_sinPiZTableGenerator_lutmem(DUALMEM,348)@20
memoryC2_uid252_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid252_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid252_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid252_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC2_uid252_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid252_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid252_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid252_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid252_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid252_sinPiZTableGenerator_lutmem_q <= memoryC2_uid252_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1(REG,400)@22
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q <= memoryC2_uid252_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid62_fpSinPiTest(BITSELECT,61)@19
zPPolyEval_uid62_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(56 downto 0);
zPPolyEval_uid62_fpSinPiTest_b <= zPPolyEval_uid62_fpSinPiTest_in(56 downto 39);
--yT1_uid254_sinPiZPolyEval(BITSELECT,253)@19
yT1_uid254_sinPiZPolyEval_in <= zPPolyEval_uid62_fpSinPiTest_b;
yT1_uid254_sinPiZPolyEval_b <= yT1_uid254_sinPiZPolyEval_in(17 downto 5);
--ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg(DELAY,1013)
ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid254_sinPiZPolyEval_b, xout => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a(DELAY,794)@19
ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q, xout => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0(REG,399)@22
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q <= ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid327_pT1_uid255_sinPiZPolyEval(MULT,326)@23
prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid327_pT1_uid255_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid327_pT1_uid255_sinPiZPolyEval_b);
prodXY_uid327_pT1_uid255_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_a <= (others => '0');
prodXY_uid327_pT1_uid255_sinPiZPolyEval_b <= (others => '0');
prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_a <= reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q;
prodXY_uid327_pT1_uid255_sinPiZPolyEval_b <= reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q;
prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid327_pT1_uid255_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_q <= prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval(BITSELECT,327)@26
prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in <= prodXY_uid327_pT1_uid255_sinPiZPolyEval_q;
prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid257_sinPiZPolyEval(BITSELECT,256)@26
highBBits_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b;
highBBits_uid257_sinPiZPolyEval_b <= highBBits_uid257_sinPiZPolyEval_in(13 downto 1);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a(DELAY,796)@19
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => zAddr_uid61_fpSinPiTest_b, xout => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0(REG,401)@22
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid250_sinPiZTableGenerator_lutmem(DUALMEM,347)@23
memoryC1_uid250_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid250_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid250_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q;
memoryC1_uid250_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC1_uid250_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid250_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid250_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid250_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid250_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid250_sinPiZTableGenerator_lutmem_q <= memoryC1_uid250_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0(REG,402)@25
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q <= memoryC1_uid250_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid258_sinPiZPolyEval(ADD,257)@26
sumAHighB_uid258_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q);
sumAHighB_uid258_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid257_sinPiZPolyEval_b(12)) & highBBits_uid257_sinPiZPolyEval_b);
sumAHighB_uid258_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid258_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid258_sinPiZPolyEval_b));
sumAHighB_uid258_sinPiZPolyEval_q <= sumAHighB_uid258_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid256_sinPiZPolyEval(BITSELECT,255)@26
lowRangeB_uid256_sinPiZPolyEval_in <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid256_sinPiZPolyEval_b <= lowRangeB_uid256_sinPiZPolyEval_in(0 downto 0);
--s1_uid256_uid259_sinPiZPolyEval(BITJOIN,258)@26
s1_uid256_uid259_sinPiZPolyEval_q <= sumAHighB_uid258_sinPiZPolyEval_q & lowRangeB_uid256_sinPiZPolyEval_b;
--reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1(REG,404)@26
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q <= s1_uid256_uid259_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor(LOGICAL,1010)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top(CONSTANT,1006)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp(LOGICAL,1007)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg(REG,1008)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena(REG,1011)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd(LOGICAL,1012)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0(REG,403)@19
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q <= zPPolyEval_uid62_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg(DELAY,1000)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1002)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg(REG,1003)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux(MUX,1004)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem(DUALMEM,1001)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid330_pT2_uid261_sinPiZPolyEval(MULT,329)@27
prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid330_pT2_uid261_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid330_pT2_uid261_sinPiZPolyEval_b);
prodXY_uid330_pT2_uid261_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_a <= (others => '0');
prodXY_uid330_pT2_uid261_sinPiZPolyEval_b <= (others => '0');
prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid330_pT2_uid261_sinPiZPolyEval_b <= reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q;
prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid330_pT2_uid261_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_q <= prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval(BITSELECT,330)@30
prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in <= prodXY_uid330_pT2_uid261_sinPiZPolyEval_q;
prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid263_sinPiZPolyEval(BITSELECT,262)@30
highBBits_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b;
highBBits_uid263_sinPiZPolyEval_b <= highBBits_uid263_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,1024)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,1025)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1026)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,1014)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid61_fpSinPiTest_b, xout => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1015)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0(REG,405)@26
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid248_sinPiZTableGenerator_lutmem(DUALMEM,346)@27
memoryC0_uid248_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid248_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid248_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid248_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC0_uid248_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid248_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid248_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid248_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid248_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid248_sinPiZTableGenerator_lutmem_q <= memoryC0_uid248_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0(REG,406)@29
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q <= memoryC0_uid248_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid264_sinPiZPolyEval(ADD,263)@30
sumAHighB_uid264_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q);
sumAHighB_uid264_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid263_sinPiZPolyEval_b(21)) & highBBits_uid263_sinPiZPolyEval_b);
sumAHighB_uid264_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid264_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid264_sinPiZPolyEval_b));
sumAHighB_uid264_sinPiZPolyEval_q <= sumAHighB_uid264_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid262_sinPiZPolyEval(BITSELECT,261)@30
lowRangeB_uid262_sinPiZPolyEval_in <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid262_sinPiZPolyEval_b <= lowRangeB_uid262_sinPiZPolyEval_in(1 downto 0);
--s2_uid262_uid265_sinPiZPolyEval(BITJOIN,264)@30
s2_uid262_uid265_sinPiZPolyEval_q <= sumAHighB_uid264_sinPiZPolyEval_q & lowRangeB_uid262_sinPiZPolyEval_b;
--fxpSinRes_uid64_fpSinPiTest(BITSELECT,63)@30
fxpSinRes_uid64_fpSinPiTest_in <= s2_uid262_uid265_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid64_fpSinPiTest_b <= fxpSinRes_uid64_fpSinPiTest_in(30 downto 5);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b(DELAY,463)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSecondOperand_uid66_fpSinPiTest(MUX,65)@30
multSecondOperand_uid66_fpSinPiTest_s <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q;
multSecondOperand_uid66_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSecondOperand_uid66_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSecondOperand_uid66_fpSinPiTest_s IS
WHEN "0" => multSecondOperand_uid66_fpSinPiTest_q <= fxpSinRes_uid64_fpSinPiTest_b;
WHEN "1" => multSecondOperand_uid66_fpSinPiTest_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => multSecondOperand_uid66_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor(LOGICAL,843)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q <= not (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a or ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b);
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena(REG,844)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd(LOGICAL,845)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b <= en;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a and ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b;
--cPi_uid52_fpSinPiTest(CONSTANT,51)
cPi_uid52_fpSinPiTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest(BITSELECT,242)@25
LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q(63 downto 0);
LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in(63 downto 0);
--leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest(BITJOIN,243)@25
leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b & GND_q;
--leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest(CONSTANT,215)
leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor(LOGICAL,982)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q <= not (ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a or ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b);
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena(REG,983)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q = "1") THEN
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd(LOGICAL,984)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b <= en;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a and ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b;
--X32dto0_uid214_alignedZ_uid51_fpSinPiTest(BITSELECT,213)@19
X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(32 downto 0);
X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b <= X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in(32 downto 0);
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg(DELAY,974)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b, xout => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem(DUALMEM,975)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia
);
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq(32 downto 0);
--zs_uid177_lzcZ_uid50_fpSinPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid50_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest(BITJOIN,214)@23
leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid50_fpSinPiTest_q;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor(LOGICAL,993)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q <= not (ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a or ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b);
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena(REG,994)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd(LOGICAL,995)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a and ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg(DELAY,985)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => z_uid48_fpSinPiTest_q, xout => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem(DUALMEM,986)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq(64 downto 0);
--zs_uid169_lzcZ_uid50_fpSinPiTest(CONSTANT,168)
zs_uid169_lzcZ_uid50_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid170_lzcZ_uid50_fpSinPiTest(BITSELECT,169)@19
rVStage_uid170_lzcZ_uid50_fpSinPiTest_in <= z_uid48_fpSinPiTest_q;
rVStage_uid170_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid170_lzcZ_uid50_fpSinPiTest_in(64 downto 1);
--vCount_uid171_lzcZ_uid50_fpSinPiTest(LOGICAL,170)@19
vCount_uid171_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid170_lzcZ_uid50_fpSinPiTest_b;
vCount_uid171_lzcZ_uid50_fpSinPiTest_b <= zs_uid169_lzcZ_uid50_fpSinPiTest_q;
vCount_uid171_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid171_lzcZ_uid50_fpSinPiTest_a = vCount_uid171_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g(DELAY,604)@20
ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid171_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid173_lzcZ_uid50_fpSinPiTest(BITSELECT,172)@19
vStage_uid173_lzcZ_uid50_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(0 downto 0);
vStage_uid173_lzcZ_uid50_fpSinPiTest_b <= vStage_uid173_lzcZ_uid50_fpSinPiTest_in(0 downto 0);
--ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b(DELAY,562)@19
ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid173_lzcZ_uid50_fpSinPiTest_b, xout => ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid172_lzcZ_uid50_fpSinPiTest(CONSTANT,171)
mO_uid172_lzcZ_uid50_fpSinPiTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid174_lzcZ_uid50_fpSinPiTest(BITJOIN,173)@20
cStage_uid174_lzcZ_uid50_fpSinPiTest_q <= ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q & mO_uid172_lzcZ_uid50_fpSinPiTest_q;
--ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c(DELAY,564)@19
ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid170_lzcZ_uid50_fpSinPiTest_b, xout => ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid176_lzcZ_uid50_fpSinPiTest(MUX,175)@20
vStagei_uid176_lzcZ_uid50_fpSinPiTest_s <= vCount_uid171_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid176_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid50_fpSinPiTest_s, en, ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q, cStage_uid174_lzcZ_uid50_fpSinPiTest_q)
BEGIN
CASE vStagei_uid176_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= cStage_uid174_lzcZ_uid50_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid178_lzcZ_uid50_fpSinPiTest(BITSELECT,177)@20
rVStage_uid178_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid178_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid50_fpSinPiTest_in(63 downto 32);
--vCount_uid179_lzcZ_uid50_fpSinPiTest(LOGICAL,178)@20
vCount_uid179_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid50_fpSinPiTest_b;
vCount_uid179_lzcZ_uid50_fpSinPiTest_b <= zs_uid177_lzcZ_uid50_fpSinPiTest_q;
vCount_uid179_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid50_fpSinPiTest_a = vCount_uid179_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f(DELAY,603)@21
ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid180_lzcZ_uid50_fpSinPiTest(BITSELECT,179)@20
vStage_uid180_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid50_fpSinPiTest_q(31 downto 0);
vStage_uid180_lzcZ_uid50_fpSinPiTest_b <= vStage_uid180_lzcZ_uid50_fpSinPiTest_in(31 downto 0);
--ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d(DELAY,571)@20
ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid180_lzcZ_uid50_fpSinPiTest_b, xout => ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c(DELAY,570)@20
ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid50_fpSinPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid182_lzcZ_uid50_fpSinPiTest(MUX,181)@21
vStagei_uid182_lzcZ_uid50_fpSinPiTest_s <= vCount_uid179_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid182_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid50_fpSinPiTest_s, en, ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q, ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q)
BEGIN
CASE vStagei_uid182_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q;
WHEN OTHERS => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid184_lzcZ_uid50_fpSinPiTest(BITSELECT,183)@21
rVStage_uid184_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid184_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_in(31 downto 16);
--vCount_uid185_lzcZ_uid50_fpSinPiTest(LOGICAL,184)@21
vCount_uid185_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_b;
vCount_uid185_lzcZ_uid50_fpSinPiTest_b <= zs_uid183_lzcZ_uid50_fpSinPiTest_q;
vCount_uid185_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid50_fpSinPiTest_a = vCount_uid185_lzcZ_uid50_fpSinPiTest_b else "0";
--ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a(DELAY,783)@21
ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid185_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4(REG,388)@22
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q <= ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid186_lzcZ_uid50_fpSinPiTest(BITSELECT,185)@21
vStage_uid186_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid50_fpSinPiTest_q(15 downto 0);
vStage_uid186_lzcZ_uid50_fpSinPiTest_b <= vStage_uid186_lzcZ_uid50_fpSinPiTest_in(15 downto 0);
--vStagei_uid188_lzcZ_uid50_fpSinPiTest(MUX,187)@21
vStagei_uid188_lzcZ_uid50_fpSinPiTest_s <= vCount_uid185_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid188_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid188_lzcZ_uid50_fpSinPiTest_s, en, rVStage_uid184_lzcZ_uid50_fpSinPiTest_b, vStage_uid186_lzcZ_uid50_fpSinPiTest_b)
BEGIN
CASE vStagei_uid188_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_b;
WHEN "1" => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= vStage_uid186_lzcZ_uid50_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid190_lzcZ_uid50_fpSinPiTest(BITSELECT,189)@21
rVStage_uid190_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid188_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid190_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid190_lzcZ_uid50_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1(REG,383)@21
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q <= rVStage_uid190_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid191_lzcZ_uid50_fpSinPiTest(LOGICAL,190)@22
vCount_uid191_lzcZ_uid50_fpSinPiTest_a <= reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q;
vCount_uid191_lzcZ_uid50_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
vCount_uid191_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid191_lzcZ_uid50_fpSinPiTest_a = vCount_uid191_lzcZ_uid50_fpSinPiTest_b else "0";
--ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d(DELAY,601)@22
ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid191_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid192_lzcZ_uid50_fpSinPiTest(BITSELECT,191)@21
vStage_uid192_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid188_lzcZ_uid50_fpSinPiTest_q(7 downto 0);
vStage_uid192_lzcZ_uid50_fpSinPiTest_b <= vStage_uid192_lzcZ_uid50_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3(REG,385)@21
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q <= vStage_uid192_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_lzcZ_uid50_fpSinPiTest(MUX,193)@22
vStagei_uid194_lzcZ_uid50_fpSinPiTest_s <= vCount_uid191_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid194_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid194_lzcZ_uid50_fpSinPiTest_s, en, reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q, reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid194_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_lzcZ_uid50_fpSinPiTest(BITSELECT,195)@22
rVStage_uid196_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid194_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid196_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_in(7 downto 4);
--vCount_uid197_lzcZ_uid50_fpSinPiTest(LOGICAL,196)@22
vCount_uid197_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_b;
vCount_uid197_lzcZ_uid50_fpSinPiTest_b <= leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
vCount_uid197_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid197_lzcZ_uid50_fpSinPiTest_a = vCount_uid197_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid198_lzcZ_uid50_fpSinPiTest(BITSELECT,197)@22
vStage_uid198_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid194_lzcZ_uid50_fpSinPiTest_q(3 downto 0);
vStage_uid198_lzcZ_uid50_fpSinPiTest_b <= vStage_uid198_lzcZ_uid50_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3(REG,387)@22
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q <= vStage_uid198_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2(REG,386)@22
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid200_lzcZ_uid50_fpSinPiTest(MUX,199)@23
vStagei_uid200_lzcZ_uid50_fpSinPiTest_s <= vCount_uid197_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid200_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid200_lzcZ_uid50_fpSinPiTest_s, en, reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q, reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid200_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid202_lzcZ_uid50_fpSinPiTest(BITSELECT,201)@23
rVStage_uid202_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid200_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid202_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_in(3 downto 2);
--vCount_uid203_lzcZ_uid50_fpSinPiTest(LOGICAL,202)@23
vCount_uid203_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_b;
vCount_uid203_lzcZ_uid50_fpSinPiTest_b <= leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
vCount_uid203_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid203_lzcZ_uid50_fpSinPiTest_a = vCount_uid203_lzcZ_uid50_fpSinPiTest_b else "0";
--vStage_uid204_lzcZ_uid50_fpSinPiTest(BITSELECT,203)@23
vStage_uid204_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid200_lzcZ_uid50_fpSinPiTest_q(1 downto 0);
vStage_uid204_lzcZ_uid50_fpSinPiTest_b <= vStage_uid204_lzcZ_uid50_fpSinPiTest_in(1 downto 0);
--vStagei_uid206_lzcZ_uid50_fpSinPiTest(MUX,205)@23
vStagei_uid206_lzcZ_uid50_fpSinPiTest_s <= vCount_uid203_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid206_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid206_lzcZ_uid50_fpSinPiTest_s, en, rVStage_uid202_lzcZ_uid50_fpSinPiTest_b, vStage_uid204_lzcZ_uid50_fpSinPiTest_b)
BEGIN
CASE vStagei_uid206_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_b;
WHEN "1" => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= vStage_uid204_lzcZ_uid50_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid208_lzcZ_uid50_fpSinPiTest(BITSELECT,207)@23
rVStage_uid208_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid206_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid208_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid208_lzcZ_uid50_fpSinPiTest_in(1 downto 1);
--vCount_uid209_lzcZ_uid50_fpSinPiTest(LOGICAL,208)@23
vCount_uid209_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid208_lzcZ_uid50_fpSinPiTest_b;
vCount_uid209_lzcZ_uid50_fpSinPiTest_b <= GND_q;
vCount_uid209_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid209_lzcZ_uid50_fpSinPiTest_a = vCount_uid209_lzcZ_uid50_fpSinPiTest_b else "0";
--r_uid210_lzcZ_uid50_fpSinPiTest(BITJOIN,209)@23
r_uid210_lzcZ_uid50_fpSinPiTest_q <= ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q & ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q & reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q & ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q & vCount_uid197_lzcZ_uid50_fpSinPiTest_q & vCount_uid203_lzcZ_uid50_fpSinPiTest_q & vCount_uid209_lzcZ_uid50_fpSinPiTest_q;
--leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest(BITSELECT,217)@23
leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q;
leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in(6 downto 5);
--leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest(MUX,218)@23
leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b;
leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s, en, ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q, leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q, leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest(BITSELECT,226)@23
LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(40 downto 0);
LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in(40 downto 0);
--leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest(BITJOIN,227)@23
leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q;
--reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5(REG,393)@23
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q <= leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest(BITSELECT,223)@23
LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(48 downto 0);
LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in(48 downto 0);
--leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest(BITJOIN,224)@23
leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b & zs_uid183_lzcZ_uid50_fpSinPiTest_q;
--reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4(REG,392)@23
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q <= leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest(BITSELECT,220)@23
LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in(56 downto 0);
--leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest(BITJOIN,221)@23
leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b & cstAllZWE_uid8_fpSinPiTest_q;
--reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3(REG,391)@23
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q <= leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2(REG,390)@23
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest(BITSELECT,228)@23
leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1(REG,389)@23
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest(MUX,229)@24
leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q;
leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s, en, reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q, reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q, reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q, reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q;
WHEN "10" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q;
WHEN "11" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest(BITSELECT,237)@24
LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b(DELAY,628)@24
ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest(BITJOIN,238)@25
leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q;
--LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest(BITSELECT,234)@24
LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b(DELAY,626)@24
ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest(BITJOIN,235)@25
leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest(BITSELECT,231)@24
LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(62 downto 0);
LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b(DELAY,624)@24
ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest(BITJOIN,232)@25
leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2(REG,395)@24
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest(BITSELECT,239)@23
leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a(DELAY,789)@23
ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b, xout => ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1(REG,394)@24
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q <= ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest(MUX,240)@25
leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s <= reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q;
leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s, en, reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q, leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q, leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q, leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest(BITSELECT,244)@23
leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b(DELAY,638)@23
ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest(MUX,245)@25
leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q;
leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s, en, leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q, leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s IS
WHEN "0" => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q;
WHEN "1" => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid53_fpSinPiTest(BITSELECT,52)@25
pHigh_uid53_fpSinPiTest_in <= leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q;
pHigh_uid53_fpSinPiTest_b <= pHigh_uid53_fpSinPiTest_in(64 downto 39);
--reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2(REG,397)@25
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q <= pHigh_uid53_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1(REG,396)@14
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q <= sinXIsXRR_uid35_fpSinPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b(DELAY,452)@15
ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q, xout => ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid54_fpSinPiTest(MUX,53)@26
p_uid54_fpSinPiTest_s <= ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q;
p_uid54_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid54_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid54_fpSinPiTest_s IS
WHEN "0" => p_uid54_fpSinPiTest_q <= reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q;
WHEN "1" => p_uid54_fpSinPiTest_q <= cPi_uid52_fpSinPiTest_q;
WHEN OTHERS => p_uid54_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg(DELAY,835)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid54_fpSinPiTest_q, xout => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem(DUALMEM,836)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq,
address_a => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa,
data_a => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia
);
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq(25 downto 0);
--mul2xSinRes_uid67_fpSinPiTest(MULT,66)@31
mul2xSinRes_uid67_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid67_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid67_fpSinPiTest_b);
mul2xSinRes_uid67_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid67_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid67_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid67_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid67_fpSinPiTest_a <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q;
mul2xSinRes_uid67_fpSinPiTest_b <= multSecondOperand_uid66_fpSinPiTest_q;
mul2xSinRes_uid67_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid67_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid67_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid67_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid67_fpSinPiTest_q <= mul2xSinRes_uid67_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid68_fpSinPiTest(BITSELECT,67)@34
normBit_uid68_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q;
normBit_uid68_fpSinPiTest_b <= normBit_uid68_fpSinPiTest_in(51 downto 51);
--join_uid73_fpSinPiTest(BITJOIN,72)@34
join_uid73_fpSinPiTest_q <= reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q & normBit_uid68_fpSinPiTest_b;
--cstAllZWF_uid7_fpSinPiTest(CONSTANT,6)
cstAllZWF_uid7_fpSinPiTest_q <= "00000000000000000000000";
--rndOp_uid74_uid75_fpSinPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpSinPiTest_q <= join_uid73_fpSinPiTest_q & cstAllZWF_uid7_fpSinPiTest_q & VCC_q;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor(LOGICAL,856)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q <= not (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a or ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b);
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top(CONSTANT,852)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q <= "0110";
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp(LOGICAL,853)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a = ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg(REG,854)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena(REG,857)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd(LOGICAL,858)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a and ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor(LOGICAL,819)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q <= not (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a or ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b);
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena(REG,820)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd(LOGICAL,821)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a and ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg(DELAY,809)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid32_fpSinPiTest_b, xout => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem(DUALMEM,810)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia
);
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--signExtExpXRR_uid57_fpSinPiTest(BITJOIN,56)@24
signExtExpXRR_uid57_fpSinPiTest_q <= GND_q & ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q;
--reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1(REG,407)@23
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q <= r_uid210_lzcZ_uid50_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid56_fpSinPiTest(SUB,55)@24
expHardCase_uid56_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid55_fpSinPiTest_q);
expHardCase_uid56_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q);
expHardCase_uid56_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid56_fpSinPiTest_a) - UNSIGNED(expHardCase_uid56_fpSinPiTest_b));
expHardCase_uid56_fpSinPiTest_q <= expHardCase_uid56_fpSinPiTest_o(8 downto 0);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a(DELAY,803)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 9 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1(REG,408)@23
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--expP_uid59_fpSinPiTest(MUX,58)@24
expP_uid59_fpSinPiTest_s <= reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q;
expP_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid59_fpSinPiTest_s IS
WHEN "0" => expP_uid59_fpSinPiTest_q <= expHardCase_uid56_fpSinPiTest_q;
WHEN "1" => expP_uid59_fpSinPiTest_q <= signExtExpXRR_uid57_fpSinPiTest_q;
WHEN OTHERS => expP_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg(DELAY,846)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expP_uid59_fpSinPiTest_q, xout => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt(COUNTER,848)
-- every=1, low=0, high=6, step=1, init=1
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i = 5 THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg(REG,849)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux(MUX,850)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem(DUALMEM,847)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 7,
width_b => 9,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq(8 downto 0);
--highRes_uid69_fpSinPiTest(BITSELECT,68)@34
highRes_uid69_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q(50 downto 0);
highRes_uid69_fpSinPiTest_b <= highRes_uid69_fpSinPiTest_in(50 downto 27);
--lowRes_uid70_fpSinPiTest(BITSELECT,69)@34
lowRes_uid70_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q(49 downto 0);
lowRes_uid70_fpSinPiTest_b <= lowRes_uid70_fpSinPiTest_in(49 downto 26);
--fracRCompPreRnd_uid71_fpSinPiTest(MUX,70)@34
fracRCompPreRnd_uid71_fpSinPiTest_s <= normBit_uid68_fpSinPiTest_b;
fracRCompPreRnd_uid71_fpSinPiTest: PROCESS (fracRCompPreRnd_uid71_fpSinPiTest_s, en, lowRes_uid70_fpSinPiTest_b, highRes_uid69_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid71_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid71_fpSinPiTest_q <= lowRes_uid70_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid71_fpSinPiTest_q <= highRes_uid69_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid71_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest(BITJOIN,71)@34
expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid71_fpSinPiTest_q;
--expRCompFracRComp_uid76_fpSinPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpSinPiTest_a <= STD_LOGIC_VECTOR((34 downto 33 => expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q(32)) & expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q);
expRCompFracRComp_uid76_fpSinPiTest_b <= STD_LOGIC_VECTOR('0' & "00000000" & rndOp_uid74_uid75_fpSinPiTest_q);
expRCompFracRComp_uid76_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expRCompFracRComp_uid76_fpSinPiTest_a) + SIGNED(expRCompFracRComp_uid76_fpSinPiTest_b));
expRCompFracRComp_uid76_fpSinPiTest_q <= expRCompFracRComp_uid76_fpSinPiTest_o(33 downto 0);
--expRCompE_uid78_fpSinPiTest(BITSELECT,77)@34
expRCompE_uid78_fpSinPiTest_in <= expRCompFracRComp_uid76_fpSinPiTest_q(32 downto 0);
expRCompE_uid78_fpSinPiTest_b <= expRCompE_uid78_fpSinPiTest_in(32 downto 24);
--expRComp_uid79_fpSinPiTest(BITSELECT,78)@34
expRComp_uid79_fpSinPiTest_in <= expRCompE_uid78_fpSinPiTest_b(7 downto 0);
expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(7 downto 0);
--reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2(REG,413)@34
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q <= expRComp_uid79_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c(DELAY,499)@35
ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q, xout => ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor(LOGICAL,908)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q <= not (ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a or ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b);
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top(CONSTANT,878)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q <= "0100000";
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp(LOGICAL,879)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q <= "1" when ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a = ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b else "0";
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg(REG,880)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena(REG,909)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q = "1") THEN
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd(LOGICAL,910)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b <= en;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a and ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b;
--frac_uid13_fpSinPiTest(BITSELECT,12)@0
frac_uid13_fpSinPiTest_in <= a(22 downto 0);
frac_uid13_fpSinPiTest_b <= frac_uid13_fpSinPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinPiTest_a <= frac_uid13_fpSinPiTest_b;
fracXIsZero_uid14_fpSinPiTest_b <= cstAllZWF_uid7_fpSinPiTest_q;
fracXIsZero_uid14_fpSinPiTest_q <= "1" when fracXIsZero_uid14_fpSinPiTest_a = fracXIsZero_uid14_fpSinPiTest_b else "0";
--expXIsMax_uid12_fpSinPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinPiTest_a <= exp_uid9_fpSinPiTest_b;
expXIsMax_uid12_fpSinPiTest_b <= cstAllOWE_uid6_fpSinPiTest_q;
expXIsMax_uid12_fpSinPiTest_q <= "1" when expXIsMax_uid12_fpSinPiTest_a = expXIsMax_uid12_fpSinPiTest_b else "0";
--exc_I_uid15_fpSinPiTest(LOGICAL,14)@0
exc_I_uid15_fpSinPiTest_a <= expXIsMax_uid12_fpSinPiTest_q;
exc_I_uid15_fpSinPiTest_b <= fracXIsZero_uid14_fpSinPiTest_q;
exc_I_uid15_fpSinPiTest_q <= exc_I_uid15_fpSinPiTest_a and exc_I_uid15_fpSinPiTest_b;
--InvFracXIsZero_uid16_fpSinPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinPiTest_a <= fracXIsZero_uid14_fpSinPiTest_q;
InvFracXIsZero_uid16_fpSinPiTest_q <= not InvFracXIsZero_uid16_fpSinPiTest_a;
--exc_N_uid17_fpSinPiTest(LOGICAL,16)@0
exc_N_uid17_fpSinPiTest_a <= expXIsMax_uid12_fpSinPiTest_q;
exc_N_uid17_fpSinPiTest_b <= InvFracXIsZero_uid16_fpSinPiTest_q;
exc_N_uid17_fpSinPiTest_q <= exc_N_uid17_fpSinPiTest_a and exc_N_uid17_fpSinPiTest_b;
--excRNaN_uid83_fpSinPiTest(LOGICAL,82)@0
excRNaN_uid83_fpSinPiTest_a <= exc_N_uid17_fpSinPiTest_q;
excRNaN_uid83_fpSinPiTest_b <= exc_I_uid15_fpSinPiTest_q;
excRNaN_uid83_fpSinPiTest_q <= excRNaN_uid83_fpSinPiTest_a or excRNaN_uid83_fpSinPiTest_b;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg(DELAY,898)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid83_fpSinPiTest_q, xout => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt(COUNTER,874)
-- every=1, low=0, high=32, step=1, init=1
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i = 31 THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i - 32;
ELSE
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i,6));
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg(REG,875)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux(MUX,876)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s, ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q, ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem(DUALMEM,899)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia
);
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq(0 downto 0);
--reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1(REG,410)@34
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q <= expRCompE_uid78_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--udf_uid80_fpSinPiTest(COMPARE,79)@35
udf_uid80_fpSinPiTest_cin <= GND_q;
udf_uid80_fpSinPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000" & GND_q) & '0';
udf_uid80_fpSinPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q(8)) & reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q) & udf_uid80_fpSinPiTest_cin(0);
udf_uid80_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(udf_uid80_fpSinPiTest_a) - SIGNED(udf_uid80_fpSinPiTest_b));
udf_uid80_fpSinPiTest_n(0) <= not udf_uid80_fpSinPiTest_o(11);
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor(LOGICAL,869)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q <= not (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a or ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b);
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top(CONSTANT,865)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q <= "011111";
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp(LOGICAL,866)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q);
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q <= "1" when ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a = ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b else "0";
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg(REG,867)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena(REG,870)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd(LOGICAL,871)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b <= en;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a and ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b;
--InvExc_N_uid18_fpSinPiTest(LOGICAL,17)@0
InvExc_N_uid18_fpSinPiTest_a <= exc_N_uid17_fpSinPiTest_q;
InvExc_N_uid18_fpSinPiTest_q <= not InvExc_N_uid18_fpSinPiTest_a;
--InvExc_I_uid19_fpSinPiTest(LOGICAL,18)@0
InvExc_I_uid19_fpSinPiTest_a <= exc_I_uid15_fpSinPiTest_q;
InvExc_I_uid19_fpSinPiTest_q <= not InvExc_I_uid19_fpSinPiTest_a;
--expXIsZero_uid10_fpSinPiTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinPiTest_a <= exp_uid9_fpSinPiTest_b;
expXIsZero_uid10_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
expXIsZero_uid10_fpSinPiTest_q <= "1" when expXIsZero_uid10_fpSinPiTest_a = expXIsZero_uid10_fpSinPiTest_b else "0";
--InvExpXIsZero_uid20_fpSinPiTest(LOGICAL,19)@0
InvExpXIsZero_uid20_fpSinPiTest_a <= expXIsZero_uid10_fpSinPiTest_q;
InvExpXIsZero_uid20_fpSinPiTest_q <= not InvExpXIsZero_uid20_fpSinPiTest_a;
--exc_R_uid21_fpSinPiTest(LOGICAL,20)@0
exc_R_uid21_fpSinPiTest_a <= InvExpXIsZero_uid20_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest_b <= InvExc_I_uid19_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest_c <= InvExc_N_uid18_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
exc_R_uid21_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
exc_R_uid21_fpSinPiTest_q <= exc_R_uid21_fpSinPiTest_a and exc_R_uid21_fpSinPiTest_b and exc_R_uid21_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg(DELAY,859)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid21_fpSinPiTest_q, xout => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt(COUNTER,861)
-- every=1, low=0, high=31, step=1, init=1
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i,5));
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg(REG,862)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux(MUX,863)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s <= en;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux: PROCESS (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s, ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q, ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem(DUALMEM,860)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq,
address_a => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa,
data_a => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia
);
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--xRegAndUdf_uid81_fpSinPiTest(LOGICAL,80)@35
xRegAndUdf_uid81_fpSinPiTest_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q;
xRegAndUdf_uid81_fpSinPiTest_b <= udf_uid80_fpSinPiTest_n;
xRegAndUdf_uid81_fpSinPiTest_q <= xRegAndUdf_uid81_fpSinPiTest_a and xRegAndUdf_uid81_fpSinPiTest_b;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor(LOGICAL,882)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q <= not (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a or ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b);
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena(REG,883)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd(LOGICAL,884)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a and ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg(DELAY,872)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid10_fpSinPiTest_q, xout => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem(DUALMEM,873)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--excRZero_uid82_fpSinPiTest(LOGICAL,81)@35
excRZero_uid82_fpSinPiTest_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q;
excRZero_uid82_fpSinPiTest_b <= xRegAndUdf_uid81_fpSinPiTest_q;
excRZero_uid82_fpSinPiTest_q <= excRZero_uid82_fpSinPiTest_a or excRZero_uid82_fpSinPiTest_b;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor(LOGICAL,895)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q <= not (ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a or ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b);
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena(REG,896)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q = "1") THEN
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd(LOGICAL,897)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b <= en;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a and ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg(DELAY,885)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_n, xout => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem(DUALMEM,886)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq,
address_a => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa,
data_a => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia
);
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid84_fpSinPiTest(BITJOIN,83)@35
excSelBits_uid84_fpSinPiTest_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q & excRZero_uid82_fpSinPiTest_q & ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q;
--reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0(REG,411)@35
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q <= excSelBits_uid84_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--excSel_uid85_fpSinPiTest(LOOKUP,84)@36
excSel_uid85_fpSinPiTest: PROCESS (reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q) IS
WHEN "000" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN "001" => excSel_uid85_fpSinPiTest_q <= "01";
WHEN "010" => excSel_uid85_fpSinPiTest_q <= "10";
WHEN "011" => excSel_uid85_fpSinPiTest_q <= "10";
WHEN "100" => excSel_uid85_fpSinPiTest_q <= "11";
WHEN "101" => excSel_uid85_fpSinPiTest_q <= "11";
WHEN "110" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN "111" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN OTHERS =>
excSel_uid85_fpSinPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid92_fpSinPiTest(MUX,91)@36
expRPostExc_uid92_fpSinPiTest_s <= excSel_uid85_fpSinPiTest_q;
expRPostExc_uid92_fpSinPiTest: PROCESS (expRPostExc_uid92_fpSinPiTest_s, en, ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q, ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q, cstAllZWE_uid8_fpSinPiTest_q, cstAllOWE_uid6_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid92_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid92_fpSinPiTest_q <= ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q;
WHEN "01" => expRPostExc_uid92_fpSinPiTest_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q;
WHEN "10" => expRPostExc_uid92_fpSinPiTest_q <= cstAllZWE_uid8_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid92_fpSinPiTest_q <= cstAllOWE_uid6_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid92_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracNaN_uid86_fpSinPiTest(CONSTANT,85)
fracNaN_uid86_fpSinPiTest_q <= "00000000000000000000001";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor(LOGICAL,921)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q <= not (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a or ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b);
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena(REG,922)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd(LOGICAL,923)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a and ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg(DELAY,911)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinPiTest_b, xout => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem(DUALMEM,912)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 34,
width_b => 23,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq(22 downto 0);
--fracRComp_uid77_fpSinPiTest(BITSELECT,76)@34
fracRComp_uid77_fpSinPiTest_in <= expRCompFracRComp_uid76_fpSinPiTest_q(23 downto 0);
fracRComp_uid77_fpSinPiTest_b <= fracRComp_uid77_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2(REG,412)@34
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q <= fracRComp_uid77_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c(DELAY,496)@35
ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q, xout => ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpSinPiTest(MUX,87)@36
fracRPostExc_uid88_fpSinPiTest_s <= excSel_uid85_fpSinPiTest_q;
fracRPostExc_uid88_fpSinPiTest: PROCESS (fracRPostExc_uid88_fpSinPiTest_s, en, ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q, cstAllZWF_uid7_fpSinPiTest_q, fracNaN_uid86_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpSinPiTest_s IS
WHEN "00" => fracRPostExc_uid88_fpSinPiTest_q <= ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q;
WHEN "01" => fracRPostExc_uid88_fpSinPiTest_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q;
WHEN "10" => fracRPostExc_uid88_fpSinPiTest_q <= cstAllZWF_uid7_fpSinPiTest_q;
WHEN "11" => fracRPostExc_uid88_fpSinPiTest_q <= fracNaN_uid86_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sinXR_uid97_fpSinPiTest(BITJOIN,96)@36
sinXR_uid97_fpSinPiTest_q <= ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q & expRPostExc_uid92_fpSinPiTest_q & fracRPostExc_uid88_fpSinPiTest_q;
--xOut(GPOUT,4)@36
q <= sinXR_uid97_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_divrnd.vhd | 10 | 5592 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVRND.VHD ***
--*** ***
--*** Function: Output Stage, Rounding ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 2 ***
--***************************************************
ENTITY hcc_divrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divrnd;
ARCHITECTURE rtl OF hcc_divrnd IS
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC;
signal overflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "00";
satinff <= '0';
zipinff <= '0';
naninff <= '0';
overflowbitff <= '0';
FOR k IN 1 TO 52 LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
satinff <= satin;
zipinff <= zipin;
naninff <= nanin;
overflowbitff <= manoverflow(53);
roundmantissaff <= mantissain(53 DOWNTO 2) + (zerovec & mantissain(1));
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(13 DOWNTO 1) <= exponentin(13 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(13 DOWNTO 1) +
(zerovec(12 DOWNTO 1) & overflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissain(1);
gmoa: FOR k IN 2 TO 53 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissain(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
-- 12/05/09 - make sure exponentnode = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentnode(12)) AND NOT(exponentnode(13))) OR
satinff OR (exponentnode(12) AND NOT(exponentnode(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipinff OR exponentnode(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= naninff;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR naninff;
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_clz36x6.vhd | 10 | 2148 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36X6.VHD ***
--*** ***
--*** Function: 6 bit Count Leading Zeros in a ***
--*** 36 bit number ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36x6 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36x6;
ARCHITECTURE rtl of fp_clz36x6 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerogroup : STD_LOGIC;
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(k) <= position(k) AND zerogroup;
END GENERATE;
leading <= positionmux;
END rtl;
| mit |
boztalay/OZ-3 | FPGA/OZ-3_System/Output_Extender_TB.vhd | 2 | 2582 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:49 06/12/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/Output_Extender_TB.vhd
-- Project Name: OZ-3_System
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Output_Port_MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Output_Extender_TB IS
END Output_Extender_TB;
ARCHITECTURE behavior OF Output_Extender_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Output_Port_MUX
PORT(
data : IN std_logic_vector(31 downto 0);
sel : IN std_logic_vector(1 downto 0);
output0 : OUT std_logic_vector(31 downto 0);
output1 : OUT std_logic_vector(31 downto 0);
output2 : OUT std_logic_vector(31 downto 0);
output3 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal data : std_logic_vector(31 downto 0) := (others => '0');
signal sel : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal output0 : std_logic_vector(31 downto 0);
signal output1 : std_logic_vector(31 downto 0);
signal output2 : std_logic_vector(31 downto 0);
signal output3 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Output_Port_MUX PORT MAP (
data => data,
sel => sel,
output0 => output0,
output1 => output1,
output2 => output2,
output3 => output3
);
-- Stimulus process
stim_proc: process
begin
sel(0) <= '1';
wait for 640 ns;
sel(1) <= '0';
wait for 1280 ns;
data <= x"00000006";
wait for 640 ns;
sel(0) <= '0';
wait;
end process;
END;
| mit |
LorhanSohaky/UFSCar | 2017/lab_cd/aula7/Verilog/simulation/modelsim/rtl_work/decodificador_@t@b/_primary.vhd | 1 | 92 | library verilog;
use verilog.vl_types.all;
entity decodificador_TB is
end decodificador_TB;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_invsqr_core.vhd | 10 | 8541 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** FP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 36 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_core IS
GENERIC (
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_core;
ARCHITECTURE rtl OF fp_invsqr_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(36 DOWNTO 18),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 12 LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 12 LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>36,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone,databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
invroot <= multonethr(36 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_cordic_m1_fused.vhd | 10 | 14306 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1_fused IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1_fused;
ARCHITECTURE rtl of fp_cordic_m1_fused IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_sin : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal multiplier_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode_cos : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sin_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal cos_ff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_sin : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate_cos : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input_sin(k) <= x_pipeff(cordic_depth)(k);
multiplier_input_cos(k) <= y_pipeff(cordic_depth)(k);
delay_input_sin(k) <= y_pipeff(cordic_depth)(k);
delay_input_cos(k) <= x_pipeff(cordic_depth)(k);
END GENERATE;
cmx1: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_sin,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_sin);
cmx2: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input_cos,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode_cos);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sin_ff(k) <= '0';
cos_ff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sin_ff <= delay_pipe_sin + post_estimate_sin;
cos_ff <= delay_pipe_cos + post_estimate_cos + 1;
END IF;
END IF;
END PROCESS;
pre_estimate_sin <= multipliernode_sin(2*width-2 DOWNTO width-1);
pre_estimate_cos <= multipliernode_cos(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(k+indexpoint) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate_sin(k) <= (pre_estimate_sin(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_sin(width) AND indexbitff(cordic_depth+3));
estimate_cos(k) <= (pre_estimate_cos(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate_cos(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate_sin(k) <= estimate_sin(k);
post_estimate_cos(k) <= NOT estimate_cos(k);
END GENERATE;
cda1: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_sin,
cc=>delay_pipe_sin);
cda2: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input_cos,
cc=>delay_pipe_cos);
sin_out <= sin_ff;
cos_out <= cos_ff;
END rtl;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_implementation.vhd | 10 | 516240 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27S_L2.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 mixed sign ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 2 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27S_L2 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27S_L2;
architecture rtl of hcc_MA2_27Ux27S_L2 is
constant PROD_WIDTH : positive := widthaa + widthbb + 1;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg : signed(widthaa+1 downto 1);
signal b0_reg, b1_reg : signed(widthbb downto 1);
signal p0_res, p1_res : signed(SUM2_WIDTH downto 1);
signal s1_reg : signed(SUM2_WIDTH downto 1);
begin
-- first DSP block
p0_res <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= SIGNED('0' & a0);
b0_reg <= SIGNED(b0);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= SIGNED('0' & a1);
b1_reg <= SIGNED(b1);
s1_reg <= p0_res + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27U_L2.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 unsigned ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 2 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27U_L2 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27U_L2;
architecture rtl of hcc_MA2_27Ux27U_L2 is
constant PROD_WIDTH : positive := widthaa + widthbb;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg : unsigned(widthaa downto 1);
signal b0_reg, b1_reg : unsigned(widthbb downto 1);
signal p0_res, p1_res : unsigned(SUM2_WIDTH downto 1);
signal s1_reg : unsigned(SUM2_WIDTH downto 1);
begin
-- first DSP block
p0_res <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= UNSIGNED(a0);
b0_reg <= UNSIGNED(b0);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= UNSIGNED(a1);
b1_reg <= UNSIGNED(b1);
s1_reg <= p0_res + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** HCC_MA2_27Ux27U_L3.VHD ***
--*** ***
--*** Function: Sum-of-2 27x27 unsigned ***
--*** ***
--*** 2012-04-05 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** Calculates a0*b0 + a1*b1 using 3 pipeline cycles.
--*** Designed for use with Variable Precision DSP block.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hcc_MA2_27Ux27U_L3 IS
GENERIC
(
widthaa : positive := 27;
widthbb : positive := 27;
widthcc : positive := 55
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk : IN STD_LOGIC := '1';
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1) := (OTHERS => '0');
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1) := (OTHERS => '0');
en : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
END hcc_MA2_27Ux27U_L3;
architecture rtl of hcc_MA2_27Ux27U_L3 is
constant PROD_WIDTH : positive := widthaa+widthbb;
constant SUM2_WIDTH : positive := PROD_WIDTH + 1;
signal a0_reg, a1_reg, a1_del_reg : unsigned(widthaa downto 1);
signal b0_reg, b1_reg, b1_del_reg : unsigned(widthbb downto 1);
signal p0_reg, p1_res : unsigned(SUM2_WIDTH downto 1);
signal s1_reg : unsigned(SUM2_WIDTH downto 1);
begin
-- external registers to match pipeline delay
process (clk, aclr)
begin
if (aclr = '1') then
a1_del_reg <= (others => '0');
b1_del_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (en = '1') then
a1_del_reg <= UNSIGNED(a1);
b1_del_reg <= UNSIGNED(b1);
end if;
end if;
end process;
-- first DSP block
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a0_reg <= (OTHERS => '0');
b0_reg <= (OTHERS => '0');
p0_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a0_reg <= UNSIGNED(a0);
b0_reg <= UNSIGNED(b0);
p0_reg <= RESIZE(a0_reg * b0_reg,SUM2_WIDTH);
end if;
END IF;
END PROCESS;
-- second DSP block
p1_res <= RESIZE(a1_reg * b1_reg,SUM2_WIDTH);
PROCESS (clk, aclr)
BEGIN
IF (aclr = '1') THEN
a1_reg <= (OTHERS => '0');
b1_reg <= (OTHERS => '0');
s1_reg <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
if (en = '1') then
a1_reg <= a1_del_reg;
b1_reg <= b1_del_reg;
s1_reg <= p0_reg + p1_res;
end if;
END IF;
END PROCESS;
result <= STD_LOGIC_VECTOR(RESIZE(s1_reg,widthcc));
end rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPEB.VHD ***
--*** ***
--*** Function: Behavioral Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipeb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipeb;
ARCHITECTURE rtl of hcc_addpipeb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
ccnode <= aa + bb + (zerovec & carryin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ADDPIPES.VHD ***
--*** ***
--*** Function: Synthesizable Pipelined Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_addpipes IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_addpipes;
ARCHITECTURE syn of hcc_addpipes IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-- same as v1 except 32 bit mantissa input Normalize to base level on output
ENTITY hcc_aludot_v2 IS
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_aludot_v2;
ARCHITECTURE rtl OF hcc_aludot_v2 IS
constant iopipe : integer := 0;
constant shiftspeed : integer := 0;
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal exponentnormff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal invertleftff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal invertrightff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normalizeff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (4+shiftspeed DOWNTO 1);
signal mantissaleft : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaright : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal mantissarightbus : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal alucarrybitnode, normalizecarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftmantissaleft, shiftmantissaright : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normalizenode : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal normshift : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO 32 LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aasign;
bbsignff <= bbsign;
aamantissaff <= aamantissa;
bbmantissaff <= bbmantissa;
aaexponentff <= aaexponent;
bbexponentff <= bbexponent;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (iopipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (iopipe = 0) GENERATE
aasignnode <= aasign;
bbsignnode <= bbsign;
aamantissanode <= aamantissa;
bbmantissanode <= bbmantissa;
aaexponentnode <= aaexponent;
bbexponentnode <= bbexponent;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
-- mantissa [27:1] will be "0001XXX" or "001XXX"
gen_shift_two: FOR k IN 1 TO 32 GENERATE
mantissaleft(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissaright(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
exponentnormff <= conv_std_logic_vector (0,10);
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO 32 LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
normalizeff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissaleftff <= mantissaleft;
mantissarightff <= mantissaright;
-- only use if shiftspeed = 1
--mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
exponentbaseff(2)(10 DOWNTO 1) <= exponentbaseff(1)(10 DOWNTO 1) - 129;
FOR k IN 3 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
exponentnormff <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1) + ("00000000" & normshift);
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
invertrightff(3+shiftspeed) <= invertrightff(2+shiftspeed);
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode;-- + alucarrybitnode;
normalizeff <= normalizenode;-- + normalizecarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 4+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO 32 GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
normalizecarrybitnode <= invertrightff(3+shiftspeed);
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
mantissarightbus <= mantissarightff;
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightbus,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightbus,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
-- maximum input mantissas are "001XXX" + "001XXX", maximum aluff is "01XXX"
-- or negative equivalent "100XXX"
-- need to shift to 0001XXXX
prc_norm: PROCESS (aluff)
BEGIN
CASE aluff(32 DOWNTO 29) IS
WHEN "0000" => normshift <= "00";
WHEN "0001" => normshift <= "01";
WHEN "0010" => normshift <= "10";
WHEN "0011" => normshift <= "10";
WHEN "0100" => normshift <= "11";
WHEN "0101" => normshift <= "11";
WHEN "0110" => normshift <= "11";
WHEN "0111" => normshift <= "11";
WHEN "1000" => normshift <= "11";
WHEN "1001" => normshift <= "11";
WHEN "1010" => normshift <= "11";
WHEN "1011" => normshift <= "11";
WHEN "1100" => normshift <= "10";
WHEN "1101" => normshift <= "10";
WHEN "1110" => normshift <= "01";
WHEN "1111" => normshift <= "00";
WHEN others => normshift <= "00";
END CASE;
END PROCESS;
gen_norm: FOR k IN 1 TO 29 GENERATE
normalizenode(k) <= (aluff(k) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(k+1) AND NOT(normshift(2)) AND normshift(1)) OR
(aluff(k+2) AND normshift(2) AND NOT(normshift(1))) OR
(aluff(k+3) AND normshift(2) AND normshift(1));
END GENERATE;
normalizenode(30) <= (aluff(30) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(31) AND NOT(normshift(2)) AND normshift(1)) OR
(aluff(32) AND normshift(2));
normalizenode(31) <= (aluff(31) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(aluff(32) AND (normshift(2) OR normshift(1)));
normalizenode(32) <= aluff(32);
--*** OUTPUT ***
cc <= normalizeff & exponentnormff;
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
ccnan <= ccnanff(4+shiftspeed);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1_DOT.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder (Signed Magnitude for first level ***
--*** Vector Optimized Structure) ***
--*** ***
--*** 15/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--*** TBD - what if exponents negative ***
ENTITY hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1_dot;
ARCHITECTURE rtl OF hcc_alufp1_dot IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO mantissa LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
bbsatff <= '0';
aazipff <= '0';
bbzipff <= '0';
aananff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aa(mantissa+10);
bbsignff <= bb(mantissa+10);
aamantissaff <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissaff <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentff <= aa(10 DOWNTO 1);
bbexponentff <= bb(10 DOWNTO 1);
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aasignnode <= aa(mantissa+10);
bbsignnode <= bb(mantissa+10);
aamantissanode <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissanode <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentnode <= aa(10 DOWNTO 1);
bbexponentnode <= bb(10 DOWNTO 1);
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissarightff(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** 04/05/10 - optimized structure ***
--*** 15/10/10 - bug in shiftcheckbit ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aanode, bbnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal addsubctlff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aanode <= aaff;
bbnode <= bbff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aanode <= aa;
bbnode <= bb;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3+shiftspeed LOOP
addsubctlff(k) <= addsub_resetval;
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addsubctlff(1) <= addsubnode;
FOR k IN 2 TO 2+shiftspeed LOOP
addsubctlff(k) <= addsubctlff(k-1);
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aanode(k+10) AND NOT(switch)) OR (bbnode(k+10) AND switch);
mantissarightff(k) <= (bbnode(k+10) AND NOT(switch)) OR (aanode(k+10) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aanode(k) AND NOT(switch)) OR (bbnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= addsubnode AND switch;
invertrightff(1) <= addsubnode AND NOT(switch);
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
alucarrybitnode <= addsubctlff(2+shiftspeed);
subexponentone <= aanode(10 DOWNTO 1) - bbnode(10 DOWNTO 1);
subexponenttwo <= bbnode(10 DOWNTO 1) - aanode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
-- 15/10/10 - was down to exponentshiftff(5) - zeroed any shift >= 16. Old design was ok because it
-- used shiftcheck subtract 31, not caught because unlikely to cause differences for small designs
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= addsub_resetval;
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR aasatff OR bbsatff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
ccnanff(k) <= ccnanff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
ccnan <= ccnanff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALULONG.VHD ***
--*** ***
--*** Function: fixed point adder (long) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alulong IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_alulong;
ARCHITECTURE rtl OF hcc_alulong IS
signal zerovec : STD_LOGIC_VECTOR (31 DOWNTO 1);
signal bbvec : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 31 GENERATE
zerovec(k) <= '0';
END GENERATE;
gaa: FOR k IN 1 TO 32 GENERATE
bbvec(k) <= bb(k) XOR addsub;
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aa + bbvec + (zerovec & addsub);
END IF;
END IF;
END PROCESS;
cc <= aluff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOF.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** IEEE Single Format ***
--*** ***
--*** 11/11/09 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 2 ***
--***************************************************
ENTITY hcc_castdtof IS
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtof;
ARCHITECTURE rtl OF hcc_castdtof IS
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal signnode : STD_LOGIC;
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentbiasnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaprenode, mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal upperrangecheck, lowerrangecheck : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal overrangenode, underrangenode : STD_LOGIC;
signal exponentmaxnode, zipnode, mantissanonzeronode : STD_LOGIC;
signal saturatenode, nannode, zeronode : STD_LOGIC;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 32 LOOP
ccff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
ccff <= signnode & exponentnode & mantissanode;
END IF;
END IF;
END PROCESS;
signnode <= aaff(64);
gmana: FOR k IN 1 TO 23 GENERATE
mantissanode(k) <= (mantissaprenode(k) OR nannode) AND NOT(zeronode) AND NOT(overrangenode);
END GENERATE;
gexpa: FOR k IN 1 TO 8 GENERATE
exponentnode(k) <= (exponentbiasnode(k) OR overrangenode OR nannode) AND NOT(zeronode);
END GENERATE;
-- if exponent = 2047 => saturate, if 0 => 0
exponentmaxnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
mantissanonzeronode <= aaff(52) OR aaff(51) OR aaff(50) OR aaff(49) OR
aaff(48) OR aaff(47) OR aaff(46) OR aaff(45) OR
aaff(44) OR aaff(43) OR aaff(42) OR aaff(41) OR
aaff(40) OR aaff(39) OR aaff(38) OR aaff(37) OR
aaff(36) OR aaff(35) OR aaff(34) OR aaff(33) OR
aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR
aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR
aaff(24) OR aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
upperrangecheck <= aaff(63 DOWNTO 53) - 1151; -- 1150 = 254, 1151 = 255
lowerrangecheck <= aaff(63 DOWNTO 53) - 897; -- 897 = 1, 896 = 0
overrangenode <= NOT(upperrangecheck(11)) AND NOT(lowerrangecheck(11)) AND NOT(nannode);
underrangenode <= lowerrangecheck(11);
saturatenode <= overrangenode AND NOT(mantissanonzeronode);
nannode <= exponentmaxnode AND mantissanonzeronode;
zeronode <= zipnode OR underrangenode;
exponentbiasnode <= aaff(63 DOWNTO 53) - 896;
gra: IF (roundconvert = 0) GENERATE
mantissaprenode <= aaff(52 DOWNTO 30);
END GENERATE;
grb: IF (roundconvert = 1) GENERATE
mantissaprenode <= aaff(52 DOWNTO 30) + aaff(29);
END GENERATE;
-- OUTPUTS
cc <= ccff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** if (swRoundConvert == 0 && ***
--*** swOutputPipe == 0) : ***
--*** 1 + swNormSpeed + 1 ***
--*** else ***
--*** 2 + swDoubleSpeed*swRoundConvert + ***
--*** swNormSpeed + 1 ***
--***************************************************
ENTITY hcc_castdtol IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtol;
ARCHITECTURE rtl OF hcc_castdtol IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,outputpipe=>1,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytol
GENERIC MAP (normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** if (swRoundConvert == 0 && ***
--*** swOutputPipe == 0) : 1 ***
--*** else ***
--*** 2 + swDoubleSpeed*swRoundConvert ***
--***************************************************
ENTITY hcc_castdtoy IS
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castdtoy;
ARCHITECTURE rtl OF hcc_castdtoy IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (53+11*target DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expmaxnode, zipnode, mannonzeronode : STD_LOGIC;
signal satnode, nannode : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentff : exponentfftype;
signal satdelff, zipdelff, nandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- ieee754: sign (64), 8 exponent (63:53), 52 mantissa (52:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(13:1)
-- multiplier, divider : (SIGN)('1')(52:1), exponent(13:1)
-- (multiplier & divider use unsigned numbers, sign packed with input)
gza: IF (roundconvert = 1) GENERATE
gzb: FOR k IN 1 TO 53+11*target GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
-- if exponent = 1023 => saturate, if 0 => 0
expmaxnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
mannonzeronode <= aaff(52) OR aaff(51) OR aaff(50) OR aaff(49) OR
aaff(48) OR aaff(47) OR aaff(46) OR aaff(45) OR
aaff(44) OR aaff(43) OR aaff(42) OR aaff(41) OR
aaff(40) OR aaff(39) OR aaff(38) OR aaff(37) OR
aaff(36) OR aaff(35) OR aaff(34) OR aaff(33) OR
aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR
aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR
aaff(24) OR aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
satnode <= expmaxnode AND NOT(mannonzeronode);
nannode <= expmaxnode AND mannonzeronode;
gexpa: FOR k IN 1 TO 11 GENERATE
expnode(k) <= (aaff(k+52) OR expmaxnode) AND NOT(zipnode);
END GENERATE;
expnode(12) <= '0';
expnode(13) <= '0';
--**************************************
--*** direct to multipier or divider ***
--**************************************
gmda: IF (target = 0) GENERATE
-- already in "01"&mantissa format used by multiplier and divider
fracnode <= aaff(64) & '1' & aaff(52 DOWNTO 1);
gmdb: IF (outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
gmdc: IF (outputpipe = 1) GENERATE
pmda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 67 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fracnode & expnode;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
END GENERATE;
--***********************
--*** internal format ***
--***********************
gxa: IF (target = 1) GENERATE
fracnode(64) <= aaff(64);
fracnode(63) <= aaff(64);
fracnode(62) <= aaff(64);
fracnode(61) <= aaff(64);
fracnode(60) <= aaff(64);
fracnode(59) <= NOT(aaff(64)); -- '1' XOR sign
gfa: FOR k IN 1 TO 52 GENERATE
fracnode(k+6)<= (aaff(k) XOR aaff(64));
END GENERATE;
gfb: FOR k IN 1 TO 6 GENERATE
fracnode(k)<= aaff(64); -- '0' XOR sign
END GENERATE;
--*** OUTPUT STAGE(S) ***
gsa: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
gsb: IF (outputpipe = 1 AND
((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0))) GENERATE
gsc: IF (roundconvert = 0) GENERATE
mantissanode <= fracnode;
END GENERATE;
gsd: IF (roundconvert = 1) GENERATE
mantissanode <= fracnode + (zerovec(63 DOWNTO 1) & aaff(64));
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= mantissanode & expnode;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
gse: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsf: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
prcb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
END LOOP;
satdelff <= "00";
zipdelff <= "00";
nandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentff(1)(13 DOWNTO 1) <= expnode;
exponentff(2)(13 DOWNTO 1) <= exponentff(1)(13 DOWNTO 1);
satdelff(1) <= satnode;
satdelff(2) <= satdelff(1);
zipdelff(1) <= zipnode;
zipdelff(2) <= zipdelff(1);
nandelff(1) <= nannode;
nandelff(2) <= nandelff(1);
END IF;
END IF;
END PROCESS;
cc <= mantissanode & exponentff(2)(13 DOWNTO 1);
ccsat <= satdelff(2);
cczip <= zipdelff(2);
ccnan <= nandelff(2);
END GENERATE;
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOD.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** IEEE Double Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 2 ***
--***************************************************
ENTITY hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castftod;
ARCHITECTURE rtl OF hcc_castftod IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal signnode : STD_LOGIC;
signal exponentnode, exponentbiasnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal tailnode : STD_LOGIC_VECTOR (29 DOWNTO 1);
signal exponentmaxnode, zipnode, mantissanonzeronode : STD_LOGIC;
signal saturatenode, nannode : STD_LOGIC;
BEGIN
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
-- FOR k IN 1 TO 32 LOOP
-- aaff(k) <= '0';
-- END LOOP;
FOR k IN 1 TO 64 LOOP
ccff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= signnode & exponentnode & mantissanode;
END IF;
END IF;
END PROCESS;
aaff <= aa;
signnode <= aaff(32);
mantissanode <= aaff(23 DOWNTO 1) & "00000000000000000000000000000";
gexpa: FOR k IN 1 TO 11 GENERATE
exponentnode(k) <= (exponentbiasnode(k) OR exponentmaxnode) AND NOT(zipnode);
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
exponentmaxnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
-- mantissanonzeronode <= aaff(23) OR aaff(22) OR aaff(21) OR
-- aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
-- aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
-- aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
-- aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
-- aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
saturatenode <= exponentmaxnode AND NOT(mantissanonzeronode);
nannode <= exponentmaxnode AND mantissanonzeronode;
-- gta: FOR k IN 1 TO 29 GENERATE
-- tailnode(k) <= nannode;
-- END GENERATE;
exponentbiasnode <= ("000" & aaff(31 DOWNTO 24)) + 896;
-- OUTPUTS
cc <= ccff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 3 + swSingleNormSpeed ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - divider mantissa aa to aaff ***
--*** 16/04/09 - add NAN support ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 1 + swOutputPipe (target = 0,1) ***
--*** 1 (target = 2) ***
--***************************************************
ENTITY hcc_castftox IS
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castftox;
ARCHITECTURE rtl OF hcc_castftox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmaxnode, mannonzeronode : STD_LOGIC;
signal satnode, zipnode, nannode : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC;
BEGIN
-- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1)
-- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1)
-- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x)
gza: IF (roundconvert = 1) GENERATE
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gro: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
nanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fractional & exponent;
satff <= satnode;
zipff <= zipnode;
nanff <= nannode;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
expmaxnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
mannonzeronode <= aaff(23) OR aaff(22) OR aaff(21) OR
aaff(20) OR aaff(19) OR aaff(18) OR aaff(17) OR
aaff(16) OR aaff(15) OR aaff(14) OR aaff(13) OR
aaff(12) OR aaff(11) OR aaff(10) OR aaff(9) OR
aaff(8) OR aaff(7) OR aaff(6) OR aaff(5) OR
aaff(4) OR aaff(3) OR aaff(2) OR aaff(1);
satnode <= expmaxnode AND NOT(mannonzeronode);
nannode <= expmaxnode AND mannonzeronode;
gexpa: FOR k IN 1 TO 8 GENERATE
expnode(k) <= (aaff(k+23) OR expmaxnode) AND NOT(zipnode);
END GENERATE;
expnode(9) <= '0';
expnode(10) <= '0';
--*** internal format ***
gxa: IF (target = 0) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= aaff(32);
fracnode(mantissa-2) <= aaff(32);
fracnode(mantissa-3) <= aaff(32);
fracnode(mantissa-4) <= aaff(32);
fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign
gxb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gxc: FOR k IN 1 TO mantissa-29 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gxd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gxe: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
exponent <= expnode;
END GENERATE;
--*** direct to multiplier ***
gma: IF (target = 1) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign
gmb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gmc: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gmd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gme: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
-- never register output
--*** direct to divider ***
gda: IF (target = 2) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= '1';
fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1);
gfb: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= '0';
END GENERATE;
fractional <= fracnode;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
--*** OUTPUTS ***
goa: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
ccnan <= nanff;
END GENERATE;
gob: IF ((target = 0 AND outputpipe = 0) OR
(target = 1 AND outputpipe = 0) OR
(target = 2)) GENERATE
cc <= fractional & exponent;
ccsat <= satnode;
cczip <= zipnode;
ccnan <= nannode;
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- castftoy : float <=> internal double
ENTITY hcc_castftoy IS
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castftoy;
ARCHITECTURE rtl OF hcc_castftoy IS
signal floatnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
-- if ftoy target divider or multiplier, need unsigned output
-- if ftoy target = 1 (internal), ftox target = 0, xtoy target = 1
-- if ftoy target = 0 (multiplier, divider), ftox target = 2 (divider), xtoy target = 0 (mult&div)
gaa: IF (target = 1) GENERATE
one: hcc_castftox
GENERIC MAP(target=>0,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtoy
GENERIC MAP(target=>1,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END GENERATE;
gab: IF (target = 0) GENERATE
one: hcc_castftox
GENERIC MAP(target=>2,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtoy
GENERIC MAP(target=>0,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc,ccsat=>ccsat,cczip=>cczip,ccnan=>ccnan);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOD.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + ***
--*** swRoundConvert*(1 + swDoubleSpeed); ***
--***************************************************
ENTITY hcc_castltod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castltod;
ARCHITECTURE rtl OF hcc_castltod IS
signal fit : STD_LOGIC;
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
yvector(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
yvector(77 DOWNTO 73) <= "00000";
END GENERATE;
yvector(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
yvector(k) <= '0';
END GENERATE;
yvector(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
core: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOX.VHD ***
--*** ***
--*** Function: Cast Long to Internal Single ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltox IS
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castltox;
ARCHITECTURE rtl OF hcc_castltox IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aaff(32) & aaff(32) & aaff(32) & aaff(32) & aaff(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR aaff(28)) OR
(aaff(32) AND aaff(31) AND aaff(30) AND aaff(29) AND aaff(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aaff(32) OR aaff(31) OR aaff(30) OR aaff(29) OR aaff(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
cc(k+10) <= (aaff(k) AND fit) OR (aaff(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aaff(32) OR aaff(31)) OR
(aaff(32) AND aaff(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aaff(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
cc(k+10) <= (aaff(k) AND fit) OR (aaff(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOY.VHD ***
--*** ***
--*** Function: Cast Long to Internal Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltoy IS
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castltoy;
ARCHITECTURE rtl OF hcc_castltoy IS
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gxa: IF (unsigned = 0) GENERATE
cc(77 DOWNTO 73) <= aaff(32) & aaff(32) & aaff(32) & aaff(32) & aaff(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(77 DOWNTO 73) <= "00000";
END GENERATE;
cc(72 DOWNTO 41) <= aaff;
gza: FOR k IN 14 TO 40 GENERATE
cc(k) <= '0';
END GENERATE;
cc(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
ccsat <= '0';
cczip <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip, yvectornan : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,aanan=>aanan,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip,ccnan=>yvectornan);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,aanan=>yvectornan,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOF.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support, also fixed zero/infinity/nan mantissa ***
--*** 29/04/09 - zero output if mantissa in zero ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--******************************************************************************
ENTITY hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtof;
ARCHITECTURE rtl OF hcc_castxtof IS
-- latency = 5 if normspeed = 1
-- latency = 7 if normspeed = 2 (extra pipe in normusgn3236 and output stage)
type exptopfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type expbotfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal count : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal absnode, absroundnode, absff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : expbotfftype;
signal roundoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC_VECTOR (3+normspeed DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2+2*normspeed DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal preexpnode, expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal mantissaroundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode, maxmantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal zeromantissaff, maxmantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
signal ccsgn : STD_LOGIC;
signal aaexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (23 DOWNTO 1);
component hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
absff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
roundoverflowff <= '0';
FOR k IN 1 TO 3+normspeed LOOP
satff(k) <= '0';
zipff(k) <= '0';
nanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2+2*normspeed LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 1+normspeed LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
absff <= absnode + absroundnode;
fracoutff <= fracout;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
-- add 4 because of maximum 4 bits wordgrowth in X mantissa
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) + "0000000100";
exptopff(3)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1) - ("0000" & count);
roundoverflowff <= roundoverflow(24);
satff(1) <= aasat;
FOR k IN 2 TO 3+normspeed LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO 3+normspeed LOOP
zipff(k) <= zipff(k-1);
END LOOP;
nanff(1) <= aanan;
FOR k IN 2 TO 3+normspeed LOOP
nanff(k) <= nanff(k-1);
END LOOP;
signff(1) <= aaff(mantissa+10);
FOR k IN 2 TO 2+2*normspeed LOOP
signff(k) <= signff(k-1);
END LOOP;
zeronumberff(1) <= NOT(zeronumber(mantissa));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsa: IF (normspeed = 1) GENERATE
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissanode(k) AND NOT(zeromantissanode)) OR maxmantissanode;
END LOOP;
END IF;
END IF;
END PROCESS;
preexpnode <= exptopff(3)(10 DOWNTO 1);
END GENERATE;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsb: IF (normspeed = 2) GENERATE
pnb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
expbotff(1)(10 DOWNTO 1) <= "0000000000";
expbotff(2)(10 DOWNTO 1) <= "0000000000";
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaroundff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(1)(10 DOWNTO 1) <= exptopff(3)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expnode;
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expbotff(2)(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
mantissaroundff <= mantissanode;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissaroundff(k) AND NOT(zeromantissaff)) OR maxmantissaff;
END LOOP;
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END IF;
END PROCESS;
preexpnode <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
-- round absolute value any way - need register on input of cntusgn
gaa: FOR k IN 1 TO mantissa GENERATE
absnode(k) <= aaff(k+10) XOR aaff(mantissa+10);
END GENERATE;
absroundnode <= zerovec(mantissa-1 DOWNTO 1) & aaff(mantissa+10);
zeronumber(1) <= absff(1);
gzma: FOR k IN 2 TO mantissa GENERATE
zeronumber(k) <= zeronumber(k-1) OR absff(k);
END GENERATE;
core: hcc_normusgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absff(mantissa DOWNTO 1),countout=>count,
fracout=>fracout);
roundoverflow(1) <= fracout(7);
gna: FOR k IN 2 TO 24 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+6);
END GENERATE;
expnode <= preexpnode(10 DOWNTO 1) + ("000000000" & roundoverflowff);
-- always round single output (round to nearest even)
roundbit <= (fracoutff(mantissa-24) AND fracoutff(mantissa-25)) OR
(NOT(fracoutff(mantissa-24)) AND fracoutff(mantissa-25) AND
(fracoutff(mantissa-26) OR fracoutff(mantissa-27) OR fracoutff(mantissa-28)));
mantissanode <= fracoutff(mantissa-2 DOWNTO mantissa-24) +
(zerovec(22 DOWNTO 1) & roundbit);
--ML March 8, 2011 consider expnode(10 DOWNTO 9) for zeroexpnode and maxexpnode calculation
zeroexpnode <= NOT(expnode(10) OR
expnode(9) OR expnode(8) OR expnode(7) OR
expnode(6) OR expnode(5) OR expnode(4) OR
expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(10)) AND NOT(expnode(9)) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- all following '1' when true
-- 24/03/09 - zeroexpnode, maxexpnode also zeros mantissa (SRC bug)
zeromantissanode <= roundoverflowff OR zeroexpnode OR maxexpnode OR
expnode(9) OR expnode(10) OR
zipff(3+normspeed) OR satff(3+normspeed) OR
zeronumberff(1+normspeed);
maxmantissanode <= nanff(3+normspeed);
zeroexponentnode <= zeroexpnode OR expnode(10) OR
zipff(3+normspeed) OR zeronumberff(1+normspeed);
maxexponentnode <= maxexpnode OR (expnode(9) AND NOT(expnode(10))) OR
satff(3+normspeed) OR nanff(3+normspeed);
--*** OUTPUTS ***
cc(32) <= signff(2+2*normspeed);
cc(31 DOWNTO 24) <= exponentff;
cc(23 DOWNTO 1) <= mantissaff(23 DOWNTO 1);
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccsgn <= signff(2+2*normspeed);
ccexp <= exponentff;
ccman <= mantissaff(23 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOL.VHD ***
--*** ***
--*** Function: Cast Internal Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: ***
--*** 1 + swSingleNormSpeed ***
--***************************************************
ENTITY hcc_castxtol IS
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtol;
ARCHITECTURE rtl OF hcc_castxtol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout, nanout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
leftshiftnum <= aa(10 DOWNTO 1) - "0010011010"; -- 154 is 1.0 point
rightshiftnum <= "0010011010" - aa(10 DOWNTO 1);
leftshiftmax <= aa(10 DOWNTO 1) - "0010111010"; -- 186 is the max - if +ve, saturate
rightshiftmin <= aa(10 DOWNTO 1) - "0001111010"; -- 122 is the min - if -ve, zero
selectleftbit <= rightshiftnum(10);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(10));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(10);
gmab: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb32
PORT MAP (inbus=>aa(42 DOWNTO 11),shift=>leftshiftnum(5 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb32
PORT MAP (inbus=>aa(42 DOWNTO 11),shift=>rightshiftnum(5 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gmac: IF (normspeed = 2) GENERATE
sftlp: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(42 DOWNTO 11),shift=>leftshiftnum(5 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(42 DOWNTO 11),shift=>rightshiftnum(5 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbnan: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanan,cc=>nanout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus;
rightshiftbusff <= rightshiftbus;
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout OR nanout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOY.VHD ***
--*** ***
--*** Function: Cast Internal Single to ***
--*** Internal Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN port ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castxtoy;
ARCHITECTURE rtl OF hcc_castxtoy IS
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
BEGIN
-- x : 32/36 signed mantissa, 10 bit exponent
-- y : (internal) 64 signed mantissa, 13 bit exponent
exponentadjust <= conv_std_logic_vector (896,13);
cc(67+10*target DOWNTO 68+10*target-mantissa) <= aa(mantissa+10 DOWNTO 11);
gxa: FOR k IN 14 TO 67+10*target-mantissa GENERATE
cc(k) <= aa(11);
END GENERATE;
cc(13 DOWNTO 1) <= ("000" & aa(10 DOWNTO 1)) + exponentadjust;
ccsat <= aasat;
cczip <= aazip;
ccnan <= aanan;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support, also fixed zero/infinity/nan mantissa ***
--*** 29/04/09 - zero output if mantissa in zero ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swRoundConvert*swDoubleSpeed + ***
--*** swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff, nanff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode, maxmantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff, maxmantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff, maxmantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
nanff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
nanff(1) <= aanan;
FOR k IN 2 TO satffdepth LOOP
nanff(k) <= nanff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- zero mantissa if when 0 or infinity result
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
maxmantissanode <= nanff(satffdepth);
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 12/05/09 - make sure than exp = -1 doesn't trigger max node
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth) OR nanff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (fracoutff(k+10) AND NOT(zeromantissanode)) OR maxmantissanode;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissaroundff(k) OR maxmantissaff) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) OR maxexponentff) AND NOT(zeroexponentff);
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
maxmantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissaroundnode(k) AND NOT(zeromantissadelff)) OR maxmantissadelff;
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
maxmantissadelff <= maxmantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode, nannode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,aanan=>aanan,
cc=>midnode,
ccsat=>satnode,cczip=>zipnode,ccnan=>nannode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,aanan=>nannode,
cc=>cc);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOL.VHD ***
--*** ***
--*** Function: Cast Internal Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Latency: normspeed+1 ***
--***************************************************
ENTITY hcc_castytol IS
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytol;
ARCHITECTURE rtl OF hcc_castytol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout, nanout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_lsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
midpoint <= conv_std_logic_vector (1054,13);
maxpoint <= conv_std_logic_vector (1118,13);
minpoint <= conv_std_logic_vector (1022,13);
leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point
rightshiftnum <= midpoint - aa(13 DOWNTO 1);
-- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre
leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate
rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero
selectleftbit <= rightshiftnum(13);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(13));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13);
gsa: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gsb: IF (normspeed > 1) GENERATE
sftlp: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbnan: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanan,cc=>nanout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus(64 DOWNTO 33);
rightshiftbusff <= rightshiftbus(64 DOWNTO 33);
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout OR nanout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOX.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** Internal Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** support ***
--*** 24/08/10 - fixed multiple bugs ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : OPERATIONS ***
--***************************************************
-- input always signed y format (mult, divide, have output option
ENTITY hcc_castytox IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_castytox;
ARCHITECTURE rtl OF hcc_castytox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal overflowcheck : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal exponentmaximum, exponentminimum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal chkexpsat, chkexpzip : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expsatbit, expzipbit : STD_LOGIC;
signal exponentnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC;
signal satoutff, zipoutff, nanoutff : STD_LOGIC;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
exponentmaximum <= conv_std_logic_vector (1151,13); -- 1151 = 1023+128 = 255
exponentminimum <= conv_std_logic_vector (897,13); -- 897 = 1023-126 = 1
exponentadjust <= conv_std_logic_vector (896,13); -- 896 = 1023-127
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satinff <= '0';
zipinff <= '0';
naninff <= '0';
satoutff <= '0';
zipoutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
ccff <= fractional & exponent;
satinff <= aasat;
zipinff <= aazip;
naninff <= aanan;
satoutff <= satinff OR expsatbit;
zipoutff <= zipinff OR expzipbit;
nanoutff <= naninff;
END IF;
END IF;
END PROCESS;
chkexpsat <= aaff(13 DOWNTO 1) - exponentmaximum; -- ok when -ve
chkexpzip <= aaff(13 DOWNTO 1) - exponentminimum; -- ok when +ve
expsatbit <= NOT(chkexpsat(13)) OR (NOT(aaff(13)) AND aaff(12));
expzipbit <= chkexpzip(13) OR aaff(13);
exponentnode <= aaff(13 DOWNTO 1) - exponentadjust;
gxa: FOR k IN 1 TO 8 GENERATE
exponent(k) <= (exponentnode(k) OR expsatbit) AND NOT(expzipbit);
END GENERATE;
exponent(10 DOWNTO 9) <= "00";
fracnode <= aaff(77 DOWNTO 78-mantissa);
gma: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gmb: IF (roundconvert = 1) GENERATE
-- issue is when max positive turned into negative number (01111XXX to 10000XXX)
-- min negative (11111) to min positive (00000) no issue
-- but this code zeros round bit if fracnode is "X1111...111"
overflowcheck(1) <= aaff(78-mantissa);
gmc: FOR k IN 2 TO mantissa-1 GENERATE
overflowcheck(k) <= overflowcheck(k-1) AND aaff(77-mantissa+k);
END GENERATE;
roundbit <= NOT(overflowcheck(mantissa-1)) AND aaff(77-mantissa);
fractional <= fracnode + (zerovec(mantissa-1 DOWNTO 1) & roundbit);
END GENERATE;
cc <= ccff;
ccsat <= satoutff;
cczip <= zipoutff;
ccnan <= nanoutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn32;
ARCHITECTURE rtl OF hcc_cntsgn32 IS
type positiontype IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(2) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(4) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(5) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(6) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(7) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(8) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(2) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(3) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(4) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(5) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(6) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(7) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(8) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 8 GENERATE
sec(k) <= (possec(k) AND NOT(frac(32))) OR (NOT(negsec(k)) AND frac(32));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(31 DOWNTO 28),
position=>position(1)(5 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(27 DOWNTO 24),
position=>position(2)(5 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(23 DOWNTO 20),
position=>position(3)(5 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(19 DOWNTO 16),
position=>position(4)(5 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(15 DOWNTO 12),
position=>position(5)(5 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(11 DOWNTO 8),
position=>position(6)(5 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(7 DOWNTO 4),
position=>position(7)(5 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>5)
PORT MAP (signbit=>frac(32),inbus=>lastfrac,
position=>position(8)(5 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(32);
gmc: FOR k IN 1 TO 5 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8));
END GENERATE;
count(6) <= '0';
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn36;
ARCHITECTURE rtl OF hcc_cntsgn36 IS
type positiontype IS ARRAY (9 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32);
possec(2) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(3) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(4) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(5) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(6) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(7) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(8) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(9) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(35) AND frac(34) AND frac(33) AND frac(32);
negsec(2) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(3) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(4) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(5) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(6) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(7) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(8) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(9) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 9 GENERATE
sec(k) <= (possec(k) AND NOT(frac(36))) OR (NOT(negsec(k)) AND frac(36));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(9) <= sec(9) AND NOT(sec(8)) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND
NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(35 DOWNTO 32),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(31 DOWNTO 28),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(27 DOWNTO 24),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(23 DOWNTO 20),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(19 DOWNTO 16),
position=>position(5)(6 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(15 DOWNTO 12),
position=>position(6)(6 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(11 DOWNTO 8),
position=>position(7)(6 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(7 DOWNTO 4),
position=>position(8)(6 DOWNTO 1));
pnin: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>lastfrac,
position=>position(9)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(36);
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8)) OR
(position(9)(k) AND sel(9));
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSCOMB64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuscomb64 IS
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuscomb64;
ARCHITECTURE rtl of hcc_cntuscomb64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn36;
ARCHITECTURE rtl OF hcc_cntusgn36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32) OR frac(31) OR frac(30);
sec(2) <= frac(29) OR frac(28) OR frac(27) OR frac(26) OR frac(25) OR frac(24);
sec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20) OR frac(19) OR frac(18);
sec(4) <= frac(17) OR frac(16) OR frac(15) OR frac(14) OR frac(13) OR frac(12);
sec(5) <= frac(11) OR frac(10) OR frac(9) OR frac(8) OR frac(7) OR frac(6);
sec(6) <= frac(5) OR frac(4) OR frac(3) OR frac(2) OR frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(35 DOWNTO 30),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(29 DOWNTO 24),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(23 DOWNTO 18),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(17 DOWNTO 12),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(11 DOWNTO 6),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(5 DOWNTO 1) & '0';
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSPIPE64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuspipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuspipe64;
ARCHITECTURE rtl of hcc_cntuspipe64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroup, firstzeroff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
firstzeroff(1) <= zerogroup(1);
firstzeroff(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzeroff(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzeroff(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzeroff(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzeroff(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzeroff(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzeroff(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzeroff(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzeroff(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzeroff(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzeroff(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzeroff(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAYBIT.VHD ***
--*** ***
--*** Function: Delay a single bit an ***
--*** arbitrary number of stages ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
END hcc_delaybit;
ARCHITECTURE rtl OF hcc_delaybit IS
signal delff : STD_LOGIC_VECTOR (delay DOWNTO 1);
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
delff(1) <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
END IF;
END IF;
END PROCESS;
cc <= delff(1);
END GENERATE;
gdb: IF (delay > 1) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO delay LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
FOR k IN 2 TO delay LOOP
delff(k) <= delff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(delay);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELMEM.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** Note: this code megawizard generated ***
--*** ***
--*** 12/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delmem IS
GENERIC (
width : positive := 79;
delay : positive := 7
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delmem;
ARCHITECTURE SYN OF hcc_delmem IS
signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1);
COMPONENT altshift_taps
GENERIC (
lpm_hint : STRING;
lpm_type : STRING;
number_of_taps : NATURAL;
tap_distance : NATURAL;
width : NATURAL
);
PORT (
taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clken : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
delcore: altshift_taps
GENERIC MAP (
lpm_hint => "RAM_BLOCK_TYPE=M512",
lpm_type => "altshift_taps",
number_of_taps => 1,
tap_distance => delay,
width => width
)
PORT MAP (
clock => sysclk,
clken => enable,
shiftin => aa,
taps => dummy,
shiftout => cc
);
END SYN;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftcomb32;
ARCHITECTURE rtl OF hcc_lsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 64 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_lsftcomb64;
ARCHITECTURE rtl OF hcc_lsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
gcd: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE36.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftpipe36;
ARCHITECTURE rtl OF hcc_lsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE64.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 64 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_lsftpipe64;
ARCHITECTURE rtl OF hcc_lsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
gcd: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 2 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL2727S.VHD ***
--*** ***
--*** Function: 2 pipeline stage signed 27 bit ***
--*** SV(behavioral/synthesizable) ***
--*** ***
--*** 30/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul2727s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul2727s;
ARCHITECTURE rtl OF hcc_mul2727s IS
attribute preserve : boolean;
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
attribute preserve of aaff : signal is true;
attribute preserve of bbff : signal is true;
signal multiplyff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
multiplyff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
multiplyff <= aaff * bbff;
END IF;
END IF;
END PROCESS;
cc <= multiplyff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236B.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236b IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236b;
ARCHITECTURE rtl OF hcc_mul3236b IS
attribute preserve : boolean;
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
attribute preserve of aaff : signal is true;
attribute preserve of bbff : signal is true;
signal mulff, muloutff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
mulff(k) <= '0';
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= aaff * bbff;
muloutff <= mulff;
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236T.VHD ***
--*** ***
--*** Function: 3 pipeline stage signed 32 or ***
--*** 36 bit truncated multiplier ***
--*** with faithful rounding, for use ***
--*** with Arria V. ***
--*** ***
--*** 2012-04-17 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236t IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
BEGIN
assert (width <= 36);
END hcc_mul3236t;
ARCHITECTURE syn OF hcc_mul3236t IS
signal mulaah, mulbbh : STD_LOGIC_VECTOR(36 downto 19);
signal mulaal, mulbbl : STD_LOGIC_VECTOR(18 downto 1);
signal multone : STD_LOGIC_VECTOR(72 DOWNTO 37); -- 36 bits
signal multtwo : STD_LOGIC_VECTOR(55 DOWNTO 19); -- 37 bits
signal mulaaff, mulbbff, prodff : STD_LOGIC;
signal addmult : STD_LOGIC_VECTOR(72 DOWNTO 34);
signal addmultff : STD_LOGIC_VECTOR(72 DOWNTO (73 - width));
component hcc_mul2727s IS
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_MA2_27Ux27S_L2 is
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
aclr : IN STD_LOGIC;
clk : IN STD_LOGIC;
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
en : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
BEGIN
mulaah <= mulaa(width DOWNTO (width - 17));
mulaal <= mulaa((width - 18) DOWNTO 1) & ((36 - width) DOWNTO 1 => '0');
mulbbh <= mulbb(width DOWNTO (width - 17));
mulbbl <= mulbb((width - 18) DOWNTO 1) & ((36 - width) DOWNTO 1 => '0');
mone: hcc_mul2727s
GENERIC MAP (width=>18)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulaah,bb=>mulbbh,
cc=>multone);
mtwo: hcc_MA2_27Ux27S_L2
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>37)
PORT MAP (aclr=>reset,clk=>sysclk,
a0=>mulaal,
a1=>mulbbl,
b0=>mulbbh,
b1=>mulaah,
en=>enable,
result=>multtwo);
addmult <= (multone(72 DOWNTO 37) & '1' & prodff & '1') +
((72 DOWNTO 56 => multtwo(55)) & multtwo(55 DOWNTO 35) & '1');
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulaaff <= '0';
mulbbff <= '0';
prodff <= '0';
addmultff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulaaff <= mulaal(18);
mulbbff <= mulbbl(18);
prodff <= mulaaff AND mulbbff;
addmultff <= addmult(72 DOWNTO (73 - width));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END syn;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_28S.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 28S: Stratix 2, 8 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_28s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_28s;
ARCHITECTURE syn of hcc_mul54us_28s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecsix, vecsev : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(54 DOWNTO 19);
mulonebb <= mulbb(54 DOWNTO 19);
multwoaa <= mulaa(18 DOWNTO 1);
multwobb <= mulbb(36 DOWNTO 19);
multhraa <= mulaa(18 DOWNTO 1);
multhrbb <= mulbb(54 DOWNTO 37);
mulforaa <= mulbb(18 DOWNTO 1);
mulforbb <= mulaa(36 DOWNTO 19);
mulfivaa <= mulbb(18 DOWNTO 1);
mulfivbb <= mulaa(54 DOWNTO 37);
-- {A,C) * {B,D}
-- AAC
-- BBD
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= zerovec(22 DOWNTO 1) & multwoout;
vectwo <= zerovec(4 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(22 DOWNTO 1) & mulforout;
vecfor <= zerovec(4 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 58 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(57 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 58 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 58 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 72 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(57 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= zerovec(32 DOWNTO 1) & sumoneff(58 DOWNTO 19);
vecnin <= zerovec(32 DOWNTO 1) & caroneff(58 DOWNTO 19);
vecten <= muloneout(72 DOWNTO 1);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 9),
datab => cartwoff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_29S.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 Created from HCC_MUL54USS ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_29s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_29s;
ARCHITECTURE syn of hcc_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 9),
datab => cartwoff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY hcc_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_38s;
ARCHITECTURE rtl OF hcc_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (64 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone(72 DOWNTO 9) +
(zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 27));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE altera_mf.all;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_3XS.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 3XS: Stratix 3, 10 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** For QII8.0 LPM_MULT always creates a 10 ***
--*** 18x18 multiplier 54x54 core ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_3xs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54us_3xs;
ARCHITECTURE syn of hcc_mul54us_3xs IS
component lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end component;
BEGIN
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => 4,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 54,
lpm_widthb => 54,
lpm_widthp => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54US_57S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 57S: Stratix V/Arria V; 3 27x27, 1 18x18 ***
--*** ***
--*** 2012-04-13 SPF ***
--*** ***
--*** (c) 2012 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54us_57s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR(54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR(54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR(64 DOWNTO 1)
);
END hcc_mul54us_57s;
ARCHITECTURE rtl OF hcc_mul54us_57s IS
-- width of first adder including carry (register/FMax trade-off)
constant ADD1WIDTH : positive := 35;
signal multone : STD_LOGIC_VECTOR(108 DOWNTO 55); -- 54 bits
signal multtwo : STD_LOGIC_VECTOR(82 DOWNTO 28); -- 55 bits (sum-of-2)
signal multthree : STD_LOGIC_VECTOR(54 DOWNTO 23); -- 32 bits
constant HI : positive := 2*54;
constant LO : positive := (HI - 64) + 1;
constant H2 : positive := HI;
constant L2 : positive := LO + ADD1WIDTH - 1;
constant H1 : positive := LO + ADD1WIDTH - 2;
constant L1 : positive := LO;
constant LX : positive := LO - 1;
signal argone : STD_LOGIC_VECTOR(H2 DOWNTO LX);
signal argtwo : STD_LOGIC_VECTOR(H2 DOWNTO LX);
signal argoneff : STD_LOGIC_VECTOR(H2 DOWNTO L2);
signal argtwoff : STD_LOGIC_VECTOR(H2 DOWNTO L2);
signal stageone : STD_LOGIC_VECTOR(L2 DOWNTO LX);
signal stagetwo : STD_LOGIC_VECTOR(H2 DOWNTO H1);
signal stageoneff : STD_LOGIC_VECTOR(L2 DOWNTO L1);
signal addmultff : STD_LOGIC_VECTOR(H2 DOWNTO L1);
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component hcc_MA2_27Ux27U_L2 is
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
aclr : IN STD_LOGIC;
clk : IN STD_LOGIC;
a0 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
en : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
BEGIN
mone: fp_mul2s
GENERIC MAP (widthaa=>27,widthbb=>27,widthcc=>54)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 28),databb=>mulbb(54 DOWNTO 28),
result=>multone);
mtwo: hcc_MA2_27Ux27U_L2
GENERIC MAP (widthaa=>27,widthbb=>27,widthcc=>55)
PORT MAP (aclr=>reset,clk=>sysclk,
a0=>mulaa(27 DOWNTO 1),
a1=>mulbb(27 DOWNTO 1),
b0=>mulbb(54 DOWNTO 28),
b1=>mulaa(54 DOWNTO 28),
en=>enable,
result=>multtwo);
mthree: fp_mul2s
GENERIC MAP (widthaa=>16,widthbb=>16,widthcc=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(27 DOWNTO 12),databb=>mulbb(27 DOWNTO 12),
result=>multthree);
argone <= multone(108 DOWNTO 55) & multthree(54 DOWNTO LX);
argtwo <= (108 DOWNTO 83 => '0') & multtwo(82 DOWNTO LX);
stageone <= ('0' & argone(H1 DOWNTO LX)) +
('0' & argtwo(H1 DOWNTO LX));
stagetwo <= (argoneff(H2 DOWNTO L2) & stageoneff(L2)) +
(argtwoff(H2 DOWNTO L2) & '1');
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
argoneff <= (others => '0');
argtwoff <= (others => '0');
stageoneff <= (others => '0');
addmultff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
argoneff <= argone(H2 DOWNTO L2);
argtwoff <= argtwo(H2 DOWNTO L2);
stageoneff <= stageone(L2 DOWNTO L1);
addmultff(H2 DOWNTO L2) <= stagetwo(H2 DOWNTO L2);
addmultff(H1 DOWNTO L1) <= stageoneff(H1 DOWNTO L1);
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USB.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 31/01/08 ML see below ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- 31/01/08 - output right shifted so same as synthesable core
-- (now "001X" >= 2, "0001X" < 2
ENTITY hcc_mul54usb IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0 -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54usb;
ARCHITECTURE rtl OF hcc_mul54usb IS
constant delaydepth : integer := 4 - 2*device;
type muldelfftype IS ARRAY (delaydepth DOWNTO 1) OF STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal muldelff : muldelfftype;
signal mulnode : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal mulonenode, multwonode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multhrnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 72 GENERATE
zerovec(k) <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 108 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO delaydepth LOOP
FOR j IN 1 TO 72 LOOP
muldelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= mulnode;
muldelff(1)(72 DOWNTO 1) <= mulff(108 DOWNTO 37);
FOR k IN 2 TO delaydepth LOOP
muldelff(k)(72 DOWNTO 1) <= muldelff(k-1)(72 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- full multiplier
gpa: IF (doubleaccuracy = 1) GENERATE
mulonenode <= zerovec(54 DOWNTO 1);
multwonode <= zerovec(54 DOWNTO 1);
multhrnode <= zerovec(72 DOWNTO 1);
mulnode <= aaff * bbff;
END GENERATE;
-- pruned multiplier (18x18 LSB contribution missing)
gpb: IF (doubleaccuracy = 0) GENERATE
mulonenode <= aaff(18 DOWNTO 1) * bbff(54 DOWNTO 19);
multwonode <= bbff(18 DOWNTO 1) * aaff(54 DOWNTO 19);
multhrnode <= aaff(54 DOWNTO 19) * bbff(54 DOWNTO 19);
mulnode <= (multhrnode & zerovec(36 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & mulonenode & zerovec(18 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & multwonode & zerovec(18 DOWNTO 1));
END GENERATE;
cc <= muldelff(delaydepth)(72 DOWNTO 9);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
ENTITY hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_muldot_v1;
ARCHITECTURE rtl OF hcc_muldot_v1 IS
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC;
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC;
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_svmult1
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
end component;
BEGIN
biasvalue <= conv_std_logic_vector (127,10);
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
exponentff <= conv_std_logic_vector (0,10);
aasignff <= '0';
bbsignff <= '0';
signff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff);-- - biasvalue;
aasignff <= aa(32);
bbsignff <= bb(32);
signff <= aasignff XOR bbsignff;
END IF;
END IF;
END PROCESS;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
--bmult5: hcc_mul2727s
-- GENERIC MAP (width=>27)
-- PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
-- aa=>aamantissa,bb=>bbmantissa,
-- cc=>multiply);
multcore: hcc_svmult1
PORT MAP (clock0=>sysclk,reset=>reset,dataa_0=>aamantissa,datab_0=>bbmantissa,result=>multiply);
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
--normalize(mantissa DOWNTO mantissa-2) <= "000";
--gnma: FOR k IN 1 TO mantissa-3 GENERATE
-- normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
-- (multiply(56-mantissa+k) AND NOT(multiply(52)));
--END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= '0';
ccsatff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
-- a x inf = inf
ccsatff <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
-- 0 x inf = nan
-- a x nan = nan
ccnanff <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
--cczipff <= '0';
--ccsatff <= '0';
--ccnanff <= '0';
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- multiplier will either be "0001XXXX" or "001XXXX"
-- use this as worst case next level will be "001111" + "001111" = "01111" or negative equivalent
ccmantissa <= multiply (54 DOWNTO 23);
ccsign <= signff;
ccexponent <= exponentff(10 DOWNTO 1);
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1VEC.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 29/04/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1vec IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 1; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1vec;
ARCHITECTURE rtl OF hcc_mulfp1vec IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "00";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - "0001111111";
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_older: IF (device < 2) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
END GENERATE;
gen_twos_newer: IF (device = 2) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--*** OUTPUTS ***
cc(mantissa+10 DOWNTO 11) <= mantissaff;
gen_out_older: IF (device < 2) GENERATE
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
gen_out_newer: IF (device = 2) GENERATE
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1X.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** 11/08/09 - add divider interface output ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0;
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1x;
ARCHITECTURE rtl OF hcc_mulfp1x IS
signal mulinaa, mulinbb : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal mulinaasat, mulinaazip, mulinaanan : STD_LOGIC;
signal mulinbbsat, mulinbbzip, mulinbbnan : STD_LOGIC;
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccsatnode, cczipnode, ccnannode : STD_LOGIC;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmantissa, divposmantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normmantissa : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal normshiftbit : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC;
signal manmultff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expmultff : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- ieee output
signal absnode : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal absolute : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal absoluteff : STD_LOGIC_VECTOR (mantissa-3 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal manroundnode : STD_LOGIC_VECTOR (26 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal expplusnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, manoutmax : STD_LOGIC;
signal expoutzero, expoutmax : STD_LOGIC;
component hcc_mulfp3236 IS
GENERIC (
mantissa : positive; -- 32 or 36
device : integer;
synthesize : integer
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfppn3236 IS
GENERIC (
mantissa : positive; -- 32 or 36
device : integer;
synthesize : integer
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
mulinaa <= aa;
mulinbb <= bb;
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinaanan <= aanan;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
mulinbbnan <= bbnan;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
gma: IF (outputscale = 0) GENERATE
mulone: hcc_mulfp3236
GENERIC MAP (mantissa=>mantissa,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bb=>mulinbb,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
cc=>ccnode,ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
END GENERATE;
gmb: IF (outputscale = 1) GENERATE
multwo: hcc_mulfppn3236
GENERIC MAP (mantissa=>mantissa,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulinaa,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bb=>mulinbb,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
cc=>ccnode,ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
END GENERATE;
--*** OUTPUTS ***
--***********************
--*** INTERNAL FORMAT ***
--***********************
gxo: IF (xoutput = 1) GENERATE
cc <= ccnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
ccnan <= ccnannode;
END GENERATE;
--*******************************************
--*** ANOTHER SINGLE PRECISION MULTIPLIER ***
--*******************************************
gmo: IF (multoutput = 1) GENERATE
-- lose 4 bits of precision for now, update hcc_mulfp3236 later
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 2's complement
gna: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
pmo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
manmultff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expmultff(k) <= '0';
END LOOP;
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manmultff <= normmantissa(mantissa-4 DOWNTO 1) & "0000";
expmultff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= manmultff;
cc(10 DOWNTO 1) <= expmultff;
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END GENERATE;
--**********************************
--*** A SINGLE PRECISION DIVIDER ***
--**********************************
gdo: IF (divoutput = 1) GENERATE
-- lose 4 bits of precision for now, update hcc_mulfp3236 later
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 2's complement
gda: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
-- do not need to trap overflow, as maximum -ve number cannot happen, as inputs
-- will be 0111...*10000
divmantissa <= normmantissa(mantissa-4 DOWNTO 1) & "0000";
gdb: FOR k IN 1 TO mantissa-1 GENERATE
divposmantissa(k) <= divmantissa(k) XOR mantissanode(mantissa);
END GENERATE;
-- divider output is signed magnitude
divposmantissa(mantissa) <= mantissanode(mantissa);
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
pmo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
manmultff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expmultff(k) <= '0';
END LOOP;
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manmultff <= divposmantissa + mantissanode(mantissa);
expmultff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= manmultff;
cc(10 DOWNTO 1) <= expmultff;
ccsat <= ccsatff;
cczip <= cczipff;
ccnan <= ccnanff;
END GENERATE;
--**********************
--*** IEEE754 Output ***
--**********************
gio: IF (ieeeoutput = 1) GENERATE
-- +ve result: 000001XXXXX or 00001XXXXX
-- -ve result: 111110XXXXX or 11110XXXXX
mantissanode <= ccnode(mantissa+10 DOWNTO 11);
-- normmantissa will be "001XXX" or 1's complement
gna: FOR k IN 1 TO mantissa-3 GENERATE
normmantissa(k) <= ( ((mantissanode(k) AND NOT(mantissanode(mantissa-4))) OR
(mantissanode(k+1) AND mantissanode(mantissa-4)))
AND NOT(mantissanode(mantissa)) ) OR
(((mantissanode(k) AND mantissanode(mantissa-4)) OR
(mantissanode(k+1) AND NOT(mantissanode(mantissa-4))))
AND mantissanode(mantissa));
END GENERATE;
normshiftbit <= (mantissanode(mantissa-4) AND NOT(mantissanode(mantissa))) OR
(NOT(mantissanode(mantissa-4)) AND mantissanode(mantissa));
gaa: FOR k IN 1 TO mantissa-3 GENERATE
absnode(k) <= normmantissa(k) XOR normmantissa(mantissa-3);
END GENERATE;
absolute <= absnode(mantissa-3 DOWNTO 1) + normmantissa(mantissa-3);
pia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa-3 LOOP
absoluteff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= "00";
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absoluteff <= absolute;
expshiftff <= ccnode(10 DOWNTO 1) + normshiftbit;
ccsatff <= ccsatnode;
cczipff <= cczipnode;
ccnanff <= ccnannode;
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (manroundnode(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (expplusnode(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff(1) <= normmantissa(mantissa-4);
signoutff(2) <= signoutff(1);
END IF;
END IF;
END PROCESS;
roundbit <= absoluteff(mantissa-29);
manroundnode <= absoluteff(mantissa-3 DOWNTO mantissa-28)+ roundbit;
overflownode(1) <= roundbit;
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= overflownode(k-1) AND absoluteff(mantissa-30+k);
END GENERATE;
expplusnode <= expshiftff + ("000000000" & overflownode(24));
-- both '1' when true
expmax <= expplusnode(8) AND expplusnode(7) AND expplusnode(6) AND expplusnode(5) AND
expplusnode(4) AND expplusnode(3) AND expplusnode(2) AND expplusnode(1);
expzero <= NOT(expplusnode(8) OR expplusnode(7) OR expplusnode(6) OR expplusnode(5) OR
expplusnode(4) OR expplusnode(3) OR expplusnode(2) OR expplusnode(1));
manoutzero <= ccsatff OR cczipff OR expmax OR expzero OR
expshiftff(10) OR expshiftff(9);
manoutmax <= ccnanff;
expoutzero <= cczipff OR expzero OR expshiftff(10);
expoutmax <= expmax OR expshiftff(9) OR ccnanff;
cc(32) <= signoutff(2);
cc(31 DOWNTO 24) <= expoutff;
cc(23 DOWNTO 1) <= manoutff;
-- dummy
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= ccnode(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP2X.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/01/08 - see notes below ***
--*** 21/04/09 - add NAN support, also fix zero ***
--*** infinity and nan mantissa for ieee output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 28/01/08 - correct manoverflow for ieee ***
--*** output, effects of mantissa shift for both ***
--*** ieee and mult output, test output widths, ***
--*** also reversed exp and man order in ieee ***
--*** output ***
--*** 31/08/08 - behavioral and synth mults both ***
--*** now return "001X" (> 2) OR "0001X" (<2) ***
--*** change xoutput to 1 bit less right shift ***
--***(behavioral mult changed) ***
--***************************************************
ENTITY hcc_mulfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier or divider (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4), 2 = "Stratix V"
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp2x;
ARCHITECTURE rtl OF hcc_mulfp2x IS
-- 5 if stratix 2, 3 if stratix 3/4, 3 also for SV/AV.
function pipeline_latency(device : integer) return positive is
begin
case device is
when 0 => return 5;
when others => return 3;
end case;
end function pipeline_latency;
constant signdepth : positive := pipeline_latency(device);
type ccxexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type cceexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- multiplier core interface
signal mulinaaman, mulinbbman : STD_LOGIC_VECTOR(54 DOWNTO 1);
signal mulinaaexp, mulinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal mulinaasat, mulinaazip, mulinaanan : STD_LOGIC;
signal mulinbbsat, mulinbbzip, mulinbbnan : STD_LOGIC;
signal mulinaasign, mulinbbsign : STD_LOGIC;
signal mulinaasignff, mulinbbsignff : STD_LOGIC;
signal mulsignff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal ccmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccexpnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatnode, cczipnode, ccnannode : STD_LOGIC;
-- output section (x out)
signal ccmanshiftnode, signedccxmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccxsatff, ccxzipff, ccxnanff : STD_LOGIC;
signal ccxexpdelff : ccxexpdelfftype;
signal ccxsatdelff, ccxzipdelff, ccxnandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
-- output section (ieeeout)
signal shiftroundbit : STD_LOGIC;
signal cceroundnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal cceround : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceroundcarry : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccemannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal ccemanoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal cceexpoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ccesignbitff : STD_LOGIC;
signal cceroundff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatff, ccezipff, ccenanff : STD_LOGIC;
signal ccesignff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal cceexpdelff : cceexpdelfftype;
signal ccesatdelff, ccezipdelff, ccenandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal ccesigndelff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal cceexpbase, cceexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatbase, ccezipbase, ccenanbase : STD_LOGIC;
signal cceexpmax, cceexpzero : STD_LOGIC;
signal manoutzero, manoutmax, expoutzero, expoutmax : STD_LOGIC;
signal manoverflow : STD_LOGIC;
-- output section (multout)
signal shiftmanbit : STD_LOGIC;
signal manshiftnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manshiftff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccexpdelff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatdelff, cczipdelff, ccnandelff : STD_LOGIC;
signal muloutsignff : STD_LOGIC;
-- debug
signal aaexp, bbexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (11 + 2*multoutput + 2*xoutput DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (54+10*xoutput DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_mulufp54
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section - Normalization, if required ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT IN ALL CASES SIGN BIT IS PACKED IN MSB ***
--*** OF UNSIGNED MULTIPLIER ***
--********************************************************
--*** ieee754 input when multiplier input is from cast ***
--*** cast now creates different ***
--*** formats for multiplier, divider, and alu ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from another double multiplier (special ***
--*** output mode normalizes to 54 bit mantissa and ***
--*** 13 bit exponent ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from internal format, must be normed ***
--*** by normfp2x first, creates [S][1][mantissa...] ***
--********************************************************
mulinaaman <= '0' & aa(66 DOWNTO 14);
mulinaaexp <= aa(13 DOWNTO 1);
mulinbbman <= '0' & bb(66 DOWNTO 14);
mulinbbexp <= bb(13 DOWNTO 1);
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinaanan <= aanan;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
mulinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
mulinaasign <= aa(67);
mulinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Multiplier Section ***
--*** ***
--**************************************************
mult: hcc_mulufp54
GENERIC MAP (doubleaccuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mulinaaman,aaexp=>mulinaaexp,
aasat=>mulinaasat,aazip=>mulinaazip,aanan=>mulinaanan,
bbman=>mulinbbman,bbexp=>mulinbbexp,
bbsat=>mulinbbsat,bbzip=>mulinbbzip,bbnan=>mulinbbnan,
ccman=>ccmannode,ccexp=>ccexpnode,
ccsat=>ccsatnode,cczip=>cczipnode,ccnan=>ccnannode);
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulinaasignff <= '0';
mulinbbsignff <= '0';
FOR k IN 1 TO signdepth LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulinaasignff <= mulinaasign;
mulinbbsignff <= mulinbbsign;
mulsignff(1) <= mulinaasignff XOR mulinbbsignff;
FOR k IN 2 TO signdepth LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
-- result will be "001X" (>2) or "0001X" (<2)
-- Y is SSSSS1 (<2) - therefore right shift 2 bits
-- 31/08/08 - behavioral mult changed to be same as synth one
ccmanshiftnode <= "00" & ccmannode(64 DOWNTO 3);
goxb: FOR k IN 1 TO 64 GENERATE
signedccxmannode(k) <= ccmanshiftnode(k) XOR mulsignff(signdepth);
END GENERATE;
goxc: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= signedccxmannode;
cc(13 DOWNTO 1) <= ccexpnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
ccnan <= ccnannode;
END GENERATE;
goxd: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goxe: IF (roundconvert = 0) GENERATE
ccxroundnode <= signedccxmannode;
END GENERATE;
goxf: IF (roundconvert = 1) GENERATE
ccxroundnode <= signedccxmannode + (zerovec(63 DOWNTO 1) & mulsignff(signdepth));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
ccxroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccxexpff(k) <= '0';
END LOOP;
ccxsatff <= '0';
ccxzipff <= '0';
ccxnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxroundff <= ccxroundnode;
ccxexpff <= ccexpnode;
ccxsatff <= ccsatnode;
ccxzipff <= cczipnode;
ccxnanff <= ccnannode;
END IF;
END IF;
END PROCESS;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundff;
cc(13 DOWNTO 1) <= ccxexpff(13 DOWNTO 1);
ccsat <= ccxsatff;
cczip <= ccxzipff;
ccnan <= ccxnanff;
END GENERATE;
goxg: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
ccxexpdelff(1)(k) <= '0';
ccxexpdelff(2)(k) <= '0';
END LOOP;
ccxsatdelff <= "00";
ccxzipdelff <= "00";
ccxnandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxexpdelff(1)(13 DOWNTO 1) <= ccexpnode;
ccxexpdelff(2)(13 DOWNTO 1) <= ccxexpdelff(1)(13 DOWNTO 1);
ccxsatdelff(1) <= ccsatnode;
ccxsatdelff(2) <= ccxsatdelff(1);
ccxzipdelff(1) <= cczipnode;
ccxzipdelff(2) <= ccxzipdelff(1);
ccxnandelff(1) <= ccnannode;
ccxnandelff(2) <= ccxnandelff(1);
END IF;
END IF;
END PROCESS;
goxh: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(signdepth),
cc=>ccxroundnode);
END GENERATE;
goxi: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(signdepth),
cc=>ccxroundnode);
END GENERATE;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundnode;
cc(13 DOWNTO 1) <= ccxexpdelff(2)(13 DOWNTO 1);
ccsat <= ccxsatdelff(2);
cczip <= ccxzipdelff(2);
ccnan <= ccxnandelff(2);
END GENERATE;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftroundbit <= NOT(ccmannode(62));
goeb: FOR k IN 1 TO 55 GENERATE -- format "01"[52..1]R
cceroundnode(k) <= (ccmannode(k+7) AND shiftroundbit) OR
(ccmannode(k+8) AND NOT(shiftroundbit));
END GENERATE;
goec: IF (roundconvert = 0) GENERATE
ccemannode <= cceroundnode(53 DOWNTO 2);
poia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (ccemannode(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR manoutmax;
END LOOP;
ccesignbitff <= mulsignff(signdepth);
END IF;
END IF;
END PROCESS;
cceexpplus <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit)); -- change 28/01/08
ccesatbase <= ccsatnode;
ccezipbase <= cczipnode;
ccenanbase <= ccnannode;
manoverflow <= '0'; -- change 28/01/08
--*** OUTPUTS ***
cc(64) <= ccesignbitff;
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goed: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
cceroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
cceexpff(k) <= '0';
END LOOP;
ccesatff <= '0';
ccezipff <= '0';
ccenanff <= '0';
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
cceroundff <= cceroundnode(55 DOWNTO 2) + cceroundcarry;
-- change 28/01/08
cceexpff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
ccesatff <= ccsatnode;
ccezipff <= cczipnode;
ccenanff <= ccnannode;
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (cceroundff(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
ccesignff(1) <= mulsignff(signdepth);
ccesignff(2) <= ccesignff(1);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundff(54);
cceexpbase <= cceexpff(13 DOWNTO 1);
ccesatbase <= ccesatff;
ccezipbase <= ccezipff;
ccenanbase <= ccenanff;
cceexpplus <= cceexpbase + ("000000000000" & cceroundff(54));
--*** OUTPUTS ***
cc(64) <= ccesignff(2);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goef: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
goeg: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceround);
END GENERATE;
goeh: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceround);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
cceexpdelff(1)(k) <= '0';
cceexpdelff(2)(k) <= '0';
END LOOP;
ccesatdelff <= "00";
ccezipdelff <= "00";
ccenandelff <= "00";
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesigndelff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- change 28/01/08
cceexpdelff(1)(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
cceexpdelff(2)(13 DOWNTO 1) <= cceexpdelff(1)(13 DOWNTO 1);
ccesatdelff(1) <= ccsatnode;
ccesatdelff(2) <= ccesatdelff(1);
ccezipdelff(1) <= cczipnode;
ccezipdelff(2) <= ccezipdelff(1);
ccenandelff(1) <= ccnannode;
ccenandelff(2) <= ccenandelff(1);
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= (cceround(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
ccesigndelff(1) <= mulsignff(signdepth);
ccesigndelff(2) <= ccesigndelff(1);
ccesigndelff(3) <= ccesigndelff(2);
END IF;
END IF;
END PROCESS;
manoverflow <= cceround(54);
cceexpbase <= cceexpdelff(2)(13 DOWNTO 1);
ccesatbase <= ccesatdelff(2);
ccezipbase <= ccezipdelff(2);
ccenanbase <= ccenandelff(2);
cceexpplus <= cceexpbase + ("000000000000" & cceround(54));
--*** OUTPUTS ***
cc(64) <= ccesigndelff(3);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
cceexpmax <= cceexpplus(11) AND cceexpplus(10) AND cceexpplus(9) AND cceexpplus(8) AND
cceexpplus(7) AND cceexpplus(6) AND cceexpplus(5) AND cceexpplus(4) AND
cceexpplus(3) AND cceexpplus(2) AND cceexpplus(1);
cceexpzero <= NOT(cceexpplus(11) OR cceexpplus(10) OR cceexpplus(9) OR cceexpplus(8) OR
cceexpplus(7) OR cceexpplus(6) OR cceexpplus(5) OR cceexpplus(4) OR
cceexpplus(3) OR cceexpplus(2) OR cceexpplus(1));
-- zip or exp condition turns mantissa zero
manoutzero <= ccesatbase OR ccezipbase OR
cceexpmax OR cceexpzero OR
cceexpplus(13) OR cceexpplus(12) OR
manoverflow;
manoutmax <= ccenanbase;
expoutzero <= ccezipbase OR cceexpzero OR cceexpplus(13);
expoutmax <= cceexpmax OR cceexpplus(12) OR ccenanbase;
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
--********************************************************
--*** if output directly into DP mult, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required, no round ***
--********************************************************
goma: IF (multoutput = 1) GENERATE -- to another multiplier
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftmanbit <= NOT(ccmannode(62));
gomb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]
manshiftnode(k) <= (ccmannode(k+8) AND shiftmanbit) OR
(ccmannode(k+9) AND NOT(shiftmanbit));
END GENERATE;
poma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccexpdelff(k) <= '0';
END LOOP;
ccsatdelff <= '0';
cczipdelff <= '0';
ccnandelff <= '0';
muloutsignff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manshiftff <= manshiftnode;
-- change 28/01/08
ccexpdelff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftmanbit));
ccsatdelff <= ccsatnode;
cczipdelff <= cczipnode;
ccnandelff <= ccnannode;
muloutsignff <= mulsignff(signdepth);
END IF;
END IF;
END PROCESS;
cc(67) <= muloutsignff;
cc(66 DOWNTO 14) <= manshiftff(53 DOWNTO 1);
cc(13 DOWNTO 1) <= ccexpdelff(13 DOWNTO 1);
ccsat <= ccsatdelff;
cczip <= cczipdelff;
ccnan <= ccnandelff;
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
aaman <= aa(67 DOWNTO 14);
bbman <= bb(67 DOWNTO 14);
gdba: IF (xoutput = 1) GENERATE
gdbb: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
ccman <= signedccxmannode;
ccexp <= ccexpnode;
END GENERATE;
gdbc: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
ccman <= ccxroundff;
ccexp <= ccxexpff(13 DOWNTO 1);
END GENERATE;
gdbd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
ccman <= ccxroundnode;
ccexp <= ccxexpdelff(2)(13 DOWNTO 1);
END GENERATE;
END GENERATE;
-- change 28/01/08
gdbe: IF (ieeeoutput = 1) GENERATE
ccexp <= cceexpoutff;
ccman <= "01" & ccemanoutff;
END GENERATE;
-- change 28/01/08
gdbf: IF (multoutput = 1) GENERATE
ccexp <= ccexpdelff(13 DOWNTO 1);
ccman <= '0' & manshiftff(53 DOWNTO 1);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff, bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236t
GENERIC (width : positive);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
ccsatff <= "00";
cczipff <= "00";
ccnanff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
ccnanff(2) <= ccnanff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1 AND device /= 3) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gsc: IF (synthesize = 1 AND device = 3) GENERATE
tmult: hcc_mul3236t
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout(2*mantissa DOWNTO mantissa+1));
mulout(mantissa DOWNTO 1) <= (others => '0');
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc <= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFPPN3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function, with post-norm ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfppn3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfppn3236;
ARCHITECTURE rtl OF hcc_mulfppn3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aamanff, bbmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff : STD_LOGIC;
signal bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aapos, aaneg, bbpos, bbneg : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal aanumff, bbnumff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal selnode : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal sel, selff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal expadjff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal expadjnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- assume that result > 2
-- if output likely in [62..59] shift 0, if in [58..55] shift 4,
-- if in [54..51] shift 8, else shift 12 (adjust exponent accordingly)
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aamanff(k) <= '0';
bbmanff(k) <= '0';
END LOOP;
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 3 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
ccsatff <= "000";
cczipff <= "000";
ccnanff <= "000";
aanumff <= "0000";
bbnumff <= "0000";
selff <= "0000";
expadjff <= "0000";
FOR k IN 1 TO mantissa LOOP
manoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman;
bbmanff <= bbman;
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
expff(3)(10 DOWNTO 1) <= expff(2)(10 DOWNTO 1) + expadjnode;
FOR k IN 1 TO 4 LOOP
aanumff(k) <= (aapos(k) AND NOT(aa(32))) OR (aaneg(k) AND aa(32));
bbnumff(k) <= (bbpos(k) AND NOT(bb(32))) OR (bbneg(k) AND bb(32));
END LOOP;
selff <= sel;
-- "0" when sel(1), "4" when sel(2), "8" when sel(3), "12" when sel(4)
-- don't adjust during a saturate or zero condition
expadjff(2 DOWNTO 1) <= "00";
expadjff(3) <= (sel(2) OR sel(4)) AND NOT(ccsatff(1) OR cczipff(1));
expadjff(4) <= (sel(3) OR sel(4)) AND NOT(ccsatff(1) OR cczipff(1));
-- output left shift
-- mulpipe is [64..1], 44 bit output is in [62..19] for 32 bit
-- mulpipe is [72..1], 44 bit output is in [70..27] for 36 bits
FOR k IN mantissa DOWNTO 1 LOOP
manoutff(k) <= (mulout(k+mantissa-2) AND selff(1)) OR
(mulout(k+mantissa-6) AND selff(2)) OR
(mulout(k+mantissa-10) AND selff(3)) OR
(mulout(k+mantissa-14) AND selff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
aapos(1) <= aamanff(mantissa-1) OR aamanff(mantissa-2) OR aamanff(mantissa-3) OR aamanff(mantissa-4);
aapos(2) <= aamanff(mantissa-5) OR aamanff(mantissa-6) OR aamanff(mantissa-7) OR aamanff(mantissa-8);
aapos(3) <= aamanff(mantissa-9) OR aamanff(mantissa-10) OR aamanff(mantissa-11) OR aamanff(mantissa-12);
aapos(4) <= aamanff(mantissa-13) OR aamanff(mantissa-14) OR aamanff(mantissa-15) OR aamanff(mantissa-16);
bbpos(1) <= bbmanff(mantissa-1) OR bbmanff(mantissa-2) OR bbmanff(mantissa-3) OR bbmanff(mantissa-4);
bbpos(2) <= bbmanff(mantissa-5) OR bbmanff(mantissa-6) OR bbmanff(mantissa-7) OR bbmanff(mantissa-8);
bbpos(3) <= bbmanff(mantissa-9) OR bbmanff(mantissa-10) OR bbmanff(mantissa-11) OR bbmanff(mantissa-12);
bbpos(4) <= bbmanff(mantissa-13) OR bbmanff(mantissa-14) OR bbmanff(mantissa-15) OR bbmanff(mantissa-16);
aaneg(1) <= aamanff(mantissa-1) AND aamanff(mantissa-2) AND aamanff(mantissa-3) AND aamanff(mantissa-4);
aaneg(2) <= aamanff(mantissa-5) AND aamanff(mantissa-6) AND aamanff(mantissa-7) AND aamanff(mantissa-8);
aaneg(3) <= aamanff(mantissa-9) AND aamanff(mantissa-10) AND aamanff(mantissa-11) AND aamanff(mantissa-12);
aaneg(4) <= aamanff(mantissa-13) AND aamanff(mantissa-14) AND aamanff(mantissa-15) AND aamanff(mantissa-16);
bbneg(1) <= bbmanff(mantissa-1) AND bbmanff(mantissa-2) AND bbmanff(mantissa-3) AND bbmanff(mantissa-4);
bbneg(2) <= bbmanff(mantissa-5) AND bbmanff(mantissa-6) AND bbmanff(mantissa-7) AND bbmanff(mantissa-8);
bbneg(3) <= bbmanff(mantissa-9) AND bbmanff(mantissa-10) AND bbmanff(mantissa-11) AND bbmanff(mantissa-12);
bbneg(4) <= bbmanff(mantissa-13) AND bbmanff(mantissa-14) AND bbmanff(mantissa-15) AND bbmanff(mantissa-16);
selnode(1) <= aanumff(1) AND bbnumff(1);
selnode(2) <= (aanumff(1) AND bbnumff(2)) OR
(aanumff(2) AND bbnumff(1));
selnode(3) <= (aanumff(2) AND bbnumff(2)) OR
(aanumff(1) AND bbnumff(3)) OR
(aanumff(3) AND bbnumff(1));
sel(1) <= selnode(1); -- shift 0
sel(2) <= NOT(selnode(1)) AND selnode(2); -- shift 4
sel(3) <= NOT(selnode(1)) AND NOT(selnode(2)) AND selnode(3); -- shift 8
sel(4) <= NOT(selnode(1)) AND NOT(selnode(2)) AND NOT(selnode(3)); -- shift 12
expadjnode <= "000000" & expadjff;
--***************
--*** OUTPUTS ***
--***************
cc <= manoutff(mantissa) & manoutff(mantissa) & manoutff(mantissa DOWNTO 3) & expff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONG.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullong IS
GENERIC (
unsigned : integer := 0; -- 0 = signed, 1 = unsigned
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullong;
ARCHITECTURE rtl OF hcc_mullong IS
component hcc_mullongb
GENERIC (unsigned : integer := 0); -- 0 = signed, 1 = unsigned
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_mullongs
GENERIC (unsigned : integer := 0); -- 0 = signed, 1 = unsigned
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gba: IF (synthesize = 0) GENERATE
mulb: hcc_mullongb
GENERIC MAP (unsigned=>unsigned)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,
cc=>cc);
END GENERATE;
gsa: IF (synthesize = 1) GENERATE
muls: hcc_mullongs
GENERIC MAP (unsigned=>unsigned)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,
cc=>cc);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGB.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** behavioral ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongb IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongb;
ARCHITECTURE rtl OF hcc_mullongb IS
signal aabit, bbbit : STD_LOGIC;
signal aaff, bbff : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (66 DOWNTO 1);
signal muloutff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
aabit <= aa(32);
bbbit <= bb(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
aabit <= '0';
bbbit <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 33 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 66 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 32 LOOP
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aabit & aa;
bbff <= bbbit & bb;
mulff <= aaff * bbff;
muloutff <= mulff(32 DOWNTO 1);
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGS.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** synthesizable ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongs IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongs;
ARCHITECTURE syn OF hcc_mullongs IS
signal mulnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gsa: IF (unsigned = 0) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
gua: IF (unsigned = 1) GENERATE
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 32,
width_b => 32,
width_result => 64
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulnode
);
END GENERATE;
mulcc <= mulnode(32 DOWNTO 1);
END syn;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 21/04/09 - add NAN support ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
-- 5 if stratix 2, 3 if stratix 3/4, 3 also for SV/AV.
function pipeline_latency(device : integer) return positive is
begin
case device is
when 0 => return 5;
when others => return 3;
end case;
end function pipeline_latency;
constant normtype : integer := 0;
constant pipedepth : positive := pipeline_latency(device);
type expfftype IS ARRAY (pipedepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, aananff : STD_LOGIC;
signal bbsatff, bbzipff, bbnanff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (pipedepth DOWNTO 1);
component hcc_mul54usb
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0 -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_3xs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_28s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_29s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_38s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54us_57s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO pipedepth LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
FOR k IN 1 TO pipedepth LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
bbsatff <= bbsat;
bbzipff <= bbzip;
bbnanff <= bbnan;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO pipedepth LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO pipedepth LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
-- multiply 0 X infinity is invalid OP, NAN out
ccnanff(1) <= aananff OR bbnanff OR (aazipff AND bbsatff) OR (bbzipff AND aasatff);
FOR k IN 2 TO pipedepth LOOP
ccnanff(k) <= ccnanff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO pipedepth LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
GENERIC MAP (doubleaccuracy=>doubleaccuracy,device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
gma: IF (device = 0 AND doubleaccuracy = 0) GENERATE
smone: hcc_mul54us_28s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmb: IF (device = 0 AND doubleaccuracy = 1) GENERATE
smtwo: hcc_mul54us_29s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmc: IF (device = 1 AND doubleaccuracy = 0) GENERATE
smthr: hcc_mul54us_38s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gmd: IF ((device = 1 OR device = 2) AND doubleaccuracy = 1) GENERATE
smfor: hcc_mul54us_3xs
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
gme: IF (device = 2 AND doubleaccuracy = 0) GENERATE
smfiv: hcc_mul54us_57s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(pipedepth)(13 DOWNTO 1);
ccsat <= ccsatff(pipedepth);
cczip <= cczipff(pipedepth);
ccnan <= ccnanff(pipedepth);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** 16/04/09 - add NAN support ***
--*** 08/11/10 - +0,-0 mantissa case ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : ***
--***************************************************
--***************************************************
--*** NOTES: ***
--*** normalize signed numbers (x input format) ***
--*** for 1x multipliers ***
--*** format signed32/36 bit mantissa and 10 bit ***
--*** exponent ***
--*** unsigned numbers for divider (S,1,23 bit ***
--*** mantissa for divider) divider packed into ***
--*** 32/36bit mantissa + exponent ***
--***************************************************
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff, aananff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal maximumnumberff : STD_LOGIC;
signal zeroexponent, zeroexponentff : STD_LOGIC;
signal exponentmiddle : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatdelff, aazipdelff, aanandelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
ccnan <= aananff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
maximumnumberff <= '0';
zeroexponentff <= '0';
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
aanandelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exponentmiddle;
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
-- 08/11/09
maximumnumberff <= aaff(mantissa+10) XOR aaff(mantissa+9);
zeroexponentff <= zeroexponent;
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
aanandelff(1) <= aanan;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
aanandelff(k) <= aanandelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
-- 08/11/10 - also where exponentmiddle is used
-- '1' if true : if countsign 0, then "111...111" (-0) or "000...000" (+0) case, zero exponent output
zeroexponent <= NOT(countsign(6) OR countsign(5) OR countsign(4) OR
countsign(3) OR countsign(2) OR countsign(1) OR maximumnumberff);
gen_exp_mid: FOR k IN 1 TO 10 GENERATE
exponentmiddle(k) <= exptopff(2)(k) AND NOT(zeroexponentff);
END GENERATE;
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
ccnan <= aanandelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
ccnan <= aanandelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
ccnan <= aanandelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** check in target=0 code ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal overflowcondition : STD_LOGIC;
signal overflowconditionff : STD_LOGIC;
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
aananff(1) <= aanan;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
aananff(k) <= aananff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth = 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(2)(13 DOWNTO 1);
END GENERATE;
gxc: IF (expbotffdepth > 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth-1 LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) +
("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
overflowcondition <= '0'; -- 20/05/09 used in exponent calculation
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
overflowbitnode(1) <= normalaaff(1);
gova: FOR k IN 2 TO 55 GENERATE
overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k);
END GENERATE;
gng: IF (doublespeed = 0) GENERATE
overflowcondition <= overflowbitnode(55);
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
overflowconditionff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
overflowconditionff <= overflowbitnode(55);
END IF;
END IF;
END PROCESS;
overflowcondition <= overflowconditionff;
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
-- overflow cannot happen here, dont insert
overflowcondition <= '0'; -- 20/05/09 used for exponent
pnf: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
png: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
end rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftcomb32;
ARCHITECTURE rtl OF hcc_rsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(32) AND shift(5));
END GENERATE;
levthr(32) <= levtwo(32);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftcomb36;
ARCHITECTURE rtl OF hcc_rsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(36) AND shift(6));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(36) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(36) <= levtwo(36);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE36.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftpipe36;
ARCHITECTURE rtl OF hcc_rsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(36) AND shiftff(2));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(36) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(36) <= levtwoff(36);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SGNPSTN.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small signed ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_sgnpstn IS
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_sgnpstn;
ARCHITECTURE rtl OF hcc_sgnpstn IS
signal pluspos, minuspos : STD_LOGIC_VECTOR (width DOWNTO 1);
BEGIN
paa: PROCESS (inbus)
BEGIN
CASE inbus IS
WHEN "0000" => pluspos <= conv_std_logic_vector (0,width);
WHEN "0001" => pluspos <= conv_std_logic_vector (offset+3,width);
WHEN "0010" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0011" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0100" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0101" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0110" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0111" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "1000" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1001" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1010" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1011" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1100" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1101" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1110" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1111" => pluspos <= conv_std_logic_vector (offset,width);
WHEN others => pluspos <= conv_std_logic_vector (0,width);
END CASE;
CASE inbus IS
WHEN "0000" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0001" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0010" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0011" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0100" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0101" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0110" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0111" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "1000" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1001" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1010" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1011" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1100" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1101" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1110" => minuspos <= conv_std_logic_vector (offset+3,width);
WHEN "1111" => minuspos <= conv_std_logic_vector (0,width);
WHEN others => minuspos <= conv_std_logic_vector (0,width);
END CASE;
END PROCESS;
gaa: FOR k IN 1 TO width GENERATE
position(k) <= (pluspos(k) AND NOT(signbit)) OR (minuspos(k) AND signbit);
END GENERATE;
END rtl;
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: svmult1.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altmult_add ACCUM_SLOAD_REGISTER="UNREGISTERED" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_AUTO_BLACKBOX="ALL" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_REGISTER="UNREGISTERED" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Stratix V" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_C0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=27 WIDTH_B=27 WIDTH_RESULT=54 clock0 dataa datab result
--VERSION_BEGIN 11.1SP1 cbx_alt_ded_mult_y 2011:11:23:21:10:03:SJ cbx_altera_mult_add 2011:11:23:21:10:03:SJ cbx_altmult_add 2011:11:23:21:10:03:SJ cbx_cycloneii 2011:11:23:21:10:03:SJ cbx_lpm_add_sub 2011:11:23:21:10:03:SJ cbx_lpm_mult 2011:11:23:21:10:03:SJ cbx_mgl 2011:11:23:21:12:10:SJ cbx_padd 2011:11:23:21:10:03:SJ cbx_parallel_add 2011:11:23:21:10:03:SJ cbx_stratix 2011:11:23:21:10:03:SJ cbx_stratixii 2011:11:23:21:10:03:SJ cbx_util_mgl 2011:11:23:21:10:03:SJ VERSION_END
--synthesis_resources = altera_mult_add 1 dsp_mac 1 reg 54
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY svmult1_mult_add_3jm3 IS
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END svmult1_mult_add_3jm3;
ARCHITECTURE RTL OF svmult1_mult_add_3jm3 IS
signal dataaff, databff: unsigned (26 DOWNTO 0);
signal prod : unsigned (53 DOWNTO 0);
BEGIN
pmult: process( clock0, reset, dataa, dataaff, datab, databff)
begin
if reset = '1' then
dataaff <= (others => '0');
databff <= (others => '0');
prod <= (others => '0');
elsif (clock0'event and clock0='1') then
dataaff <= UNSIGNED(dataa);
databff <= UNSIGNED(datab);
prod <= dataaff * databff;
end if;
end process;
result <= STD_LOGIC_VECTOR(prod);
END RTL; --svmult1_mult_add_3jm3
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY hcc_svmult1 IS
PORT
(
clock0 : IN STD_LOGIC := '1';
reset : IN STD_LOGIC := '0';
dataa_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (26 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END hcc_svmult1;
ARCHITECTURE RTL OF hcc_svmult1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (53 DOWNTO 0);
COMPONENT svmult1_mult_add_3jm3
PORT (
clock0 : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (53 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(53 DOWNTO 0);
svmult1_mult_add_3jm3_component : svmult1_mult_add_3jm3
PORT MAP (
clock0 => clock0,
reset => reset,
dataa => dataa_0,
datab => datab_0,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: C_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: C_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: ENABLE_PRELOAD_CONSTANT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: LOADCONST_VALUE NUMERIC "64"
-- Retrieval info: PRIVATE: MULT_COEFSEL STRING "0"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGC NUMERIC "0"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REG_ACCUM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: MULT_REG_SYSTOLIC_DELAY NUMERIC "0"
-- Retrieval info: PRIVATE: NUM_MULT STRING "1"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "0"
-- Retrieval info: PRIVATE: RNFORMAT STRING "54"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "54"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SYSTOLIC_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: SYSTOLIC_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "27"
-- Retrieval info: PRIVATE: WIDTHB STRING "27"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUM_SLOAD_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: COEF0_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF0_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF1_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF2_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_0 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_1 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_2 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_3 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_4 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_5 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_6 NUMERIC "0"
-- Retrieval info: CONSTANT: COEF3_7 NUMERIC "0"
-- Retrieval info: CONSTANT: COEFSEL0_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_C0 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_0 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_1 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_2 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_DIRECTION_3 STRING "ADD"
-- Retrieval info: CONSTANT: PREADDER_MODE STRING "SIMPLE"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SYSTOLIC_DELAY1 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: SYSTOLIC_DELAY3 STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "54"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 27 0 INPUT GND "dataa_0[26..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 27 0 INPUT GND "datab_0[26..0]"
-- Retrieval info: USED_PORT: result 0 0 54 0 OUTPUT GND "result[53..0]"
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 27 0 dataa_0 0 0 27 0
-- Retrieval info: CONNECT: @datab 0 0 27 0 datab_0 0 0 27 0
-- Retrieval info: CONNECT: result 0 0 54 0 @result 0 0 54 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL svmult1_inst.vhd FALSE
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
| mit |
boztalay/OZ-3 | FPGA/OZ-3_System/four_dig_7seg.vhd | 3 | 3099 | ----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
-- give it a 50 MHz clock and data and it'll start working.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end four_dig_7seg;
architecture Behavioral of four_dig_7seg is
--//Signals\\--
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--This process takes the data to display and
--multiplexes 4-bit chunks of it according
--to the input clock. The 4-bit chunks are
--sent to the decoder and the anode lines
--are switched to activate one digit at a time
disp_data: process(display_data, clock) is
variable clk_count : integer := 0; --A variable to count the clock ticks
variable disp_count : integer := 0; --A variable to hold on to which digit
begin --is currently being displayed
if rising_edge(clock) then
clk_count := clk_count + 1;
if clk_count = 100000 then --Refresh rate with 100000 is about 125 Hz for the entire display
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then --First digit
anodes <= "1110";
to_decoder <= display_data(3 downto 0);
elsif disp_count = 1 then --Second digit
anodes <= "1101";
to_decoder <= display_data(7 downto 4);
elsif disp_count = 2 then --Third digit
anodes <= "1011";
to_decoder <= display_data(11 downto 8);
elsif disp_count = 3 then --Fourth digit
anodes <= "0111";
to_decoder <= display_data(15 downto 12);
end if;
end process;
--This represents a ROM that will act as the
--individual 7-segment decoder for each digit
--of the display
with to_decoder select
to_display <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_lnrndpipe.vhd | 10 | 6310 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNRNDPIPE.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Pipelined ***
--*** Round ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnrndpipe IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnrndpipe;
ARCHITECTURE rtl OF dp_lnrndpipe IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal roundmantissanode : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : exponentfftype;
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal manoverflowff : STD_LOGIC;
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzv: FOR k IN 1 TO manwidth+1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "000";
signff <= "000";
infinityff <= "000";
zeroff <= "000";
manoverflowff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
exponentff(3)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
nanff(3) <= nanff(2);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
infinityff(3) <= infinityff(2);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
zeroff(3) <= zeroff(2);
signff(1) <= signln;
signff(2) <= signff(1);
signff(3) <= signff(2);
manoverflowff <= manoverflow(53);
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissanode(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentff(1)(expwidth+2 DOWNTO 1) <= "00" & exponentln(expwidth DOWNTO 1);
exponentff(2)(expwidth+2 DOWNTO 1) <= (exponentff(1)(expwidth+2 DOWNTO 1)) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowff);
FOR k IN 1 TO expwidth LOOP
exponentff(3)(k) <= (exponentff(2)(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
rndadd: dp_fxadd
GENERIC MAP(width=>manwidth,pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mantissaln(manwidth+1 DOWNTO 2),bb=>zerovec(manwidth DOWNTO 1),
carryin=>mantissaln(1),
cc=>roundmantissanode);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO 53 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinityff(2) OR NOT(zeroff(2));
-- setmantissa to "11..11" when nan
setmanmax <= nanff(2);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(2));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(2) OR infinityff(2);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(3);
mantissaout <= mantissaff;
exponentout <= exponentff(3)(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff(3);
overflowout <= infinityff(3);
zeroout <= zeroff(3);
END rtl;
| mit |
satputeaditya/vernier-ring-oscillator-tdc | coincidence_detector.vhd | 1 | 1249 | -- coincidence_detector.vhd
--**********************************************************************
-- Program to detect if STOP pulse is leading and lagging edge wrt START
--**********************************************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity coincidence_detector is
port (
rst : in std_logic;
slow_clk : in std_logic;
fast_clk : in std_logic;
leading : out std_logic; -- SLOW CLK = Reference
lagging : out std_logic -- SLOW CLK = Reference
);
end entity;
architecture behave of coincidence_detector is
signal edge_1 : std_logic;
signal edge_2 : std_logic;
signal rising_edge : std_logic;
signal falling_edge : std_logic;
begin
process(rst,slow_clk,fast_clk)
begin
if rst = '1' then
edge_1 <= '0';
edge_2 <= '0';
elsif FAST_CLK'event and FAST_CLK = '1' then
edge_1 <= SLOW_CLK;
edge_2 <= edge_1;
end if;
end process;
rising_edge <= edge_1 and (not edge_2);
falling_edge <= edge_2 and (not edge_1);
leading <= rising_edge;
lagging <= falling_edge;
end behave; | mit |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/example_design/rtl/example_top.vhd | 1 | 65422 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves both as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic
(
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER
: string := "TG_TEST";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
SEL_VICTIM_LINE : integer := 0;
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IODELAY_HP_MODE : string := "ON";
-- to phy_top
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP : string := "IODELAY_MIG";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency.
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL";
-- # = "INTERNAL", "EXTERNAL"
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port
(
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant ECC_WIDTH : integer := ECCWIDTH;
constant ECC_TEST : string := "OFF";
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
generic(
BANK_WIDTH : integer;
CK_WIDTH : integer;
COL_WIDTH : integer;
CS_WIDTH : integer;
nCS_PER_RANK : integer;
CKE_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_PER_DM : integer;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DRAM_WIDTH : integer;
ECC : string;
DATA_WIDTH : integer;
ECC_TEST : string;
PAYLOAD_WIDTH : integer;
ECC_WIDTH : integer;
MC_ERR_ADDR_WIDTH : integer;
nBANK_MACHS : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
PHY_CONTROL_MASTER_BANK : integer;
AL : string;
nAL : integer;
BURST_MODE : string;
BURST_TYPE : string;
CL : integer;
OUTPUT_DRV : string;
RTT_NOM : string;
ADDR_CMD_MODE : string;
REG_CTRL : string;
CLKIN_PERIOD : integer;
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
tCKE : integer;
tFAW : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
tPRDI : integer;
SIM_BYPASS_INIT_CAL : string;
SIMULATION : string;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
IODELAY_HP_MODE : string;
IBUF_LPWR_MODE : string;
DATA_IO_IDLE_PWRDWN : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
CKE_ODT_AUX : string;
USER_REFRESH : string;
WRLVL : string;
ORDERING : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
TCQ : integer;
CMD_PIPE_PLUS1 : string;
tCK : integer;
nCK_PER_CLK : integer;
DIFF_TERM_SYSCLK : string;
DEBUG_PORT : string;
TEMP_MON_CONTROL : string;
IODELAY_GRP : string;
SYSCLK_TYPE : string;
REFCLK_TYPE : string;
SYS_RST_PORT : string;
REFCLK_FREQ : real;
DIFF_TERM_REFCLK : string;
DRAM_TYPE : string;
CAL_WIDTH : string;
STARVE_LIMIT : integer;
RST_ACT_LOW : integer
);
port(
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v1_9_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
ADDR_WIDTH : integer;
DATA_WIDTH : integer;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
EYE_TEST : string;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
manual_clear_error : in std_logic;
tg_only_rst : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH-1)) downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v1_9_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector(2*nCK_PER_CLK-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_req : std_logic;
signal app_sr_active : std_logic;
signal app_ref_req : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_req : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector(64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK - 1) downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic;
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal wr_data_counts : std_logic_vector(47 downto 0);
signal rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic;
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic;
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic;
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic;
signal dbg_clear_error : std_logic;
signal vio_tg_rst : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_pi_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_po_f_dec : std_logic;
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic;
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_PER_DM => DQ_PER_DM,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
IODELAY_HP_MODE => IODELAY_HP_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
PHY_CONTROL_MASTER_BANK => PHY_CONTROL_MASTER_BANK,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
DM_WIDTH => DM_WIDTH,
nCK_PER_CLK => nCK_PER_CLK,
tCK => tCK,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
SYSCLK_TYPE => SYSCLK_TYPE,
REFCLK_TYPE => REFCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
REFCLK_FREQ => REFCLK_FREQ,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
IODELAY_GRP => IODELAY_GRP,
CAL_WIDTH => CAL_WIDTH,
STARVE_LIMIT => STARVE_LIMIT,
DRAM_TYPE => DRAM_TYPE,
RST_ACT_LOW => RST_ACT_LOW
)
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => app_sr_active,
app_ref_req => '0',
app_ref_ack => app_ref_ack,
app_zq_req => '0',
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v1_9_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
--BL_WIDTH => BL_WIDTH,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error,
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8-1 downto 0),
memc_wr_data => app_wdf_data(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen,
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w,
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => wr_data_counts,
rd_data_counts => rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen <= '0';
vio_pause_traffic <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error <= '0';
po_win_tg_rst <= '0';
vio_tg_rst <= '0';
wdt_en_w <= '1';
dbg_sel_pi_incdec <= '0';
dbg_sel_po_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
end architecture arch_example_top;
| mit |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.vhd | 1 | 111054 | --*****************************************************************************
-- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : MIG
-- / / Filename : ddr_phy_top.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Jan 31 2012
-- \___\/\___\
--
--Device : 7 Series
--Design Name : DDR3 SDRAM
--Purpose : Top level memory interface block. Instantiates a clock
-- and reset generator, the memory controller, the phy and
-- the user interface blocks.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mig_7series_v4_0_ddr_phy_top is
generic (
TCQ : integer := 100; -- Register delay (simulation only)
DDR3_VDD_OP_VOLT : string := "135"; -- Voltage mode used for DDR3
AL : string := "0"; -- Additive Latency option
BANK_WIDTH : integer := 3; -- # of bank bits
BURST_MODE : string := "8"; -- Burst length
BURST_TYPE : string := "SEQ"; -- Burst type
CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
CL : integer := 5;
COL_WIDTH : integer := 12; -- column address width
CS_WIDTH : integer := 1; -- # of unique CS outputs
CKE_WIDTH : integer := 1; -- # of cke outputs
CWL : integer := 5;
DM_WIDTH : integer := 8; -- # of DM (data mask)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_TYPE : string := "DDR3";
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides
LP_DDR_CK_WIDTH : integer := 2;
-- Hard PHY parameters
PHYCTL_CMD_FIFO : string := "FALSE";
-- five fields, one per possible I/O bank, 4 bits in each field,
-- 1 per lane data=1/ctl=0
DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c";
DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f";
-- defines the byte lanes in I/O banks being used in the interface
-- 1- Used, 0- Unused
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- defines the bit lanes in I/O banks being used in the interface. Each
-- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000";
BANK_MAP : std_logic_vector(35 downto 0) := X"000000000";
CAS_MAP : std_logic_vector(11 downto 0) := X"000";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
CKE_ODT_AUX : string := "FALSE";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"000";
WE_MAP : std_logic_vector(11 downto 0) := X"000";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
-- This parameter must be set based on memory clock frequency
-- It must be set to 4 for frequencies above 533 MHz?? (undecided)
-- and set to 2 for 533 MHz and below
PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly
nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T"
BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT"
DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT"
DATA_IO_IDLE_PWRDWN : string := "ON"; -- # = "ON" or "OFF"
IODELAY_GRP : string := "IODELAY_MIG";
FPGA_SPEED_GRADE : integer := 1;
IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option
OUTPUT_DRV : string := "HIGH"; -- to calib_top
REG_CTRL : string := "OFF"; -- to calib_top
RTT_NOM : string := "60"; -- to calib_top
RTT_WR : string := "120"; -- to calib_top
tCK : integer := 2500; -- pS
tRFC : integer := 110000; -- pS
tREFI : integer := 7800000; -- pS
DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2
WRLVL : string := "OFF"; -- to calib_top
DEBUG_PORT : string := "OFF"; -- to calib_top
RANKS : integer := 4;
ODT_WIDTH : integer := 1;
ROW_WIDTH : integer := 16; -- DRAM address bus width
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- calibration Address. The address given below will be used for calibration
-- read and write operations.
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
-- Simulation /debug options
SIM_BYPASS_INIT_CAL : string := "OFF";
-- Parameter used to force skipping
-- or abbreviation of initialization
-- and calibration. Overrides
-- SIM_INIT_OPTION, SIM_CAL_OPTION,
-- and disables various other blocks
--parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps
--parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps
REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz)
USE_CS_PORT : integer := 1; -- Support chip select output
USE_DM_PORT : integer := 1; -- Support data mask output
USE_ODT_PORT : integer := 1; -- Support ODT output
RD_PATH_REG : integer := 0; -- optional registers in the read path
-- to MC for timing improvement.
-- =1 enabled, = 0 disabled
IDELAY_ADJ : string := "ON"; -- ON: IDELAY-1, OFF: No change
FINE_PER_BIT : string := "ON"; -- ON: Use per bit calib for complex rdlvl
CENTER_COMP_MODE : string := "ON"; -- ON: use PI stg2 tap compensation
PI_VAL_ADJ : string := "ON"; -- ON: PI stg2 tap -1 for centering
TAPSPERKCLK : integer := 56;
SKIP_CALIB : string := "FALSE"; -- skip calibration define
POC_USE_METASTABLE_SAMP : string := "FALSE";
FPGA_VOLT_TYPE : string := "N"
);
port (
clk : in std_logic; -- Fabric logic clock
-- To MC, calib_top, hard PHY
clk_div2 : in std_logic; -- mem_refclk divided by 2 for PI indec
rst_div2 : in std_logic; -- reset in clk_div2 domain
clk_ref : in std_logic; -- Idelay_ctrl reference clock
-- To hard PHY (external source)
freq_refclk : in std_logic; -- To hard PHY for Phasers
mem_refclk : in std_logic; -- Memory clock to hard PHY
pll_lock : in std_logic; -- System PLL lock signal
sync_pulse : in std_logic; -- 1/N sync pulse used to
-- synchronize all PHASERS
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
error : in std_logic; -- Support for TG error detect
rst_tg_mc : out std_logic; -- Support for TG error detect
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
rst : in std_logic;
iddr_rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
-- From MC
mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mc_reset_n : in std_logic;
mc_odt : in std_logic_vector(1 downto 0);
mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
-- AUX - For ODT and CKE assertion during reads and writes
mc_aux_out0 : in std_logic_vector(3 downto 0);
mc_aux_out1 : in std_logic_vector(3 downto 0);
mc_cmd_wren : in std_logic;
mc_ctl_wren : in std_logic;
mc_cmd : in std_logic_vector(2 downto 0);
mc_cas_slot : in std_logic_vector(1 downto 0);
mc_data_offset : in std_logic_vector(5 downto 0);
mc_data_offset_1 : in std_logic_vector(5 downto 0);
mc_data_offset_2 : in std_logic_vector(5 downto 0);
mc_rank_cnt : in std_logic_vector(1 downto 0);
-- Write
mc_wrdata_en : in std_logic;
mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0);
idle : in std_logic;
-- DDR bus signals
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
calib_tap_req : out std_logic;
calib_tap_load : in std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_poc : out std_logic_vector(1023 downto 0);
-- FIFO status flags
phy_mc_ctl_full : out std_logic;
phy_mc_cmd_full : out std_logic;
phy_mc_data_full : out std_logic;
-- Calibration status and resultant outputs
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0)
);
end entity;
architecture arch_ddr_phy_top of mig_7series_v4_0_ddr_phy_top is
-- function to OR the bits in a vectored signal
function OR_BR (inp_var: std_logic_vector)
return std_logic is
variable temp: std_logic := '0';
begin
for idx in inp_var'range loop
temp := temp or inp_var(idx);
end loop;
return temp;
end function;
-- Calculate number of slots in the system
function CALC_nSLOTS return integer is
begin
if (OR_BR(SLOT_1_CONFIG) = '1') then
return (2);
else
return (1);
end if;
end function;
function SIM_INIT_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_INIT");
elsif (SIM_BYPASS_INIT_CAL = "FAST" or
SIM_BYPASS_INIT_CAL = "SIM_FULL") then
return ("SKIP_PU_DLY");
else
return ("NONE");
end if;
end function;
function SIM_CAL_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_CAL");
elsif (SIM_BYPASS_INIT_CAL = "FAST") then
return ("FAST_CAL");
elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or
SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then
return ("FAST_WIN_DETECT");
else
return ("NONE");
end if;
end function;
function CALC_WRLVL_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("OFF");
else
return (WRLVL);
end if;
end function;
function HIGHEST_BANK_W return integer is
begin
if (BYTE_LANES_B4 /= "0000") then
return (5);
elsif (BYTE_LANES_B3 /= "0000") then
return (4);
elsif (BYTE_LANES_B2 /= "0000") then
return (3);
elsif (BYTE_LANES_B1 /= "0000") then
return (2);
else
return (1);
end if;
end function;
function HIGHEST_LANE_B0_W return integer is
begin
if (BYTE_LANES_B0(3) = '1') then
return (4);
elsif (BYTE_LANES_B0(2) = '1') then
return (3);
elsif (BYTE_LANES_B0(1) = '1') then
return (2);
elsif (BYTE_LANES_B0(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B1_W return integer is
begin
if (BYTE_LANES_B1(3) = '1') then
return (4);
elsif (BYTE_LANES_B1(2) = '1') then
return (3);
elsif (BYTE_LANES_B1(1) = '1') then
return (2);
elsif (BYTE_LANES_B1(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B2_W return integer is
begin
if (BYTE_LANES_B2(3) = '1') then
return (4);
elsif (BYTE_LANES_B2(2) = '1') then
return (3);
elsif (BYTE_LANES_B2(1) = '1') then
return (2);
elsif (BYTE_LANES_B2(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B3_W return integer is
begin
if (BYTE_LANES_B3(3) = '1') then
return (4);
elsif (BYTE_LANES_B3(2) = '1') then
return (3);
elsif (BYTE_LANES_B3(1) = '1') then
return (2);
elsif (BYTE_LANES_B3(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B4_W return integer is
begin
if (BYTE_LANES_B4(3) = '1') then
return (4);
elsif (BYTE_LANES_B4(2) = '1') then
return (3);
elsif (BYTE_LANES_B4(1) = '1') then
return (2);
elsif (BYTE_LANES_B4(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_W return integer is
begin
if (HIGHEST_LANE_B4_W /= 0) then
return (HIGHEST_LANE_B4_W+16);
elsif (HIGHEST_LANE_B3_W /= 0) then
return (HIGHEST_LANE_B3_W+12);
elsif (HIGHEST_LANE_B2_W /= 0) then
return (HIGHEST_LANE_B2_W+8);
elsif (HIGHEST_LANE_B1_W /= 0) then
return (HIGHEST_LANE_B1_W+4);
else
return (HIGHEST_LANE_B0_W);
end if;
end function;
function N_CTL_LANES_B0 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B1 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B2 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B3 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B4 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function CTL_BANK_B0 return std_logic is
begin
if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or
(not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or
(not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or
(not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B1 return std_logic is
begin
if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or
(not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or
(not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or
(not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B2 return std_logic is
begin
if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or
(not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or
(not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or
(not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B3 return std_logic is
begin
if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or
(not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or
(not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or
(not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B4 return std_logic is
begin
if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or
(not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or
(not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or
(not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_W return std_logic_vector is
variable ctl_bank_var : std_logic_vector(2 downto 0);
begin
if (CTL_BANK_B0 = '1') then
ctl_bank_var := "000";
elsif (CTL_BANK_B1 = '1') then
ctl_bank_var := "001";
elsif (CTL_BANK_B2 = '1') then
ctl_bank_var := "010";
elsif (CTL_BANK_B3 = '1') then
ctl_bank_var := "011";
elsif (CTL_BANK_B4 = '1') then
ctl_bank_var := "100";
else
ctl_bank_var := "000";
end if;
return (ctl_bank_var);
end function;
function ODD_PARITY (inp_var : std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for idx in inp_var'range loop
tmp := tmp XOR inp_var(idx);
end loop;
return tmp;
end ODD_PARITY;
-- Calculate number of slots in the system
constant nSLOTS : integer := CALC_nSLOTS;
constant CLK_PERIOD : integer := tCK * nCK_PER_CLK;
-- Parameter used to force skipping or abbreviation of initialization
-- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
-- disables various other blocks depending on the option selected
-- This option should only be used during simulation. In the case of
-- the "SKIP" option, the testbench used should also not be modeling
-- propagation delays.
-- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
-- "NONE" = options determined by the individual parameter settings
-- "SIM_FULL" = skip power-up delay. FULL calibration performed without
-- averaging algorithm turned ON during window detection.
-- "SKIP" = skip power-up delay. Skip calibration not yet supported.
-- "FAST" = skip power-up delay, and calibrate (read leveling, write
-- leveling, and phase detector) only using one DQS group, and
-- apply the results to all other DQS groups.
constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W;
constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W;
constant WRLVL_W : string := CALC_WRLVL_W;
constant HIGHEST_BANK : integer := HIGHEST_BANK_W;
-- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W;
-- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W;
-- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W;
-- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W;
-- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W;
constant HIGHEST_LANE : integer := HIGHEST_LANE_W;
constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4;
-- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
-- This should be the case since the PLL should be placed adjacent
-- to the same IO Bank as Ck/Addr/Cmd and Control
constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W;
function CTL_BYTE_LANE_W return std_logic_vector is
variable ctl_byte_lane_var: std_logic_vector(7 downto 0);
begin
if (N_CTL_LANES = 4) then
ctl_byte_lane_var := "11100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00110100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111000";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then
ctl_byte_lane_var := "00000100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001110";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001101";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001000";
else
ctl_byte_lane_var := "11100100";
end if;
return (ctl_byte_lane_var);
end function;
constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W;
function PI_DIV2_INCDEC_FUN return string is
begin
if (DRAM_TYPE = "DDR2") then
return ("FALSE");
elsif ((FPGA_VOLT_TYPE = "L") and (nCK_PER_CLK = 4)) then
return ("TRUE");
else
return ("FALSE");
end if;
end function;
constant PI_DIV2_INCDEC : string := PI_DIV2_INCDEC_FUN;
component mig_7series_v4_0_ddr_mc_phy_wrapper is
generic (
TCQ : integer;
tCK : integer;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN :string;
IODELAY_GRP : string;
FPGA_SPEED_GRADE : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
BANK_WIDTH : integer;
CKE_WIDTH : integer;
CS_WIDTH : integer;
CK_WIDTH : integer;
CWL : integer;
DDR2_DQSN_ENABLE : string;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
RANKS : integer;
ODT_WIDTH : integer;
REG_CTRL : string;
ROW_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IBUF_LPWR_MODE : string;
LP_DDR_CK_WIDTH : integer;
PHYCTL_CMD_FIFO : string;
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
HIGHEST_BANK : integer;
HIGHEST_LANE : integer;
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SIM_CAL_OPTION : string;
MASTER_PHY_CTL : integer;
DRAM_WIDTH : integer;
POC_USE_METASTABLE_SAMP : string;
PI_DIV2_INCDEC : string
);
port (
rst : in std_logic;
iddr_rst : in std_logic;
clk : in std_logic;
clk_div2 : in std_logic;
freq_refclk : in std_logic;
mem_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
mmcm_ps_clk : in std_logic;
idelayctrl_refclk : in std_logic;
phy_cmd_wr_en : in std_logic;
phy_data_wr_en : in std_logic;
phy_ctl_wd : in std_logic_vector(31 downto 0);
phy_ctl_wr : in std_logic;
phy_if_empty_def : in std_logic;
phy_if_reset : in std_logic;
data_offset_1 : in std_logic_vector(5 downto 0);
data_offset_2 : in std_logic_vector(5 downto 0);
aux_in_1 : in std_logic_vector(3 downto 0);
aux_in_2 : in std_logic_vector(3 downto 0);
idelaye2_init_val : out std_logic_vector(4 downto 0);
oclkdelay_init_val : out std_logic_vector(5 downto 0);
if_empty : out std_logic;
phy_ctl_full : out std_logic;
phy_cmd_full : out std_logic;
phy_data_full : out std_logic;
phy_pre_data_a_full : out std_logic;
ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0);
phy_mc_go : out std_logic;
phy_write_calib : in std_logic;
phy_read_calib : in std_logic;
calib_in_common : in std_logic;
calib_sel : in std_logic_vector(5 downto 0);
calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0);
po_fine_enable : in std_logic_vector(2 downto 0);
po_coarse_enable : in std_logic_vector(2 downto 0);
po_fine_inc : in std_logic_vector(2 downto 0);
po_coarse_inc : in std_logic_vector(2 downto 0);
po_counter_load_en : in std_logic;
po_counter_read_en : in std_logic;
po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0);
po_counter_load_val : in std_logic_vector(8 downto 0);
po_counter_read_val : out std_logic_vector(8 downto 0);
pi_counter_read_val : out std_logic_vector(5 downto 0);
pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_fine_enable : in std_logic;
pi_fine_inc : in std_logic;
pi_counter_load_en : in std_logic;
pi_counter_load_val : in std_logic_vector(5 downto 0);
idelay_ce : in std_logic;
idelay_inc : in std_logic;
idelay_ld : in std_logic;
idle : in std_logic;
pi_phase_locked : out std_logic;
pi_phase_locked_all : out std_logic;
pi_dqs_found : out std_logic;
pi_dqs_found_all : out std_logic;
pi_dqs_out_of_range : out std_logic;
phy_init_data_sel : in std_logic;
mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_odt : in std_logic_vector(1 downto 0);
mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
mux_reset_n : in std_logic;
rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_parity : out std_logic;
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_pi_counter_read_en : in std_logic;
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
byte_sel_cnt : in std_logic_vector(DQS_CNT_WIDTH downto 0);
fine_delay_incdec_pb : in std_logic_vector(DRAM_WIDTH-1 downto 0);
fine_delay_sel : in std_logic;
pd_out : out std_logic
);
end component mig_7series_v4_0_ddr_mc_phy_wrapper;
component mig_7series_v4_0_ddr_calib_top is
generic (
TCQ : integer;
nCK_PER_CLK : integer;
tCK : integer;
DDR3_VDD_OP_VOLT : string ;
CLK_PERIOD : integer;
N_CTL_LANES : integer;
DRAM_TYPE : string;
PRBS_WIDTH : integer;
HIGHEST_LANE : integer;
HIGHEST_BANK : integer;
BANK_TYPE : string;
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
CTL_BYTE_LANE : std_logic_vector(7 downto 0);
CTL_BANK : std_logic_vector(2 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
BANK_WIDTH : integer;
CA_MIRROR : string;
COL_WIDTH : integer;
nCS_PER_RANK : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_WIDTH : integer;
ROW_WIDTH : integer;
RANKS : integer;
CS_WIDTH : integer;
CKE_WIDTH : integer;
DDR2_DQSN_ENABLE : string;
PER_BIT_DESKEW : string;
NUM_DQSFOUND_CAL : integer := 1020;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
AL : string;
TEST_AL : string := "0";
ADDR_CMD_MODE : string;
BURST_MODE : string;
BURST_TYPE : string;
nCL : integer;
nCWL : integer;
tRFC : integer;
tREFI : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string;
USE_ODT_PORT : integer;
WRLVL : string;
PRE_REV3ES : string;
SIM_INIT_OPTION : string;
SIM_CAL_OPTION : string;
CKE_ODT_AUX : string;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer;
DEBUG_PORT : string;
SKIP_CALIB : string;
POC_USE_METASTABLE_SAMP : string;
PI_DIV2_INCDEC : string
);
port (
clk : in std_logic;
rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
phy_ctl_ready : in std_logic;
phy_ctl_full : in std_logic;
phy_cmd_full : in std_logic;
phy_data_full : in std_logic;
write_calib : out std_logic;
read_calib : out std_logic;
calib_ctl_wren : out std_logic;
calib_cmd_wren : out std_logic;
calib_seq : out std_logic_vector(1 downto 0);
calib_aux_out : out std_logic_vector(3 downto 0);
calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0);
calib_odt : out std_logic_vector(1 downto 0);
calib_cmd : out std_logic_vector(2 downto 0);
calib_wrdata_en : out std_logic;
calib_rank_cnt : out std_logic_vector(1 downto 0);
calib_cas_slot : out std_logic_vector(1 downto 0);
calib_data_offset_0 : out std_logic_vector(5 downto 0);
calib_data_offset_1 : out std_logic_vector(5 downto 0);
calib_data_offset_2 : out std_logic_vector(5 downto 0);
phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_reset_n : out std_logic;
calib_sel : out std_logic_vector(5 downto 0);
calib_in_common : out std_logic;
calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0);
phy_if_empty_def : out std_logic;
phy_if_reset : out std_logic;
pi_phaselocked : in std_logic;
pi_phase_locked_all : in std_logic;
pi_found_dqs : in std_logic;
pi_dqs_found_all : in std_logic;
pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0);
pi_counter_read_val : in std_logic_vector(5 downto 0);
pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_en_stg2_f : out std_logic;
pi_stg2_f_incdec : out std_logic;
pi_stg2_load : out std_logic;
pi_stg2_reg_l : out std_logic_vector(5 downto 0);
idelay_ce : out std_logic;
idelay_inc : out std_logic;
idelay_ld : out std_logic;
po_sel_stg2stg3 : out std_logic_vector(2 downto 0);
po_stg2_c_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_c : out std_logic_vector(2 downto 0);
po_stg2_f_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_f : out std_logic_vector(2 downto 0);
po_counter_load_en : out std_logic;
po_counter_read_val : in std_logic_vector(8 downto 0);
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
phy_if_empty : in std_logic;
idelaye2_init_val : in std_logic_vector(4 downto 0);
oclkdelay_init_val : in std_logic_vector(5 downto 0);
tg_err : in std_logic;
rst_tg_mc : out std_logic;
phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0);
phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
calib_writes : out std_logic;
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
pi_phase_locked_err : out std_logic;
pi_dqsfound_err : out std_logic;
wrcal_err : out std_logic;
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
poc_sample_pd : in std_logic;
calib_tap_req : out std_logic;
calib_tap_load : in std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
dbg_pi_phaselock_start : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_poc : out std_logic_vector(1023 downto 0);
prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
byte_sel_cnt : out std_logic_vector(DQS_CNT_WIDTH downto 0);
fine_delay_incdec_pb : out std_logic_vector(DRAM_WIDTH-1 downto 0);
fine_delay_sel : out std_logic;
pd_out : in std_logic
);
end component mig_7series_v4_0_ddr_calib_top;
signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0);
signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0);
signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0);
signal phy_mc_go : std_logic;
signal phy_ctl_full : std_logic;
signal phy_cmd_full : std_logic;
signal phy_data_full : std_logic;
signal phy_pre_data_a_full : std_logic;
signal if_empty : std_logic;
signal phy_write_calib : std_logic;
signal phy_read_calib : std_logic;
signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_sel : std_logic_vector(5 downto 0);
signal calib_in_common : std_logic;
signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_phase_locked : std_logic;
signal pi_phase_locked_all : std_logic;
signal pi_found_dqs : std_logic;
signal pi_dqs_found_all : std_logic;
signal pi_dqs_out_of_range : std_logic;
signal pi_enstg2_f : std_logic;
signal pi_stg2_fincdec : std_logic;
signal pi_stg2_load : std_logic;
signal pi_stg2_reg_l : std_logic_vector(5 downto 0);
signal idelay_ce : std_logic;
signal idelay_inc : std_logic;
signal idelay_ld : std_logic;
signal po_sel_stg2stg3 : std_logic_vector(2 downto 0);
signal po_stg2_cincdec : std_logic_vector(2 downto 0);
signal po_enstg2_c : std_logic_vector(2 downto 0);
signal po_stg2_fincdec : std_logic_vector(2 downto 0);
signal po_enstg2_f : std_logic_vector(2 downto 0);
signal po_counter_read_val : std_logic_vector(8 downto 0);
signal pi_counter_read_val : std_logic_vector(5 downto 0);
signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_reset_n : std_logic;
signal calib_aux_out : std_logic_vector(3 downto 0);
signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal calib_odt : std_logic_vector(1 downto 0);
signal calib_ctl_wren : std_logic;
signal calib_cmd_wren : std_logic;
signal calib_wrdata_en : std_logic;
signal calib_cmd : std_logic_vector(2 downto 0);
signal calib_seq : std_logic_vector(1 downto 0);
signal calib_data_offset_0 : std_logic_vector(5 downto 0);
signal calib_data_offset_1 : std_logic_vector(5 downto 0);
signal calib_data_offset_2 : std_logic_vector(5 downto 0);
signal calib_rank_cnt : std_logic_vector(1 downto 0);
signal calib_cas_slot : std_logic_vector(1 downto 0);
signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal mux_aux_out : std_logic_vector(3 downto 0);
signal aux_out_map : std_logic_vector(3 downto 0);
signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal mux_cmd : std_logic_vector(2 downto 0);
signal mux_cmd_wren : std_logic;
signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal mux_ctl_wren : std_logic;
signal mux_cas_slot : std_logic_vector(1 downto 0);
signal mux_data_offset : std_logic_vector(5 downto 0);
signal mux_data_offset_1 : std_logic_vector(5 downto 0);
signal mux_data_offset_2 : std_logic_vector(5 downto 0);
signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_rank_cnt : std_logic_vector(1 downto 0);
signal mux_reset_n : std_logic;
signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
signal mux_wrdata_en : std_logic;
signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_odt : std_logic_vector(1 downto 0);
signal phy_if_empty_def : std_logic;
signal phy_if_reset : std_logic;
signal phy_init_data_sel : std_logic;
signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal phy_rddata_valid_w : std_logic;
signal rddata_valid_reg : std_logic;
signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal idelaye2_init_val : std_logic_vector(4 downto 0);
signal oclkdelay_init_val : std_logic_vector(5 downto 0);
signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0);
signal init_wrcal_complete_i : std_logic;
signal phy_ctl_wd_i : std_logic_vector(31 downto 0);
signal po_counter_load_en : std_logic;
signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0);
signal all_zeros : std_logic_vector(8 downto 0):= (others => '0');
signal byte_sel_cnt : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal fine_delay_incdec_pb : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal fine_delay_sel : std_logic;
signal pd_out : std_logic;
-- 3-stage synchronizer registers
signal pi_fine_enable : std_logic;
signal pi_fine_inc : std_logic;
signal pi_counter_load_en : std_logic;
signal pi_counter_load_val : std_logic_vector(5 downto 0);
signal pi_rst_dqs_find : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_enstg2_f_div2r1 : std_logic;
signal pi_enstg2_f_div2r2 : std_logic;
signal pi_enstg2_f_div2r3 : std_logic;
signal pi_stg2_fincdec_div2r1 : std_logic;
signal pi_stg2_fincdec_div2r2 : std_logic;
signal pi_stg2_fincdec_div2r3 : std_logic;
signal pi_stg2_load_div2r1 : std_logic;
signal pi_stg2_load_div2r2 : std_logic;
signal pi_stg2_load_div2r3 : std_logic;
signal rst_stg1_cal_div2r1 : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal rst_stg1_cal_div2r2 : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_stg2_reg_l_div2r1 : std_logic_vector(5 downto 0);
signal pi_stg2_reg_l_div2r2 : std_logic_vector(5 downto 0);
signal pi_stg2_reg_l_div2r3 : std_logic_vector(5 downto 0);
signal pi_dqs_find_rst : std_logic_vector(HIGHEST_BANK-1 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of pi_fine_enable : signal is "TRUE";
attribute ASYNC_REG of pi_fine_inc : signal is "TRUE";
attribute ASYNC_REG of pi_counter_load_en : signal is "TRUE";
attribute ASYNC_REG of pi_counter_load_val : signal is "TRUE";
attribute ASYNC_REG of pi_rst_dqs_find : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r3 : signal is "TRUE";
attribute ASYNC_REG of rst_stg1_cal_div2r1 : signal is "TRUE";
attribute ASYNC_REG of rst_stg1_cal_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_dqs_find_rst : signal is "TRUE";
signal pi_stg2_fine_enable, pi_stg2_fine_enable_r1 : std_logic;
signal pi_stg2_fine_inc, pi_stg2_fine_inc_r1 : std_logic;
signal pi_stg2_load_en, pi_stg2_load_en_r1 : std_logic;
signal pi_stg2_load_val : std_logic_vector(5 downto 0);
begin
--***************************************************************************
dbg_rddata_valid <= rddata_valid_reg;
dbg_rddata <= rd_data_reg;
dbg_rd_data_offset <= calib_rd_data_offset_i0;
calib_rd_data_offset_0 <= calib_rd_data_offset_i0;
dbg_pi_phaselocked_done <= pi_phase_locked_all;
dbg_po_counter_read_val <= po_counter_read_val;
dbg_pi_counter_read_val <= pi_counter_read_val;
dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i;
init_wrcal_complete <= init_wrcal_complete_i;
--***************************************************************************
--***************************************************************************
-- Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec
--***************************************************************************
div2_incdec : if (PI_DIV2_INCDEC = "TRUE") generate
-- 3-stage synchronizer
process (clk_div2) begin
if (rising_edge(clk_div2)) then
-- Phaser_In fine enable
pi_enstg2_f_div2r1 <= pi_enstg2_f after (TCQ) * 1 ps;
pi_enstg2_f_div2r2 <= pi_enstg2_f_div2r1 after (TCQ) * 1 ps;
pi_enstg2_f_div2r3 <= pi_enstg2_f_div2r2 after (TCQ) * 1 ps;
-- Phaser_In fine incdec
pi_stg2_fincdec_div2r1 <= pi_stg2_fincdec after (TCQ) * 1 ps;
pi_stg2_fincdec_div2r2 <= pi_stg2_fincdec_div2r1 after (TCQ) * 1 ps;
pi_stg2_fincdec_div2r3 <= pi_stg2_fincdec_div2r2 after (TCQ) * 1 ps;
-- Phaser_In stage2 load
pi_stg2_load_div2r1 <= pi_stg2_load after (TCQ) * 1 ps;
pi_stg2_load_div2r2 <= pi_stg2_load_div2r1 after (TCQ) * 1 ps;
pi_stg2_load_div2r3 <= pi_stg2_load_div2r2 after (TCQ) * 1 ps;
-- Phaser_In stage2 load value
pi_stg2_reg_l_div2r1 <= pi_stg2_reg_l after (TCQ) * 1 ps;
pi_stg2_reg_l_div2r2 <= pi_stg2_reg_l_div2r1 after (TCQ) * 1 ps;
pi_stg2_reg_l_div2r3 <= pi_stg2_reg_l_div2r2 after (TCQ) * 1 ps;
-- Phaser_In reset DQSFOUND
rst_stg1_cal_div2r1 <= rst_stg1_cal after (TCQ) * 1 ps;
rst_stg1_cal_div2r2 <= rst_stg1_cal_div2r1 after (TCQ) * 1 ps;
pi_dqs_find_rst <= rst_stg1_cal_div2r2 after (TCQ) * 1 ps;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
pi_stg2_fine_enable_r1 <= pi_stg2_fine_enable after (TCQ) * 1 ps;
pi_stg2_fine_inc_r1 <= pi_stg2_fine_inc after (TCQ) * 1 ps;
pi_stg2_load_en_r1 <= pi_stg2_load_en after (TCQ) * 1 ps;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_fine_enable = '1') or (pi_stg2_fine_enable_r1 = '1')) then
pi_stg2_fine_enable <= '0' after (TCQ) * 1 ps;
elsif (pi_enstg2_f_div2r3 = '1') then
pi_stg2_fine_enable <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_fine_inc = '1') or (pi_stg2_fine_inc_r1 = '1')) then
pi_stg2_fine_inc <= '0' after (TCQ) * 1 ps;
elsif (pi_stg2_fincdec_div2r3 = '1') then
pi_stg2_fine_inc <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
pi_stg2_load_en <= '0' after (TCQ) * 1 ps;
elsif (pi_stg2_load_div2r3 = '1') then
pi_stg2_load_en <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
pi_stg2_load_val <= (others => '0') after (TCQ) * 1 ps;
elsif (pi_stg2_load_div2r3 = '1') then
pi_stg2_load_val <= pi_stg2_reg_l_div2r3 after (TCQ) * 1 ps;
end if;
end if;
end process;
pi_fine_enable <= pi_stg2_fine_enable;
pi_fine_inc <= pi_stg2_fine_inc;
pi_counter_load_en <= pi_stg2_load_en;
pi_counter_load_val <= pi_stg2_load_val;
pi_rst_dqs_find <= pi_dqs_find_rst;
end generate div2_incdec;
div4_incdec : if (PI_DIV2_INCDEC = "FALSE") generate
pi_fine_enable <= pi_enstg2_f;
pi_fine_inc <= pi_stg2_fincdec;
pi_counter_load_en <= pi_stg2_load;
pi_counter_load_val <= pi_stg2_reg_l;
pi_rst_dqs_find <= rst_stg1_cal;
end generate div4_incdec;
--***************************************************************************
clock_gen : for i in 0 to (CK_WIDTH-1) generate
ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i);
ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1);
end generate;
--***************************************************************************
-- During memory initialization and calibration the calibration logic drives
-- the memory signals. After calibration is complete the memory controller
-- drives the memory signals.
-- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
--***************************************************************************
cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate
cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate
cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate
mc_cs_n_temp(v) <= mc_cs_n(v) ;
end generate;
cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate
mc_cs_n_temp(v) <= '1' ;
end generate;
end generate;
end generate;
cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate
mc_cs_n_temp <= mc_cs_n ;
end generate;
mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata;
mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0');
mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address;
mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank;
mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n;
mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n;
mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n;
mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n;
mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n;
mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out;
mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt;
mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke;
mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren;
mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren;
mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en;
mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd;
mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot;
mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0;
mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1;
mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2;
-- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
mux_rank_cnt <= "00";
-- Assigning cke & odt for DDR2 & DDR3
-- No changes for DDR3 & DDR2 dual rank
-- DDR2 single rank systems might potentially need 3 odt signals.
-- Aux_out[2] will have the odt toggled by phy and controller
-- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
-- all of the three odt bits or some of them might be used.
-- mapping done in mc_phy_wrapper module
aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate
aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) &
mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and
(RANKS = 1)) else
mux_aux_out;
end generate;
wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate
aux_out_map <= "0000";
end generate;
init_calib_complete <= phy_init_data_sel;
phy_mc_ctl_full <= phy_ctl_full;
phy_mc_cmd_full <= phy_cmd_full;
phy_mc_data_full <= phy_pre_data_a_full;
--***************************************************************************
-- Generate parity for DDR3 RDIMM.
--***************************************************************************
gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate
parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) &
mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) &
mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3));
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) &
mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) &
mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2));
process (clk)
begin
if (clk'event and clk = '1') then
parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps;
end if;
end process;
process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps;
end process;
end generate;
gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
end if;
end process;
process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
end process;
end generate;
end generate;
gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
parity(2) <= '0' after (TCQ)*1 ps;
parity(3) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
end generate;
--***************************************************************************
-- Code for optional register stage in read path to MC for timing
--***************************************************************************
RD_REG_TIMING : if(RD_PATH_REG = 1) generate
process (clk)
begin
if (clk'event and clk='1') then
rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps;
rd_data_reg <= rd_data_map after (TCQ)*1 ps;
end if;
end process;
end generate;
RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate
process (phy_rddata_valid_w, rd_data_map)
begin
rddata_valid_reg <= phy_rddata_valid_w;
rd_data_reg <= rd_data_map;
end process;
end generate;
phy_rddata_valid <= rddata_valid_reg;
phy_rd_data <= rd_data_reg;
--***************************************************************************
-- Hard PHY and accompanying bit mapping logic
--***************************************************************************
phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset &
mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd);
u_ddr_mc_phy_wrapper : mig_7series_v4_0_ddr_mc_phy_wrapper
generic map (
TCQ => TCQ,
tCK => tCK,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP => IODELAY_GRP,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
DATA_IO_IDLE_PWRDWN=> DATA_IO_IDLE_PWRDWN,
nCK_PER_CLK => nCK_PER_CLK,
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
CK_WIDTH => CK_WIDTH,
CWL => CWL,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
DM_WIDTH => DM_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
REG_CTRL => REG_CTRL,
ROW_WIDTH => ROW_WIDTH,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH,
PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
HIGHEST_BANK => HIGHEST_BANK,
HIGHEST_LANE => HIGHEST_LANE,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CKE_ODT_AUX => CKE_ODT_AUX,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
SIM_CAL_OPTION => SIM_CAL_OPTION,
MASTER_PHY_CTL => MASTER_PHY_CTL,
DRAM_WIDTH => DRAM_WIDTH,
POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
PI_DIV2_INCDEC => PI_DIV2_INCDEC
)
port map (
rst => rst,
iddr_rst => iddr_rst,
clk => clk,
clk_div2 => clk_div2,
-- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
-- For memory frequencies below 400 MHz mem_refclk = mem_refclk and
-- freq_refclk = 2x or 4x mem_refclk such that it remains in the
-- 400~1066 MHz range
freq_refclk => freq_refclk,
mem_refclk => mem_refclk,
pll_lock => pll_lock,
sync_pulse => sync_pulse,
mmcm_ps_clk => mmcm_ps_clk,
idelayctrl_refclk => clk_ref,
phy_cmd_wr_en => mux_cmd_wren,
phy_data_wr_en => mux_wrdata_en,
-- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
-- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
-- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
-- The fields ACTPRE, and BankCount are only used
-- when the hard PHY counters are used by the MC.
phy_ctl_wd => phy_ctl_wd_i,
phy_ctl_wr => mux_ctl_wren,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
data_offset_1 => mux_data_offset_1,
data_offset_2 => mux_data_offset_2,
aux_in_1 => aux_out_map,
aux_in_2 => aux_out_map,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
if_empty => if_empty,
phy_ctl_full => phy_ctl_full,
phy_cmd_full => phy_cmd_full,
phy_data_full => phy_data_full,
phy_pre_data_a_full => phy_pre_data_a_full,
ddr_clk => ddr_clk,
phy_mc_go => phy_mc_go,
phy_write_calib => phy_write_calib,
phy_read_calib => phy_read_calib,
calib_in_common => calib_in_common,
calib_sel => calib_sel,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
po_fine_enable => po_enstg2_f,
po_coarse_enable => po_enstg2_c,
po_fine_inc => po_stg2_fincdec,
po_coarse_inc => po_stg2_cincdec,
po_counter_load_en => po_counter_load_en,
po_counter_read_en => '1',
po_sel_fine_oclk_delay => po_sel_stg2stg3,
po_counter_load_val => all_zeros,
po_counter_read_val => po_counter_read_val,
pi_counter_read_val => pi_counter_read_val,
pi_rst_dqs_find => pi_rst_dqs_find,
pi_fine_enable => pi_fine_enable,
pi_fine_inc => pi_fine_inc,
pi_counter_load_en => pi_counter_load_en,
pi_counter_load_val => pi_counter_load_val,
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
idle => idle,
pi_phase_locked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_dqs_found => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
-- Currently not being used. May be used in future if periodic reads
-- become a requirement. This output could also be used to signal a
-- catastrophic failure in read capture and the need for re-cal
pi_dqs_out_of_range => pi_dqs_out_of_range,
phy_init_data_sel => phy_init_data_sel,
mux_address => mux_address,
mux_bank => mux_bank,
mux_cas_n => mux_cas_n,
mux_cs_n => mux_cs_n,
mux_ras_n => mux_ras_n,
mux_odt => mux_odt,
mux_cke => mux_cke,
mux_we_n => mux_we_n,
parity_in => parity,
mux_wrdata => mux_wrdata,
mux_wrdata_mask => mux_wrdata_mask,
mux_reset_n => mux_reset_n,
rd_data => rd_data_map,
ddr_addr => ddr_addr,
ddr_ba => ddr_ba,
ddr_cas_n => ddr_cas_n,
ddr_cke => ddr_cke,
ddr_cs_n => ddr_cs_n,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
ddr_parity => ddr_parity,
ddr_ras_n => ddr_ras_n,
ddr_we_n => ddr_we_n,
ddr_reset_n => ddr_reset_n,
ddr_dq => ddr_dq,
ddr_dqs => ddr_dqs,
ddr_dqs_n => ddr_dqs_n,
dbg_pi_counter_read_en => '1',
ref_dll_lock => ref_dll_lock,
rst_phaser_ref => rst_phaser_ref,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i,
byte_sel_cnt => byte_sel_cnt,
fine_delay_incdec_pb => fine_delay_incdec_pb,
fine_delay_sel => fine_delay_sel,
pd_out => pd_out
);
--***************************************************************************
-- Soft memory initialization and calibration logic
--***************************************************************************
u_ddr_calib_top : mig_7series_v4_0_ddr_calib_top
generic map (
TCQ => TCQ,
DDR3_VDD_OP_VOLT => DDR3_VDD_OP_VOLT,
nCK_PER_CLK => nCK_PER_CLK,
tCK => tCK,
CLK_PERIOD => CLK_PERIOD,
N_CTL_LANES => N_CTL_LANES,
DRAM_TYPE => DRAM_TYPE,
PRBS_WIDTH => 8,
HIGHEST_LANE => HIGHEST_LANE,
HIGHEST_BANK => HIGHEST_BANK,
BANK_TYPE => BANK_TYPE,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
DQS_BYTE_MAP => DQS_BYTE_MAP,
CTL_BYTE_LANE => CTL_BYTE_LANE,
CTL_BANK => CTL_BANK,
SLOT_1_CONFIG => SLOT_1_CONFIG,
BANK_WIDTH => BANK_WIDTH,
CA_MIRROR => CA_MIRROR,
COL_WIDTH => COL_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
ROW_WIDTH => ROW_WIDTH,
RANKS => RANKS,
CS_WIDTH => CS_WIDTH,
CKE_WIDTH => CKE_WIDTH,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
PER_BIT_DESKEW => "OFF",
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
AL => AL,
ADDR_CMD_MODE => ADDR_CMD_MODE,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
nCL => CL,
nCWL => CWL,
tRFC => tRFC,
tREFI => tREFI,
OUTPUT_DRV => OUTPUT_DRV,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
RTT_WR => RTT_WR,
USE_ODT_PORT => USE_ODT_PORT,
WRLVL => WRLVL_W,
PRE_REV3ES => PRE_REV3ES,
SIM_INIT_OPTION => SIM_INIT_OPTION,
SIM_CAL_OPTION => SIM_CAL_OPTION,
CKE_ODT_AUX => CKE_ODT_AUX,
DEBUG_PORT => DEBUG_PORT,
IDELAY_ADJ => IDELAY_ADJ,
FINE_PER_BIT => FINE_PER_BIT,
CENTER_COMP_MODE => CENTER_COMP_MODE,
PI_VAL_ADJ => PI_VAL_ADJ,
TAPSPERKCLK => TAPSPERKCLK,
SKIP_CALIB => SKIP_CALIB,
POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
PI_DIV2_INCDEC => PI_DIV2_INCDEC
)
port map (
clk => clk,
rst => rst,
slot_0_present => slot_0_present,
slot_1_present => slot_1_present,
-- PHY Control Block and IN_FIFO status
phy_ctl_ready => phy_mc_go,
phy_ctl_full => '0',
phy_cmd_full => '0',
phy_data_full => '0',
-- hard PHY calibration modes
write_calib => phy_write_calib,
read_calib => phy_read_calib,
-- Signals from calib logic to be MUXED with MC
-- signals before sending to hard PHY
calib_ctl_wren => calib_ctl_wren,
calib_cmd_wren => calib_cmd_wren,
calib_seq => calib_seq,
calib_aux_out => calib_aux_out,
calib_odt => calib_odt,
calib_cke => calib_cke,
calib_cmd => calib_cmd,
calib_wrdata_en => calib_wrdata_en,
calib_rank_cnt => calib_rank_cnt,
calib_cas_slot => calib_cas_slot,
calib_data_offset_0 => calib_data_offset_0,
calib_data_offset_1 => calib_data_offset_1,
calib_data_offset_2 => calib_data_offset_2,
phy_address => phy_address,
phy_bank => phy_bank,
phy_cs_n => phy_cs_n,
phy_ras_n => phy_ras_n,
phy_cas_n => phy_cas_n,
phy_we_n => phy_we_n,
phy_reset_n => phy_reset_n,
-- DQS count and ck/addr/cmd to be mapped to calib_sel
-- based on parameter that defines placement of ctl lanes
-- and DQS byte groups in each bank. When phy_write_calib
-- is de-asserted calib_sel should select CK/addr/cmd/ctl.
calib_sel => calib_sel,
calib_in_common => calib_in_common,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
-- DQS Phaser_IN calibration/status signals
pi_phaselocked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_found_dqs => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i(HIGHEST_LANE-1 downto 0),
pi_rst_stg1_cal => rst_stg1_cal,
pi_en_stg2_f => pi_enstg2_f,
pi_stg2_f_incdec => pi_stg2_fincdec,
pi_stg2_load => pi_stg2_load,
pi_stg2_reg_l => pi_stg2_reg_l,
pi_counter_read_val => pi_counter_read_val,
device_temp => device_temp,
tempmon_sample_en => tempmon_sample_en,
-- IDELAY tap enable and inc signals
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
-- DQS Phaser_OUT calibration/status signals
po_sel_stg2stg3 => po_sel_stg2stg3,
po_stg2_c_incdec => po_stg2_cincdec,
po_en_stg2_c => po_enstg2_c,
po_stg2_f_incdec => po_stg2_fincdec,
po_en_stg2_f => po_enstg2_f,
po_counter_load_en => po_counter_load_en,
po_counter_read_val => po_counter_read_val,
phy_if_empty => if_empty,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
tg_err => error,
rst_tg_mc => rst_tg_mc,
phy_wrdata => phy_wrdata,
-- From calib logic To data IN_FIFO
-- DQ IDELAY tap value from Calib logic
-- port to be added to mc_phy by Gary
dlyval_dq => open,
-- From data IN_FIFO To Calib logic and MC/UI
phy_rddata => rd_data_map,
-- From calib logic To MC
phy_rddata_valid => phy_rddata_valid_w,
calib_rd_data_offset_0 => calib_rd_data_offset_i0,
calib_rd_data_offset_1 => calib_rd_data_offset_1,
calib_rd_data_offset_2 => calib_rd_data_offset_2,
calib_writes => open,
-- Mem Init and Calibration status To MC
init_calib_complete => phy_init_data_sel,
init_wrcal_complete => init_wrcal_complete_i,
-- Debug Error signals
pi_phase_locked_err => dbg_pi_phaselock_err,
pi_dqsfound_err => dbg_pi_dqsfound_err,
wrcal_err => dbg_wrcal_err,
-- MMCM phase shift clock control
psen => psen,
psincdec => psincdec,
psdone => psdone,
poc_sample_pd => poc_sample_pd,
-- skip calibration
calib_tap_req => calib_tap_req,
calib_tap_load => calib_tap_load,
calib_tap_addr => calib_tap_addr,
calib_tap_val => calib_tap_val,
calib_tap_load_done => calib_tap_load_done,
-- Debug Signals
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_calib_top => dbg_calib_top,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_poc => dbg_poc,
prbs_final_dqs_tap_cnt_r => prbs_final_dqs_tap_cnt_r,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps,
byte_sel_cnt => byte_sel_cnt,
fine_delay_incdec_pb => fine_delay_incdec_pb,
fine_delay_sel => fine_delay_sel,
pd_out => pd_out
);
end architecture arch_ddr_phy_top;
| mit |
fabioperez/space-invaders-vhdl | lib/pc.vhd | 1 | 3176 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- PLAYER CONTROLLER
--------------------------------------------------------------------------------
-- TODO:
-- Remove output clock_o;
-- Define constants/generics instead of magic numbers
-- Change aux_x/aux_y to something more explanatory
--------------------------------------------------------------------------------
entity pc is
generic
(
-- screen limits (follows game resolution)
res_x : integer := 160;
res_y : integer := 120;
-- used to take into account the dimensions of the ship
aux_y : integer := 0;
aux_x : integer := 1;
-- y-position of the player ship
pos_y : integer := 5;
-- clock divider
clock_div : integer := 2
);
port
(
-- input commands for reset or movement
reset_i, enable_i : in std_logic;
-- movement direction ('0' = left, 1' = right)
right_flag_i : in std_logic;
-- clock input
clock_i : in std_logic;
-- player position output
clock_o : out std_logic; -- TODO: remove
position_x_o : buffer integer range 0 to res_x;
position_y_o : out integer range 0 to res_y
);
end entity;
architecture behavior of pc is
-- clock signal for updating x position
signal clock_s : std_logic;
begin
-- counter that generates the clock signal for updating x position
pc_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
-- register: keeps the position of the player ship
pc_movement:
process (reset_i, enable_i,clock_s)
begin
-- asynchronous reset of x coordinate
if reset_i = '1' then
position_x_o <= res_x/2 - aux_x/2;
else
-- move the ship according to right_flag_i input
if rising_edge(clock_s) and enable_i ='1' then
if right_flag_i = '1' then
position_x_o <= position_x_o + 1; -- move right
elsif right_flag_i = '0' then
position_x_o <= position_x_o - 1; -- move left
end if;
-- check boundaries
if position_x_o + aux_x > res_x-5 then
position_x_o <= res_x-aux_x-5;
end if;
if position_x_o < 5 then
position_x_o <= 5;
end if;
end if;
end if;
end process;
-- updates output position with new y-position
position_y_o <= pos_y + aux_y/2;
end architecture;
| mit |
SLongofono/Senior_Design_Capstone | hdl/system_top.vhd | 1 | 9545 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 04/21/2018 01:23:15 PM
-- Module Name: system_top - Behavioral
-- Description: System-level wrapper for processor components
--
-- Additional Comments: "Death must be so beautiful. To lie in te soft brown earth,
-- with the grasses waving above one's head, and listen to
-- silence. To have no yesterday, and no tomorrow. To forget
-- time, to forget life, to forget Vivado, to be at peace."
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.config.all;
entity system_top is
Port(
clk: in std_logic;
rst: in std_logic;
status: out std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end system_top;
architecture Behavioral of system_top is
--------------------------------------------------------------------------------
-- Components Forward Declarations
--------------------------------------------------------------------------------
component simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
MMU_addr_in: out doubleword; -- 64-bits address for load/store
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_store: out std_logic; -- High to toggle store
MMU_load: out std_logic; -- High to toggle load
MMU_busy: in std_logic; -- High when busy
MMU_ready_instr: out std_logic; -- Ready for a new instruction (initiates fetch)
MMU_addr_instr: out doubleword; -- Instruction Address (AKA PC)
MMU_alignment: out std_logic_vector(3 downto 0);-- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_instr_out: in doubleword; -- 64-Bits instruction out for fetch
MMU_error: in std_logic_vector(5 downto 0) -- Error bits from MMU
);
end component;
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out doubleword; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end component;
--------------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------------
signal s_MMU_addr_in: doubleword; -- 64-bits address for load/store
signal s_MMU_data_in: doubleword; -- 64-bits data for store
signal s_MMU_satp: doubleword; -- Signals address translation privilege
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
signal s_MMU_store: std_logic; -- High to toggle store
signal s_MMU_load: std_logic; -- High to toggle load
signal s_MMU_busy: std_logic; -- High when busy
signal s_MMU_ready_instr: std_logic; -- Ready for a new instruction (initiates fetch)
signal s_MMU_addr_instr: doubleword; -- Instruction Address (AKA PC)
signal s_MMU_alignment: std_logic_vector(3 downto 0);-- alignment in bytes
signal s_MMU_data_out: doubleword; -- 64-Bits data out for load
signal s_MMU_instr_out: doubleword; -- 64-Bits instruction out for fetch
signal s_MMU_error: std_logic_vector(5 downto 0); -- Error bits from MMU
begin
--------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------
bestCore: simple_core
port map(
status => status,
clk => clk,
rst => rst,
MMU_addr_in => s_MMU_addr_in,
MMU_data_in => s_MMU_data_in,
MMU_satp => s_MMU_satp,
MMU_mode => s_MMU_mode,
MMU_store => s_MMU_store,
MMU_load => s_MMU_load,
MMU_busy => s_MMU_busy,
MMU_ready_instr => s_MMU_ready_instr,
MMU_addr_instr => s_MMU_addr_instr,
MMU_alignment => s_MMU_alignment,
MMU_data_out => s_MMU_data_out,
MMU_instr_out => s_MMU_instr_out,
MMU_error => s_MMU_error
);
memmy: MMU
port map(
clk => clk,
rst => rst,
addr_in => s_MMU_addr_in,
data_in => s_MMU_data_in,
satp => s_MMU_satp,
mode => s_MMU_mode,
store => s_MMU_store,
load => s_MMU_load,
busy => s_MMU_busy,
ready_instr => s_MMU_ready_instr,
addr_instr => s_MMU_addr_instr,
alignment => s_MMU_alignment,
data_out => s_MMU_data_out,
instr_out => s_MMU_instr_out,
error => s_MMU_error,
LED => LED,
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
sck => sck,
cs_n => cs_n,
dq => dq
);
--------------------------------------------------------------------------------
-- Do Work
--------------------------------------------------------------------------------
end Behavioral;
| mit |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ram2ddrxadc.vhd | 2 | 19856 | -------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddrxadc.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity ram2ddrxadc is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end ram2ddrxadc;
architecture Behavioral of ram2ddrxadc is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
--device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stSetCmd, stCheckRdy, stWaitRdy, stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
-- address for current request
signal mem_addr : std_logic_vector(26 downto 0);
-- command for current request
signal mem_cmd : std_logic_vector(2 downto 0);
-- active-high strobe for 'cmd' and 'addr'
signal mem_en : std_logic;
signal mem_rdy : std_logic;
-- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_rdy : std_logic;
signal mem_wdf_data : std_logic_vector(63 downto 0);
-- active-high last 'wdf_data'
signal mem_wdf_end : std_logic;
signal mem_wdf_mask : std_logic_vector(7 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(63 downto 0);
-- active-high last 'rd_data'
signal mem_rd_data_end : std_logic;
-- active-high 'rd_data' valid
signal mem_rd_data_valid : std_logic;
-- active-high calibration complete
signal mem_init_calib_complete : std_logic;
-- delayed valid
signal rd_vld : std_logic;
-- delayed end
signal rd_end : std_logic;
-- delayed data
signal rd_data_1, rd_data_2 : std_logic_vector(63 downto 0);
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
--attribute KEEP : string;
--attribute KEEP of mem_addr : signal is "TRUE";
--attribute KEEP of mem_cmd : signal is "TRUE";
--attribute KEEP of mem_en : signal is "TRUE";
--attribute KEEP of mem_wdf_data : signal is "TRUE";
--attribute KEEP of mem_wdf_end : signal is "TRUE";
--attribute KEEP of mem_wdf_mask : signal is "TRUE";
--attribute KEEP of mem_wdf_wren : signal is "TRUE";
--attribute KEEP of mem_rd_data : signal is "TRUE";
--attribute KEEP of mem_rd_data_end : signal is "TRUE";
--attribute KEEP of mem_rd_data_valid : signal is "TRUE";
--attribute KEEP of mem_rdy : signal is "TRUE";
--attribute KEEP of mem_wdf_rdy : signal is "TRUE";
--attribute KEEP of mem_init_calib_complete : signal is "TRUE";
--attribute KEEP of temp : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering all inputs
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: ddr
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
--device_temp_i => device_temp_i,
init_calib_complete => mem_init_calib_complete);
rstn <= not rst_i;
rst <= rst_i or mem_ui_rst;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Synchronous process
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- State machine transitions
NEXT_STATE_DECODE: process(cState, mem_init_calib_complete, mem_rdy,
mem_wdf_rdy, ram_cen_int, ram_oen_int, ram_wen_int)
begin
nState <= cState;
case(cState) is
when stIdle =>
if mem_init_calib_complete = '1' then -- memory initialized
if mem_rdy = '1' then -- check for memory ready
if mem_wdf_rdy = '1' then -- write ready
if ram_cen_int = '0' and
(ram_oen_int = '0' or ram_wen_int = '0') then
nState <= stSetCmd;
end if;
end if;
end if;
end if;
when stSetCmd =>
nState <= stCheckRdy;
when stCheckRdy => -- check for memory ready
if mem_rdy = '0' then
nState <= stWaitRdy;
else
nState <= stWaitCen;
end if;
when stWaitRdy =>
if mem_rdy = '1' then -- wait for memory ready
nState <= stWaitCen;
end if;
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others =>
nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Memory control signals
------------------------------------------------------------------------
MEM_CTL: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stIdle or cState = stWaitCen then
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
mem_en <= '0';
elsif cState = stSetCmd then
-- ui command
if ram_wen_int = '0' then -- write
mem_cmd <= CMD_WRITE;
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
mem_en <= '1';
elsif ram_oen_int = '0' then -- read
mem_cmd <= CMD_READ;
mem_en <= '1';
end if;
end if;
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Address decoder that forms the data mask
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stCheckRdy then
case(ram_a_int(2 downto 1)) is
when "00" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11111110";
else -- 16-bit
mem_wdf_mask <= "11111100";
end if;
when "01" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11111011";
else -- 16-bit
mem_wdf_mask <= "11110011";
end if;
when "10" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11101111";
else -- 16-bit
mem_wdf_mask <= "11001111";
end if;
when "11" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "01111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "10111111";
else -- 16-bit
mem_wdf_mask <= "00111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Write data and address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stCheckRdy then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
mem_addr <= ram_a_int(26 downto 3) & "000";
end if;
end if;
end process WR_DATA_ADDR;
------------------------------------------------------------------------
-- Mask the data output
------------------------------------------------------------------------
-- delay stage for the valid and end signals (for an even better
-- synchronization)
SYNC: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
rd_vld <= mem_rd_data_valid;
rd_end <= mem_rd_data_end;
rd_data_1 <= mem_rd_data;
rd_data_2 <= rd_data_1;
end if;
end process SYNC;
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if rst = '1' then
ram_dq_o <= (others => '0');
elsif cState = stWaitCen and rd_vld = '1' and rd_end = '1' then
case(ram_a_int(2 downto 1)) is
when "00" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(15 downto 8) &
rd_data_2(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(7 downto 0) &
rd_data_2(7 downto 0);
else -- 16-bit
ram_dq_o <= rd_data_2(15 downto 0);
end if;
when "01" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(31 downto 24) &
rd_data_2(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(23 downto 16) &
rd_data_2(23 downto 16);
else -- 16-bit
ram_dq_o <= rd_data_2(31 downto 16);
end if;
when "10" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(47 downto 40) &
rd_data_2(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(39 downto 32) &
rd_data_2(39 downto 32);
else -- 16-bit
ram_dq_o <= rd_data_2(47 downto 32);
end if;
when "11" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(63 downto 56) &
rd_data_2(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(55 downto 48) &
rd_data_2(55 downto 48);
else -- 16-bit
ram_dq_o <= rd_data_2(63 downto 48);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
| mit |
WebWorkDeveloper/SQL-editor | public/src/libs/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| mit |
SLongofono/Senior_Design_Capstone | StupidCore/UART_TX_CTRL.vhd | 1 | 4747 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit |
fabioperez/space-invaders-vhdl | lib/io/keyboard.vhd | 1 | 2172 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
ARCHITECTURE a OF keyboard IS
SIGNAL INCNT : std_logic_vector(3 downto 0);
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
SIGNAL READ_CHAR : std_logic;
SIGNAL INFLAG, ready_set : std_logic;
SIGNAL keyboard_clk_filtered : std_logic;
SIGNAL filter : std_logic_vector(7 downto 0);
BEGIN
PROCESS (read, ready_set)
BEGIN
IF read = '1' THEN scan_ready <= '0';
ELSIF ready_set'EVENT and ready_set = '1' THEN
scan_ready <= '1';
END IF;
END PROCESS;
--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
Clock_filter: PROCESS
BEGIN
WAIT UNTIL clock_25Mhz'EVENT AND clock_25Mhz= '1';
filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
filter(7) <= keyboard_clk;
IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
ELSIF filter= "00000000" THEN keyboard_clk_filtered <= '0';
END IF;
END PROCESS Clock_filter;
--This process reads in serial data coming from the terminal
PROCESS
BEGIN
WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
IF RESET='1' THEN
INCNT <= "0000";
READ_CHAR <= '0';
ELSE
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
READ_CHAR<= '1';
ready_set<= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1;
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
SHIFTIN(8) <= KEYBOARD_DATA;
ready_set <= '0';
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN(7 DOWNTO 0);
READ_CHAR <='0';
ready_set <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
| mit |
SLongofono/Senior_Design_Capstone | hdl/decode.vhd | 2 | 22081 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Decode Unit
-- Determines the intruction type
-- Parses out all possible fields (whether or not they are relevant)
-- May sign extend and prepare a full immediate address, I'm not sure if
-- this is the right place to do this yet. For now, just pulls the 12 or 20 bit
-- raw immediate value based on instruction type. See config.vhd for typedefs and constants
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end decode;
architecture Behavioral of decode is
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_instr_t: instr_t;
signal s_shamt: std_logic_vector(4 downto 0);
signal s_csr: std_logic_vector(11 downto 0);
begin
-- Update instruction type whenever it changes
process(instr)
begin
s_imm12 <= (others => '0');
s_imm20 <= (others => '0');
s_instr_t<= (others => '1');
s_shamt <= (others => '0');
s_csr <= (others => '0');
case instr(6 downto 0) is
when LUI_T =>
s_instr_t <= instr_LUI;
s_imm20 <= instr(31 downto 12);
when AUIPC_T =>
s_instr_t <= instr_AUIPC;
s_imm20 <= instr(31 downto 12);
when JAL_T =>
s_instr_t <= instr_JAL;
s_imm20 <= instr(31) & instr(19 downto 12) & instr(20) & instr(30 downto 21);
when JALR_T =>
s_instr_t <= instr_JALR;
s_imm12 <= instr(31 downto 20);
when BRANCH_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_BEQ;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "001" =>
s_instr_t <= instr_BNE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "100" =>
s_instr_t <= instr_BLT;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "101" =>
s_instr_t <= instr_BGE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "110" =>
s_instr_t <= instr_BLTU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "111" =>
s_instr_t <= instr_BGEU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when others => -- error state
end case;
when LOAD_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_LB;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_LH;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_LW;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_LBU;
s_imm12 <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_LHU;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_LWU;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_LD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when STORE_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_SB;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "001" =>
s_instr_t <= instr_SH;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "010" =>
s_instr_t <= instr_SW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_SD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => -- error state
end case;
when ALUI_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDI;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_SLTI;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_SLTIU;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_XORI;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_ORI;
s_imm12 <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_ANDI;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLI;
s_shamt <= instr(24 downto 20);
when "101" =>
if (instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAI;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLI;
s_shamt <= instr(24 downto 20);
end if;
when others => -- error state
end case;
when ALU_T =>
if(instr(31 downto 25)="0000001") then
-- Case RV32M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MUL;
when "001" => s_instr_t <= instr_MULH;
when "010" => s_instr_t <= instr_MULHSU;
when "011" => s_instr_t <= instr_MULHU;
when "100" => s_instr_t <= instr_DIV;
when "101" => s_instr_t <= instr_DIVU;
when "110" => s_instr_t <= instr_REM;
when "111" => s_instr_t <= instr_REMU;
when others => -- error state
end case;
else
-- Case RV32I
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUB;
else
s_instr_t <= instr_ADD;
end if;
when "001" =>
s_instr_t <= instr_SLL;
when "010" =>
s_instr_t <= instr_SLT;
when "011" =>
s_instr_t <= instr_SLTU;
when "100" =>
s_instr_t <= instr_XOR;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRA;
else
s_instr_t <= instr_SRL;
end if;
when "110" =>
s_instr_t <= instr_OR;
when "111" =>
s_instr_t <= instr_AND;
when others => -- error state
end case;
end if;
when FENCE_T =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FENCE;
else
s_instr_t <= instr_FENCEI;
end if;
when CSR_T =>
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 20) = "000000000000") then
s_instr_t <= instr_EBREAK;
elsif(instr(31 downto 20) = "000000000001") then
s_instr_t <= instr_ECALL;
elsif(instr(31 downto 20) = "000000000010") then
s_instr_t <= instr_URET;
elsif(instr(31 downto 20) = "000100000010") then
s_instr_t <= instr_SRET;
elsif(instr(31 downto 20) = "001100000010") then
s_instr_t <= instr_MRET;
elsif(instr(31 downto 20) = "000100000101") then
s_instr_t <= instr_WFI;
elsif(instr(31 downto 25) = "0001001") then
s_instr_t <= instr_SFENCEVM;
else
end if;
when "001" =>
s_instr_t <= instr_CSRRW;
s_csr <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_CSRRS;
s_csr <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_CSRRC;
s_csr <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_CSRRWI;
s_csr <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_CSRRSI;
s_csr <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_CSRRCI;
s_csr <= instr(31 downto 20);
when others => -- error state
end case;
when ALUW_T =>
if(instr(31 downto 25) = "0000001") then
-- Case RV64M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MULW;
when "100" => s_instr_t <= instr_DIVW;
when "101" => s_instr_t <= instr_DIVUW;
when "110" => s_instr_t <= instr_REMW;
when "111" => s_instr_t <= instr_REMUW;
when others => --error state
end case;
else
-- Case 64I ALU
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUBW;
else
s_instr_t <= instr_ADDW;
end if;
when "001" =>
s_instr_t <= instr_SLLW;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAW;
else
s_instr_t <= instr_SRLW;
end if;
when others => -- error state
end case;
end if;
when ALUIW_T =>
-- case RV64I
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDIW;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLIW;
s_shamt <= instr(24 downto 20);
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAIW;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLIW;
s_shamt <= instr(24 downto 20);
end if;
when others => --error state
end case;
when ATOM_T =>
if(instr(14 downto 12)="011") then
-- case RV64A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRD;
when "00011" => s_instr_t <= instr_SCD;
when "00001" => s_instr_t <= instr_AMOSWAPD;
when "00000" => s_instr_t <= instr_AMOADDD;
when "00100" => s_instr_t <= instr_AMOXORD;
when "01100" => s_instr_t <= instr_AMOANDD;
when "01000" => s_instr_t <= instr_AMOORD;
when "10000" => s_instr_t <= instr_AMOMIND;
when "10100" => s_instr_t <= instr_AMOMAXD;
when "11000" => s_instr_t <= instr_AMOMINUD;
when "11100" => s_instr_t <= instr_AMOMAXUD;
when others => --error state
end case;
else
-- case RV32A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRW;
when "00011" => s_instr_t <= instr_SCW;
when "00001" => s_instr_t <= instr_AMOSWAPW;
when "00000" => s_instr_t <= instr_AMOADDW;
when "00100" => s_instr_t <= instr_AMOXORW;
when "01100" => s_instr_t <= instr_AMOANDW;
when "01000" => s_instr_t <= instr_AMOORW;
when "10000" => s_instr_t <= instr_AMOMINW;
when "10100" => s_instr_t <= instr_AMOMAXW;
when "11000" => s_instr_t <= instr_AMOMINUW;
when "11100" => s_instr_t <= instr_AMOMAXUW;
when others => --error state
end case;
end if;
when FLOAD_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FLW;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_FLD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when FSTORE_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FSW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_FSD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => --error state
end case;
when FMADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMADDS;
else
s_instr_t <= instr_FMADDD;
end if;
when FMSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMSUBS;
else
s_instr_t <= instr_FMSUBD;
end if;
when FNADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMADDS;
else
s_instr_t <= instr_FNMADDD;
end if;
when FNSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMSUBS;
else
s_instr_t <= instr_FNMSUBD;
end if;
when FPALU_T =>
case instr(31 downto 25) is
when "0000000" =>
s_instr_t <= instr_FADDS;
when "0000100" =>
s_instr_t <= instr_FSUBS;
when "0001000" =>
s_instr_t <= instr_FMULS;
when "0001100" =>
s_instr_t <= instr_FDIVS;
when "0101100" =>
s_instr_t <= instr_FSQRTS;
when "0010000" =>
if (instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJS;
elsif (instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJNS;
else
s_instr_t <= instr_FSGNJXS;
end if;
when "0010100" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMINS;
else
s_instr_t <= instr_FMAXS;
end if;
when "1100000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWS;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUS;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLS;
else
s_instr_t <= instr_FCVTLUS;
end if;
when "1110000" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMVXW;
else
s_instr_t <= instr_FCLASSS;
end if;
when "1010000" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQS;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTS;
else
s_instr_t <= instr_FLES;
end if;
when "1101000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTSW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTSWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTSL;
else
s_instr_t <= instr_FCVTSLU;
end if;
when "1111000" =>
s_instr_t <= instr_FMVWX;
when "0000001" =>
s_instr_t <= instr_FADDD;
when "0000101" =>
s_instr_t <= instr_FSUBD;
when "0001001" =>
s_instr_t <= instr_FMULD;
when "0001101" =>
s_instr_t <= instr_FDIVD;
when "0101101" =>
s_instr_t <= instr_FSQRTD;
when "0010001" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJND;
else
s_instr_t <= instr_FSGNJXD;
end if;
when "0010101" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMIND;
else
s_instr_t <= instr_FMAXD;
end if;
when "0100000" =>
s_instr_t <= instr_FCVTSD;
when "0100001" =>
s_instr_t <= instr_FCVTDS;
when "1010001" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTD;
else
s_instr_t <= instr_FLED;
end if;
when "1110001" =>
if(instr(14 downto 12) = "001") then
s_instr_t <= instr_FCLASSD;
else
s_instr_t <= instr_FMVXD;
end if;
when "1100001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWD;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUD;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLD;
else
s_instr_t <= instr_FCVTLUD;
end if;
when "1101001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTDW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTDWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTDL;
else
s_instr_t <= instr_FCVTDLU;
end if;
when "1111001" =>
s_instr_t <= instr_FMVDX;
when others => --error state
end case;
when others => -- error state
end case;
end process;
rd <= instr(11 downto 7);
rs1 <= instr(19 downto 15);
rs2 <= instr(24 downto 20);
rs3 <= instr(31 downto 27);
funct3 <= instr(14 downto 12);
funct6 <= instr(31 downto 26);
funct7 <= instr(31 downto 25);
opcode <= instr(6 downto 0);
imm12 <= s_imm12;
imm20 <= s_imm20;
shamt <= s_shamt;
csr <= s_csr;
instr_code <= s_instr_t;
end Behavioral;
| mit |
SLongofono/Senior_Design_Capstone | StupidCore/RAM.vhd | 1 | 7870 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
done: out STD_LOGIC;
write, read: in STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
component ram2ddrxadc
port(
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
-- The RAM is accessing 2 bytes per access
ram_a : in std_logic_vector(26 downto 0); -- input address
ram_dq_i : in std_logic_vector(15 downto 0); -- input data
ram_dq_o : out std_logic_vector(15 downto 0); -- output data
ram_cen : in std_logic; -- chip enable
ram_oen : in std_logic; -- output enable
ram_wen : in std_logic; -- write enable
ram_ub : in std_logic; -- upper byte
ram_lb : in std_logic; -- lower byte
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
-- Physical RAM Pin Signals
signal ram_cen, ram_oen, ram_wen, ram_ub, ram_lb: std_logic;
signal ram_dq_o, ram_dq_i: std_logic_vector (15 downto 0);
type memory_states IS (IDLE_STATE, PREPARE_STATE, READ_STATE, WRITE_STATE, INTERMITENT_STATE);
-- Where current state and next_state are pretty self-forward, last state will check
signal current_state, next_state, last_state: memory_states := IDLE_STATE;
signal temp_data_write, temp_data_read: std_logic_vector(63 downto 0);
signal ram_a: std_logic_vector(26 downto 0);
-- Result
signal read_out: std_logic_vector(15 downto 0) := (others => '0');
-- Counters
signal hundred_nano_seconds_elapsed, wait_counter : integer range 0 to 150 := 0;
signal s_read : std_logic := '0';
signal writeOnce, readOnce : std_logic := '0';
begin
ram2ddr: ram2ddrxadc
port map(
clk_200MHz_i=>clk_200,
rst_i=>rst,
device_temp_i=>"000000000000",
ram_a=>ram_a,
ram_dq_i=>ram_dq_o,
ram_dq_o=>ram_dq_i,
ram_cen=>ram_cen,
ram_oen=>ram_oen,
ram_wen=>ram_wen,
ram_ub=>ram_ub,
ram_lb=>ram_lb,
ddr2_addr=>ddr2_addr,
ddr2_ba=>ddr2_ba,
ddr2_ras_n=>ddr2_ras_n,
ddr2_cas_n=>ddr2_cas_n,
ddr2_we_n=>ddr2_we_n,
ddr2_ck_p=>ddr2_ck_p,
ddr2_ck_n=>ddr2_ck_n,
ddr2_cke=>ddr2_cke,
ddr2_cs_n=>ddr2_cs_n,
ddr2_dm=>ddr2_dm,
ddr2_odt=>ddr2_odt,
ddr2_dq=>ddr2_dq,
ddr2_dqs_p=>ddr2_dqs_p,
ddr2_dqs_n=>ddr2_dqs_n
);
process(clk_100,rst) begin
if(rst = '1') then
current_state <= IDLE_STATE;
elsif(rising_edge(clk_100)) then
current_state <= next_state;
end if;
end process;
process(current_state, rst, clk_100) begin
if(rst = '1') then
read_out <= (others => '0');
readOnce <= '0';
writeOnce <= '0';
elsif(rising_edge(clk_100)) then
next_state <= current_state;
case current_state is
-- State IDLE_STATE: Disable chip enable, write and read
when IDLE_STATE =>
ram_cen <= '1';
ram_oen <= '1';
ram_wen <= '1';
if(read = '1') then
s_read <= '1';
next_state <= PREPARE_STATE;
elsif(write = '1') then
s_read <= '0';
next_state <= PREPARE_STATE;
end if;
-- State PREPARE_STATE: Assert whatever needs to be asserted
when PREPARE_STATE =>
-- Reset the counters
hundred_nano_seconds_elapsed <= 0;
wait_counter <= 0;
-- Read
if(s_read = '1') then
readOnce <= '1';
ram_oen <= '0';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '1';
next_state <= READ_STATE;
-- Write
else
writeOnce <= '1';
ram_oen <= '1';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '0';
next_state <= WRITE_STATE;
end if;
-- State READ_STATE: Waits until the delta time indicated by the
-- data sheet has elapsed to finish reading
when READ_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
-- Wait till the necessary clock cycles elapsed while it's recording the data
if(hundred_nano_seconds_elapsed > 22) then
read_out <= ram_dq_i;
next_state <= INTERMITENT_STATE;
end if;
when WRITE_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
if(hundred_nano_seconds_elapsed > 27) then
next_state <= INTERMITENT_STATE;
-- Dummy read_out to signal we are done writing
read_out <= (5 => '1', others => '0');
end if;
-- State INTERMITENT_STATE: The done flag will be raised to allow the MMU
-- to continue onto the next byte
when INTERMITENT_STATE =>
read_out <= ram_dq_i;
next_state <= IDLE_STATE;
when others =>
next_state <= IDLE_STATE;
end case;
end if;
end process;
ram_dq_o <= data_in;
ram_a <= contr_addr_in;
data_out <= read_out;
done <= '1' when current_state = INTERMITENT_STATE else '0';
end Behavioral;
| mit |
SLongofono/Senior_Design_Capstone | hdl/ROM_Controller.vhd | 1 | 10896 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
-- so, acc, hold: in STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(63 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end ROM_controller_SPI;
architecture Behavioral of ROM_controller_SPI is
signal CFGCLK, CFGMCLK, EOS, PREQ: std_logic;
signal SCLK: std_logic := '0';
signal read_command: std_logic_vector(8 downto 0) := (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
signal address_signal: std_logic_vector(23 downto 0) := (others => '0');
signal command_ctr, address_ctr, data_1_ctr, data_2_ctr, dummy_ctr: natural := 0;
signal done_1_flag, done_2_flag: std_logic := '1';
signal data_register_1, data_register_2 : std_logic_vector(63 downto 0) := (others => '0');
type spi_states is (idle, command, address, data_out_one_low, data_out_one_high, data_out_two, dummy, deasrt);
signal curr_state, next_state : spi_states := idle;
signal sckl_o,locked : std_logic;
signal s_t_si: std_logic;
signal s_clok_wat: std_logic := '0';
signal data_counter: natural := 0;
signal stop: std_logic := '0';
signal s_done: std_logic := '0';
signal retarded_counter : integer := 0;
signal one_clock_cycle: integer := 0;
signal s_read: std_logic;
signal counter_s : std_logic;
signal counter_o : std_logic_vector(30 downto 0) := (others => '0');
signal buffered_read : std_logic;
begin
retarded_ctr_adder: process(clk_25, rst) begin
if(rst = '1') then
retarded_counter <= 0;
elsif(rising_edge(clk_25)) then
if(read = '1' and retarded_counter < 100) then
retarded_counter <= retarded_counter + 1;
end if;
end if;
end process;
read_proc: process(clk_25, rst, read) begin
if(rst = '1') then
one_clock_cycle <= 0;
s_read <= '0';
elsif(rising_edge(clk_25) and read = '1') then
one_clock_cycle <= one_clock_cycle + 1;
if(one_clock_cycle = 0) then
s_read <= '1';
elsif(one_clock_cycle = 1) then
s_read <= '0';
end if;
end if;
end process;
latch_qd: process(qd(1)) begin
buffered_read <= qd(1);
end process;
retarded_ctr_fsm: process(clk_25, rst, s_read) begin
if(rst = '1') then
cs_n <= '1';
SCLK <= '0';
si_t <= '0';
wp_t <= '1';
data_out <= (others => '0');
-- data_register_1 <= (others => '0');
elsif(rising_edge(clk_25)) then
if(retarded_counter > 0) then
sclk <= sclk xor '1';
end if;
case retarded_counter is
when 0 =>
si_t <= '0';
s_done <= '0';
si_i <= '0';
wp <= '0';
cs_n <= '1';
if(s_read = '1') then
cs_n <= '0';
end if;
wp_t <= '1';
when 1 => -- Wait for cs_n to propagate (?)
cs_n <= '0';
-- Opcode in starts
when 2 =>
si_i <= '0';
when 3 =>
si_i <= '0';
when 4 =>
si_i <= '0';
when 5 =>
si_i <= '0';
when 6 =>
si_i <= '0';
when 7 =>
si_i <= '0';
when 8 =>
si_i <= '1';
when 9 =>
si_i <= '1';
-- Address_in starts
when 10 =>
--si_t <= '1';
si_i <= address_in(23);
when 11 =>
si_i <= address_in(22);
when 12 =>
si_i <= address_in(21);
when 13 =>
si_i <= address_in(20);
when 14 =>
si_i <= address_in(19);
when 15 =>
si_i <= address_in(18);
when 16 =>
si_i <= address_in(17);
when 17 =>
si_i <= address_in(16);
when 18 =>
si_i <= address_in(15);
when 19 =>
si_i <= address_in(14);
when 20 =>
si_i <= address_in(13);
when 21 =>
si_i <= address_in(12);
when 22 =>
si_i <= address_in(11);
when 23 =>
si_i <= address_in(10);
when 24 =>
si_i <= address_in(9);
when 25 =>
si_i <= address_in(8);
when 26 =>
si_i <= address_in(7);
when 27 =>
si_i <= address_in(6);
when 28 =>
si_i <= address_in(5);
when 29 =>
si_i <= address_in(4);
when 30 =>
si_i <= address_in(3);
when 31 =>
si_i <= address_in(2);
when 32 =>
si_i <= address_in(1);
when 33 =>
si_i <= address_in(0);
when 34 =>
si_t <= '1';
-- Start of Data
-- Data comes out MSB first in bytes, like so
-- [7][6][5][4][3][2][1][0] | [7][6][5][4][...]
when 35 =>
data_out(7) <= buffered_read;
when 36 =>
data_out(6) <= buffered_read;
when 37 =>
data_out(5) <= buffered_read;
when 38 =>
data_out(4) <= buffered_read;
when 39 =>
data_out(3) <= buffered_read;
when 40 =>
data_out(2) <= buffered_read;
when 41 =>
data_out(1) <= buffered_read;
when 42 =>
data_out(0) <= buffered_read;
when 43 =>
data_out(15) <= buffered_read;
when 44 =>
data_out(14) <= buffered_read;
when 45 =>
data_out(13) <= buffered_read;
when 46 =>
data_out(12) <= buffered_read;
when 47 =>
data_out(11) <= buffered_read;
when 48 =>
data_out(10) <= buffered_read;
when 49 =>
data_out(9) <= buffered_read;
when 50 =>
data_out(8) <= buffered_read;
-- Byte 3
when 51 =>
data_out(23) <= buffered_read;
when 52 =>
data_out(22) <= buffered_read;
when 53 =>
data_out(21) <= buffered_read;
when 54 =>
data_out(20) <= buffered_read;
when 55 =>
data_out(19) <= buffered_read;
when 56 =>
data_out(18) <= buffered_read;
when 57 =>
data_out(17) <= buffered_read;
when 58 =>
data_out(16) <= buffered_read;
-- Byte 4
when 59 =>
data_out(31) <= buffered_read;
when 60 =>
data_out(30) <= buffered_read;
when 61 =>
data_out(29) <= buffered_read;
when 62 =>
data_out(28) <= buffered_read;
when 63 =>
data_out(27) <= buffered_read;
when 64 =>
data_out(26) <= buffered_read;
when 65 =>
data_out(25) <= buffered_read;
when 66 =>
data_out(24) <= buffered_read;
-- Byte 5
when 67 =>
data_out(39) <= buffered_read;
when 68 =>
data_out(38) <= buffered_read;
when 69 =>
data_out(37) <= buffered_read;
when 70 =>
data_out(36) <= buffered_read;
when 71 =>
data_out(35) <= buffered_read;
when 72 =>
data_out(34) <= buffered_read;
when 73 =>
data_out(33) <= buffered_read;
when 74 =>
data_out(32) <= buffered_read;
-- Byte 6
when 75 =>
data_out(47) <= buffered_read;
when 76 =>
data_out(46) <= buffered_read;
when 77 =>
data_out(45) <= buffered_read;
when 78 =>
data_out(44) <= buffered_read;
when 79 =>
data_out(43) <= buffered_read;
when 80 =>
data_out(42) <= buffered_read;
when 81 =>
data_out(41) <= buffered_read;
when 82 =>
data_out(40) <= buffered_read;
-- Byte 7
when 83 =>
data_out(55) <= buffered_read;
when 84 =>
data_out(54) <= buffered_read;
when 85 =>
data_out(53) <= buffered_read;
when 86 =>
data_out(52) <= buffered_read;
when 87 =>
data_out(51) <= buffered_read;
when 88 =>
data_out(50) <= buffered_read;
when 89 =>
data_out(49) <= buffered_read;
when 90 =>
data_out(48) <= buffered_read;
-- Byte 8
when 91 =>
data_out(63) <= buffered_read;
when 92 =>
data_out(62) <= buffered_read;
when 93 =>
data_out(61) <= buffered_read;
when 94 =>
data_out(60) <= buffered_read;
when 95 =>
data_out(59) <= buffered_read;
when 96 =>
data_out(58) <= buffered_read;
when 97 =>
data_out(57) <= buffered_read;
when 98 =>
data_out(56) <= buffered_read;
cs_n <= '1';
done <= '1';
si_t <= '0';
when others =>
end case;
end if;
end process;
-- QUAD command if switch 2 is off, SINGLE READ if switch 2 is on
read_command <= (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
--done <= s_done;
address_signal <= address_in;
--data_out <= data_register_1;
--pragma synthesis_off
counter <= retarded_counter;
--pragma synthesis_on
end Behavioral;
| mit |
tcsiwula/java_code | classes/cs345/code_examples/antlr_github_copy/grammars/vhdl/examples/signed.vhd | 5 | 10990 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L);
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R);
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R);
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) < R;
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) <= SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) <= R;
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) > SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) > R;
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) >= SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) >= R;
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
end STD_LOGIC_SIGNED;
| mit |
akshayp/college-projects | vhdl/pong/bat.vhd | 1 | 2926 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bat IS
PORT ( clr, CLKBAT : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : IN std_logic;
read : OUT std_logic;
paddle_1, paddle_2 : OUT INTEGER RANGE 0 to 48);
END bat;
ARCHITECTURE position OF bat IS
TYPE STATE_TYPE IS (wait_ready, read_data, read_low);
SIGNAL state: STATE_TYPE;
SIGNAL clock_enable :Std_logic;
signal a, b, c, d ,e, f, g, h : std_logic_vector(15 downto 0);
BEGIN
a <= "0001101100011011";
b <= "1111000000011011";
c <= "0001110100011101";
d <= "1111000000011101";
e <= "0100110001001100";
f <= "1111000001001100";
g <= "0100110101001101";
h <= "1111000001001101";
PROCESS(scan_ready, CLR,CLKBAT, clock_enable)
VARIABLE pdl_1, pdl_2 : INTEGER RANGE 0 to 48; -- temporary position
BEGIN
IF clr='0' THEN
pdl_1 := 32;
pdl_2 := 32;
state <= read_low;
ELSIF CLKBAT'EVENT AND CLKBAT = '1' THEN
case state is
when read_low =>
read <= '0';
state <= wait_ready;
WHEN wait_ready =>
IF scan_ready = '1' THEN
read <= '1';
state <= read_data;
ELSE
state <= wait_ready;
END IF;
WHEN read_data =>
IF (("00011011" & scan_code) = a) THEN
pdl_1 := pdl_1 + 1;
paddle_1 <= pdl_1;
state <= read_low;
ELSIF (("11110000" & scan_code) = b) then
pdl_1 :=pdl_1;
paddle_1 <= pdl_1;
state <= read_low;
ELSIF (("00011101" & scan_code) = c) THEN
pdl_1 := pdl_1 - 1;
paddle_1 <= pdl_1;
state <= read_low;
elsif (("11110000" & scan_code) = d) then
pdl_1 :=pdl_1;
paddle_1 <= pdl_1;
state <= read_low;
elsIF (("01001100" & scan_code) = e) THEN
pdl_2 := pdl_2 + 1;
paddle_2 <=pdl_2;
state <= read_low;
elsif (("11110000" & scan_code) = f) then
pdl_2 :=pdl_2;
state <= read_low;
ELSIF (("01001101" & scan_code) = g) THEN
pdl_2 := pdl_2 - 1;
paddle_2 <=pdl_2;
state <= read_low;
elsif ("11110000" & scan_code = h) then
pdl_2 :=pdl_2;
paddle_2 <=pdl_2;
state <= read_low;
END IF;
end case;
END IF;
IF pdl_1 >16 AND pdl_1 < 48 THEN
Paddle_1 <=pdl_1;
ELSIF pdl_1 <= 15 THEN
Paddle_1 <= 16;
ELSIF pdl_1 >= 49 THEN
Paddle_1 <= 48;
END IF;
IF pdl_2 >16 AND pdl_2 < 48 THEN
Paddle_2 <=pdl_2;
ELSIF pdl_2 <= 15 THEN
Paddle_2 <= 16;
ELSIF pdl_2 >= 49 THEN
Paddle_2 <= 48;
END IF;
END PROCESS;
END position;
| mit |
inmagik/html-map-designer | lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| mit |
AmitThakur/vhdl | mealy/mealy1.vhd | 2 | 772 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END mealy ;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock ='1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
PROCESS ( y, w )
BEGIN
CASE y IS
WHEN A =>
z <= '0' ;
WHEN B =>
z <= w ;
END CASE ;
END PROCESS ;
END Behavior ;
| mit |
shamoons/linguist-samples | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
hamsternz/FPGA_Webserver | hdl/tx/tx_interface.vhd | 1 | 8508 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tx_interface - Behavioral
--
-- Description: To send data streams out to an Ethernet PHY over RGMII
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tx_interface is
Port ( clk125MHz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
--
phy_ready : in STD_LOGIC;
link_10mb : in STD_LOGIC;
link_100mb : in STD_LOGIC;
link_1000mb : in STD_LOGIC;
---
arp_request : in STD_LOGIC;
arp_granted : out STD_LOGIC;
arp_valid : in STD_LOGIC;
arp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
icmp_request : in STD_LOGIC;
icmp_granted : out STD_LOGIC;
icmp_valid : in STD_LOGIC;
icmp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
udp_request : in STD_LOGIC;
udp_granted : out STD_LOGIC;
udp_valid : in STD_LOGIC;
udp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
tcp_request : in STD_LOGIC;
tcp_granted : out STD_LOGIC;
tcp_valid : in STD_LOGIC;
tcp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end tx_interface;
architecture Behavioral of tx_interface is
component tx_arbiter is
generic (
idle_time : std_logic_vector(5 downto 0));
Port ( clk : in STD_LOGIC;
ready : in STD_LOGIC;
ch0_request : in STD_LOGIC;
ch0_granted : out STD_LOGIC;
ch0_valid : in STD_LOGIC;
ch0_data : in STD_LOGIC_VECTOR (7 downto 0);
ch1_request : in STD_LOGIC;
ch1_granted : out STD_LOGIC;
ch1_valid : in STD_LOGIC;
ch1_data : in STD_LOGIC_VECTOR (7 downto 0);
ch2_request : in STD_LOGIC;
ch2_granted : out STD_LOGIC;
ch2_valid : in STD_LOGIC;
ch2_data : in STD_LOGIC_VECTOR (7 downto 0);
ch3_request : in STD_LOGIC;
ch3_granted : out STD_LOGIC;
ch3_valid : in STD_LOGIC;
ch3_data : in STD_LOGIC_VECTOR (7 downto 0);
merged_data_valid : out STD_LOGIC;
merged_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component tx_add_crc32 is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC := '0';
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end component;
component tx_add_preamble is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end component;
signal merged_data_valid : STD_LOGIC;
signal merged_data : STD_LOGIC_VECTOR (7 downto 0);
signal with_crc_data_valid : STD_LOGIC;
signal with_crc_data : STD_LOGIC_VECTOR (7 downto 0);
signal framed_data_valid : STD_LOGIC;
signal framed_data : STD_LOGIC_VECTOR (7 downto 0);
signal data : STD_LOGIC_VECTOR (7 downto 0);
signal data_valid : STD_LOGIC;
signal data_enable : STD_LOGIC;
signal data_error : STD_LOGIC;
component tx_rgmii is
Port ( clk : in STD_LOGIC;
clk90 : in STD_LOGIC;
phy_ready : in STD_LOGIC;
data_valid : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_error : in STD_LOGIC;
data_enable : in STD_LOGIC := '1';
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end component ;
begin
i_tx_arbiter: tx_arbiter generic map(idle_time => "010111") Port map (
clk => clk125MHz,
------------------------------
ready => phy_ready,
ch0_request => tcp_request,
ch0_granted => tcp_granted,
ch0_data => tcp_data,
ch0_valid => tcp_valid,
ch1_request => arp_request,
ch1_granted => arp_granted,
ch1_data => arp_data,
ch1_valid => arp_valid,
ch2_request => icmp_request,
ch2_granted => icmp_granted,
ch2_data => icmp_data,
ch2_valid => icmp_valid,
ch3_request => udp_request,
ch3_granted => udp_granted,
ch3_data => udp_data,
ch3_valid => udp_valid,
merged_data_valid => merged_data_valid,
merged_data => merged_data);
--i_ila_0: ila_0 port map (
-- clk => clk125Mhz,
-- probe0(0) => merged_data_valid,
-- probe1(0) => merged_data_valid,
-- probe2 => merged_data,
-- probe3(0) => merged_data_valid);
i_tx_add_crc32: tx_add_crc32 port map (
clk => clk125MHz,
data_valid_in => merged_data_valid,
data_in => merged_data,
data_valid_out => with_crc_data_valid,
data_out => with_crc_data);
i_tx_add_preamble: tx_add_preamble port map (
clk => clk125MHz,
data_valid_in => with_crc_data_valid,
data_in => with_crc_data,
data_valid_out => framed_data_valid,
data_out => framed_data);
----------------------------------------------------------------------
-- A FIFO needs to go here to slow down data for the 10/100 operation.
--
-- Plan is for a 4K FIFO, with an almost full at about 2500. That will
-- Allow space for a full packet and at least 50 cycles for latency
-- within the feedback loop.
----------------------------------------------------------------------
-- A module need to go here to adapt the output of the FIFO to the
-- slowere speeds
--
-- link_10mb : in STD_LOGIC;
-- link_100mb : in STD_LOGIC;
-- link_1000mb : in STD_LOGIC;
----------------------------------------------------------------------
i_tx_rgmii: tx_rgmii port map (
clk => clk125MHz,
clk90 => clk125MHz90,
phy_ready => phy_ready,
data_valid => framed_data_valid,
data => framed_data,
data_error => '0',
data_enable => '1',
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
end Behavioral;
| mit |
xiehuiqi220/package-json-editor | bower_components/ace/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| mit |
hamsternz/FPGA_Webserver | testbenches/tb_main_design_arp.vhd | 1 | 10234 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_main_design_arp is
end tb_main_design_arp;
architecture Behavioral of tb_main_design_arp is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"A0B3CC4CF9EF";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"000000000000";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
constant our_mac : std_logic_vector(47 downto 0) := x"AB_89_67_45_23_02"; -- NOTE this is 02:23:45:67:89:AB
constant our_ip : std_logic_vector(31 downto 0) := x"0A_00_00_0A";
constant our_netmask : std_logic_vector(31 downto 0) := x"00_FF_FF_FF";
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip
) port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 72 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 200000 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 73 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= x"FF";
when 9 => input_data <= x"FF";
when 10 => input_data <= x"FF";
when 11 => input_data <= x"FF";
when 12 => input_data <= x"FF";
when 13 => input_data <= x"FF";
-- Source MAC address
when 14 => input_data <= x"A0";
when 15 => input_data <= x"B3";
when 16 => input_data <= x"CC";
when 17 => input_data <= x"4C";
when 18 => input_data <= x"F9";
when 19 => input_data <= x"EF";
------------------------
-- ARP packet
------------------------
when 20 => input_data <= x"08"; -- Ether Type 08:06 << ARP!
when 21 => input_data <= x"06";
when 22 => input_data <= x"00"; -- Media type
when 23 => input_data <= x"01";
when 24 => input_data <= x"08"; -- Protocol (IP)
when 25 => input_data <= x"00";
when 26 => input_data <= x"06"; -- Hardware address length
when 27 => input_data <= x"04"; -- Protocol address length
-- Operation
when 28 => input_data <= x"00";
when 29 => input_data <= x"01"; -- request
-- Target MAC
when 30 => input_data <= arp_src_hw(47 downto 40);
when 31 => input_data <= arp_src_hw(39 downto 32);
when 32 => input_data <= arp_src_hw(31 downto 24);
when 33 => input_data <= arp_src_hw(23 downto 16);
when 34 => input_data <= arp_src_hw(15 downto 8);
when 35 => input_data <= arp_src_hw( 7 downto 0);
-- Target IP
when 36 => input_data <= arp_src_ip(31 downto 24);
when 37 => input_data <= arp_src_ip(23 downto 16);
when 38 => input_data <= arp_src_ip(15 downto 8);
when 39 => input_data <= arp_src_ip( 7 downto 0);
-- Source MAC
when 40 => input_data <= arp_tgt_hw(47 downto 40);
when 41 => input_data <= arp_tgt_hw(39 downto 32);
when 42 => input_data <= arp_tgt_hw(31 downto 24);
when 43 => input_data <= arp_tgt_hw(23 downto 16);
when 44 => input_data <= arp_tgt_hw(15 downto 8);
when 45 => input_data <= arp_tgt_hw( 7 downto 0);
-- Source IP
when 46 => input_data <= arp_tgt_ip(31 downto 24);
when 47 => input_data <= arp_tgt_ip(23 downto 16);
when 48 => input_data <= arp_tgt_ip(15 downto 8);
when 49 => input_data <= arp_tgt_ip( 7 downto 0);
-- We can release the bus now and go back to the idle state.
when 50 => input_data <= x"00";
when 51 => input_data <= x"00";
when 52 => input_data <= x"00";
when 53 => input_data <= x"00";
when 54 => input_data <= x"00";
when 55 => input_data <= x"00";
when 56 => input_data <= x"00";
when 57 => input_data <= x"00";
when 58 => input_data <= x"00";
when 59 => input_data <= x"00";
when 60 => input_data <= x"00";
when 61 => input_data <= x"00";
when 62 => input_data <= x"00";
when 63 => input_data <= x"00";
when 64 => input_data <= x"00";
when 65 => input_data <= x"00";
when 66 => input_data <= x"00";
when 67 => input_data <= x"12";
when 68 => input_data <= x"12";
when 69 => input_data <= x"12";
when 70 => input_data <= x"12";
when 71 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral;
| mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_request.vhd | 1 | 7048 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: rx_arp_request - Behavioral
--
-- Description: Receive ARP packets and decode them
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rx_arp is
Port ( clk : in STD_LOGIC;
packet_data : in STD_LOGIC_VECTOR (7 downto 0);
packet_data_valid : in STD_LOGIC;
arp_de : out STD_LOGIC := '0';
arp_op_request : out STD_LOGIC := '0';
arp_sender_hw : out STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
arp_sender_ip : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
arp_target_hw : out STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
arp_target_ip : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'));
end rx_arp;
architecture Behavioral of rx_arp is
signal ethertype_data : std_logic_vector(15 downto 0) := (others => '0');
signal data : std_logic_vector(8*28-1 downto 0) := (others => '0');
signal hwtype : std_logic_vector(15 downto 0) := (others => '0');
signal ptype : std_logic_vector(15 downto 0) := (others => '0');
signal hlen : std_logic_vector(7 downto 0) := (others => '0');
signal plen : std_logic_vector(7 downto 0) := (others => '0');
signal op : std_logic_vector(15 downto 0) := (others => '0');
signal sender_hw : std_logic_vector(47 downto 0) := (others => '0');
signal sender_ip : std_logic_vector(31 downto 0) := (others => '0');
signal target_hw : std_logic_vector(47 downto 0) := (others => '0');
signal target_ip : std_logic_vector(31 downto 0) := (others => '0');
signal ethertype_valid : std_logic := '0';
signal hwtype_valid : std_logic := '0';
signal ptype_valid : std_logic := '0';
signal len_valid : std_logic := '0';
signal op_valid : std_logic := '0';
signal op_request : std_logic := '0';
signal packet_valid_delay : std_logic := '0';
signal valid_count : unsigned(5 downto 0) := (others => '0');
begin
---------------------------------------------
-- Breaking out fields for easy reference
-------------------------------------------
hwtype <= data( 7+8*0+8 downto 0+8*0+8) & data(15+8*0+8 downto 8+8*0+8);
ptype <= data( 7+8*2+8 downto 0+8*2+8) & data(15+8*2+8 downto 8+8*2+8);
hlen <= data( 7+8*4+8 downto 0+8*4+8);
plen <= data(15+8*4+8 downto 8+8*4+8);
op <= data( 7+8*6+8 downto 0+8*6+8) & data(15+8*6+8 downto 8+8*6+8);
process(clk)
begin
if rising_edge(clk) then
arp_de <= '0';
arp_op_request <= op_request;
arp_sender_hw <= sender_hw;
arp_sender_ip <= sender_ip;
arp_target_hw <= target_hw;
arp_target_ip <= target_ip;
if ethertype_valid = '1' and hwtype_valid = '1' and ptype_valid = '1' and
len_valid = '1' and op_valid = '1' and valid_count = 41 then
arp_de <= '1';
end if;
sender_hw <= data(15+8*12+8 downto 0+8*8+8);
sender_ip <= data(15+8*16+8 downto 0+8*14+8);
target_hw <= data(15+8*22+8 downto 0+8*18+8);
target_ip <= packet_data & data(15+8*26 downto 0+8*24+8);
ethertype_valid <= '0';
hwtype_valid <= '0';
ptype_valid <= '0';
op_valid <= '0';
op_request <= '0';
len_valid <= '0';
---------------------------------
-- Validate the ethernet protocol
---------------------------------
if ethertype_data = x"0806" then
ethertype_valid <= '1';
end if;
----------------------------
-- Validate operation code
----------------------------
if hwtype = x"0001" then
hwtype_valid <= '1';
end if;
if ptype = x"0800" then
ptype_valid <= '1';
end if;
----------------------------
-- Validate operation code
----------------------------
if op = x"0001" then
op_valid <= '1';
op_request <= '1';
end if;
if op = x"0002" then
op_valid <= '1';
op_request <= '0';
end if;
if hlen = x"06" and plen = x"04" then
len_valid <= '1';
end if;
-------------------------------------------
-- Move the data through the shift register
-------------------------------------------
ethertype_data <= ethertype_data(7 downto 0) & data(15 downto 8);
data <= packet_data & data(data'high downto 8);
if packet_valid_delay = '1' then
if valid_count /= 63 then -- Clamp at max value
valid_count <= valid_count+1;
end if;
else
valid_count <= (others => '0');
end if;
packet_valid_delay <= packet_data_valid;
end if;
end process;
end Behavioral;
| mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_tx_fifo.vhd | 1 | 3511 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: my_fifo - Behavioral
--
-- Description: A 32 entry FIFO using inferred storage
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_tx_fifo is
Port ( clk : in STD_LOGIC;
arp_in_write : in STD_LOGIC;
arp_in_full : out STD_LOGIC;
arp_in_op_request : in STD_LOGIC;
arp_in_tgt_hw : in STD_LOGIC_VECTOR(47 downto 0);
arp_in_tgt_ip : in STD_LOGIC_VECTOR(31 downto 0);
arp_out_empty : out std_logic := '0';
arp_out_read : in std_logic := '0';
arp_out_op_request : out std_logic := '0';
arp_out_tgt_hw : out std_logic_vector(47 downto 0) := (others => '0');
arp_out_tgt_ip : out std_logic_vector(31 downto 0) := (others => '0'));
end arp_tx_fifo;
architecture Behavioral of arp_tx_fifo is
component fifo_32 is
port (
clk : in std_logic;
full : out std_logic;
write_en : in std_logic;
data_in : in std_logic_vector;
empty : out std_logic;
read_en : in std_logic;
data_out : out std_logic_vector);
end component;
signal data_in : std_logic_vector(80 downto 0) := (others => '0');
signal data_out : std_logic_vector(80 downto 0) := (others => '0');
begin
arp_out_op_request <= data_out(80);
arp_out_tgt_hw <= data_out(79 downto 32);
arp_out_tgt_ip <= data_out(31 downto 0);
data_in <= arp_in_op_request & arp_in_tgt_hw & arp_in_tgt_ip;
i_generic_fifo: fifo_32
port map (
clk => clk,
full => arp_in_full,
write_en => arp_in_write,
data_in => data_in,
empty => arp_out_empty,
read_en => arp_out_read,
data_out => data_out);
end Behavioral; | mit |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_build_reply.vhd | 1 | 11819 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: icmp_build_reply - Behavioral
--
-- Description: Build the ICMP reply packet by adding headers to the data.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity icmp_build_reply is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
ether_is_ipv4 : in STD_LOGIC;
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0);
ip_version : in STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : in STD_LOGIC_VECTOR (7 downto 0);
ip_length : in STD_LOGIC_VECTOR (15 downto 0);
ip_identification : in STD_LOGIC_VECTOR (15 downto 0);
ip_flags : in STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : in STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : in STD_LOGIC_VECTOR (7 downto 0);
ip_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : in STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : in STD_LOGIC_VECTOR (31 downto 0);
icmp_type : in STD_LOGIC_VECTOR (7 downto 0);
icmp_code : in STD_LOGIC_VECTOR (7 downto 0);
icmp_checksum : in STD_LOGIC_VECTOR (15 downto 0);
icmp_identifier : in STD_LOGIC_VECTOR (15 downto 0);
icmp_sequence : in STD_LOGIC_VECTOR (15 downto 0));
end icmp_build_reply;
architecture Behavioral of icmp_build_reply is
signal count : unsigned(5 downto 0) := (others => '0');
type t_delay is array( 0 to 42) of std_logic_vector(8 downto 0);
signal delay : t_delay := (others => (others => '0'));
signal flipped_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal flipped_our_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal h_ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
signal h_ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal h_icmp_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_icmp_identifier : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_icmp_sequence : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal checksum_static1 : unsigned(19 downto 0) := x"04500";
signal checksum_static2 : unsigned(19 downto 0) := x"08001";
signal checksum_part1 : unsigned(19 downto 0) := (others => '0');
signal checksum_part2 : unsigned(19 downto 0) := (others => '0');
signal checksum_part3 : unsigned(19 downto 0) := (others => '0');
signal checksum_part4 : unsigned(19 downto 0) := (others => '0');
signal checksum_final : unsigned(15 downto 0) := (others => '0');
begin
flipped_src_ip <= h_ip_src_ip(7 downto 0) & h_ip_src_ip(15 downto 8) & h_ip_src_ip(23 downto 16) & h_ip_src_ip(31 downto 24);
flipped_our_ip <= our_ip(7 downto 0) & our_ip(15 downto 8) & our_ip(23 downto 16) & our_ip(31 downto 24);
process(clk)
variable v_icmp_check : unsigned (16 downto 0);
begin
if rising_edge(clk) then
-- This splits the IP checksumming over four cycles
checksum_part1 <= checksum_static1 + unsigned(h_ip_identification)
+ unsigned(flipped_src_ip(31 downto 16))
+ unsigned(flipped_src_ip(15 downto 0));
checksum_part2 <= checksum_static2 + unsigned(h_ip_length)
+ unsigned(flipped_our_ip(31 downto 16))
+ unsigned(flipped_our_ip(15 downto 0));
checksum_part3 <= to_unsigned(0,20) + checksum_part1(15 downto 0) + checksum_part1(19 downto 16)
+ checksum_part2(15 downto 0) + checksum_part2(19 downto 16);
checksum_part4 <= to_unsigned(0,20) + checksum_part3(15 downto 0) + checksum_part3(19 downto 16);
checksum_final <= not(checksum_part4(15 downto 0) + checksum_part4(19 downto 16));
if data_valid_in = '1' then
if count /= "101011" then
count <= count+1;
end if;
else
if count = "000000" or count = "101011" then
count <= (others => '0');
else
count <= count+1;
end if;
end if;
if count = 0 and data_valid_in = '1' then
v_icmp_check(15 downto 0) := unsigned(icmp_checksum);
v_icmp_check(16) := '0';
v_icmp_check := v_icmp_check + 8;
v_icmp_check := v_icmp_check + v_icmp_check(16 downto 16);
h_ether_src_mac <= ether_src_mac;
h_ip_src_ip <= ip_src_ip;
h_ip_length <= ip_length;
h_icmp_checksum <= std_logic_vector(v_icmp_check(15 downto 0));
h_icmp_identifier <= icmp_identifier;
h_icmp_sequence <= icmp_sequence;
end if;
if count /= "000000" then
data_valid_out <= '1';
end if;
case count is
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
-- when "000000" => data_out <= (others => '0'); data_valid_out <= '0';
when "000001" => data_out <= h_ether_src_mac( 7 downto 0);
when "000010" => data_out <= h_ether_src_mac(15 downto 8);
when "000011" => data_out <= h_ether_src_mac(23 downto 16);
when "000100" => data_out <= h_ether_src_mac(31 downto 24);
when "000101" => data_out <= h_ether_src_mac(39 downto 32);
when "000110" => data_out <= h_ether_src_mac(47 downto 40);
-- Source MAC address
when "000111" => data_out <= our_mac( 7 downto 0);
when "001000" => data_out <= our_mac(15 downto 8);
when "001001" => data_out <= our_mac(23 downto 16);
when "001010" => data_out <= our_mac(31 downto 24);
when "001011" => data_out <= our_mac(39 downto 32);
when "001100" => data_out <= our_mac(47 downto 40);
-- Ethernet frame tyoe
when "001101" => data_out <= x"08"; -- Ether Type 08:00 - IP
when "001110" => data_out <= x"00";
------------------------
-- IP Header
------------------------
when "001111" => data_out <= x"45"; -- Protocol & Header Len
when "010000" => data_out <= x"00";
when "010001" => data_out <= h_ip_length(15 downto 8); -- Length
when "010010" => data_out <= h_ip_length(7 downto 0);
when "010011" => data_out <= h_ip_identification(15 downto 8); -- Identificaiton
when "010100" => data_out <= h_ip_identification(7 downto 0);
when "010101" => data_out <= x"00"; -- Flags and offset
when "010110" => data_out <= x"00";
when "010111" => data_out <= x"80"; -- TTL
when "011000" => data_out <= x"01"; -- Protocol
when "011001" => data_out <= std_logic_vector(checksum_final(15 downto 8));
when "011010" => data_out <= std_logic_vector(checksum_final(7 downto 0));
when "011011" => data_out <= our_ip( 7 downto 0); -- Source IP Address
when "011100" => data_out <= our_ip(15 downto 8);
when "011101" => data_out <= our_ip(23 downto 16);
when "011110" => data_out <= our_ip(31 downto 24);
when "011111" => data_out <= h_ip_src_ip( 7 downto 0); -- Destination IP address
when "100000" => data_out <= h_ip_src_ip(15 downto 8); -- (bounce back to the source)
when "100001" => data_out <= h_ip_src_ip(23 downto 16);
when "100010" => data_out <= h_ip_src_ip(31 downto 24);
-------------------------------------
-- ICMP Header
-------------------------------------
when "100011" => data_out <= x"00"; -- ICMP Type = reply
when "100100" => data_out <= x"00"; -- Code
when "100101" => data_out <= h_icmp_checksum(7 downto 0); -- Checksum
when "100110" => data_out <= h_icmp_checksum(15 downto 8);
when "100111" => data_out <= h_icmp_identifier(7 downto 0); -- Identifier
when "101000" => data_out <= h_icmp_identifier(15 downto 8);
when "101001" => data_out <= h_icmp_sequence(7 downto 0); -- Sequence
when "101010" => data_out <= h_icmp_sequence(15 downto 8);
when others => data_valid_out <= delay(0)(8);
data_out <= delay(0)(7 downto 0);
end case;
delay(0 to delay'high-1) <= delay(1 to delay'high);
delay(delay'high) <= data_valid_in & data_in;
end if;
end process;
end Behavioral;
| mit |
Remillard/VHDL-Mode | Test/beautify_test.vhd | 1 | 26841 | -------------------------------------------------------------------------------
-- Last update : Fri Jun 14 13:31:50 2019
-- Project : VHDL Mode for Sublime Text
-------------------------------------------------------------------------------
-- Description: This VHDL file is intended as a test of scope and beautifier
-- functions for the VHDL Mode package. It should never be actually compiled
-- as I do several strange things to make sure various aspects of beautification
-- and syntax scoping are checked.
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- VHDL-2008 package library use.
package master_bfm is new work.avalon_bfm_pkg
generic map
(
G_DATA_WIDTH => 32,
G_ADDR_WIDTH => 10,
G_BURST_WIDTH => 4
);
use work.master_bfm.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
/*
VHDL-2008 Block Comment
test zone.
*/
--/* Invalid layered
commenting */
--/* Valid layered
-- commenting */
-------------------------------------------------------------------------------
-- ENTITY STYLE TEST
-------------------------------------------------------------------------------
---------------------------------------
-- Sloppy Comment Test
-- Basically checking that comments are
-- preserved and do not affect
-- beautification or port copying.
---------------------------------------
-- Comment above
entity my_entity is -- comments everywhere
generic( -- I mean everywhere
DATA_WIDTH : integer := 8; -- This value is 8
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4" -- This comment should align with prior
); -- Holy crap another comment -- with a comment inside the -- comment
port ( -- What about a comment here?
-- Basic ports
clk : in std_logic;
-- Another comment on a line by itself!
reset : in std_logic; -- And here's an inline comment.
--d : in std_logic; -- Oh no! I commented out an actual line
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic); -- And finally
-- A final
end entity my_entity; -- Comment
-- Comment below.
---------------------------------------
-- Blank Entity (and variations)
---------------------------------------
entity foobar is
end entity foobar;
entity entity_1 is
end entity_1;
entity entity_1 is
end entity;
package foo2 is
end package foo2;
package body foo2 is
end package body foo2;
architecture test of thing is
begin
end architecture test;
configuration MY_IDENT of thing is
end configuration MY_IDENT;
---------------------------------------
-- K&R Style Approximate. entity/end
-- form the main block which shares the
-- same indent level, and inside opening
-- parens are on the same line as the
-- keyword, closing parens are at same
-- level as keyword.
---------------------------------------
entity kr_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : type(3 downto 0) := X"4";
item_12345 : out type
);
end entity kr_style_entity;
---------------------------------------
-- Allman Style (C Style). Parens share
-- same indent level as associated keyword
---------------------------------------
entity allman_style_entity is
generic
(
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port
(
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type
);
end entity allman_style_entity;
---------------------------------------
-- Lisp Style: emacs vhdl-mode style
-- with the closing paren on the final
-- item line.
---------------------------------------
entity lisp_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type);
end entity lisp_style_entity;
--------------------------------------------------------------------------------
-- EXTENDED ENTITY TEST -- Uses the passive statements, assertion, a passive
-- procedure, a passive process. VHDL-2008 inclusion of PSL Directives is
-- beyond the scope of this as I don't have a PSL syntax file.
--------------------------------------------------------------------------------
entity passive_test is
generic (
G_ADDR_WIDTH : integer := 10;
G_DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(G_ADDR_WIDTH-1 downto 0);
data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
we : in std_logic;
data_out : out std_logic_vector(G_DATA_WIDTH-1 downto 0)
);
begin
CHECK : assert (G_DATA_WIDTH <= 32)
report "ERROR : DATA WIDTH TOO LARGE (>32)"
severity ERROR;
TIME_CHECK : process (we) is
begin
if (we = '1') then
report "MEMORY WRITTEN AT TIME" & to_string(now);
end if;
end process TIME_CHECK;
my_passive_procedure(clk, addr, result);
end entity passive_test;
-------------------------------------------------------------------------------
-- END ENTITY TEST
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 0 HERE IF ALL TESTS PASS
-------------------------------------------------------------------------------
configuration foobar of my_entity is
use work.my_package.all;
for rtl
use lala.other_thing.all;
end for;
end configuration foobar;
architecture rtl of my_entity is
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- COMPONENT STYLE TEST. Also checking lexing of variations in optional
-- words for components.
-------------------------------------------------------------------------------
-- K&R Style
component kr_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component kr_style_component;
-- Allman Style
component allman_style_component
generic
(
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port
(
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component allman_style_component;
-- Lisp Style
component lisp_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4");
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic);
end component;
-------------------------------------------------------------------------------
-- END COMPONENT STYLE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- SIGNALS TEST
-------------------------------------------------------------------------------
signal my_signal_1 : std_logic;
signal my_signal_2 : std_logic_vector(3 downto 0);
signal a, b, c : std_logic := '1';
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
constant C_CLOCK_PERIOD : real := 1.23e-9;
constant MY_PI : real := 3.141592654;
constant C_FOO, C_BAR : integer := 999;
constant C_OPERATOR_CHECK : std_logic_vector(31 downto 0) :=
std_logic_vector(to_unsigned(1, 8)) &
std_logic_vector(to_unsigned(2, 8)) &
std_logic_vector(to_unsigned(3, 8)) &
std_logic_vector(to_unsigned(4, 8));
alias slv is std_logic_vector;
alias 'c' is letter_c;
alias + is plus;
alias bus_rev : std_logic_vector is bus_thing;
begin
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INSTANTIATION TESTS
-------------------------------------------------------------------------------
-- Direct entity instantiation tests.
-- K&R Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : entity work.my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q);
-- Component instantiation tests
-- K&R Style
my_entity_1 : component my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q,
x(1) => z,
y(3 downto 0) => 9,
z(x'range) => zz);
i_if_cpu : if_cpu
port map (
clk => clk,
reset => reset,
a => a,
b => b
);
-------------------------------------------------------------------------------
-- END OF INSTANTIATION TESTS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MIXED CODE TESTS
-------------------------------------------------------------------------------
SEQUENTIAL_PROCESS : process (clk, reset)
variable my_variable : integer;
shared variable alpha : std_logic_vector(31 downto 0);
begin
-- If/then normal style
IF_LABEL : if (reset = '1') then
q1 <= '0';
q2_long <= '1';
q3 <= b"1010Y";
octal_test <= 12o"01234567_XY";
hex_test := 7X"0123456789--aAbBcCdDeEfF_XY"; -- Comment
bool_test := true;
elsif rising_edge(clk) then
if (ce = '1') then
q1 <= d1;
q2_long <= d2_long;
-- Some syntax number matching.
x0 <= 25_6;
x1 <= 16#1234_ABCD_EF#;
x2 <= 10#1024#E+00;
x3 <= 1_024e-9;
y0 <= 3.141_592_654;
y1 <= 1_2.5e-9;
y2 <= 2#0.1_0#;
y3 <= 10#10_24.0#E+00;
z0 <= math_pi;
a <= 3 + 4;
pt1 <= 0;
pt2 <= (0);
end if;
end if;
-- If/then Leo style (heaven help us)
if (my_condition_a = 1)
then a <= b;
elsif (my_condition_b = 2)
then c <= d;
else e <= f;
end if;
-- Extremely long conditional test
if (((a and b) and (x or y) or
((m or n) and c
or d) and
boolean)) then
g <= h;
end if;
-- Case test long form
CASE_LABEL : case my_tester is
when 1 =>
a <= b;
c <= d;
when 2 =>
e <= f;
g <= h;
when 3 =>
i <= j;
k <= l;
when 4 =>
foo <= (others => '0');
when others =>
null;
end case CASE_LABEL;
-- Case test compact form
-- The fix for the alignment of => breaks alignment here, but it's
-- probably okay. Compact is already readable.
case my_test is
when a => a <= b;
when c => c <= d;
when others => e <= f;
end case;
-- Case test for alignment of => in a case statement.
case my_alignment_test is
when a =>
long_signal_name <= (others => '0');
when b =>
another_long_name <= (others => '0');
when others =>
a_third_long_name <= (others => '0');
end case;
end process SEQUENTIAL_PROCESS;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
COMBINATORIAL_PROCESS : process (all)
begin
wait;
wait until (a > b);
wait for 10 ns;
-- Procedure calls
SUBPROGRAM_CALL_LABEL : my_subprogram_call(values);
ANOTHER_CALL : some_write(L, string'("Text"));
write(L, string'("foobar"));
std.env.stop(0);
stop(0);
-- Loop tests
MY_BASIC_LOOP : loop
end loop MY_BASIC_LOOP;
MY_LOOP : loop
MY_INNER_LOOP : loop
next;
end loop MY_INNER_LOOP;
MY_WHILE_LOOP : while (a > b) loop
a <= b;
end loop;
exit;
end loop MY_LOOP;
MY_FOR_LOOP : for index in 0 to 9 loop
if (condition) then
a := b;
counter := counter + 1;
else
next;
end if;
end loop MY_FOR_LOOP;
end process COMBINATORIAL_PROCESS;
-------------------------------------------------------------------------------
-- Process name variations
-------------------------------------------------------------------------------
process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : postponed process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end postponed process LABEL;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-- Assignment statements
foo <= bar;
foo(99) <= signal_name;
foo(15 downto 0) <= other_signal_name(15 downto 0);
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
foo(to_integer(my_unsigned)) <= 97;
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
adder1 <= ( '0' & add_l) + ( '0' & add_m);
adder2 <= ("0" & add_r) + ('0' & add_b);
adder <= ('0' & adder1) + ('0' & adder2);
bus_rw <= '1' when (condition) else '0';
mux_output <= selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
mux_output <=
selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
with my_signal select
address <=
adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select
a <= adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select a <=
tiny when choice1,
bigger when choice2,
really_long when choice3,
X"0000" when others;
data_bus_miso <=
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"FFFFFFFF" when others;
assert (condition)
report "This string would \nget printed in a simulator. -- Comment Test /* Other comment test */"
severity WARNING;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
MY_GENERATOR : for x in 0 to 7 generate
signal a : std_logic;
begin
x <= a;
end generate MY_GENERATOR;
for i in foobar'range generate
end generate;
for x in std_logic_vector generate
end generate;
for index in 0 to 9 generate
end generate;
MY_THING : if (x>1) generate
else
elsif (y<0) generate
end generate;
MY_CASE_GEN : case thing generate
when choice =>
when choice =>
end generate MY_CASE_GEN;
end architecture rtl;
-------------------------------------------------------------------------------
-- Syntax testing some architecture end clause variations.
-------------------------------------------------------------------------------
architecture testing of my_entity is
begin
end architecture testing;
architecture testing of my_entity is
begin
end testing;
architecture testing of my_entity is
begin
end architecture;
architecture testing of my_entity is
begin
end;
-------------------------------------------------------------------------------
-- PACKAGE, PROCEDURE, AND FUNCTION TESTS
-------------------------------------------------------------------------------
package my_package is
-------------------------------------------------------------------------------
-- Type and constant declarations
-------------------------------------------------------------------------------
-- Fairly simple enumerated type.
type MY_STATES is (IDLE, STATE1, STATE2, STATE3);
-- Enumerated type with entries on different lines
type MY_STATES is
(
IDLE,
S1,
S2,
S3
);
-- Complex type with record
type T_MY_TYPE is record
name : type;
name : type;
name : type(3 downto 0);
name : other_type;
really_long_name : yat;
a, b, c : std_logic;
end record;
type T_MY_ARRAY_TYPE is array (3 downto 0) of integer;
type word is array (0 to 31) of bit;
type state_counts is array (idle to error) of natural;
type state_counts is array (controller_state range idle to error) of natural;
type coeff_array is array (coeff_ram_address'reverse_range) of real;
type my_range is range 0 to 31;
type bit_index is range 0 to number_of_bits-1;
type resistance is range 0 to 1e9 units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
-- Simple constant
constant C_CLOCK_SPEED : real := 3.75e-9; -- seconds
-- Complex constant
constant C_MY_BFM_INIT : T_MY_TYPE :=
(
clk => 'z',
addr => (others => '0'),
addr_data => (others => '0'),
oe_n => 'z',
gta_n => 'z'
);
-------------------------------------------------------------------------------
-- Procedure Declarations
-------------------------------------------------------------------------------
-- K&R Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE
);
-- Allman Style. It looks a little like the GNU style because parens are
-- indented, however it's only because these are being treated as the code
-- block. Might be able to mix it up a little with the continuation
-- clauses.
procedure my_init_procedure
(
signal name : inout type
);
-- Lisp Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- One line style
function reverse_bus (bus_in : in std_logic_vector) return std_logic_vector;
-- K&R Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Lisp Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer) return boolean;
end package my_package;
package body my_package is
-------------------------------------------------------------------------------
-- Procedure Body Tests
-------------------------------------------------------------------------------
-- K&R Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Allman Style
procedure elbc_gpcm_init
(
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Lisp Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-------------------------------------------------------------------------------
-- Function Body Tests
-------------------------------------------------------------------------------
-- Single line style.
function reverse_bus (bus_in : in slv) return slv is
variable bus_out : std_logic_vector(bus_in'range);
alias bus_in_rev : std_logic_vector(bus_in'reverse_range) is bus_in;
begin
for i in bus_in_rev'range loop
bus_out(i) := bus_in_rev(i);
end loop;
return bus_out;
end; -- function reverse_bus
-- K&$ Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
variable foo, bar : std_logic;
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Lisp Style
function onehot_vector (
size : in integer;
index : in integer) return slv is
variable vector_out : std_logic_vector(size-1 downto 0);
begin
for i in vector_out'range loop
if (i = index) then
vector_out(i) := '1';
else
vector_out(i) := '0';
end if;
end loop;
return vector_out;
end function onehot_vector;
-- Padding function
function make_miso_word (d_in : std_logic_vector)
return std_logic_vector is
variable d_out : std_logic_vector(C_SPI_DATA_LEN-1 downto 0);
begin
end function make_miso_word;
end package body my_package;
| mit |
hamsternz/FPGA_Webserver | hdl/transport/transport_commit_buffer.vhd | 1 | 7231 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: transport_commit_buffer - Behavioral
--
-- Description: Somewhere to hold the data outbound packet while waiting to
-- be granted access to the TX interface.
-- If the buffer gets over-run with data (e.g. if the TX interface is
-- busy) then it drops the packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity transport_commit_buffer is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end transport_commit_buffer;
architecture Behavioral of transport_commit_buffer is
type a_data_buffer is array(0 to 2047) of std_logic_vector(8 downto 0);
signal data_buffer : a_data_buffer := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of data_buffer : signal is "block";
signal read_addr : unsigned(10 downto 0) := (others => '1');
signal write_addr : unsigned(10 downto 0) := (others => '0');
signal committed_addr : unsigned(10 downto 0) := (others => '1');
type s_read_state is (read_idle, read_reading1, read_reading, read_waiting);
signal read_state : s_read_state := read_idle;
type s_write_state is (write_idle, write_writing, write_aborted);
signal write_state : s_write_state := write_idle;
signal i_packet_out_valid : std_logic := '0';
signal i_packet_out_valid_last : std_logic := '0';
signal i_packet_out_data : std_logic_vector(7 downto 0) := (others => '0');
constant fcs_length : integer := 4;
constant interpacket_gap : integer := 12;
constant for_next_preamble : integer := 8;
-- counter for the delay between packets
signal read_pause : unsigned(5 downto 0) := to_unsigned(fcs_length + interpacket_gap + for_next_preamble-1,6);
signal write_data : std_logic_vector(8 downto 0);
signal read_data : std_logic_vector(8 downto 0);
begin
with data_valid_in select write_data <= data_valid_in & data_in when '1',
(others => '0') when others;
i_packet_out_valid <= read_data(8);
i_packet_out_data <= read_data(7 downto 0);
packet_out_valid <= i_packet_out_valid;
packet_out_data <= i_packet_out_data;
infer_dp_mem_process: process(clk)
variable this_read_addr : unsigned(10 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if write_state = write_writing or data_valid_in = '1' then
data_buffer(to_integer(write_addr)) <= write_data;
end if;
this_read_addr := read_addr;
if i_packet_out_valid = '0' then
if read_addr = committed_addr or i_packet_out_valid_last = '1' then
packet_out_request <= '0';
else
packet_out_request <= '1';
if packet_out_granted = '1' then
this_read_addr := read_addr + 1;
end if;
end if;
else
this_read_addr := read_addr + 1;
end if;
i_packet_out_valid_last <= i_packet_out_valid;
read_data <= data_buffer(to_integer(this_read_addr));
read_addr <= this_read_addr;
end if;
end process;
process(clk)
variable write_data : std_logic_vector(8 downto 0);
begin
if rising_edge(clk) then
-------------------------------------------------
-- Writing the data into the buffer. If the buffer
-- would overrun the then packet is dropped (i.e.
-- committed_addr will not be updated).
------------------------------------------------
case write_state is
when write_writing =>
if write_addr+1 = read_addr then
-------------------------------------------------------
-- If we would wrap around? Is so then abort the packet
-------------------------------------------------------
write_addr <= committed_addr;
write_state <= write_aborted;
else
write_addr <= write_addr + 1;
if data_valid_in = '0' then
committed_addr <= write_addr;
write_state <= write_idle;
end if;
end if;
when write_aborted =>
---------------------------------------------------------
-- Wait until the data_valid_in drop at the end of packet
---------------------------------------------------------
if data_valid_in = '0' then
write_state <= write_idle;
end if;
when others => -- write_idle state
if data_valid_in = '1' then
write_addr <= write_addr + 1;
write_state <= write_writing;
end if;
end case;
end if;
end process;
end Behavioral; | mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_handler.vhd | 1 | 13243 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: arp_handler - Behavioral
--
-- Description: Processing for ARP packets.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
------------- From the RFC ---------------------------------------
-- 1: ?Do I have the hardware type in ar$hrd?
-- 2: Yes: (almost definitely)
-- 3: [optionally check the hardware length ar$hln]
-- 4: ?Do I speak the protocol in ar$pro?
-- 5: Yes:
-- 6: [optionally check the protocol length ar$pln]
-- 7: Merge_flag := false
-- 8: If the pair <protocol type, sender protocol address> is
-- 9: already in my translation table, update the sender
--10: hardware address field of the entry with the new
--11: information in the packet and set Merge_flag to true.
--12: ?Am I the target protocol address?
--13: Yes:
--14: If Merge_flag is false, add the triplet <protocol type,
--15: sender protocol address, sender hardware address> to
--16: the translation table.
--17: ?Is the opcode ares_op$REQUEST? (NOW look at the opcode!!)
--18: Yes:
--20: Swap hardware and protocol fields, putting the local
--21: hardware and protocol addresses in the sender fields.
--22: Set the ar$op field to ares_op$REPLY
--23: Send the packet to the (new) target hardware address on
--24: the same hardware on which the request was received.
-------------------------------------------------------------------
-- Lines 1 - 6 : Has already been checked in the RX_ARP module.
-- Lines 7 & 11: Any ARP packet that comes through will update the 256-entry table,
-- always forcing Merge_flag to be true.
-- Line 12 : Need to compare against my IP address - if match then
-- Lines 14-16 : Can be ignored as Merge Flag is true
-- Lines 17 : The op_request field can be used as the CE for the outbound FIFO
-- Lines 20-24 : Requires the our MAC address to place in the etherent and ARP header
-- To send an ARP reply we need to queue the following:
-- ce <= (op_request)
-- dest eth MAC <= src eth MAC
-- src eth MAC <= our eth MAC
-- src hw address <= our eth MAC
-- src prot address <= our IP address
-- op <= REPLY
-- target hw address <= src hw address
-- target prot address <= src prot address
--
-- To start ARP discovery we need to queue the following:
-- ce <= '1'
-- dest eth MAC <= FF:FF:FF:FF:FF:FF
-- src eth MAC <= our eth MAC
-- src hw address <= our eth MAC
-- src prot address <= our IP address
-- op <= REQUEST
-- target hw address <= Desired IP Address
-- target prot address <= 00:00:00:00:00:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0);
-- For the wider design to send any ARP on the wire
queue_request : in std_logic;
queue_request_ip : in std_logic_vector(31 downto 0);
-- to enable IP->MAC lookup for outbound packets
update_valid : out std_logic := '0';
update_ip : out std_logic_vector(31 downto 0) := (others => '0');
update_mac : out std_logic_vector(47 downto 0) := (others => '0'));
end arp_handler;
architecture Behavioral of arp_handler is
component rx_arp is
Port ( clk : in STD_LOGIC;
packet_data_valid : in STD_LOGIC;
packet_data : in STD_LOGIC_VECTOR (7 downto 0);
arp_de : out STD_LOGIC;
arp_op_request : out STD_LOGIC;
arp_sender_hw : out STD_LOGIC_VECTOR(47 downto 0);
arp_sender_ip : out STD_LOGIC_VECTOR(31 downto 0);
arp_target_hw : out STD_LOGIC_VECTOR(47 downto 0);
arp_target_ip : out STD_LOGIC_VECTOR(31 downto 0));
end component;
signal arp_tx_write : std_logic := '0';
signal arp_tx_full : std_logic := '0';
signal arp_tx_op_request : std_logic := '0';
signal arp_tx_src_hw : std_logic_vector(47 downto 0) := our_mac;
signal arp_tx_src_ip : std_logic_vector(31 downto 0) := our_ip;
signal arp_tx_tgt_hw : std_logic_vector(47 downto 0) := (others => '0');
signal arp_tx_tgt_ip : std_logic_vector(31 downto 0) := our_ip;
signal arp_in_write : STD_LOGIC := '0';
signal arp_in_full : STD_LOGIC := '0';
signal arp_in_op_request : STD_LOGIC := '0';
signal arp_in_src_hw : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
signal arp_in_src_ip : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal arp_in_tgt_hw : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
signal arp_in_tgt_ip : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
component arp_tx_fifo
Port ( clk : in STD_LOGIC;
arp_in_write : in STD_LOGIC;
arp_in_full : out STD_LOGIC;
arp_in_op_request : in STD_LOGIC;
arp_in_tgt_hw : in STD_LOGIC_VECTOR(47 downto 0);
arp_in_tgt_ip : in STD_LOGIC_VECTOR(31 downto 0);
arp_out_empty : out std_logic;
arp_out_read : in std_logic := '0';
arp_out_op_request : out std_logic;
arp_out_tgt_hw : out std_logic_vector(47 downto 0);
arp_out_tgt_ip : out std_logic_vector(31 downto 0));
end component;
signal arp_out_empty : std_logic;
signal arp_out_read : std_logic := '0';
signal arp_out_op_request : std_logic;
signal arp_out_src_hw : std_logic_vector(47 downto 0);
signal arp_out_src_ip : std_logic_vector(31 downto 0);
signal arp_out_tgt_hw : std_logic_vector(47 downto 0);
signal arp_out_tgt_ip : std_logic_vector(31 downto 0);
component arp_send_packet
Port ( clk : in STD_LOGIC;
-- Interface to the outgoing ARP queue
arp_fifo_empty : in std_logic;
arp_fifo_read : out std_logic := '0';
arp_op_request : in std_logic;
arp_src_hw : in std_logic_vector(47 downto 0);
arp_src_ip : in std_logic_vector(31 downto 0);
arp_tgt_hw : in std_logic_vector(47 downto 0);
arp_tgt_ip : in std_logic_vector(31 downto 0);
-- Interface into the Ethernet TX subsystem
packet_request : out std_logic := '0';
packet_granted : in std_logic := '0';
packet_valid : out std_logic;
packet_data : out std_logic_vector(7 downto 0));
end component;
signal hold_request : std_logic := '0';
signal hold_request_ip : std_logic_vector(31 downto 0) := (others => '0');
begin
i_rx_arp: rx_arp Port map (
clk => clk,
packet_data_valid => packet_in_valid,
packet_data => packet_in_data,
arp_de => arp_in_write,
arp_op_request => arp_in_op_request,
arp_sender_hw => arp_in_src_hw,
arp_sender_ip => arp_in_src_ip,
arp_target_hw => arp_in_tgt_hw,
arp_target_ip => arp_in_tgt_ip);
process(clk)
begin
if rising_edge(clk) then
if arp_in_write = '0' or ((arp_in_src_ip and our_netmask) /= (our_ip and our_netmask))then
-- If there is no write , or it is not for our IP subnet then ignore it
-- and queue any request for a new ARP broadcast
update_valid <= '0';
arp_tx_write <= '0';
if queue_request = '1' then
arp_tx_write <= '1';
arp_tx_op_request <= '1';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= (others => '0');
arp_tx_tgt_ip <= queue_request_ip;
elsif hold_request = '1' then
-- if a request was delayed, then write it.
arp_tx_write <= '1';
arp_tx_op_request <= '1';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= (others => '0');
arp_tx_tgt_ip <= hold_request_ip;
hold_request <= '0';
end if;
else
-- It is a write for our subnet, so update the ARP resolver table.
update_valid <= '1';
update_ip <= arp_in_src_ip;
update_mac <= arp_in_src_hw;
if arp_in_op_request = '1' and arp_in_tgt_ip = our_ip and arp_tx_full = '0' then
-- And if it is a request for our MAC, then send it
-- by queuing the outbound reply
arp_tx_write <= '1';
arp_tx_op_request <= '0';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= arp_in_src_hw;
arp_tx_tgt_ip <= arp_in_src_ip;
-- If the request to send an ARP packet gets gazumped by a request
-- from the wire, then hold onto it to and send it next.
hold_request <= queue_request;
hold_request_ip <= queue_request_ip;
end if;
end if;
end if;
end process;
i_arp_tx_fifo: arp_tx_fifo Port map (
clk => clk,
arp_in_write => arp_tx_write,
arp_in_full => arp_tx_full,
arp_in_op_request => arp_tx_op_request,
arp_in_tgt_hw => arp_tx_tgt_hw,
arp_in_tgt_ip => arp_tx_tgt_ip,
arp_out_empty => arp_out_empty,
arp_out_read => arp_out_read,
arp_out_op_request => arp_out_op_request,
arp_out_tgt_hw => arp_out_tgt_hw,
arp_out_tgt_ip => arp_out_tgt_ip);
i_arp_send_packet: arp_send_packet port map (
clk => clk,
arp_fifo_empty => arp_out_empty,
arp_fifo_read => arp_out_read,
arp_op_request => arp_out_op_request,
arp_src_hw => our_mac,
arp_src_ip => our_ip,
arp_tgt_hw => arp_out_tgt_hw,
arp_tgt_ip => arp_out_tgt_ip,
packet_request => packet_out_request,
packet_granted => packet_out_granted,
packet_data => packet_out_data,
packet_valid => packet_out_valid);
end Behavioral;
| mit |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine_seq_generator.vhd | 1 | 2264 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_seq_generator - Behavioral
--
-- Description: A very bad random SYN number generator
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_seq_generator is
Port ( clk : in STD_LOGIC;
seq : out STD_LOGIC_VECTOR (31 downto 0));
end tcp_engine_seq_generator;
architecture Behavioral of tcp_engine_seq_generator is
signal state : unsigned (31 downto 0) := (others => '0');
begin
seq <= std_logic_vector(state);
process(clk)
begin
if rising_edge(clk) then
state <= state+1;
end if;
end process;
end Behavioral;
| mit |
wifidar/wifidar_fpga | src/uart_minibuf.vhd | 2 | 2698 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart_minibuf is
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out std_logic_vector(7 downto 0);
index_data_in: out std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
sample_buffer_full: in std_logic;
uart_send_data: out std_logic;
uart_ready: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end uart_minibuf;
architecture behavioral of uart_minibuf is
type uart_minibuf_state is (reset,waiting,upper_half,upper_half_hold,lower_half,lower_half_hold);
signal curr_state: uart_minibuf_state;
signal curr_index: integer range 0 to (2**10)-1 := 0;
signal uart_ready_prev: std_logic := '0';
signal buffer_full_prev: std_logic := '0';
signal end_buff: std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(clk)) then
uart_ready_prev <= uart_ready;
buffer_full_prev <= sample_buffer_full;
if((buffer_full_prev = '1') and (sample_buffer_full = '0')) then
end_buff <= '1';
end if;
case curr_state is
when reset =>
curr_state <= waiting;
when waiting =>
data_out <= (others => '0');
curr_index <= 0;
uart_send_data <= '0';
if(sample_buffer_full = '1') then
curr_state <= upper_half;
end if;
when upper_half =>
if(curr_index = 0) then
data_out <= "1" & data_in(13 downto 7);
else
data_out <= "0" & data_in(13 downto 7);
end if;
if(uart_ready = '1') then
uart_send_data <= '1';
curr_state <= upper_half_hold;
end if;
when upper_half_hold =>
if(uart_ready = '0') then
uart_send_data <= '0';
end if;
if(uart_ready = '1' and uart_ready_prev = '0') then
curr_state <= lower_half;
end if;
when lower_half =>
curr_index <= curr_index + 1;
data_out <= "0" & data_in(6 downto 0);
if(uart_ready = '1') then
uart_send_data <= '1';
curr_state <= lower_half_hold;
end if;
when lower_half_hold =>
if(uart_ready = '0') then
uart_send_data <= '0';
end if;
if(uart_ready = '1' and uart_ready_prev = '0') then
curr_state <= upper_half;
end if;
if(end_buff = '1') then
end_buff <= '0';
curr_state <= waiting;
end if;
end case;
end if;
end process;
index_data_in <= std_logic_vector(to_unsigned(curr_index,integer(ceil(log(real(num_samples))/log(real(2)))) + 1));
end behavioral;
| mit |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/TMDS_Clocking.vhd | 14 | 11908 | -------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS
-- Data channels. Connect this module directly to the top-level TMDS Clock pins
-- and a 200/300 MHz reference clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TMDS_Clocking is
Generic (
kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
Port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk!
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
SerialClk : out std_logic;
PixelClk : out std_logic;
aLocked : out std_logic);
end TMDS_Clocking;
architecture Behavioral of TMDS_Clocking is
constant kDlyRstDelay : natural := 32;
signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic;
signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused,
drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal LOCKED_int, rRdyRst : std_logic;
signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic;
signal rMMCM_Reset_q : std_logic_vector(1 downto 0);
signal rMMCM_Locked_q : std_logic_vector(1 downto 0);
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rLockLostRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rLockLostRst);
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rLockLostRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rLockLostRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => aDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
RdyLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aDlyLckd,
OutClk => RefClk,
oRst => rRdyRst);
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "TMDS_33")
port map
(
O => CLK_IN_hdmi_clk,
I => TMDS_Clk_p,
IB => TMDS_Clk_n);
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV and BUFR primitive.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_hdmi_clk,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => CLK_OUT_5x_hdmi_clk,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_hdmi_clk,
CLKIN1 => CLK_IN_hdmi_clk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => rMMCM_Reset_q(0));
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR one the clock returns
MMCM_Reset: process(rLockLostRst, RefClk)
begin
if (rLockLostRst = '1') then
rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min
elsif Rising_Edge(RefClk) then
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process MMCM_Reset;
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_Locked);
MMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked;
rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked;
end if;
end process MMCM_LockedDetect;
GlitchFreeLocked: process(rRdyRst, RefClk)
begin
if (rRdyRst = '1') then
aLocked <= '0';
elsif Rising_Edge(RefClk) then
aLocked <= rMMCM_Locked_q(0);
end if;
end process GlitchFreeLocked;
end Behavioral;
| mit |
carlosrd/DAS | P4/Parte C (Opcional 2)/binToSeg.vhd | 5 | 1631 | ----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end binToSeg;
architecture Converter of binToSeg is
begin
with bin select
displaySeg <= "11111100" when "0000", -- 0 => Leds: A,B,C,D,E,F
"01100000" when "0001", -- 1 => Leds: B,C
"11011010" when "0010", -- 2 => Leds: A,B,G,E,D
"11110010" when "0011", -- 3 => Leds: A,B,C,D,G
"01100110" when "0100", -- 4 => Leds: B,C,F,G
"10110110" when "0101", -- 5 => Leds: A,C,D,F,G
"10111110" when "0110", -- 6 => Leds: A,C,D,E,F,G
"11100000" when "0111", -- 7 => Leds: A,B,C
"11111110" when "1000", -- 8 => Leds: A,B,C,D,E,F,G
"11110110" when "1001", -- 9 => Leds: A,B,C,D,F,G
"11101110" when "1010", -- A(10) => Leds: A,B,C,E,F,G
"00111110" when "1011", -- B(11) => Leds: A,B,C,D,E,F,G
"10011100" when "1100", -- C(12) => Leds: A,D,E,F
"01111010" when "1101", -- D(13) => Leds: A,B,C,D,E,F
"10011110" when "1110", -- E(14) => Leds: A,D,E,F,G
"10001110" when "1111", -- F(15) => Leds: A,E,F,G
"00000001" when others; -- En cualquier otro caso encendemos el "."
end Converter;
| mit |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/dvi2rgb.vhd | 1 | 11028 | -------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => "dgl_dvi_edid.txt") -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
| mit |
es17m014/vhdl-counter | src/vhdl/bin2bcd_.vhd | 1 | 1073 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : bin2bcd_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Converts a binary vector into a bcd coded number
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity bin2bcd is
port(
digits_i : in std_logic_vector(13 downto 0);
bcd_o : out std_logic_vector(16 downto 0));
end bin2bcd;
| mit |
es17m014/vhdl-counter | src/old/vhdl/debounce_.vhd | 1 | 1117 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : debounce_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity debounce_4btn is
generic (N : integer := 4);
port (data_i : in std_logic;
clk_i : in std_logic;
reset_i : in std_logic;
qout_o : out std_logic_vector(N-1 downto 0));
end debounce_4btn;
| mit |
TheMassController/VHDL_experimenting | project/complete_system/test/two_brams_tb.vhd | 1 | 6382 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library tb;
use tb.bus_tb_pkg.all;
use tb.depp_tb_pkg.all;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
entity two_brams_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of two_brams_tb is
constant clk_period : time := 20 ns;
signal clk : std_logic := '0';
signal usb_db : std_logic_vector(7 downto 0);
signal usb_write : std_logic;
signal usb_astb : std_logic;
signal usb_dstb : std_logic;
signal usb_wait : std_logic;
signal addr : bus_address_type;
signal data : bus_data_type;
signal wMask : bus_write_mask;
begin
clk <= not clk after (clk_period/2);
main : process
variable bus_address : bus_address_type := (others => '0');
variable bus_writeData : bus_data_type := (others => '0');
variable bus_readData : bus_data_type := (others => '0');
variable depp_address : depp_address_type := (others => '0');
variable depp_data : depp_data_type := (others => '0');
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Write then read") then
-- Set both fast read and fast write
depp_data(depp_mode_fast_write_bit) := '1';
depp_data(depp_mode_fast_read_bit) := '1';
depp_address := std_logic_vector(to_unsigned(depp2bus_mode_register_start, depp_address'length));
depp_tb_depp_write_to_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address,
data => depp_data
);
-- Set the bus address to all zeros
depp_tb_bus_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => bus_address
);
-- Set the writemask to all 1
depp_address := std_logic_vector(to_unsigned(depp2bus_write_mask_reg_start, depp_address'length));
depp_data := (others => '1');
depp_tb_depp_write_to_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address,
data => depp_data
);
-- Set the depp address to writeData start
depp_address := std_logic_vector(to_unsigned(depp2bus_writeData_reg_start, depp_address'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address
);
-- Start with writing
for i in 0 to 1023 loop
bus_writeData := std_logic_vector(to_unsigned(i, bus_writeData'length));
for j in 0 to 3 loop
depp_tb_depp_set_data (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => bus_writeData((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
end loop;
-- Set the bus address to all zeros
bus_address := (others => '0');
depp_tb_bus_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => bus_address
);
-- Set the depp address to readData_start
depp_address := std_logic_vector(to_unsigned(depp2bus_readData_reg_start, depp_address'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address
);
-- Now read it back
for i in 0 to 1023 loop
for j in 0 to 3 loop
depp_tb_depp_get_data (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => bus_readData((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
check_equal(to_integer(unsigned(bus_readData)), i);
end loop;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 1 ms);
two_brams_system : entity src.two_brams
port map (
clk_50mhz => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait
);
end architecture;
| mit |
digital-sound-antiques/vm2413 | PhaseGenerator.vhd | 2 | 3829 | --
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end PhaseGenerator;
architecture RTL of PhaseGenerator is
component PhaseMemory is port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end component;
type ML_TABLE is array (0 to 15) of std_logic_vector(4 downto 0);
constant mltbl : ML_TABLE := (
"00001","00010","00100","00110","01000","01010","01100","01110",
"10000","10010","10100","10100","11000","11000","11110","11110"
);
constant noise14_tbl : std_logic_vector(63 downto 0) :=
"1000100010001000100010001000100100010001000100010001000100010000";
constant noise17_tbl : std_logic_vector(7 downto 0) :=
"00001010";
-- Signals connected to the phase memory.
signal memwr : std_logic;
signal memout, memin : PHASE_TYPE;
-- Counter for pitch modulation;
signal pmcount : std_logic_vector(12 downto 0);
function CONV_PGOUT ( pv : PHASE_TYPE ) return PGOUT_TYPE is
begin
return pv(PHASE_TYPE'high downto PHASE_TYPE'high - PGOUT_TYPE'high);
end;
begin
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable dphase : PHASE_TYPE;
variable noise14 : std_logic;
variable noise17 : std_logic;
variable pgout_buf : PGOUT_TYPE;
begin
if reset = '1' then
pmcount <= (others=>'0');
memwr <= '0';
lastkey := (others=>'0');
dphase := (others=>'0');
noise14 := '0';
noise17 := '0';
elsif clk'event and clk='1' then if clkena = '1' then
noise <= noise14 xor noise17;
if stage = 0 then
memwr <= '0';
elsif stage = 1 then
-- Wait for memory
elsif stage = 2 then
-- Update pitch LFO counter when slot = 0 and stage = 0 (i.e. increment per 72 clocks)
if slot = 0 then
pmcount <= pmcount + '1';
end if;
-- Delta phase
dphase := (SHL("00000000"&(fnum*mltbl(CONV_INTEGER(ml))),blk)(19 downto 2));
if pm ='1' then
case pmcount(pmcount'high downto pmcount'high-1) is
when "01" =>
dphase := dphase + SHR(dphase,"111");
when "11" =>
dphase := dphase - SHR(dphase,"111");
when others => null;
end case;
end if;
-- Update Phase
if lastkey(slot) = '0' and key = '1' and (rhythm = '0' or (slot /= 14 and slot /= 17)) then
memin <= (others=>'0');
else
memin <= memout + dphase;
end if;
lastkey(slot) := key;
-- Update noise
if slot = 14 then
noise14 := noise14_tbl(CONV_INTEGER(memout(15 downto 10)));
elsif slot = 17 then
noise17 := noise17_tbl(CONV_INTEGER(memout(13 downto 11)));
end if;
pgout_buf := CONV_PGOUT(memout);
pgout <= pgout_buf;
memwr <= '1';
elsif stage = 3 then
memwr <= '0';
end if;
end if; end if;
end process;
MEM : PhaseMemory port map(clk,reset,slot,memwr,memout,memin);
end RTL;
| mit |
es17m014/vhdl-counter | src/vhdl/x7seg.vhd | 1 | 2369 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : x7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: 7 Segment display test with 1 kHz refreshrate
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of x7seg is
component gen_counter is
generic(N : integer := 8);
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_o : out std_logic_vector(N-1 downto 0));
end component;
component mux44to1 is
port (
digits_i : in std_logic_vector(15 downto 0);
sel_i : in std_logic_vector(1 downto 0);
digit_o : out std_logic_vector(3 downto 0));
end component;
component ancode is
port (
sel_i : in std_logic_vector(1 downto 0);
aen_i : in std_logic_vector(3 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0));
end component;
component hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0));
end component;
signal s_sel : std_logic_vector(1 downto 0);
signal s_digit : std_logic_vector(3 downto 0);
signal s_count : std_logic_vector(1 downto 0);
begin
s_sel <= s_count;
ss_o(7) <= '1'; -- turn off the decimal point
p_gen_counter: gen_counter
generic map (
N => 2)
port map (
clk_i => clk_i,
reset_i => reset_i,
count_o => s_count);
p_mux44to1: mux44to1
port map (
digits_i => digits_i,
sel_i => s_sel,
digit_o => s_digit);
p_ancode: ancode
port map (
sel_i => s_sel,
aen_i => aen_i,
ss_sel_o => ss_sel_o);
p_hex7seg: hex7seg
port map (
digit_i => s_digit,
ss_o => ss_o(6 downto 0));
end rtl; | mit |
es17m014/vhdl-counter | src/old/tb/tb_debouncer.vhd | 1 | 2250 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_debounce.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_debouncer is end tb_debouncer;
architecture sim of tb_debouncer is
-- Declaration of the component under test
component debouncer
port(clk_i : in std_logic; --input clock
reset_i : in std_logic;
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic);
end component debouncer;
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal btn_i : std_logic := '0';
signal deb_o : std_logic;
begin
-- Instantiate the design under test
i_debouncer : debouncer
port map (
clk_i => clk_i,
reset_i => reset_i,
btn_i => btn_i,
deb_o => deb_o);
clk_i <= not clk_i after 5 ns;
-- Generate inputs for simulation
run : process
begin
btn_i <= '0';
wait for 7 ns;
btn_i <= '0';
wait for 4 ns;
btn_i <= '0';
wait for 10 ns;
btn_i <= '1';
wait for 5 ns;
reset_i <= '1';
wait for 5 ns;
reset_i <= '0';
btn_i <= '0';
wait for 6 ns;
btn_i <= '1';
wait for 8 ns;
btn_i <= '1';
wait for 3 ns;
btn_i <= '0';
wait for 7 ns;
btn_i <= '1';
wait for 2 ns;
btn_i <= '1';
wait for 8 ns;
btn_i <= '1';
wait for 500 ns;
btn_i <= '0';
wait;
end process run;
end sim;
| mit |
LucasMahieu/TP_secu | code/AES/vhd/vhd/l_barrel.vhd | 2 | 1058 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------
-- Entity implementing shiftrow operation.
-- amount<0> controls rotation by one byte to the left
-- amount<1> controls rotation by two bytes
-- Input size configurable through generic parameter SIZE
-----------------------------------------------------------------------
-- Component Declaration
entity L_barrel is
generic ( SIZE : integer := 32 );
port (
d_in : in std_logic_vector (SIZE-1 downto 0);
amount : in std_logic_vector (1 downto 0); -- 0 to 3
d_out : out std_logic_vector (SIZE-1 downto 0) ) ;
end L_barrel;
-- Architecture of the Component
architecture a_L_barrel of L_barrel is
signal inner : std_logic_vector (SIZE-1 downto 0);
begin
inner <= d_in( SIZE/4*3-1 downto 0 ) & d_in( SIZE-1 downto SIZE/4*3 )
when ( amount(0)='1' ) else d_in;
d_out <= inner( SIZE/2-1 downto 0 ) & inner( SIZE-1 downto SIZE/2 )
when ( amount(1)='1' ) else inner;
end a_L_barrel;
| mit |
es17m014/vhdl-counter | src/vhdl/io_ctrl_.vhd | 1 | 1670 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: io control module according spec
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity io_ctrl is
port (clk_i : in std_logic; -- clock input
reset_i : in std_logic; -- central reset
digits_i : in std_logic_vector(13 downto 0); -- four digit in one digits vector
sw_i : in std_logic_vector(15 downto 0); -- 16 input switches
pb_i : in std_logic_vector(3 downto 0); -- 4 control buttons
ss_o : out std_logic_vector(7 downto 0); -- data for all 7-segment digits
ss_sel_o : out std_logic_vector(3 downto 0); -- selection vector for the 7-segment digit
swclean_o : out std_logic_vector(15 downto 0); -- 16 switches to internal logic
pbclean_o : out std_logic_vector(3 downto 0)); -- 4 buttons to internal logic
end io_ctrl;
| mit |
digital-sound-antiques/vm2413 | vm2413.vhd | 2 | 10377 | --
-- VM2413.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
constant MAXCH : integer := 9;
constant MAXSLOT : integer := MAXCH * 2;
subtype CH_TYPE is integer range 0 to MAXCH-1;
subtype SLOT_TYPE is integer range 0 to MAXSLOT-1;
subtype STAGE_TYPE is integer range 0 to 3;
subtype REGS_VECTOR_TYPE is std_logic_vector(23 downto 0);
type REGS_TYPE is record
INST : std_logic_vector(3 downto 0);
VOL : std_logic_vector(3 downto 0);
SUS : std_logic;
KEY : std_logic;
BLK : std_logic_vector(2 downto 0);
FNUM : std_logic_vector(8 downto 0);
end record;
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE;
subtype VOICE_ID_TYPE is integer range 0 to 37;
subtype VOICE_VECTOR_TYPE is std_logic_vector(35 downto 0);
type VOICE_TYPE is record
AM, PM, EG, KR : std_logic;
ML : std_logic_vector(3 downto 0);
KL : std_logic_vector(1 downto 0);
TL : std_logic_vector(5 downto 0);
WF : std_logic;
FB : std_logic_vector(2 downto 0);
AR, DR, SL, RR : std_logic_vector(3 downto 0);
end record;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE;
-- Voice Parameter Types
subtype AM_TYPE is std_logic; -- AM switch - '0':off '1':3.70Hz
subtype PM_TYPE is std_logic; -- PM switch - '0':stop '1':6.06Hz
subtype EG_TYPE is std_logic; -- Envelope type - '0':release '1':sustine
subtype KR_TYPE is std_logic; -- Keyscale Rate
subtype ML_TYPE is std_logic_vector(3 downto 0); -- Multiple
subtype WF_TYPE is std_logic; -- WaveForm - '0':sine '1':half-sine
subtype FB_TYPE is std_logic_vector(2 downto 0); -- Feedback
subtype AR_TYPE is std_logic_vector(3 downto 0); -- Attack Rate
subtype DR_TYPE is std_logic_vector(3 downto 0); -- Decay Rate
subtype SL_TYPE is std_logic_vector(3 downto 0); -- Sustine Level
subtype RR_TYPE is std_logic_vector(3 downto 0); -- Release Rate
-- F-Number, Block and Rks(Rate and key-scale) types
subtype BLK_TYPE is std_logic_vector(2 downto 0); -- Block
subtype FNUM_TYPE is std_logic_vector(8 downto 0); -- F-Number
subtype RKS_TYPE is std_logic_vector(3 downto 0); -- Rate-KeyScale
-- 18 bits phase counter
subtype PHASE_TYPE is std_logic_vector (17 downto 0);
-- Phage generator's output
subtype PGOUT_TYPE is std_logic_vector (8 downto 0);
-- Final linear output of opll
subtype LI_TYPE is std_logic_vector (8 downto 0); -- Wave in Linear
-- Total Level and Envelope output
subtype DB_TYPE is std_logic_vector(6 downto 0); -- Wave in dB, Reso: 0.375dB
subtype SIGNED_LI_VECTOR_TYPE is std_logic_vector(LI_TYPE'high + 1 downto 0);
type SIGNED_LI_TYPE is record
sign : std_logic;
value : LI_TYPE;
end record;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE;
subtype SIGNED_DB_VECTOR_TYPE is std_logic_vector(DB_TYPE'high + 1 downto 0);
type SIGNED_DB_TYPE is record
sign : std_logic;
value : DB_TYPE;
end record;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE;
-- Envelope generator states
subtype EGSTATE_TYPE is std_logic_vector(1 downto 0);
constant Attack : EGSTATE_TYPE := "01";
constant Decay : EGSTATE_TYPE := "10";
constant Release : EGSTATE_TYPE := "11";
constant Finish : EGSTATE_TYPE := "00";
-- Envelope generator phase
subtype EGPHASE_TYPE is std_logic_vector(22 downto 0);
-- Envelope data (state and phase)
type EGDATA_TYPE is record
state : EGSTATE_TYPE;
phase : EGPHASE_TYPE;
end record;
subtype EGDATA_VECTOR_TYPE is std_logic_vector(EGSTATE_TYPE'high + EGPHASE_TYPE'high + 1 downto 0);
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE;
component Opll port(
XIN : in std_logic;
XOUT : out std_logic;
XENA : in std_logic;
D : in std_logic_vector(7 downto 0);
A : in std_logic;
CS_n : in std_logic;
WE_n : in std_logic;
IC_n : in std_logic;
MO : out std_logic_vector(9 downto 0);
RO : out std_logic_vector(9 downto 0)
);
end component;
component Controller port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
wr : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
am : out AM_TYPE;
pm : out PM_TYPE;
wf : out WF_TYPE;
ml : out ML_TYPE;
tl : out DB_TYPE;
fb : out FB_TYPE;
ar : out AR_TYPE;
dr : out DR_TYPE;
sl : out SL_TYPE;
rr : out RR_TYPE;
blk : out BLK_TYPE;
fnum : out FNUM_TYPE;
rks : out RKS_TYPE;
key : out std_logic;
rhythm : out std_logic
);
end component;
-- Slot and stage counter
component SlotCounter
generic (
DELAY : integer range 0 to MAXSLOT*4-1
);
port(
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out SLOT_TYPE;
stage : out STAGE_TYPE
);
end component;
component EnvelopeGenerator
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE
);
end component;
component PhaseGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end component;
component Operator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
WF : in WF_TYPE;
FB : in FB_TYPE;
noise : in std_logic;
pgout : in PGOUT_TYPE;
egout : in DB_TYPE;
faddr : out CH_TYPE;
fdata : in SIGNED_LI_TYPE;
opout : out SIGNED_DB_TYPE
);
end component;
component OutputGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
opout : in SIGNED_DB_TYPE;
faddr : in CH_TYPE;
fdata : out SIGNED_LI_TYPE;
maddr : in SLOT_TYPE;
mdata : out SIGNED_LI_TYPE
);
end component;
component TemporalMixer port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end component;
end VM2413;
package body VM2413 is
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE is
begin
return regs.INST & regs.VOL & "00" & regs.SUS & regs.KEY & regs.BLK & regs.FNUM;
end CONV_REGS_VECTOR;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE is
begin
return (
INST=>vec(23 downto 20), VOL=>vec(19 downto 16),
SUS=>vec(13), KEY=>vec(12), BLK=>vec(11 downto 9), FNUM=>vec(8 downto 0)
);
end CONV_REGS;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE is
begin
return inst.AM & inst.PM & inst.EG & inst.KR &
inst.ML & inst.KL & inst.TL & inst.WF & inst.FB &
inst.AR & inst.DR & inst.SL & inst.RR;
end CONV_VOICE_VECTOR;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE is
begin
return (
AM=>inst_vec(35), PM=>inst_vec(34), EG=>inst_vec(33), KR=>inst_vec(32),
ML=>inst_vec(31 downto 28), KL=>inst_vec(27 downto 26), TL=>inst_vec(25 downto 20),
WF=>inst_vec(19), FB=>inst_vec(18 downto 16),
AR=>inst_vec(15 downto 12), DR=>inst_vec(11 downto 8), SL=>inst_vec(7 downto 4), RR=>inst_vec(3 downto 0)
);
end CONV_VOICE;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE is
begin
return li.sign & li.value;
end;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE is
begin
return db.sign & db.value;
end;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE is
begin
return data.state & data.phase;
end;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE is
begin
return ( state => vec(vec'high downto EGPHASE_TYPE'high + 1),
phase => vec(EGPHASE_TYPE'range) );
end;
end VM2413;
| mit |
es17m014/vhdl-counter | src/old/vhdl/cntr_.vhd | 1 | 1719 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the counter module
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity cntr is
port (clk_i : in std_logic; -- clock input
reset_i : in std_logic; -- central reset
cntrup_i : in std_logic; -- counts up if signal is '1'
cntrdown_i : in std_logic; -- counts down if signal is '1'
cntrreset_i : in std_logic; -- sets counter to 0x0 if signal is '1'
cntrhold_i : in std_logic; -- holds count value if signal is '1'
cntr0_i : in std_logic_vector(7 downto 0); -- Digit 0 from internal logic
cntr1_i : in std_logic_vector(7 downto 0); -- Digit 1 from internal logic
cntr2_i : in std_logic_vector(7 downto 0); -- Digit 2 from internal logic
cntr3_i : in std_logic_vector(7 downto 0)); -- Digit 3 from internal logic
end cntr;
| mit |
LucasMahieu/TP_secu | code/AES/vhd/DDR_reg.vhd | 2 | 1065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_register;
architecture small of DDR_register is
signal high_data, low_data : std_logic_vector( SIZE-1 downto 0 );
begin
HIGH_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
high_data <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then
high_data <= din_hi;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
LOW_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
low_data <= ( others=>'0' );
elsif ( clk'event and clk='0' ) then
low_data <= din_lo;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
dout_hi <= high_data;
dout_lo <= low_data;
end small;
| mit |
LucasMahieu/TP_secu | code/AES/vhd/Sbox.vhd | 2 | 4859 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-- Component Declaration
entity sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end sbox;
-- Architecture of the Component
architecture a_sbox of sbox is
component DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); --
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component aff_trans port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end component;
component aff_trans_inv port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end component;
component gfmap port (
a : in std_logic_vector (7 downto 0);
ah, al : out std_logic_vector (3 downto 0));
end component;
component quadrato port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component x_e is port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0) );
end component;
component gf_molt is port (
a, b: in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component gf_inv is port (
a_in : std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component gfmapinv is port (
ah, al : in std_logic_vector (3 downto 0);
a : out std_logic_vector (7 downto 0) );
end component;
-- Internal Signal (4 std_logic)
signal ah, a1h, al, a1l, o, n, m, l, i, g, f,
p, p_hi, p_lo, q, d, d_hi, d_lo, r, r_hi, r_lo : std_logic_vector (3 downto 0);
-- Internal Signal (8 bit)
signal s, t, v, z : std_logic_vector (7 downto 0);
signal s_enc_buffer : T_ENCDEC;
begin
-- Affine Trasnformation
gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
v <= b_in;
end generate;
gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate
ati:aff_trans_inv port map (b_in, s);
v <= s when (ctrl_dec = C_DEC) else b_in;
end generate;
-- Map
mp:gfmap port map (v, ah, al);
-- First Square
qua1:quadrato port map (ah, o);
-- Second Square
qua2:quadrato port map (al, n);
-- X [e]
xe:x_e port map (o, m);
-- First Moltiplicator
molt1:gf_molt port map (ah, al, l);
f <= ah xor al;
i <= m xor n;
g <= i xor l;
-- Inverter
--inv:gf_inv port map (q, d);
inv:gf_inv port map (g, q);
temp_reg_p : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>ah, din_lo=>ah, --dout=>p,
dout_hi=>p_hi, dout_lo=>p_lo,
rst=>reset, clk=>clock );
p <= p_hi when ( clock = '1' ) else p_lo;
--temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( g, q, reset, clock );
temp_reg_q : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>q, din_lo=>q, --dout=>d,
dout_hi=>d_hi, dout_lo=>d_lo,
rst=>reset, clk=>clock );
d <= d_hi when ( clock = '1' ) else d_lo;
temp_reg_r : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>f, din_lo=>f, --dout=>r,
dout_hi=>r_hi, dout_lo=>r_lo,
rst=>reset, clk=>clock );
r <= r_hi when ( clock = '1' ) else r_lo;
gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_enc_buffer <= C_ENC;
end generate; -- gen002e : if ( not C_INCLUDE_DECODING_LOGIC )
gen002d : if ( C_INCLUDE_DECODING_LOGIC ) generate
S_ENC_PROC : process( reset, clock )
begin
if ( reset=RESET_ACTIVE ) then
s_enc_buffer <= C_ENC;
elsif ( clock'event and clock='1' ) then
s_enc_buffer <= ctrl_dec;
end if;
end process S_ENC_PROC;
end generate; -- gen002d : if ( C_INCLUDE_DECODING_LOGIC )
-- Second Moltiplicator
molt2:gf_molt port map (p, d, a1h);
-- Third Moltiplicator
molt3:gf_molt port map (d, r, a1l);
-- Inverse Map
mapinv:gfmapinv port map (a1h, a1l, z);
-- Inverse Affine Transformation
at:aff_trans port map (z, t);
gen001e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
b_out <= t;
end generate;
gen001d : if ( C_INCLUDE_DECODING_LOGIC ) generate
b_out <= z when ( s_enc_buffer=C_DEC ) else t;
end generate;
end a_sbox;
| mit |